coreboot-gerrit October 2016

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Patch set updated for coreboot: google/gru: pass the gpio power supply enable pin to bl31
by Patrick Georgi 06 Oct '16

06 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16719 -gerrit commit d4075f58e5f0ea30fac71d3c6f3fb6c040b835b7 Author: Lin Huang <hl(a)rock-chips.com> Date: Mon Aug 22 17:35:40 2016 -0700 google/gru: pass the gpio power supply enable pin to bl31 We need to disable some regulators when device goes into suspend. This means that we need to pass some gpios to bl31, and disable these gpios when bl31 runs the suspend function. BRANCH=None BUG=chrome-os-partner:56423 TEST=enter suspend, measure suspend gpios go to low [pg: also update arm-trusted-firmware to match] Change-Id: Ia0835e16f7e65de6dd24a892241f0af542ec5b4b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0f3332ef2136fd93f7faad579386ba5af003cf70 Original-Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/374046 Original-Commit-Ready: Caesar Wang <wxt(a)rock-chips.com> Original-Tested-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- 3rdparty/arm-trusted-firmware | 2 +- src/mainboard/google/gru/board.h | 3 +++ src/mainboard/google/gru/mainboard.c | 43 ++++++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+), 1 deletion(-) diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index e4f51ee..bfd9251 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit e4f51eee91187e980f5e0e436c65f325fc35c94b +Subproject commit bfd925139fdbc2e87979849907b34843aa326994 diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index 382c462..7880cca 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -25,6 +25,9 @@ #define GPIO_POWEROFF GPIO(1, A, 6) #define GPIO_RESET GPIO(0, B, 3) #define GPIO_WP GPIO(1, C, 2) +#define GPIO_P15V_EN GPIO(0, B, 2) +#define GPIO_P30V_EN GPIO(0, B, 4) +#define GPIO_P18V_AUDIO_PWREN GPIO(0, A, 2) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 8359ca4..902228b 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -43,6 +43,48 @@ static void configure_emmc(void) rkclk_configure_emmc(); } +static void register_gpio_suspend(void) +{ + /* + * these 3 pin to disable gpio2 ~ gpio4 1.5v, 1.8v, 3.3v power supply + * so need to shut down the power supply from high voltage to + * low voltage, and consider register_bl31() appends to the front off + * the list, we should register 1.5v enable pin to 3.3v enable pin + */ + static struct bl31_gpio_param param_p15_en = { + .h = { + .type = PARAM_SUSPEND_GPIO, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_LOW, + }, + }; + param_p15_en.gpio.index = GET_GPIO_NUM(GPIO_P15V_EN); + register_bl31_param(&param_p15_en.h); + + static struct bl31_gpio_param param_p18_audio_en = { + .h = { + .type = PARAM_SUSPEND_GPIO, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_LOW, + }, + }; + param_p18_audio_en.gpio.index = GET_GPIO_NUM(GPIO_P18V_AUDIO_PWREN); + register_bl31_param(&param_p18_audio_en.h); + + static struct bl31_gpio_param param_p30_en = { + .h = { + .type = PARAM_SUSPEND_GPIO, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_LOW, + }, + }; + param_p30_en.gpio.index = GET_GPIO_NUM(GPIO_P30V_EN); + register_bl31_param(&param_p30_en.h); +} + static void register_reset_to_bl31(void) { static struct bl31_gpio_param param_reset = { @@ -184,6 +226,7 @@ static void mainboard_init(device_t dev) setup_usb(); register_reset_to_bl31(); register_poweroff_to_bl31(); + register_gpio_suspend(); } static void enable_backlight_booster(void)

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Patch set updated for coreboot: soc/intel/skylake: Implement Global Reset MEI message
by Rizwan Qureshi 06 Oct '16

06 Oct '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16902 -gerrit commit ac6c7b5ad718c04b510c489d5204e861778243e8 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Fri Aug 19 12:33:42 2016 +0530 soc/intel/skylake: Implement Global Reset MEI message As per ME BWG, there are two mechanism to generate a Global Reset (resets both host and Intel ME), one is through CF9h IO write of 6h or Eh with "CF9h Global Reset" (CF9GR) bit set, PMC PCI offset ACh[20]. Another is to issue the Global Reset MEI message. Because any attempts to cause global reset without synchronizing the two sides might cause unwanted side effects, such as unwritten flash data that will get destroyed if the host were to cause a global reset without informing Intel ME firmware, the recommended method is to send a Global Reset MEI message when the following conditions are met: The PCH chipset firmware just needs to complete the Intel ME Interface #1 initialization and check the Intel ME HFSTS state if Intel ME is not in ERROR state and is accepting MEI commands then firmware should be able to use Global Reset MEI message to trigger global reset. Furthermore, if Intel ME is in ERROR state, BIOS can use I/O 0xCF9 write of 0x06 or 0x0E command with PCH ETR3 register bit [20] to perform the global reset. BUG=none BRANCH=none TEST=Verified Global Reset MEI message is able to perform platform global issue in ME good state. Change-Id: If326a137eeadaa695668b76b84c510e12c546024 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 3 +- src/soc/intel/skylake/include/soc/iomap.h | 2 + src/soc/intel/skylake/include/soc/me.h | 66 +++ src/soc/intel/skylake/me.c | 695 ++++++++++++++++++++++++++++++ src/soc/intel/skylake/me_status.c | 324 -------------- 5 files changed, 765 insertions(+), 325 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ccd38ab..bf429ef 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -36,6 +36,7 @@ romstage-y += flash_controller.c romstage-y += gpio.c romstage-y += memmap.c romstage-y += monotonic_timer.c +romstage-y += me.c romstage-y += pch.c romstage-y += pcr.c romstage-y += pei_data.c @@ -59,7 +60,7 @@ ramstage-y += i2c.c ramstage-y += igd.c ramstage-y += irq.c ramstage-y += lpc.c -ramstage-y += me_status.c +ramstage-y += me.c ramstage-y += memmap.c ramstage-y += monotonic_timer.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index feba302..e736d3b 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -56,6 +56,8 @@ #define GPIO_BASE_SIZE 0x10000 +#define HECI1_BASE_ADDRESS 0xfed1a000 + /* * I/O port address space */ diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 423e9d1..b726711 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -21,6 +21,10 @@ /* * Management Engine PCI registers */ +#define PCI_ME_CMDSTS 0x04 +#define ME_CMDSTS_MSE 2 +#define ME_CMDSTS_BME 4 +#define PCI_ME_BAR 0x10 #define PCI_ME_HFSTS1 0x40 #define ME_HFS_CWS_RESET 0 #define ME_HFS_CWS_INIT 1 @@ -177,6 +181,68 @@ struct me_hfs3 { u32 power_down_mitigation: 1; } __attribute__ ((packed)); +/* + * Management Engine MMIO registers + */ +#define MMIO_ME_CB_WW 0x00 +#define MMIO_HOST_CSR 0x04 + +struct host_csr { + u32 int_en: 1; + u32 int_sts: 1; + u32 int_gen: 1; + u32 host_ready: 1; + u32 host_reset: 1; + u32 rsv: 3; + u32 host_read_ptr: 8; + u32 host_write_ptr: 8; + u32 me_cir_depth: 8; +} __attribute__ ((packed)); + +#define MMIO_ME_CB_RW 0x08 +#define MMIO_ME_CSR 0x0C + +struct me_csr { + u32 int_en: 1; + u32 int_sts: 1; + u32 int_gen: 1; + u32 host_ready: 1; + u32 host_reset: 1; + u32 rsv: 3; + u32 me_read_ptr: 8; + u32 me_write_ptr: 8; + u32 me_cir_buff: 8; +} __attribute__ ((packed)); + +#define MMIO_ME_D0I3 0x800 + +/* Reset Request */ +#define MKHI_GLOBAL_RESET 0x0b + +#define GR_ORIGIN_BIOS_MEM_INIT 0x01 +#define GR_ORIGIN_BIOS_POST 0x02 +#define GR_ORIGIN_MEBX 0x03 + +#define GLOBAL_RST_TYPE 0x01 + +#define BIOS_HOST_ADD 0x00 +#define HECI_MKHI_ADD 0x07 + +#define MAX_HECI_MESSAGE 5 +#define HECI_TIMEOUT 15000000 /* 15sec */ +#define HECI_SEND_TIMEOUT 5000000 /* 5sec */ +#define HECI_READ_TIMEOUT 5000000 /* 5sec */ +#define HECI_DELAY 1000 /* 1ms */ + +struct mei_header { + u32 client_address: 8; + u32 host_address: 8; + u32 length: 9; + u32 reserved: 6; + u32 is_complete: 1; +} __attribute__ ((packed)); + void intel_me_status(void); +int send_global_reset(void); #endif diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c new file mode 100644 index 0000000..7f62eef --- /dev/null +++ b/src/soc/intel/skylake/me.c @@ -0,0 +1,695 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/me.h> +#include <delay.h> +#include <timer.h> + +static inline void me_read_dword_ptr(void *ptr, int offset) +{ + u32 dword = pci_read_config32(PCH_DEV_ME, offset); + memcpy(ptr, &dword, sizeof(dword)); +} + +static inline void me_write_dword(int offset, u32 value) +{ + pci_write_config32(PCH_DEV_ME, offset, value); +} + +static inline void me_mmio_read_dword_ptr(void *ptr, u16 offset) +{ + u32 dword = read32((void *)(HECI1_BASE_ADDRESS + offset)); + memcpy(ptr, &dword, sizeof(dword)); +} + +static inline void me_mmio_write_dword_ptr(u16 offset, u32 value) +{ + write32((void *)(HECI1_BASE_ADDRESS + offset), value); +} + +/* HFSTS1[3:0] Current Working State Values */ +static const char *me_cws_values[] = { + [ME_HFS_CWS_RESET] = "Reset", + [ME_HFS_CWS_INIT] = "Initializing", + [ME_HFS_CWS_REC] = "Recovery", + [3] = "Unknown (3)", + [4] = "Unknown (4)", + [ME_HFS_CWS_NORMAL] = "Normal", + [ME_HFS_CWS_WAIT] = "Platform Disable Wait", + [ME_HFS_CWS_TRANS] = "OP State Transition", + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", + [9] = "Unknown (9)", + [10] = "Unknown (10)", + [11] = "Unknown (11)", + [12] = "Unknown (12)", + [13] = "Unknown (13)", + [14] = "Unknown (14)", + [15] = "Unknown (15)", +}; + +/* HFSTS1[8:6] Current Operation State Values */ +static const char *me_opstate_values[] = { + [ME_HFS_STATE_PREBOOT] = "Preboot", + [ME_HFS_STATE_M0_UMA] = "M0 with UMA", + [ME_HFS_STATE_M3] = "M3 without UMA", + [ME_HFS_STATE_M0] = "M0 without UMA", + [ME_HFS_STATE_BRINGUP] = "Bring up", + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" +}; + +/* HFSTS1[19:16] Current Operation Mode Values */ +static const char *me_opmode_values[] = { + [ME_HFS_MODE_NORMAL] = "Normal", + [ME_HFS_MODE_DEBUG] = "Debug", + [ME_HFS_MODE_DIS] = "Soft Temporary Disable", + [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" +}; + +/* HFSTS1[15:12] Error Code Values */ +static const char *me_error_values[] = { + [ME_HFS_ERROR_NONE] = "No Error", + [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", + [ME_HFS_ERROR_IMAGE] = "Image Failure", + [ME_HFS_ERROR_DEBUG] = "Debug Failure" +}; + +/* HFSTS2[31:28] ME Progress Code */ +static const char *me_progress_values[] = { + [ME_HFS2_PHASE_ROM] = "ROM Phase", + [1] = "Unknown (1)", + [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", + [ME_HFS2_PHASE_BUP] = "BUP Phase", + [4] = "Unknown (4)", + [5] = "Unknown (5)", + [ME_HFS2_PHASE_HOST_COMM] = "Host Communication", + [7] = "Unknown (7)", + [8] = "Unknown (8)" +}; + +/* HFSTS2[27:24] Power Management Event */ +static const char *me_pmevent_values[] = { + [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = + "Clean Moff->Mx wake", + [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = + "Moff->Mx wake after an error", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = + "Clean global reset", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = + "Global reset after an error", + [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = + "Clean Intel ME reset", + [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = + "Intel ME reset due to exception", + [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = + "Pseudo-global reset", + [ME_HFS2_PMEVENT_CM0_CM3] = + "CM0->CM3", + [ME_HFS2_PMEVENT_CM3_CM0] = + "CM3->CM0", + [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = + "Non-power cycle reset", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = + "Power cycle reset through M3", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = + "Power cycle reset through Moff", + [ME_HFS2_PMEVENT_CMX_CMOFF] = + "Cx/Mx->Cx/Moff", + [ME_HFS2_PMEVENT_CM0_CM0PG] = + "CM0->CM0PG", + [ME_HFS2_PMEVENT_CM3_CM3PG] = + "CM3->CM3PG", + [ME_HFS2_PMEVENT_CM0PG_CM0] = + "CM0PG->CM0" + +}; + +/* Progress Code 0 states */ +static const char *me_progress_rom_values[] = { + [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", + [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" +}; + +/* Progress Code 1 states */ +static const char *me_progress_bup_values[] = { + [ME_HFS2_STATE_BUP_INIT] = + "Initialization starts", + [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = + "Disable the host wake event", + [ME_HFS2_STATE_BUP_CG_ENABLE] = + "Enabling CG for cset", + [ME_HFS2_STATE_BUP_PM_HND_EN] = + "Enabling PM handshaking", + [ME_HFS2_STATE_BUP_FLOW_DET] = + "Flow determination start process", + [ME_HFS2_STATE_BUP_PMC_PATCHING] = + "PMC Patching process", + [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = + "Get VSCC params", + [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = + "Set VSCC params", + [ME_HFS2_STATE_BUP_VSCC_ERR] = + "Error reading/matching the VSCC table in the descriptor", + [ME_HFS2_STATE_BUP_EFSS_INIT] = + "Initialize EFFS", + [ME_HFS2_STATE_BUP_CHECK_STRAP] = + "Check to see if straps say ME DISABLED", + [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = + "Timeout waiting for PWROK", + [ME_HFS2_STATE_BUP_STRAP_DIS] = + "EFFS says ME disabled", + [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = + "Possibly handle BUP manufacturing override strap", + [ME_HFS2_STATE_BUP_M3] = + "Bringup in M3", + [ME_HFS2_STATE_BUP_M0] = + "Bringup in M0", + [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = + "Flow detection error", + [ME_HFS2_STATE_BUP_M3_CLK_ERR] = + "M3 clock switching error", + [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = + "Host error - CPU reset timeout, DID timeout, memory missing", + [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = + "M3 kernel load", + [ME_HFS2_STATE_BUP_T32_MISSING] = + "T34 missing - cannot program ICC", + [ME_HFS2_STATE_BUP_WAIT_DID] = + "Waiting for DID BIOS message", + [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = + "Waiting for DID BIOS message failure", + [ME_HFS2_STATE_BUP_DID_NO_FAIL] = + "DID reported no error", + [ME_HFS2_STATE_BUP_ENABLE_UMA] = + "Enabling UMA", + [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = + "Enabling UMA error", + [ME_HFS2_STATE_BUP_SEND_DID_ACK] = + "Sending DID Ack to BIOS", + [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = + "Sending DID Ack to BIOS error", + [ME_HFS2_STATE_BUP_M0_CLK] = + "Switching clocks in M0", + [ME_HFS2_STATE_BUP_M0_CLK_ERR] = + "Switching clocks in M0 error", + [ME_HFS2_STATE_BUP_TEMP_DIS] = + "ME in temp disable", + [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = + "M0 kernel load", +}; + +void intel_me_status(void) +{ + struct me_hfs _hfs, *hfs = &_hfs; + struct me_hfs2 _hfs2, *hfs2 = &_hfs2; + struct me_hfs3 _hfs3, *hfs3 = &_hfs3; + + me_read_dword_ptr(hfs, PCI_ME_HFSTS1); + me_read_dword_ptr(hfs2, PCI_ME_HFSTS2); + me_read_dword_ptr(hfs3, PCI_ME_HFSTS3); + + /* Check Current States */ + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfs->fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfs->ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfs->fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfs->mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfs->boot_options_present ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfs->update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D3 Support : %s\n", + hfs->d3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", + hfs->d0i3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", + hfs2->low_power_state ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Power Gated : %s\n", + hfs2->power_gating_ind ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfs2->cpu_replaced_sts ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfs2->cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %s\n", + me_cws_values[hfs->working_state]); + printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", + me_opstate_values[hfs->operation_state]); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", + me_opmode_values[hfs->operation_mode]); + printk(BIOS_DEBUG, "ME: Error Code : %s\n", + me_error_values[hfs->error_code]); + printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", + me_progress_values[hfs2->progress_code]); + printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", + me_pmevent_values[hfs2->current_pmevent]); + + printk(BIOS_DEBUG, "ME: Progress Phase State : "); + switch (hfs2->progress_code) { + case ME_HFS2_PHASE_ROM: /* ROM Phase */ + printk(BIOS_DEBUG, "%s", + me_progress_rom_values[hfs2->current_state]); + break; + + case ME_HFS2_PHASE_UKERNEL: /* uKernel Phase */ + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + break; + + case ME_HFS2_PHASE_BUP: /* Bringup Phase */ + if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) + && me_progress_bup_values[hfs2->current_state]) + printk(BIOS_DEBUG, "%s", + me_progress_bup_values[hfs2->current_state]); + else + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + break; + + case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ + if (!hfs2->current_state) + printk(BIOS_DEBUG, "Host communication established"); + else + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + break; + + default: + printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", + hfs2->progress_code, hfs2->current_state); + } + printk(BIOS_DEBUG, "\n"); + + /* Power Down Mitigation Status */ + printk(BIOS_DEBUG, "ME: Power Down Mitigation : %s\n", + hfs3->power_down_mitigation ? "YES" : "NO"); + + if (hfs3->power_down_mitigation) { + printk(BIOS_INFO, "ME: PD Mitigation State : "); + if (hfs3->encrypt_key_override == 1 && + hfs3->encrypt_key_check == 0 && + hfs3->pch_config_change == 0) + printk(BIOS_INFO, "Normal Operation"); + else if (hfs3->encrypt_key_override == 1 && + hfs3->encrypt_key_check == 1 && + hfs3->pch_config_change == 0) + printk(BIOS_INFO, "Issue Detected and Recovered"); + else + printk(BIOS_INFO, "Issue Detected but not Recovered"); + printk(BIOS_INFO, "\n"); + + printk(BIOS_DEBUG, "ME: Encryption Key Override : %s\n", + hfs3->encrypt_key_override ? "Workaround Applied" : + "Unable to override"); + printk(BIOS_DEBUG, "ME: Encryption Key Check : %s\n", + hfs3->encrypt_key_check ? "FAIL" : "PASS"); + printk(BIOS_DEBUG, "ME: PCH Configuration Info : %s\n", + hfs3->pch_config_change ? "Changed" : "No Change"); + + printk(BIOS_DEBUG, "ME: Firmware SKU : "); + switch (hfs3->fw_sku) { + case ME_HFS3_FW_SKU_CONSUMER: + printk(BIOS_DEBUG, "Consumer\n"); + break; + case ME_HFS3_FW_SKU_CORPORATE: + printk(BIOS_DEBUG, "Corporate\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown (0x%x)\n", hfs3->fw_sku); + } + } +} +static int wait_heci_ready(void) +{ + struct stopwatch sw; + int timeout = 0; + struct me_csr _csr, *csr = &_csr; + + stopwatch_init_msecs_expire(&sw, HECI_TIMEOUT); + while (1) { + do { + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + if (csr->host_ready) + return 0; + } while (!(timeout = stopwatch_expired(&sw))); + + if (timeout) { + printk(BIOS_ERR, + "ME_RDY bit is not set after 15 sec"); + return -1; + } + udelay(HECI_DELAY); + } +} + +static int wait_heci_cb_avail(int len) +{ + struct stopwatch sw; + int timeout = 0; + struct host_csr _csr, *csr = &_csr; + + me_mmio_read_dword_ptr(csr, MMIO_HOST_CSR); + /* + * if timeout has happend, return failure as + * the circular buffer is not empty + */ + stopwatch_init_msecs_expire(&sw, HECI_SEND_TIMEOUT); + /* Must have room for message and message header */ + while (len > (csr->me_cir_depth - (csr->host_write_ptr - + csr->host_read_ptr))) { + timeout = stopwatch_expired(&sw); + + if (timeout) { + printk(BIOS_ERR, + "Circular Buffer never emptied within 5 sec"); + return -1; + } + /* wait before trying again */ + udelay(HECI_DELAY); + /* read HOST_CSR for next iteration */ + me_mmio_read_dword_ptr(csr, MMIO_HOST_CSR); + } + return 0; +} + +static int send_heci_packet(struct mei_header *head, u32 * payload) +{ + /* compute the message lenth in dwords */ + int len = (head->length + 3) / 4; + int sts; + int index; + struct me_csr _csr, *csr = &_csr; + struct host_csr _hcsr, *hcsr = &_hcsr; + + /* + * wait until there is sufficient room in CB + */ + sts = wait_heci_cb_avail(len+1); + if (sts != 0) + return -1; + + /* Write message header */ + me_mmio_write_dword_ptr(MMIO_ME_CB_WW, *(u32 *) head); + + /* Write message body */ + for (index = 0; index < len; index++) + me_mmio_write_dword_ptr(MMIO_ME_CB_WW, payload[index]); + + /* Set Interrupt Generate bit */ + me_mmio_read_dword_ptr(hcsr, MMIO_HOST_CSR); + hcsr->int_gen = 1; + me_mmio_write_dword_ptr(MMIO_HOST_CSR, *(u32 *) hcsr); + + /* Check if ME Ready bit is set, if set to 0 then return fatal error */ + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + if (csr->host_ready) + return 0; + else + return -1; +} + +static int recv_heci_packet(struct mei_header *head, u32 * packet, + u32 * packet_size) +{ + struct me_csr _csr, *csr = &_csr; + struct host_csr _hcsr, *hcsr = &_hcsr; + int rec_msg = 0; + struct stopwatch sw; + int timeout = 0; + u32 length, index; + + /* Clear Interrupt Status bit */ + me_mmio_read_dword_ptr(hcsr, MMIO_HOST_CSR); + hcsr->int_sts = 1; + me_mmio_write_dword_ptr(MMIO_HOST_CSR, *(u32 *) hcsr); + + /* Check if circular buffer overflow */ + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + /* if yes then return fatal error */ + if ((csr->me_write_ptr - csr->me_read_ptr) > csr->me_cir_buff) + return -1; + /* + * if timeout has happend, return failure as + * the circular buffer is not empty + */ + stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); + /* go until we got message pkt */ + do { + timeout = stopwatch_expired(&sw); + + if (timeout) { + printk(BIOS_ERR, + "Circular Buffer not filled within 5 sec"); + *packet_size = 0; + return -1; + } + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + /* Read one message from HECI buffer */ + if ((csr->me_write_ptr - csr->me_read_ptr) > 0) { + me_mmio_read_dword_ptr(head, MMIO_ME_CB_RW); + /* calculate the message length in dword */ + length = ((head->length + 3) / 4); + if (head->length == 0) { + *packet_size = 0; + goto SET_IG; + } + /* Make sure, we have enough space to catch all */ + if (head->length <= *packet_size) { + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + /* get complete message into circular buffer */ + while (length > (csr->me_write_ptr - + csr->me_read_ptr)) { + udelay(HECI_DELAY); + me_mmio_read_dword_ptr(csr, + MMIO_ME_CSR); + } + /* here is the message */ + for (index = 0; index < length; index++) { + packet[index] = read32( + (void *)(HECI1_BASE_ADDRESS + + MMIO_ME_CB_RW)); + } + rec_msg = 1; + *packet_size = head->length; + } else { + /* Too small buffer */ + *packet_size = 0; + return -1; + } + } + udelay(HECI_DELAY); + } while (!rec_msg); + + /* + * Check if ME Ready bit is set, if set to 0 then return fatal error + * because ME might have reset during transaction and we might have + * read a junk data from CB + */ + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + if (!(csr->host_ready)) + return -1; +SET_IG: + /* Set Interrupt Generate bit */ + me_mmio_read_dword_ptr(hcsr, MMIO_HOST_CSR); + hcsr->int_gen = 1; + me_mmio_write_dword_ptr(MMIO_HOST_CSR, *(u32 *) hcsr); + return 0; +} + +static int +send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress) +{ + u8 retry; + int status = -1; + u32 cir_buff_depth; + struct host_csr _csr, *csr = &_csr; + struct mei_header head; + int cur = 0; + u32 slength; + + for (retry = 0; retry < MAX_HECI_MESSAGE; retry++) { + if (wait_heci_ready() != 0) + continue; + /* HECI is ready */ + me_mmio_read_dword_ptr(csr, MMIO_HOST_CSR); + cir_buff_depth = csr->me_cir_depth; + head.client_address = clientaddress; + head.host_address = hostaddress; + while (len > cur) { + /* + * Set the message complete bit if this is last packet + * in message needs to be "less than" to account for + * the header OR needs to be exact equal to CB depth + */ + if (((((len - cur) + 3) / 4) < cir_buff_depth) || + (((((len - cur) + 3) / 4) == + cir_buff_depth) && + ((((len - cur) + 3) % 4) == 0))) + head.is_complete = 1; + else + head.is_complete = 0; + /* + * calculate length for message header + * header length = smaller of CB buffer or + * remaining message + */ + slength = ((cir_buff_depth <= (((len - cur) + 3) / 4)) + ? ((cir_buff_depth - 1) * 4) + : (len - cur)); + head.length = slength; + head.reserved = 0; + /* + * send the current packet + * (cur should be treated as index for message) + */ + status = send_heci_packet(&head, (u32 *) msg); + if (status != 0) + break; + /* update the length information */ + cur += slength; + msg += cur; + } + if (status != 0) + continue; + else + return status; + } + return status; +} + +static int +recv_heci_message(u32 * message, u32 * message_size) +{ + struct mei_header head; + int cur = 0; + u8 retry; + int status = -1; + int msg_complete = 0; + u32 pkt_buff; + + for (retry = 0; retry < MAX_HECI_MESSAGE; retry++) { + if (wait_heci_ready() != 0) + continue; + /* HECI is ready */ + while ((cur < *message_size) && (msg_complete == 0)) + { + pkt_buff = *message_size - cur; + status = recv_heci_packet(&head, message + (cur >> 2), + &pkt_buff); + if (status == -1) { + *message_size = 0; + break; + } + msg_complete = head.is_complete; + if (pkt_buff == 0) { + /* if not in middle of msg and msg complete bit + * is set then this is a valid zero length msg + */ + if ((cur == 0) && (msg_complete == 1)) + status = 0; + else + status = -1; + *message_size = 0; + break; + } + cur += pkt_buff; + } + if (status != 0) + continue; + else { + *message_size = cur; + break; + } + } + return status; +} + +static int send_heci_reset_message(void) +{ + int status; + struct reset_reply { + u8 group_id; + u8 command; + u8 reserved; + u8 result; + } __attribute__ ((packed)) reply; + struct reset_message { + u8 group_id; + u8 cmd; + u8 reserved; + u8 result; + u8 req_origin; + u8 reset_type; + } __attribute__ ((packed)) msg = { + 0, MKHI_GLOBAL_RESET, 0, 0, + GR_ORIGIN_BIOS_POST, GLOBAL_RST_TYPE}; + u32 reply_size; + + status= send_heci_message((u8 *) & msg, sizeof(msg), + BIOS_HOST_ADD, HECI_MKHI_ADD); + if (status != 0) + return -1; + + reply_size = sizeof(reply); + if (recv_heci_message((u32 *) & reply, &reply_size) == -1) + return -1; + /*get reply result from HECI MSG */ + if (reply.result != 0) { + printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); + return -1; + } else { + printk(BIOS_DEBUG, "%s: Exit with Success\n", __func__); + return 0; + } +} + +int send_global_reset(void) +{ + u32 heci1_bar; + u32 heci1_cmdsts; + int status = -1; + struct me_hfs _hfs, *hfs = &_hfs; + + /* Check HECI1 BAR gets programmed */ + me_read_dword_ptr(&heci1_bar, PCI_ME_BAR); + heci1_bar &= ~0xfff; + if (heci1_bar != HECI1_BASE_ADDRESS) { + /* use default HECI BAR for SoC */ + me_write_dword(PCI_ME_BAR, HECI1_BASE_ADDRESS); + } + /* Check MMIO space & Bus master enabled */ + me_read_dword_ptr(&heci1_cmdsts, PCI_ME_CMDSTS); + if ((heci1_cmdsts & (ME_CMDSTS_MSE | ME_CMDSTS_BME)) != + (ME_CMDSTS_MSE | ME_CMDSTS_BME)) { + me_write_dword(PCI_ME_CMDSTS, ME_CMDSTS_MSE | ME_CMDSTS_BME); + } + /* Check ME operating mode */ + me_read_dword_ptr(hfs, PCI_ME_HFSTS1); + if (hfs->operation_mode) { + goto ret; + } + /* ME should be in Normal Mode for this command */ + status = send_heci_reset_message(); +ret: + return status; +} diff --git a/src/soc/intel/skylake/me_status.c b/src/soc/intel/skylake/me_status.c deleted file mode 100644 index 79d4dfb..0000000 --- a/src/soc/intel/skylake/me_status.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <stdlib.h> -#include <string.h> -#include <soc/pci_devs.h> -#include <soc/me.h> -#include <delay.h> - -static inline void me_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = pci_read_config32(PCH_DEV_ME, offset); - memcpy(ptr, &dword, sizeof(dword)); -} - -/* HFSTS1[3:0] Current Working State Values */ -static const char *me_cws_values[] = { - [ME_HFS_CWS_RESET] = "Reset", - [ME_HFS_CWS_INIT] = "Initializing", - [ME_HFS_CWS_REC] = "Recovery", - [3] = "Unknown (3)", - [4] = "Unknown (4)", - [ME_HFS_CWS_NORMAL] = "Normal", - [ME_HFS_CWS_WAIT] = "Platform Disable Wait", - [ME_HFS_CWS_TRANS] = "OP State Transition", - [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", - [9] = "Unknown (9)", - [10] = "Unknown (10)", - [11] = "Unknown (11)", - [12] = "Unknown (12)", - [13] = "Unknown (13)", - [14] = "Unknown (14)", - [15] = "Unknown (15)", -}; - -/* HFSTS1[8:6] Current Operation State Values */ -static const char *me_opstate_values[] = { - [ME_HFS_STATE_PREBOOT] = "Preboot", - [ME_HFS_STATE_M0_UMA] = "M0 with UMA", - [ME_HFS_STATE_M3] = "M3 without UMA", - [ME_HFS_STATE_M0] = "M0 without UMA", - [ME_HFS_STATE_BRINGUP] = "Bring up", - [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" -}; - -/* HFSTS1[19:16] Current Operation Mode Values */ -static const char *me_opmode_values[] = { - [ME_HFS_MODE_NORMAL] = "Normal", - [ME_HFS_MODE_DEBUG] = "Debug", - [ME_HFS_MODE_DIS] = "Soft Temporary Disable", - [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", - [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" -}; - -/* HFSTS1[15:12] Error Code Values */ -static const char *me_error_values[] = { - [ME_HFS_ERROR_NONE] = "No Error", - [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", - [ME_HFS_ERROR_IMAGE] = "Image Failure", - [ME_HFS_ERROR_DEBUG] = "Debug Failure" -}; - -/* HFSTS2[31:28] ME Progress Code */ -static const char *me_progress_values[] = { - [ME_HFS2_PHASE_ROM] = "ROM Phase", - [1] = "Unknown (1)", - [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", - [ME_HFS2_PHASE_BUP] = "BUP Phase", - [4] = "Unknown (4)", - [5] = "Unknown (5)", - [ME_HFS2_PHASE_HOST_COMM] = "Host Communication", - [7] = "Unknown (7)", - [8] = "Unknown (8)" -}; - -/* HFSTS2[27:24] Power Management Event */ -static const char *me_pmevent_values[] = { - [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = - "Clean Moff->Mx wake", - [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = - "Moff->Mx wake after an error", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = - "Clean global reset", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = - "Global reset after an error", - [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = - "Clean Intel ME reset", - [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = - "Intel ME reset due to exception", - [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = - "Pseudo-global reset", - [ME_HFS2_PMEVENT_CM0_CM3] = - "CM0->CM3", - [ME_HFS2_PMEVENT_CM3_CM0] = - "CM3->CM0", - [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = - "Non-power cycle reset", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = - "Power cycle reset through M3", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = - "Power cycle reset through Moff", - [ME_HFS2_PMEVENT_CMX_CMOFF] = - "Cx/Mx->Cx/Moff", - [ME_HFS2_PMEVENT_CM0_CM0PG] = - "CM0->CM0PG", - [ME_HFS2_PMEVENT_CM3_CM3PG] = - "CM3->CM3PG", - [ME_HFS2_PMEVENT_CM0PG_CM0] = - "CM0PG->CM0" - -}; - -/* Progress Code 0 states */ -static const char *me_progress_rom_values[] = { - [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", - [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" -}; - -/* Progress Code 1 states */ -static const char *me_progress_bup_values[] = { - [ME_HFS2_STATE_BUP_INIT] = - "Initialization starts", - [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = - "Disable the host wake event", - [ME_HFS2_STATE_BUP_CG_ENABLE] = - "Enabling CG for cset", - [ME_HFS2_STATE_BUP_PM_HND_EN] = - "Enabling PM handshaking", - [ME_HFS2_STATE_BUP_FLOW_DET] = - "Flow determination start process", - [ME_HFS2_STATE_BUP_PMC_PATCHING] = - "PMC Patching process", - [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = - "Get VSCC params", - [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = - "Set VSCC params", - [ME_HFS2_STATE_BUP_VSCC_ERR] = - "Error reading/matching the VSCC table in the descriptor", - [ME_HFS2_STATE_BUP_EFSS_INIT] = - "Initialize EFFS", - [ME_HFS2_STATE_BUP_CHECK_STRAP] = - "Check to see if straps say ME DISABLED", - [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = - "Timeout waiting for PWROK", - [ME_HFS2_STATE_BUP_STRAP_DIS] = - "EFFS says ME disabled", - [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = - "Possibly handle BUP manufacturing override strap", - [ME_HFS2_STATE_BUP_M3] = - "Bringup in M3", - [ME_HFS2_STATE_BUP_M0] = - "Bringup in M0", - [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = - "Flow detection error", - [ME_HFS2_STATE_BUP_M3_CLK_ERR] = - "M3 clock switching error", - [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = - "Host error - CPU reset timeout, DID timeout, memory missing", - [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = - "M3 kernel load", - [ME_HFS2_STATE_BUP_T32_MISSING] = - "T34 missing - cannot program ICC", - [ME_HFS2_STATE_BUP_WAIT_DID] = - "Waiting for DID BIOS message", - [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = - "Waiting for DID BIOS message failure", - [ME_HFS2_STATE_BUP_DID_NO_FAIL] = - "DID reported no error", - [ME_HFS2_STATE_BUP_ENABLE_UMA] = - "Enabling UMA", - [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = - "Enabling UMA error", - [ME_HFS2_STATE_BUP_SEND_DID_ACK] = - "Sending DID Ack to BIOS", - [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = - "Sending DID Ack to BIOS error", - [ME_HFS2_STATE_BUP_M0_CLK] = - "Switching clocks in M0", - [ME_HFS2_STATE_BUP_M0_CLK_ERR] = - "Switching clocks in M0 error", - [ME_HFS2_STATE_BUP_TEMP_DIS] = - "ME in temp disable", - [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = - "M0 kernel load", -}; - -void intel_me_status(void) -{ - struct me_hfs _hfs, *hfs = &_hfs; - struct me_hfs2 _hfs2, *hfs2 = &_hfs2; - struct me_hfs3 _hfs3, *hfs3 = &_hfs3; - - me_read_dword_ptr(hfs, PCI_ME_HFSTS1); - me_read_dword_ptr(hfs2, PCI_ME_HFSTS2); - me_read_dword_ptr(hfs3, PCI_ME_HFSTS3); - - /* Check Current States */ - printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfs->fpt_bad ? "BAD" : "OK"); - printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfs->ft_bup_ld_flr ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfs->fw_init_complete ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfs->mfg_mode ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfs->boot_options_present ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfs->update_in_progress ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: D3 Support : %s\n", - hfs->d3_support_valid ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", - hfs->d0i3_support_valid ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", - hfs2->low_power_state ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Power Gated : %s\n", - hfs2->power_gating_ind ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", - hfs2->cpu_replaced_sts ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", - hfs2->cpu_replaced_valid ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - me_cws_values[hfs->working_state]); - printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - me_opstate_values[hfs->operation_state]); - printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - me_opmode_values[hfs->operation_mode]); - printk(BIOS_DEBUG, "ME: Error Code : %s\n", - me_error_values[hfs->error_code]); - printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - me_progress_values[hfs2->progress_code]); - printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - me_pmevent_values[hfs2->current_pmevent]); - - printk(BIOS_DEBUG, "ME: Progress Phase State : "); - switch (hfs2->progress_code) { - case ME_HFS2_PHASE_ROM: /* ROM Phase */ - printk(BIOS_DEBUG, "%s", - me_progress_rom_values[hfs2->current_state]); - break; - - case ME_HFS2_PHASE_UKERNEL: /* uKernel Phase */ - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - case ME_HFS2_PHASE_BUP: /* Bringup Phase */ - if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) - && me_progress_bup_values[hfs2->current_state]) - printk(BIOS_DEBUG, "%s", - me_progress_bup_values[hfs2->current_state]); - else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ - if (!hfs2->current_state) - printk(BIOS_DEBUG, "Host communication established"); - else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - default: - printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", - hfs2->progress_code, hfs2->current_state); - } - printk(BIOS_DEBUG, "\n"); - - /* Power Down Mitigation Status */ - printk(BIOS_DEBUG, "ME: Power Down Mitigation : %s\n", - hfs3->power_down_mitigation ? "YES" : "NO"); - - if (hfs3->power_down_mitigation) { - printk(BIOS_INFO, "ME: PD Mitigation State : "); - if (hfs3->encrypt_key_override == 1 && - hfs3->encrypt_key_check == 0 && - hfs3->pch_config_change == 0) - printk(BIOS_INFO, "Normal Operation"); - else if (hfs3->encrypt_key_override == 1 && - hfs3->encrypt_key_check == 1 && - hfs3->pch_config_change == 0) - printk(BIOS_INFO, "Issue Detected and Recovered"); - else - printk(BIOS_INFO, "Issue Detected but not Recovered"); - printk(BIOS_INFO, "\n"); - - printk(BIOS_DEBUG, "ME: Encryption Key Override : %s\n", - hfs3->encrypt_key_override ? "Workaround Applied" : - "Unable to override"); - printk(BIOS_DEBUG, "ME: Encryption Key Check : %s\n", - hfs3->encrypt_key_check ? "FAIL" : "PASS"); - printk(BIOS_DEBUG, "ME: PCH Configuration Info : %s\n", - hfs3->pch_config_change ? "Changed" : "No Change"); - - printk(BIOS_DEBUG, "ME: Firmware SKU : "); - switch (hfs3->fw_sku) { - case ME_HFS3_FW_SKU_CONSUMER: - printk(BIOS_DEBUG, "Consumer\n"); - break; - case ME_HFS3_FW_SKU_CORPORATE: - printk(BIOS_DEBUG, "Corporate\n"); - break; - default: - printk(BIOS_DEBUG, "Unknown (0x%x)\n", hfs3->fw_sku); - } - } -}

1 0

Patch set updated for coreboot: rockchip/rk3399: Configure USB3 controller to work in USB2 only mode
by Patrick Georgi 06 Oct '16

06 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16717 -gerrit commit 4b1753c96132f4071f59457f10f10cfb12ec46ec Author: Liangfeng Wu <wulf(a)rock-chips.com> Date: Thu Sep 15 17:16:54 2016 +0800 rockchip/rk3399: Configure USB3 controller to work in USB2 only mode In USB2 only mode, the Type-C PHY will be held in reset and only the USB2 logic of the USB3 OTG controller and PHY will be used over the USB2 pins on the Type-C connector to support Low, Full and High-speed USB operation. BRANCH=none BUG=chrome-os-partner:56425 TEST=Go to recovery mode, plug a Type-C USB drive containing chrome OS image into both ports in all orientations, check if system can boot from USB. Change-Id: Ic265c0c91c24f63b2f9c3106eb2bb277a589233b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a37ccc5b6019967483eac6b5a360d67bc3326e93 Original-Change-Id: I582f04f84eef447ff0ba691ce60e9461ed31cfad Original-Signed-off-by: Liangfeng Wu <wulf(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/385837 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3399/usb.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/soc/rockchip/rk3399/usb.c b/src/soc/rockchip/rk3399/usb.c index f638a1e..4c731bd 100644 --- a/src/soc/rockchip/rk3399/usb.c +++ b/src/soc/rockchip/rk3399/usb.c @@ -17,6 +17,9 @@ #include <assert.h> #include <console/console.h> #include <delay.h> +#include <soc/clock.h> +#include <soc/grf.h> +#include <soc/soc.h> #include <soc/usb.h> /* SuperSpeed over Type-C is hard. We don't care about speed in firmware: just @@ -86,12 +89,24 @@ static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3) void reset_usb_otg0(void) { + /* Keep whole USB OTG0 controller in reset, then + * configure controller to work in USB 2.0 only mode. */ + write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 5)); + write32(&rk3399_grf->usb3otg0_con1, RK_CLRSETBITS(0xf << 12, 1 << 0)); + write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 5)); + printk(BIOS_DEBUG, "Starting DWC3 reset for USB OTG0\n"); reset_dwc3(rockchip_usb_otg0_dwc3); } void reset_usb_otg1(void) { + /* Keep whole USB OTG1 controller in reset, then + * configure controller to work in USB 2.0 only mode. */ + write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 6)); + write32(&rk3399_grf->usb3otg1_con1, RK_CLRSETBITS(0xf << 12, 1 << 0)); + write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 6)); + printk(BIOS_DEBUG, "Starting DWC3 reset for USB OTG1\n"); reset_dwc3(rockchip_usb_otg1_dwc3); }

1 0

Patch set updated for coreboot: rockchip: rk3399: improve write leveling flow
by Patrick Georgi 06 Oct '16

06 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16716 -gerrit commit 32f533b8f71f9e5c5787d9281602a391f4dc1923 Author: Jianqun Xu <jay.xu(a)rock-chips.com> Date: Sun Sep 11 18:26:42 2016 +0800 rockchip: rk3399: improve write leveling flow To improve sdram 800MHz and 933MHz stability, we need to modify write leveling flow to get the proper write leveling value. BUG=chrome-os-partner:56940 BRANCH=none TEST=Boot from kevin on 933MHz, and do stressapptest Change-Id: I5b24c93d4a57917fb9af7e5e2a95d8423ccbaa7e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d84bf25b3e5de373c7913e6d534a810cb984b3fd Original-Change-Id: I87efddf628c3683fcb85d6875e029cf3cbc482be Original-Signed-off-by: Jianqun Xu <jay.xu(a)rock-chips.com> Original-Signed-off-by: Xing Zheng <zhengxing(a)rock-chips.com> Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/384292 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/sdram_configs.c | 10 +-- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c | 16 ++-- .../sdram-lpddr3-hynix-4GB-666-no-odt.c | 16 ++-- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c | 16 ++-- .../sdram-lpddr3-hynix-4GB-800-no-odt.c | 56 ++++++------ .../gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 56 ++++++------ .../gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 56 ++++++------ src/soc/rockchip/rk3399/sdram.c | 99 ++++++++-------------- 8 files changed, 146 insertions(+), 179 deletions(-) diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 1235eff..2aa05a7 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -50,14 +50,10 @@ static enum dram_speeds get_sdram_index(void) if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) switch (id) { - case 0: - case 1: - case 2: - return dram_200MHz; - case 3: - return dram_666MHz_NO_ODT; - default: + case 4: return dram_800MHz; + default: + return dram_933MHz; } if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c index a9ed180..c877158 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x00800080, /* DENALI_PHY_77_DATA */ - 0x01900001, /* DENALI_PHY_78_DATA */ + 0x00000001, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00000000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0003150, /* DENALI_PHY_84_DATA */ 0x010000c0, /* DENALI_PHY_85_DATA */ 0x00100000, /* DENALI_PHY_86_DATA */ - 0x0c044208, /* DENALI_PHY_87_DATA */ + 0x07044208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x00800080, /* DENALI_PHY_205_DATA */ - 0x01900001, /* DENALI_PHY_206_DATA */ + 0x00000001, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00000000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0003150, /* DENALI_PHY_212_DATA */ 0x010000c0, /* DENALI_PHY_213_DATA */ 0x00100000, /* DENALI_PHY_214_DATA */ - 0x0c044208, /* DENALI_PHY_215_DATA */ + 0x07044208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x00800080, /* DENALI_PHY_333_DATA */ - 0x01900001, /* DENALI_PHY_334_DATA */ + 0x00000001, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00000000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0003150, /* DENALI_PHY_340_DATA */ 0x010000c0, /* DENALI_PHY_341_DATA */ 0x00100000, /* DENALI_PHY_342_DATA */ - 0x0c044208, /* DENALI_PHY_343_DATA */ + 0x07044208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x00800080, /* DENALI_PHY_461_DATA */ - 0x01900001, /* DENALI_PHY_462_DATA */ + 0x00000001, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00000000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0003150, /* DENALI_PHY_468_DATA */ 0x010000c0, /* DENALI_PHY_469_DATA */ 0x00100000, /* DENALI_PHY_470_DATA */ - 0x0c044208, /* DENALI_PHY_471_DATA */ + 0x07044208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c index ad0e30c..f57ac18 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x01c40080, /* DENALI_PHY_77_DATA */ - 0x01900002, /* DENALI_PHY_78_DATA */ + 0x00000002, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x010000c0, /* DENALI_PHY_85_DATA */ 0x00100000, /* DENALI_PHY_86_DATA */ - 0x0c054208, /* DENALI_PHY_87_DATA */ + 0x07054208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x01c40080, /* DENALI_PHY_205_DATA */ - 0x01900002, /* DENALI_PHY_206_DATA */ + 0x00000002, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x010000c0, /* DENALI_PHY_213_DATA */ 0x00100000, /* DENALI_PHY_214_DATA */ - 0x0c054208, /* DENALI_PHY_215_DATA */ + 0x07054208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x01c40080, /* DENALI_PHY_333_DATA */ - 0x01900002, /* DENALI_PHY_334_DATA */ + 0x00000002, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x010000c0, /* DENALI_PHY_341_DATA */ 0x00100000, /* DENALI_PHY_342_DATA */ - 0x0c054208, /* DENALI_PHY_343_DATA */ + 0x07054208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x01c40080, /* DENALI_PHY_461_DATA */ - 0x01900002, /* DENALI_PHY_462_DATA */ + 0x00000002, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x010000c0, /* DENALI_PHY_469_DATA */ 0x00100000, /* DENALI_PHY_470_DATA */ - 0x0c054208, /* DENALI_PHY_471_DATA */ + 0x07054208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c index 7543e10..591924d 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x01c40080, /* DENALI_PHY_77_DATA */ - 0x01900002, /* DENALI_PHY_78_DATA */ + 0x00000002, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x010000c0, /* DENALI_PHY_85_DATA */ 0x00100000, /* DENALI_PHY_86_DATA */ - 0x0c054208, /* DENALI_PHY_87_DATA */ + 0x07054208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x01c40080, /* DENALI_PHY_205_DATA */ - 0x01900002, /* DENALI_PHY_206_DATA */ + 0x00000002, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x010000c0, /* DENALI_PHY_213_DATA */ 0x00100000, /* DENALI_PHY_214_DATA */ - 0x0c054208, /* DENALI_PHY_215_DATA */ + 0x07054208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x01c40080, /* DENALI_PHY_333_DATA */ - 0x01900002, /* DENALI_PHY_334_DATA */ + 0x00000002, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x010000c0, /* DENALI_PHY_341_DATA */ 0x00100000, /* DENALI_PHY_342_DATA */ - 0x0c054208, /* DENALI_PHY_343_DATA */ + 0x07054208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x01c40080, /* DENALI_PHY_461_DATA */ - 0x01900002, /* DENALI_PHY_462_DATA */ + 0x00000002, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x010000c0, /* DENALI_PHY_469_DATA */ 0x00100000, /* DENALI_PHY_470_DATA */ - 0x0c054208, /* DENALI_PHY_471_DATA */ + 0x07054208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c index fde24c7..21f7044 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c @@ -660,11 +660,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_56_DATA */ 0x00000000, /* DENALI_PHY_57_DATA */ 0x00000000, /* DENALI_PHY_58_DATA */ - 0x02800280, /* DENALI_PHY_59_DATA */ - 0x02800280, /* DENALI_PHY_60_DATA */ - 0x02800280, /* DENALI_PHY_61_DATA */ - 0x02800280, /* DENALI_PHY_62_DATA */ - 0x00000280, /* DENALI_PHY_63_DATA */ + 0x02700270, /* DENALI_PHY_59_DATA */ + 0x02700270, /* DENALI_PHY_60_DATA */ + 0x02700270, /* DENALI_PHY_61_DATA */ + 0x02700270, /* DENALI_PHY_62_DATA */ + 0x00000270, /* DENALI_PHY_63_DATA */ 0x00000000, /* DENALI_PHY_64_DATA */ 0x00000000, /* DENALI_PHY_65_DATA */ 0x00000000, /* DENALI_PHY_66_DATA */ @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x00b30080, /* DENALI_PHY_77_DATA */ - 0x01900003, /* DENALI_PHY_78_DATA */ + 0x00000003, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x020000c0, /* DENALI_PHY_85_DATA */ 0x00100001, /* DENALI_PHY_86_DATA */ - 0x0c054208, /* DENALI_PHY_87_DATA */ + 0x07054208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -788,11 +788,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_184_DATA */ 0x00000000, /* DENALI_PHY_185_DATA */ 0x00000000, /* DENALI_PHY_186_DATA */ - 0x02800280, /* DENALI_PHY_187_DATA */ - 0x02800280, /* DENALI_PHY_188_DATA */ - 0x02800280, /* DENALI_PHY_189_DATA */ - 0x02800280, /* DENALI_PHY_190_DATA */ - 0x00000280, /* DENALI_PHY_191_DATA */ + 0x02700270, /* DENALI_PHY_187_DATA */ + 0x02700270, /* DENALI_PHY_188_DATA */ + 0x02700270, /* DENALI_PHY_189_DATA */ + 0x02700270, /* DENALI_PHY_190_DATA */ + 0x00000270, /* DENALI_PHY_191_DATA */ 0x00000000, /* DENALI_PHY_192_DATA */ 0x00000000, /* DENALI_PHY_193_DATA */ 0x00000000, /* DENALI_PHY_194_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x00b30080, /* DENALI_PHY_205_DATA */ - 0x01900003, /* DENALI_PHY_206_DATA */ + 0x00000003, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x020000c0, /* DENALI_PHY_213_DATA */ 0x00100001, /* DENALI_PHY_214_DATA */ - 0x0c054208, /* DENALI_PHY_215_DATA */ + 0x07054208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -916,11 +916,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_312_DATA */ 0x00000000, /* DENALI_PHY_313_DATA */ 0x00000000, /* DENALI_PHY_314_DATA */ - 0x02800280, /* DENALI_PHY_315_DATA */ - 0x02800280, /* DENALI_PHY_316_DATA */ - 0x02800280, /* DENALI_PHY_317_DATA */ - 0x02800280, /* DENALI_PHY_318_DATA */ - 0x00000280, /* DENALI_PHY_319_DATA */ + 0x02700270, /* DENALI_PHY_315_DATA */ + 0x02700270, /* DENALI_PHY_316_DATA */ + 0x02700270, /* DENALI_PHY_317_DATA */ + 0x02700270, /* DENALI_PHY_318_DATA */ + 0x00000270, /* DENALI_PHY_319_DATA */ 0x00000000, /* DENALI_PHY_320_DATA */ 0x00000000, /* DENALI_PHY_321_DATA */ 0x00000000, /* DENALI_PHY_322_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x00b30080, /* DENALI_PHY_333_DATA */ - 0x01900003, /* DENALI_PHY_334_DATA */ + 0x00000003, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x020000c0, /* DENALI_PHY_341_DATA */ 0x00100001, /* DENALI_PHY_342_DATA */ - 0x0c054208, /* DENALI_PHY_343_DATA */ + 0x07054208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1044,11 +1044,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_440_DATA */ 0x00000000, /* DENALI_PHY_441_DATA */ 0x00000000, /* DENALI_PHY_442_DATA */ - 0x02800280, /* DENALI_PHY_443_DATA */ - 0x02800280, /* DENALI_PHY_444_DATA */ - 0x02800280, /* DENALI_PHY_445_DATA */ - 0x02800280, /* DENALI_PHY_446_DATA */ - 0x00000280, /* DENALI_PHY_447_DATA */ + 0x02700270, /* DENALI_PHY_443_DATA */ + 0x02700270, /* DENALI_PHY_444_DATA */ + 0x02700270, /* DENALI_PHY_445_DATA */ + 0x02700270, /* DENALI_PHY_446_DATA */ + 0x00000270, /* DENALI_PHY_447_DATA */ 0x00000000, /* DENALI_PHY_448_DATA */ 0x00000000, /* DENALI_PHY_449_DATA */ 0x00000000, /* DENALI_PHY_450_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x00b30080, /* DENALI_PHY_461_DATA */ - 0x01900003, /* DENALI_PHY_462_DATA */ + 0x00000003, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x020000c0, /* DENALI_PHY_469_DATA */ 0x00100001, /* DENALI_PHY_470_DATA */ - 0x0c054208, /* DENALI_PHY_471_DATA */ + 0x07054208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index 1544bd0..b738644 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -660,11 +660,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_56_DATA */ 0x00000000, /* DENALI_PHY_57_DATA */ 0x00000000, /* DENALI_PHY_58_DATA */ - 0x02600260, /* DENALI_PHY_59_DATA */ - 0x02600260, /* DENALI_PHY_60_DATA */ - 0x02600260, /* DENALI_PHY_61_DATA */ - 0x02600260, /* DENALI_PHY_62_DATA */ - 0x00000260, /* DENALI_PHY_63_DATA */ + 0x02700270, /* DENALI_PHY_59_DATA */ + 0x02700270, /* DENALI_PHY_60_DATA */ + 0x02700270, /* DENALI_PHY_61_DATA */ + 0x02700270, /* DENALI_PHY_62_DATA */ + 0x00000270, /* DENALI_PHY_63_DATA */ 0x00000000, /* DENALI_PHY_64_DATA */ 0x00000000, /* DENALI_PHY_65_DATA */ 0x00000000, /* DENALI_PHY_66_DATA */ @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x00b30080, /* DENALI_PHY_77_DATA */ - 0x01900003, /* DENALI_PHY_78_DATA */ + 0x00000003, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x020000c0, /* DENALI_PHY_85_DATA */ 0x00100001, /* DENALI_PHY_86_DATA */ - 0x0c054208, /* DENALI_PHY_87_DATA */ + 0x07054208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -788,11 +788,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_184_DATA */ 0x00000000, /* DENALI_PHY_185_DATA */ 0x00000000, /* DENALI_PHY_186_DATA */ - 0x02600260, /* DENALI_PHY_187_DATA */ - 0x02600260, /* DENALI_PHY_188_DATA */ - 0x02600260, /* DENALI_PHY_189_DATA */ - 0x02600260, /* DENALI_PHY_190_DATA */ - 0x00000260, /* DENALI_PHY_191_DATA */ + 0x02700270, /* DENALI_PHY_187_DATA */ + 0x02700270, /* DENALI_PHY_188_DATA */ + 0x02700270, /* DENALI_PHY_189_DATA */ + 0x02700270, /* DENALI_PHY_190_DATA */ + 0x00000270, /* DENALI_PHY_191_DATA */ 0x00000000, /* DENALI_PHY_192_DATA */ 0x00000000, /* DENALI_PHY_193_DATA */ 0x00000000, /* DENALI_PHY_194_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x00b30080, /* DENALI_PHY_205_DATA */ - 0x01900003, /* DENALI_PHY_206_DATA */ + 0x00000003, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x020000c0, /* DENALI_PHY_213_DATA */ 0x00100001, /* DENALI_PHY_214_DATA */ - 0x0c054208, /* DENALI_PHY_215_DATA */ + 0x07054208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -916,11 +916,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_312_DATA */ 0x00000000, /* DENALI_PHY_313_DATA */ 0x00000000, /* DENALI_PHY_314_DATA */ - 0x02600260, /* DENALI_PHY_315_DATA */ - 0x02600260, /* DENALI_PHY_316_DATA */ - 0x02600260, /* DENALI_PHY_317_DATA */ - 0x02600260, /* DENALI_PHY_318_DATA */ - 0x00000260, /* DENALI_PHY_319_DATA */ + 0x02700270, /* DENALI_PHY_315_DATA */ + 0x02700270, /* DENALI_PHY_316_DATA */ + 0x02700270, /* DENALI_PHY_317_DATA */ + 0x02700270, /* DENALI_PHY_318_DATA */ + 0x00000270, /* DENALI_PHY_319_DATA */ 0x00000000, /* DENALI_PHY_320_DATA */ 0x00000000, /* DENALI_PHY_321_DATA */ 0x00000000, /* DENALI_PHY_322_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x00b30080, /* DENALI_PHY_333_DATA */ - 0x01900003, /* DENALI_PHY_334_DATA */ + 0x00000003, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x020000c0, /* DENALI_PHY_341_DATA */ 0x00100001, /* DENALI_PHY_342_DATA */ - 0x0c054208, /* DENALI_PHY_343_DATA */ + 0x07054208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1044,11 +1044,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_440_DATA */ 0x00000000, /* DENALI_PHY_441_DATA */ 0x00000000, /* DENALI_PHY_442_DATA */ - 0x02600260, /* DENALI_PHY_443_DATA */ - 0x02600260, /* DENALI_PHY_444_DATA */ - 0x02600260, /* DENALI_PHY_445_DATA */ - 0x02600260, /* DENALI_PHY_446_DATA */ - 0x00000260, /* DENALI_PHY_447_DATA */ + 0x02700270, /* DENALI_PHY_443_DATA */ + 0x02700270, /* DENALI_PHY_444_DATA */ + 0x02700270, /* DENALI_PHY_445_DATA */ + 0x02700270, /* DENALI_PHY_446_DATA */ + 0x00000270, /* DENALI_PHY_447_DATA */ 0x00000000, /* DENALI_PHY_448_DATA */ 0x00000000, /* DENALI_PHY_449_DATA */ 0x00000000, /* DENALI_PHY_450_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x00b30080, /* DENALI_PHY_461_DATA */ - 0x01900003, /* DENALI_PHY_462_DATA */ + 0x00000003, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x020000c0, /* DENALI_PHY_469_DATA */ 0x00100001, /* DENALI_PHY_470_DATA */ - 0x0c054208, /* DENALI_PHY_471_DATA */ + 0x07054208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index a4d2007..362489b 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -660,11 +660,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_56_DATA */ 0x00000000, /* DENALI_PHY_57_DATA */ 0x00000000, /* DENALI_PHY_58_DATA */ - 0x02600260, /* DENALI_PHY_59_DATA */ - 0x02600260, /* DENALI_PHY_60_DATA */ - 0x02600260, /* DENALI_PHY_61_DATA */ - 0x02600260, /* DENALI_PHY_62_DATA */ - 0x00000260, /* DENALI_PHY_63_DATA */ + 0x02700270, /* DENALI_PHY_59_DATA */ + 0x02700270, /* DENALI_PHY_60_DATA */ + 0x02700270, /* DENALI_PHY_61_DATA */ + 0x02700270, /* DENALI_PHY_62_DATA */ + 0x00000270, /* DENALI_PHY_63_DATA */ 0x00000000, /* DENALI_PHY_64_DATA */ 0x00000000, /* DENALI_PHY_65_DATA */ 0x00000000, /* DENALI_PHY_66_DATA */ @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x01a20080, /* DENALI_PHY_77_DATA */ - 0x01900003, /* DENALI_PHY_78_DATA */ + 0x00000003, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00030000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x020000c0, /* DENALI_PHY_85_DATA */ 0x00100001, /* DENALI_PHY_86_DATA */ - 0x0c064208, /* DENALI_PHY_87_DATA */ + 0x07064208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -788,11 +788,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_184_DATA */ 0x00000000, /* DENALI_PHY_185_DATA */ 0x00000000, /* DENALI_PHY_186_DATA */ - 0x02600260, /* DENALI_PHY_187_DATA */ - 0x02600260, /* DENALI_PHY_188_DATA */ - 0x02600260, /* DENALI_PHY_189_DATA */ - 0x02600260, /* DENALI_PHY_190_DATA */ - 0x00000260, /* DENALI_PHY_191_DATA */ + 0x02700270, /* DENALI_PHY_187_DATA */ + 0x02700270, /* DENALI_PHY_188_DATA */ + 0x02700270, /* DENALI_PHY_189_DATA */ + 0x02700270, /* DENALI_PHY_190_DATA */ + 0x00000270, /* DENALI_PHY_191_DATA */ 0x00000000, /* DENALI_PHY_192_DATA */ 0x00000000, /* DENALI_PHY_193_DATA */ 0x00000000, /* DENALI_PHY_194_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x01a20080, /* DENALI_PHY_205_DATA */ - 0x01900003, /* DENALI_PHY_206_DATA */ + 0x00000003, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00030000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x020000c0, /* DENALI_PHY_213_DATA */ 0x00100001, /* DENALI_PHY_214_DATA */ - 0x0c064208, /* DENALI_PHY_215_DATA */ + 0x07064208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -916,11 +916,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_312_DATA */ 0x00000000, /* DENALI_PHY_313_DATA */ 0x00000000, /* DENALI_PHY_314_DATA */ - 0x02600260, /* DENALI_PHY_315_DATA */ - 0x02600260, /* DENALI_PHY_316_DATA */ - 0x02600260, /* DENALI_PHY_317_DATA */ - 0x02600260, /* DENALI_PHY_318_DATA */ - 0x00000260, /* DENALI_PHY_319_DATA */ + 0x02700270, /* DENALI_PHY_315_DATA */ + 0x02700270, /* DENALI_PHY_316_DATA */ + 0x02700270, /* DENALI_PHY_317_DATA */ + 0x02700270, /* DENALI_PHY_318_DATA */ + 0x00000270, /* DENALI_PHY_319_DATA */ 0x00000000, /* DENALI_PHY_320_DATA */ 0x00000000, /* DENALI_PHY_321_DATA */ 0x00000000, /* DENALI_PHY_322_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x01a20080, /* DENALI_PHY_333_DATA */ - 0x01900003, /* DENALI_PHY_334_DATA */ + 0x00000003, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00030000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x020000c0, /* DENALI_PHY_341_DATA */ 0x00100001, /* DENALI_PHY_342_DATA */ - 0x0c064208, /* DENALI_PHY_343_DATA */ + 0x07064208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1044,11 +1044,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_440_DATA */ 0x00000000, /* DENALI_PHY_441_DATA */ 0x00000000, /* DENALI_PHY_442_DATA */ - 0x02600260, /* DENALI_PHY_443_DATA */ - 0x02600260, /* DENALI_PHY_444_DATA */ - 0x02600260, /* DENALI_PHY_445_DATA */ - 0x02600260, /* DENALI_PHY_446_DATA */ - 0x00000260, /* DENALI_PHY_447_DATA */ + 0x02700270, /* DENALI_PHY_443_DATA */ + 0x02700270, /* DENALI_PHY_444_DATA */ + 0x02700270, /* DENALI_PHY_445_DATA */ + 0x02700270, /* DENALI_PHY_446_DATA */ + 0x00000270, /* DENALI_PHY_447_DATA */ 0x00000000, /* DENALI_PHY_448_DATA */ 0x00000000, /* DENALI_PHY_449_DATA */ 0x00000000, /* DENALI_PHY_450_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x01a20080, /* DENALI_PHY_461_DATA */ - 0x01900003, /* DENALI_PHY_462_DATA */ + 0x00000003, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00030000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x020000c0, /* DENALI_PHY_469_DATA */ 0x00100001, /* DENALI_PHY_470_DATA */ - 0x0c064208, /* DENALI_PHY_471_DATA */ + 0x07064208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 9aa2952..9211895 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -580,10 +580,9 @@ static void check_write_leveling_value(u32 channel, const struct rk3399_sdram_params *sdram_params) { - u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; + u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl; u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; - u32 i, tmp; - u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; + u32 i, j; u32 wl_value[2][4]; u32 rank = sdram_params->ch[channel].rank; @@ -602,71 +601,43 @@ static void check_write_leveling_value(u32 channel, wl_value[i][3] = (read32(&denali_phy[447]) >> 16) & 0x3ff; } - for (i = 0; i < 4; i++) { - if (((wl_value[0][i] > 0x1E0) || (wl_value[0][i] < 0x20)) && - ((wl_value[1][i] > 0x1E0) || (wl_value[1][i] < 0x20))) { - switch (i) { - case 0: - setbits_le32(&denali_phy[79], 0x1 << 16); - break; - case 1: - setbits_le32(&denali_phy[207], 0x1 << 16); - break; - case 2: - setbits_le32(&denali_phy[335], 0x1 << 16); - break; - case 3: - setbits_le32(&denali_phy[463], 0x1 << 16); - break; - default: - break; - } - } - } + /* + * PHY_8/136/264/392 + * phy_per_cs_training_multicast_en_X 1bit offset_16 + */ + clrsetbits_le32(&denali_phy[8], 0x1 << 16, 0 << 16); + clrsetbits_le32(&denali_phy[136], 0x1 << 16, 0 << 16); + clrsetbits_le32(&denali_phy[264], 0x1 << 16, 0 << 16); + clrsetbits_le32(&denali_phy[392], 0x1 << 16, 0 << 16); for (i = 0; i < rank; i++) { - - /* FIXME: denali_phy[463] value wrong if miss this delay */ - udelay(100); - - /* PI_60 PI_WRLVL_EN:RW:8:2 */ - clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); - /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ - clrsetbits_le32(&denali_pi[59], (0x1 << 8) | (0x3 << 16), - (0x1 << 8) | (i << 16)); - - select_per_cs_training_index(channel, i); - while (1) { - /* PI_174 PI_INT_STATUS:RD:8:25 */ - tmp = read32(&denali_pi[174]) >> 8; - - /* - * check status obs, - * if error maybe can not get leveling done - * PHY_40/168/296/424 phy_wrlvl_status_obs_X:0:13 - */ - obs_0 = read32(&denali_phy[40]); - obs_1 = read32(&denali_phy[168]); - obs_2 = read32(&denali_phy[296]); - obs_3 = read32(&denali_phy[424]); - if (((obs_0 >> 12) & 0x1) || - ((obs_1 >> 12) & 0x1) || - ((obs_2 >> 12) & 0x1) || - ((obs_3 >> 12) & 0x1)) - obs_err = 1; - if ((((tmp >> 10) & 0x1) == 0x1) && - (((tmp >> 13) & 0x1) == 0x1) && - (((tmp >> 4) & 0x1) == 0x0) && - (obs_err == 0)) - break; - else if ((((tmp >> 4) & 0x1) == 0x1) || - (obs_err == 1)) - printk(BIOS_DEBUG, - "check_write_leveling_value error!!!\n"); + clrsetbits_le32(&denali_phy[8], 0x1 << 24, i << 24); + clrsetbits_le32(&denali_phy[136], 0x1 << 24, i << 24); + clrsetbits_le32(&denali_phy[264], 0x1 << 24, i << 24); + clrsetbits_le32(&denali_phy[392], 0x1 << 24, i << 24); + for (j = 0; j < 4; j++) { + if (wl_value[i][j] < 0x80) + clrsetbits_le32(&denali_phy[63+j*128], + 0x3ff << 16, + (wl_value[i][j]+0x200) << 16); + else if ((wl_value[i][j] >= 0x80) && + (wl_value[i][j] < 0x100)) + clrsetbits_le32(&denali_phy[78+j*128], + 0x7 << 8, 0x1 << 8); } - /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - write32((&denali_pi[175]), 0x00003f7c); } + + /* CTL_200 ctrlupd_req 1bit offset_8 */ + clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); + + /* + * PHY_8/136/264/392 + * phy_per_cs_training_multicast_en_X 1bit offset_16 + */ + clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); } static int data_training(u32 channel,

1 0

Patch set updated for coreboot: rockchip: rk3399: improve sdram noc timing
by Patrick Georgi 06 Oct '16

06 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16713 -gerrit commit 2745c3fba7db1f835da98f0eff47004d69f0775b Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Sep 8 10:21:57 2016 -0700 rockchip: rk3399: improve sdram noc timing sdram noc timing will affect ddr latency, this patch improves rk3399 sdram noc timing so improve memory performance. BRANCH=gru BUG=chrome-os-partner:57248 TEST=Boot from kevin board Change-Id: I09e984490a7ad747ef8abfc6542d0e2c95ec19bc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 43dfe55d713d371e39d21312772fd353614b7642 Original-Change-Id: I393e74ecdeb72930ac38ae9bcf311e5654f65162 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/382725 Original-Reviewed-by: Sonny Rao <sonnyrao(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Sonny Rao <sonnyrao(a)chromium.org> Original-Commit-Queue: Sonny Rao <sonnyrao(a)chromium.org> --- .../google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c | 8 ++++---- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c | 12 ++++++------ .../google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c | 12 ++++++------ .../gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c | 8 ++++---- .../google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 8 ++++---- .../google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 16 ++++++++-------- 6 files changed, 32 insertions(+), 32 deletions(-) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c index dda6d98..a9ed180 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x0e080807}, + {0x80080807}, {0x05010605}, {0x00000002}, {0x00006076}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x0e080807}, + {0x80080807}, {0x05010605}, {0x00000002}, {0x00006076}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c index 9b0bfe7..ad0e30c 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x19151115}, - {0x10030806}, + {0x80151115}, + {0x11030806}, {0x00000002}, {0x00006206}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x19151115}, - {0x10030806}, + {0x80151115}, + {0x11030806}, {0x00000002}, {0x00006206}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c index d5d6761..7543e10 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x19151115}, - {0x10030806}, + {0x80151115}, + {0x11030806}, {0x00000002}, {0x00006206}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x19151115}, - {0x10030806}, + {0x80151115}, + {0x11030806}, {0x00000002}, {0x00006206}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c index 866759b..fde24c7 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, + {0x80191519}, {0x14040808}, {0x00000002}, {0x00006226}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, + {0x80191519}, {0x14040808}, {0x00000002}, {0x00006226}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index 034e9d8..1544bd0 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, + {0x80191519}, {0x14040808}, {0x00000002}, {0x00006226}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, + {0x80191519}, {0x14040808}, {0x00000002}, {0x00006226}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index 2ef9d0c..a4d2007 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, - {0x14040808}, + {0x801d181e}, + {0x17050a08}, {0x00000002}, - {0x00006226}, - {0x00000054}, + {0x00006426}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, - {0x14040808}, + {0x801d181e}, + {0x17050a08}, {0x00000002}, - {0x00006226}, - {0x00000054}, + {0x00006426}, + {0x0000004c}, 0x00000000 } }

1 0

New patch to review for coreboot: mainboard/ti/beaglebone: set DRIVERS_INTEL_WIFI to "n"
by Antonello Dettori 06 Oct '16

06 Oct '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16905 -gerrit commit 4c0166d3d8ae7364c258a8669850c4243dd74a86 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Oct 1 12:23:26 2016 +0200 mainboard/ti/beaglebone: set DRIVERS_INTEL_WIFI to "n" Set DRIVERS_INTEL_WIFI to "n" since it is not needed and causes the build process to fail. Change-Id: I2ae013b85990e6bca8578ce297e8784811bf5848 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/ti/beaglebone/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index a85c242..1ae9c8d 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -44,4 +44,8 @@ config UART_FOR_CONSOLE int default 0 +config DRIVERS_INTEL_WIFI + bool + default n + endif # BOARD_TI_BEAGLEBONE

1 0

New patch to review for coreboot: mainboard/cubitech/cubieboard: set DRIVERS_INTEL_WIFI to "n"
by Antonello Dettori 06 Oct '16

06 Oct '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16904 -gerrit commit 7f8ef74476541950598e333d0cf44aca1c7f0155 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Oct 1 12:23:26 2016 +0200 mainboard/cubitech/cubieboard: set DRIVERS_INTEL_WIFI to "n" Set DRIVERS_INTEL_WIFI to "n" since it is not needed and causes the build process to fail. Change-Id: Ic62e5ca760f6642d3d7e603f3911b7d2a55ce3a9 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/cubietech/cubieboard/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/cubietech/cubieboard/Kconfig b/src/mainboard/cubietech/cubieboard/Kconfig index 5aefc22..d3b1802 100644 --- a/src/mainboard/cubietech/cubieboard/Kconfig +++ b/src/mainboard/cubietech/cubieboard/Kconfig @@ -26,4 +26,8 @@ config UART_FOR_CONSOLE int default 0 +config DRIVERS_INTEL_WIFI + bool + default n + endif # BOARD_CUBIETECH_CUBIEBOARD

1 0

Patch set updated for coreboot: google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration
by Patrick Georgi 06 Oct '16

06 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16699 -gerrit commit 0124b1119df145ba32b16bd62e19efdc719283e9 Author: Jeffy Chen <jeffy.chen(a)rock-chips.com> Date: Fri Sep 2 18:16:33 2016 +0800 google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto. BUG=chrome-os-partner:56759 BRANCH=none TEST=Build Change-Id: I698fe450d48b64a06232aa44ecf91d688d9dc17a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d3edecdb135939c3264ab1b831e7821d3a3e0149 Original-Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531 Original-Signed-off-by: Jeffy Chen <jeffy.chen(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380443 Original-Commit-Ready: Alexandru Stan <amstan(a)chromium.org> Original-Tested-by: Alexandru Stan <amstan(a)chromium.org> Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org> Original-Reviewed-by: Jonathan Dixon <joth(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_rialto/sdram_configs.c | 2 +- .../sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc | 90 ++++++++++++++++++++++ 2 files changed, 91 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c index 42fa582..0e260c3 100644 --- a/src/mainboard/google/veyron_rialto/sdram_configs.c +++ b/src/mainboard/google/veyron_rialto/sdram_configs.c @@ -22,7 +22,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc" /* ram_code = 0000 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */ +#include "sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc"/* ram_code = 0001 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */ diff --git a/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc new file mode 100644 index 0000000..cf13fcb --- /dev/null +++ b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + { + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x0, + .col = 0x0, + .bk = 0x0, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x0, + .cs1_row = 0x0 + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 1, + .stride = 22, + .odt = 0 +},

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Patch set updated for coreboot: i2c/ww_ring: Change LED configuration for Gale EVT3
by Patrick Georgi 06 Oct '16

06 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16697 -gerrit commit 25088b5014c28a165a7f108eca82fdb3b5145048 Author: Suresh Rajashekara <sureshraj(a)google.com> Date: Mon Aug 15 16:18:11 2016 -0700 i2c/ww_ring: Change LED configuration for Gale EVT3 Gale EVT3 has only one LED controller (earlier we had 2). Remove the support for the second controller and also the corresponding microcode. The color values used are the same as onHub (Arkham to be specific). BUG=b:30890905 TEST=Move the device to different states manually by appropriate actions (like dev mode, rec mode etc) and observe the different colors. BRANCH=None Change-Id: I853035610ea7ea7c8d29c30d2de13c9e2e786b2b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 593905d2d69daa7482318aa5f5c5cd7cf984043e Original-Change-Id: If8f22abd605faac6f6215ef600041740ce15ea0c Original-Signed-off-by: Suresh Rajashekara <sureshraj(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/370821 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Kan Yan <kyan(a)google.com> --- src/drivers/i2c/ww_ring/ww_ring_programs.c | 232 ++++++----------------------- src/drivers/i2c/ww_ring/ww_ring_programs.h | 2 +- 2 files changed, 49 insertions(+), 185 deletions(-) diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index a35998c..5b0c8a8 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -46,36 +46,36 @@ * Solid LED display, the arguments of the set_pwm commands set intensity and * color of the display: -row_red: dw 0000000001001001b -row_green: dw 0000000010010010b -row_blue: dw 0000000100100100b +row_red: dw 0000000000000001b +row_green: dw 0000000000000010b +row_blue: dw 0000000000000100b .segment program1 mux_map_addr row_red - set_pwm 1 + set_pwm 0 end .segment program2 mux_map_addr row_green - set_pwm 1 + set_pwm 0 end .segment program3 mux_map_addr row_blue - set_pwm 1 + set_pwm 0 end */ /* RGB set to 000000, resulting in all LEDs off. */ static const uint8_t solid_000000_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9F, 0x80, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9F, 0x80, 0x40, 0, 0xC0, 0x00, 0x9F, 0x81, 0x40, 0, 0xC0, 0x00, 0x9F, 0x82, 0x40, 0, 0xC0, 0x00 }; /* Rgb set to 128, resulting in a brightish white color. */ static const uint8_t solid_808080_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9F, 0x80, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9F, 0x80, 0x40, 128, 0xC0, 0x00, 0x9F, 0x81, 0x40, 128, 0xC0, 0x00, 0x9F, 0x82, 0x40, 128, 0xC0, 0x00 }; @@ -100,20 +100,10 @@ static const TiLp55231Program solid_000000_program = { * The three internal engines seem to be competing for resources and get out * of sync in seconds if left running asynchronously. * - * When there are two separate controllers, with three engine each, they all - * run away from each other in no time, resulting in some completely chaotic - * LED behavior. - * * When solid patterns are deployed with instanteneous color intensity * changes, all three LEDs can be controlled by one engine in sequential * accesses. But the controllers still neeed to be synchronized. * - * The first controller is loaded and started first, but it sits waiting for - * the trigger from the second controller to actually start the cycle. Once - * both controllers start running, the first controller is the master, sending - * sych triggers to the second one each time the LED is supposed to be turned - * on or off. - * * The maximum timer duration of lp55231 is .48 seconds. To achieve longer * blinking intervals the loops delays are deployed. Only the first controller * intervals need to be changed, as the second one is in lockstep with the @@ -126,29 +116,26 @@ static const TiLp55231Program solid_000000_program = { */ /* * blink_solid1.src -row_red: dw 0000000001001001b -row_green: dw 0000000010010010b -row_blue: dw 0000000100100100b +row_red: dw 0000000000000001b +row_green: dw 0000000000000010b +row_blue: dw 0000000000000100b .segment program1 ld ra, 2 # LED on duration - ld rb, 10 # LED off duration + ld rb, 2 # LED off duration mux_map_addr row_red - trigger w{e} loop: - trigger s{e} - ld rc, 98 ; red intensity + ld rc, 180 ; red intensity set_pwm rc mux_map_addr row_green - ld rc, 0 ; green intensity + ld rc, 80 ; green intensity set_pwm rc mux_map_addr row_blue - ld rc, 234 ; blue intensity + ld rc, 0 ; blue intensity set_pwm rc wait1: wait 0.1 branch ra, wait1 - trigger s{e} set_pwm 0 mux_map_addr row_green set_pwm 0 @@ -158,203 +145,82 @@ wait2: wait 0.1 branch rb, wait2 branch 0, loop - -.segment program2 - end - -.segment program3 - end*/ -/* - * blink_solid2.src - -row_red: dw 0000000001001001b -row_green: dw 0000000010010010b -row_blue: dw 0000000100100100b - -.segment program1 - ld ra, 98 - ld rb, 0 - ld rc, 234 - trigger s{e} - mux_map_addr row_red -loop: - trigger w{e} - set_pwm ra ; red intensity - mux_map_addr row_green - set_pwm rb ; green intensity - mux_map_addr row_blue - set_pwm rc ; blue intensity -wait1: - wait 0.1 - branch 1, wait1 - trigger w{e} - set_pwm 0 - mux_map_addr row_green - set_pwm 0 - mux_map_addr row_red - set_pwm 0 -wait2: - wait 0.1 - branch 1, wait2 - branch 0, loop - .segment program2 end - .segment program3 end */ static const uint8_t blink_wipeout1_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 0x02, - 0x94, 0x02, 0x9f, 0x80, 0xf0, 0x00, 0xe0, 0x40, - 0x98, 255, 0x84, 0x62, 0x9f, 0x81, 0x98, 80, - 0x84, 0x62, 0x9f, 0x82, 0x98, 0, 0x84, 0x62, - 0x4c, 0x00, 0x86, 0x34, 0xe0, 0x40, 0x40, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, 0x40, 0x00, - 0x4c, 0x00, 0x86, 0x55, 0xa0, 0x04, 0xc0, 0x00, - 0xc0, 0x00, 0x00, -}; - -static const uint8_t blink_wipeout2_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 255, - 0x94, 80, 0x98, 0, 0xe0, 0x40, 0x9f, 0x80, - 0xf0, 0x00, 0x84, 0x60, 0x9f, 0x81, 0x84, 0x61, - 0x9f, 0x82, 0x84, 0x62, 0x4c, 0x00, 0xa0, 0x8b, - 0xf0, 0x00, 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, - 0x9f, 0x80, 0x40, 0x00, 0x4c, 0x00, 0xa0, 0x93, - 0xa0, 0x05, 0xc0, 0x00, 0xc0, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x90, 0x02, + 0x94, 0x02, 0x9f, 0x80, 0x98, 180, 0x84, 0x62, + 0x9f, 0x81, 0x98, 80, 0x84, 0x62, 0x9f, 0x82, + 0x98, 0, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, + 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, + 0x40, 0x00, 0x4c, 0x00, 0x86, 0x49, 0xa0, 0x03, + 0xc0, 0x00, 0xc0, 0x00, 0x00, }; static const TiLp55231Program blink_wipeout1_program = { blink_wipeout1_text, sizeof(blink_wipeout1_text), 0, - { 3, 27, 28, } -}; -static const TiLp55231Program blink_wipeout2_program = { - blink_wipeout2_text, - sizeof(blink_wipeout2_text), - 0, - { 3, 26, 26, } + { 3, 24, 25, } }; static const uint8_t blink_recovery1_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 0x02, - 0x94, 0x02, 0x9f, 0x80, 0xf0, 0x00, 0xe0, 0x40, - 0x98, 255, 0x84, 0x62, 0x9f, 0x81, 0x98, 24, - 0x84, 0x62, 0x9f, 0x82, 0x98, 0, 0x84, 0x62, - 0x4c, 0x00, 0x86, 0x34, 0xe0, 0x40, 0x40, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, 0x40, 0x00, - 0x4c, 0x00, 0x86, 0x55, 0xa0, 0x04, 0xc0, 0x00, - 0xc0, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x90, 0x02, + 0x94, 0x02, 0x9f, 0x80, 0x98, 255, 0x84, 0x62, + 0x9f, 0x81, 0x98, 50, 0x84, 0x62, 0x9f, 0x82, + 0x98, 0, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, + 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, + 0x40, 0x00, 0x4c, 0x00, 0x86, 0x49, 0xa0, 0x03, + 0xc0, 0x00, 0xc0, 0x00, 0x00, }; static const TiLp55231Program blink_recovery1_program = { blink_recovery1_text, sizeof(blink_recovery1_text), 0, - { 3, 27, 28, } -}; -static const uint8_t blink_recovery2_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 255, - 0x94, 24, 0x98, 0, 0xe0, 0x40, 0x9f, 0x80, - 0xf0, 0x00, 0x84, 0x60, 0x9f, 0x81, 0x84, 0x61, - 0x9f, 0x82, 0x84, 0x62, 0x4c, 0x00, 0xa0, 0x8b, - 0xf0, 0x00, 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, - 0x9f, 0x80, 0x40, 0x00, 0x4c, 0x00, 0xa0, 0x93, - 0xa0, 0x05, 0xc0, 0x00, 0xc0, 0x00, 0x00, -}; -static const TiLp55231Program blink_recovery2_program = { - blink_recovery2_text, - sizeof(blink_recovery2_text), - 0, - { 3, 26, 26, } + { 3, 24, 25, } }; /* * fade_in1.src * - row_red: dw 0000000001001001b - row_green: dw 0000000010010010b - row_blue: dw 0000000100100100b + row_red: dw 0000000000000001b + row_green: dw 0000000000000010b + row_blue: dw 0000000000000100b .segment program1 mux_map_addr row_red - set_pwm 0h - trigger w{e} + set_pwm 1h trigger s{2|3} end - .segment program2 mux_map_addr row_green set_pwm 0h - trigger w{1} - ramp 2, 87 + ramp 2, 50 end - .segment program3 mux_map_addr row_blue set_pwm 0h loop3: trigger w{1} - ramp 2, 155 - end -*/ -/* - * fade_in2.src - * - row_red: dw 0000000001001001b - row_green: dw 0000000010010010b - row_blue: dw 0000000100100100b - - .segment program1 - mux_map_addr row_red - set_pwm 0h - trigger s{e} - trigger s{2|3} - end - - .segment program2 - mux_map_addr row_green - set_pwm 0h - - trigger w{1} - ramp 2, 87 - end - -.segment program3 - mux_map_addr row_blue - set_pwm 0h - loop3: trigger w{1} - ramp 2, 155 + ramp 2, 255 end */ static const uint8_t fade_in1_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9f, 0x80, - 0x40, 0x00, 0xf0, 0x00, 0xe0, 0x0c, 0xc0, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0xe0, 0x80, 0x42, 0x57, - 0xc0, 0x00, 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, - 0x34, 0x9b, 0xc0, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9f, 0x80, + 0x40, 0x01, 0xe0, 0x0c, 0xc0, 0x00, 0x9f, 0x81, + 0x40, 0x00, 0xe0, 0x80, 0x46, 0x32, 0xc0, 0x00, + 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, 0x20, 0xff, + 0xc0, 0x00, 0x00, }; static const TiLp55231Program fade_in1_program = { fade_in1_text, sizeof(fade_in1_text), 0, - { 3, 8, 13, } -}; - -static const uint8_t fade_in2_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9f, 0x80, - 0x40, 0x00, 0xe0, 0x40, 0xe0, 0x0c, 0xc0, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0xe0, 0x80, 0x42, 0x57, - 0xc0, 0x00, 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, - 0x34, 0x9b, 0xc0, 0x00, 0x00, -}; -static const TiLp55231Program fade_in2_program = { - fade_in2_text, - sizeof(fade_in2_text), - 0, - { 3, 8, 13, } + { 3, 7, 12, } }; const WwRingStateProg wwr_state_programs[] = { @@ -362,12 +228,10 @@ const WwRingStateProg wwr_state_programs[] = { * for test purposes the blank screen program is set to blinking, will * be changed soon. */ - {WWR_ALL_OFF, {&solid_000000_program, &solid_000000_program} }, - {WWR_RECOVERY_PUSHED, {&solid_808080_program, &solid_808080_program} }, - {WWR_WIPEOUT_REQUEST, {&blink_wipeout1_program, - &blink_wipeout2_program} }, - {WWR_RECOVERY_REQUEST, {&blink_recovery1_program, - &blink_recovery2_program} }, - {WWR_NORMAL_BOOT, {&fade_in1_program, &fade_in2_program} }, + {WWR_ALL_OFF, {&solid_000000_program} }, + {WWR_RECOVERY_PUSHED, {&solid_808080_program} }, + {WWR_WIPEOUT_REQUEST, {&blink_wipeout1_program} }, + {WWR_RECOVERY_REQUEST, {&blink_recovery1_program} }, + {WWR_NORMAL_BOOT, {&fade_in1_program} }, {}, /* Empty record to mark the end of the table. */ }; diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.h b/src/drivers/i2c/ww_ring/ww_ring_programs.h index 9f4b928..5fb8ebf 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.h +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.h @@ -36,7 +36,7 @@ #define LP55231_NUM_OF_ENGINES 3 /* Number of lp55321 controllers on the ring */ -#define WW_RING_NUM_LED_CONTROLLERS 2 +#define WW_RING_NUM_LED_CONTROLLERS 1 /* * Structure to describe an lp55231 program: pointer to the text of the

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Patch set updated for coreboot: util/release/build-release: Update script
by Martin Roth 06 Oct '16

06 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16883 -gerrit commit bc6bf22d5163e2e5bba74ff8d898702ded384274 Author: Martin Roth <martinroth(a)google.com> Date: Tue Oct 4 16:45:17 2016 -0600 util/release/build-release: Update script - Add more help text. - Remove braces from variables where the variable is isolated. - Remove --recurse-submodules from clone. This breaks on old coreboot versions. - Add some whitespace between blocks. - Fix all shellcheck warnings. - Verify tar version and fail if it doesn't support --sort. Change-Id: I4a49df99532d9a92a4a05bceff16f96a4fc3e205 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/release/build-release | 56 ++++++++++++++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/util/release/build-release b/util/release/build-release index 11e7177..20fbfb6 100755 --- a/util/release/build-release +++ b/util/release/build-release @@ -3,10 +3,10 @@ # ${GPG_KEY_ID}: gpg key id (if not don't sign) # ${USERNAME}: username (if not default to https) # ${COMMIT_ID}: commit id (if not master) -VERSION_NAME=${1} -COMMIT_ID=${2} -USERNAME=${3} -GPG_KEY_ID=${4} +VERSION_NAME=$1 +COMMIT_ID=$2 +USERNAME=$3 +GPG_KEY_ID=$4 set -e @@ -16,32 +16,50 @@ LANG=C TZ=UTC export LC_ALL LANG TZ -if [ -z "${VERSION_NAME}" ] || [ "${VERSION_NAME}" = "--help" ]; then +if [ -z "$VERSION_NAME" ] || [ "$VERSION_NAME" = "--help" ]; then echo "usage: $0 <version> [commit id] [gpg key id] [username]" - echo "tags a new coreboot version and creates a tar archive" + echo "Tags a new coreboot version and creates a tar archive" + echo + echo "version: New version name to tag the tree with" + echo "commit id: check out this commit-id after cloning the coreboot tree" + echo "gpg key id: used to tag the version, and generate a gpg signature" + echo "username: clone the tree using ssh://USERNAME - defaults to https://" exit 1 fi + +# Verify that tar supports --sort +if ! tar --sort=name -cf /dev/null /dev/null 2>/dev/null ; then + echo "Error: The installed version of tar does not support --sort" + echo " GNU tar version 1.28 or greater is required. Exiting." + exit 1 +fi + if [ -n "${USERNAME}" ]; then - git clone --recurse-submodules ssh://${USERNAME}@review.coreboot.org:29418/coreboot.git coreboot-${VERSION_NAME} + git clone "ssh://${USERNAME}@review.coreboot.org:29418/coreboot.git" "coreboot-${VERSION_NAME}" else - git clone --recurse-submodules https://review.coreboot.org/coreboot.git coreboot-${VERSION_NAME} + git clone https://review.coreboot.org/coreboot.git "coreboot-${VERSION_NAME}" fi -cd coreboot-${VERSION_NAME} -if [ -n "${COMMIT_ID}" ]; then - git reset --hard ${COMMIT_ID} + +cd "coreboot-${VERSION_NAME}" || exit 1 +if [ -n "$COMMIT_ID" ]; then + git reset --hard "$COMMIT_ID" fi + git submodule update --init --checkout -if [ -n "${GPG_KEY_ID}" ]; then - git tag -a -s -u ${GPG_KEY_ID} --force ${VERSION_NAME} -m "coreboot version ${VERSION_NAME}" +if [ -n "$GPG_KEY_ID" ]; then + git tag -a -s -u "$GPG_KEY_ID" --force "$VERSION_NAME" -m "coreboot version $VERSION_NAME" else - git tag -a --force ${VERSION_NAME} -m "coreboot version ${VERSION_NAME}" + git tag -a --force "$VERSION_NAME" -m "coreboot version $VERSION_NAME" fi -printf "${VERSION_NAME}-$(git log --pretty=%H|head -1)\n" > .coreboot-version + +printf "%s-%s\n" "$VERSION_NAME" "$(git log --pretty=%H|head -1)" > .coreboot-version tstamp=$(git log --pretty=format:%ci -1) cd .. -tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs --exclude=coreboot-${VERSION_NAME}/3rdparty/blobs -cvf - coreboot-${VERSION_NAME} |xz -9 > coreboot-${VERSION_NAME}.tar.xz -tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs -cvf - coreboot-${VERSION_NAME}/3rdparty/blobs |xz -9 > coreboot-blobs-${VERSION_NAME}.tar.xz + +tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs --exclude="coreboot-${VERSION_NAME}/3rdparty/blobs" -cvf - "coreboot-${VERSION_NAME}" |xz -9 > "coreboot-${VERSION_NAME}.tar.xz" +tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs -cvf - "coreboot-${VERSION_NAME}/3rdparty/blobs" |xz -9 > "coreboot-blobs-${VERSION_NAME}.tar.xz" + if [ -n "${GPG_KEY_ID}" ]; then - gpg2 --armor --local-user ${GPG_KEY_ID} --output coreboot-${VERSION_NAME}.tar.xz.sig --detach-sig coreboot-${VERSION_NAME}.tar.xz - gpg2 --armor --local-user ${GPG_KEY_ID} --output coreboot-blobs-${VERSION_NAME}.tar.xz.sig --detach-sig coreboot-blobs-${VERSION_NAME}.tar.xz + gpg2 --armor --local-user "$GPG_KEY_ID" --output "coreboot-${VERSION_NAME}.tar.xz.sig" --detach-sig "coreboot-${VERSION_NAME}.tar.xz" + gpg2 --armor --local-user "$GPG_KEY_ID" --output "coreboot-blobs-${VERSION_NAME}.tar.xz.sig" --detach-sig "coreboot-blobs-${VERSION_NAME}.tar.xz" fi

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coreboot-gerrit October 2016