coreboot-gerrit October 2016

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New patch to review for coreboot: mainboard/kontron: Use C89 comments style & remove commented code
by HAOUAS Elyes 06 Oct '16

06 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16908 -gerrit commit a7a7e0a060e2123844e702fd2f9e1859daf00650 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Oct 6 19:49:55 2016 +0200 mainboard/kontron: Use C89 comments style & remove commented code Change-Id: I53a0344686921012f4e031842b5108aa4a7b79b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/kontron/986lcd-m/irq_tables.c | 20 +++++----- src/mainboard/kontron/986lcd-m/mainboard.c | 57 ++++++++++++----------------- src/mainboard/kontron/986lcd-m/mptable.c | 10 ++--- src/mainboard/kontron/986lcd-m/romstage.c | 52 ++++++++++++-------------- src/mainboard/kontron/ktqm77/hda_verb.c | 12 +++--- src/mainboard/kontron/ktqm77/mainboard.c | 4 +- src/mainboard/kontron/ktqm77/romstage.c | 14 +++---- 7 files changed, 78 insertions(+), 91 deletions(-) diff --git a/src/mainboard/kontron/986lcd-m/irq_tables.c b/src/mainboard/kontron/986lcd-m/irq_tables.c index 0c5f403..fc67c22 100644 --- a/src/mainboard/kontron/986lcd-m/irq_tables.c +++ b/src/mainboard/kontron/986lcd-m/irq_tables.c @@ -29,22 +29,22 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */ + {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */ + {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */ + {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */ + {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */ + {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */ + {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */ + {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */ + {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */ {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */ {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 2a0c147..d729533 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -41,15 +41,15 @@ static void hwm_bank(u8 bank) #define FAN_CRUISE_CONTROL_THERMAL 2 #define FAN_SPEED_5625 0 -//#define FAN_TEMPERATURE_30DEGC 0 + struct fan_speed { u8 fan_in; u16 fan_speed; }; -// FANIN Target Speed Register -// FANIN = 337500 / RPM +/* FANIN Target Speed Register */ +/* FANIN = 337500 / RPM */ struct fan_speed fan_speeds[] = { { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, @@ -79,34 +79,27 @@ static void hwm_setup(void) get_option(&cpufan_control, "cpufan_cruise_control"); cpufan_speed = FAN_SPEED_5625; get_option(&cpufan_speed, "cpufan_speed"); - //cpufan_temperature = FAN_TEMPERATURE_30DEGC; - //get_option(&cpufan_temperature, "cpufan_temperature"); sysfan_control = FAN_CRUISE_CONTROL_DISABLED; get_option(&sysfan_control, "sysfan_cruise_control"); sysfan_speed = FAN_SPEED_5625; get_option(&sysfan_speed, "sysfan_speed"); - //sysfan_temperature = FAN_TEMPERATURE_30DEGC; - //get_option(&sysfan_temperature, "sysfan_temperature"); - - // hwm_write(0x31, 0x20); // AVCC high limit - // hwm_write(0x34, 0x06); // VIN2 low limit hwm_bank(0); - hwm_write(0x59, 0x20); // Diode Selection - hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + hwm_write(0x59, 0x20); /* Diode Selection */ + hwm_write(0x5d, 0x0f); /* All Sensors Diode, not Thermistor */ hwm_bank(4); - hwm_write(0x54, 0xf1); // SYSTIN temperature offset - hwm_write(0x55, 0x19); // CPUTIN temperature offset - hwm_write(0x56, 0xfc); // AUXTIN temperature offset + hwm_write(0x54, 0xf1); /* SYSTIN temperature offset */ + hwm_write(0x55, 0x19); /* CPUTIN temperature offset */ + hwm_write(0x56, 0xfc); /* AUXTIN temperature offset */ - hwm_bank(0x80); // Default + hwm_bank(0x80); /* Default */ u8 fan_config = 0; - // 00 FANOUT is Manual Mode - // 01 FANOUT is Thermal Cruise Mode - // 10 FANOUT is Fan Speed Cruise Mode + /* 00 FANOUT is Manual Mode */ + /* 01 FANOUT is Thermal Cruise Mode */ + /* 10 FANOUT is Fan Speed Cruise Mode */ switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; @@ -115,20 +108,20 @@ static void hwm_setup(void) case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; } - // This register must be written first + /* This register must be written first */ hwm_write(0x04, fan_config); switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); /* CPUFANIN target speed */ break; case FAN_CRUISE_CONTROL_THERMAL: printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", temperatures[cpufan_temperature].deg_celsius, temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); /* CPUFANIN target temperature */ break; } @@ -136,29 +129,27 @@ static void hwm_setup(void) case FAN_CRUISE_CONTROL_SPEED: printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); /* SYSFANIN target speed */ break; case FAN_CRUISE_CONTROL_THERMAL: printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", temperatures[sysfan_temperature].deg_celsius, temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); /* SYSFANIN target temperature */ break; } - hwm_write(0x0e, 0x02); // Fan Output Step Down Time - hwm_write(0x0f, 0x02); // Fan Output Step Up Time + hwm_write(0x0e, 0x02); /* Fan Output Step Down Time */ + hwm_write(0x0f, 0x02); /* Fan Output Step Up Time */ - hwm_write(0x47, 0xaf); // FAN divisor register - hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + hwm_write(0x47, 0xaf); /* FAN divisor register */ + hwm_write(0x4b, 0x84); /* AUXFANIN speed divisor */ - hwm_write(0x40, 0x01); // Init, but no SMI# + hwm_write(0x40, 0x01); /* Init, but no SMI# */ } - - -// mainboard_enable is executed as first thing after -// enumerate_buses(). +/* mainboard_enable is executed as first thing after */ +/* enumerate_buses(). */ static void mainboard_enable(device_t dev) { diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index 2ee2890..7db977d 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -39,8 +39,8 @@ static void *smp_write_config_table(void *v) firewire_bus = firewire->bus->secondary; } - // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the - // highest bus number on the pci bus. + /* If a riser card is used, this riser is detected on bus 4, so its secondary bus is the */ + /* highest bus number on the pci bus. */ riser = dev_find_device(0x3388, 0x0021, 0); if (!riser) riser = dev_find_device(0x3388, 0x0022, 0); @@ -77,11 +77,11 @@ static void *smp_write_config_table(void *v) if (riser) { /* Old riser card */ - // riser slot top 5:8.0 + /* riser slot top 5:8.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14); - // riser slot middle 5:9.0 + /* riser slot middle 5:9.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15); - // riser slot bottom 5:a.0 + /* riser slot bottom 5:a.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16); /* New Riser Card */ diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index e9143a8..e3063b2 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. +/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> #include <string.h> @@ -57,21 +57,21 @@ static void ich7_enable_lpc(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) { - lpt_en = 1 << 2; // enable LPT + lpt_en = 1 << 2; /* enable LPT */ } - // Enable Serial IRQ + /* Enable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // Set COM1/COM2 decode range + /* Set COM1/COM2 decode range */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 + /* Enable COM1/COM2/KBD/SuperIO1+2 */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); - // Enable HWM at 0xa00 + /* Enable HWM at 0xa00 */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); - // COM3 decode + /* COM3 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); - // COM4 decode + /* COM4 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); - // io 0x300 decode + /* io 0x300 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } @@ -101,10 +101,10 @@ static void early_superio_config_w83627thg(void) dev = PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_func_mode(dev); - pnp_write_config(dev, 0x24, 0xc6); // PNPCSV + pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */ - pnp_write_config(dev, 0x29, 0x43); // GPIO settings - pnp_write_config(dev, 0x2a, 0x40); // GPIO settings + pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */ + pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */ dev = PNP_DEV(0x2e, W83627THG_SP1); pnp_set_logical_device(dev); @@ -118,7 +118,6 @@ static void early_superio_config_w83627thg(void) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1); dev = PNP_DEV(0x2e, W83627THG_KBC); @@ -126,25 +125,24 @@ static void early_superio_config_w83627thg(void) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - // pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1); dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs + pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ pnp_set_enable(dev, 1); dev = PNP_DEV(0x2e, W83627THG_GPIO2); pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); // Just enable it + pnp_set_enable(dev, 1); /* Just enable it */ dev = PNP_DEV(0x2e, W83627THG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output - pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 - pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ + pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ + pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ dev = PNP_DEV(0x2e, W83627THG_FDC); pnp_set_logical_device(dev); @@ -166,14 +164,14 @@ static void early_superio_config_w83627thg(void) dev = PNP_DEV(0x4e, W83627THG_SP1); pnp_enter_func_mode(dev); - pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values + pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */ pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); pnp_set_irq(dev, PNP_IDX_IRQ0, 11); pnp_set_enable(dev, 1); dev = PNP_DEV(0x4e, W83627THG_SP2); - pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values + pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */ pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); pnp_set_irq(dev, PNP_IDX_IRQ0, 10); @@ -201,8 +199,6 @@ static void rcba_config(void) u32 reg32; /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; @@ -267,7 +263,7 @@ static void rcba_config(void) RCBA32(0x3418) = reg32; /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; + } static void early_ich7_init(void) @@ -275,15 +271,15 @@ static void early_ich7_init(void) uint8_t reg8; uint32_t reg32; - // program secondary mlt XXX byte? + /* program secondary mlt XXX byte? */ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - // reset rtc power status + /* reset rtc power status */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); reg8 &= ~(1 << 2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - // usb transient disconnect + /* usb transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); @@ -317,7 +313,7 @@ static void early_ich7_init(void) RCBA32(0x3e0e) |= (1 << 7); RCBA32(0x3e4e) |= (1 << 7); - // next step only on ich7m b0 and later: + /* next step only on ich7m b0 and later: */ reg32 = RCBA32(0x2034); reg32 &= ~(0x0f << 16); reg32 |= (5 << 16); diff --git a/src/mainboard/kontron/ktqm77/hda_verb.c b/src/mainboard/kontron/ktqm77/hda_verb.c index 720b5a9..fdbc977 100644 --- a/src/mainboard/kontron/ktqm77/hda_verb.c +++ b/src/mainboard/kontron/ktqm77/hda_verb.c @@ -18,9 +18,9 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x11060397, // Codec Vendor / Device ID: Via VT1708S - 0x11060000, // Subsystem ID - 0x0000000c, // Number of jacks + 0x11060397, /* Codec Vendor / Device ID: Via VT1708S */ + 0x11060000, /* Subsystem ID */ + 0x0000000c, /* Number of jacks */ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x11060000 */ AZALIA_SUBVENDOR(0x0, 0x11060000), @@ -95,9 +95,9 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI - 0x80860101, // Subsystem ID - 0x00000004, // Number of jacks + 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of jacks */ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x0, 0x80860101), diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index d2d7acf..b82102a 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -159,8 +159,8 @@ static int int15_handler(void) -// mainboard_enable is executed as first thing after -// enumerate_buses(). +/* mainboard_enable is executed as first thing after */ +/* enumerate_buses(). */ static void mainboard_enable(device_t dev) { diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 57a7fa2..6976b78 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -78,8 +78,8 @@ static void pnp_exit_ext_func_mode(device_t dev) void mainboard_config_superio(void) { - int lvds_3v = 0; // 0 (5V) or 1 (3V3) - int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled + int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */ + int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */ device_t dev = PNP_DEV(0x2e, 0x9); pnp_enter_ext_func_mode(dev); pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ @@ -114,17 +114,17 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server + .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, .gbe_enable = 1, .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel + /* 0 = leave channel enabled */ + /* 1 = disable dimm 0 on channel */ + /* 2 = disable dimm 1 on channel */ + /* 3 = disable dimm 0+1 on channel */ .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600,

1 0

Patch set updated for coreboot: mainboard/amd: Use C89 comments style & remove commented code
by HAOUAS Elyes 06 Oct '16

06 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16907 -gerrit commit ab8230c33d144b50539c5a9de2bd01f48ebd3a8e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Oct 6 18:37:35 2016 +0200 mainboard/amd: Use C89 comments style & remove commented code Change-Id: I137b27ffb0e54a9ca6b0bd3a454b1d99b3e1c22b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/bettong/BiosCallOuts.c | 1 - src/mainboard/amd/bettong/OemCustomize.c | 4 +- src/mainboard/amd/bettong/mptable.c | 1 - src/mainboard/amd/bimini_fam10/mainboard.c | 40 -- src/mainboard/amd/bimini_fam10/resourcemap.c | 11 +- src/mainboard/amd/bimini_fam10/romstage.c | 29 +- src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c | 13 +- src/mainboard/amd/db-ft3b-lc/OemCustomize.c | 120 +++--- src/mainboard/amd/db-ft3b-lc/romstage.c | 1 - src/mainboard/amd/dinar/OemCustomize.c | 11 +- src/mainboard/amd/dinar/OptionsIds.h | 9 - src/mainboard/amd/dinar/acpi_tables.c | 8 +- src/mainboard/amd/dinar/buildOpts.c | 107 ++--- src/mainboard/amd/dinar/gpio.c | 427 +++++++++----------- src/mainboard/amd/dinar/gpio.h | 418 ++++++++++---------- src/mainboard/amd/dinar/mainboard.c | 3 - src/mainboard/amd/dinar/mptable.c | 3 +- src/mainboard/amd/dinar/platform_cfg.h | 11 +- src/mainboard/amd/dinar/rd890_cfg.c | 13 +- src/mainboard/amd/dinar/rd890_cfg.h | 24 +- src/mainboard/amd/dinar/romstage.c | 4 +- src/mainboard/amd/dinar/sb700_cfg.c | 34 +- src/mainboard/amd/dinar/sb700_cfg.h | 3 +- src/mainboard/amd/inagua/BiosCallOuts.c | 14 +- src/mainboard/amd/inagua/OemCustomize.c | 19 +- src/mainboard/amd/inagua/OptionsIds.h | 8 - src/mainboard/amd/inagua/PlatformGnbPcieComplex.h | 82 ++-- src/mainboard/amd/inagua/broadcom.c | 197 +++++----- src/mainboard/amd/inagua/buildOpts.c | 108 ++--- src/mainboard/amd/inagua/mainboard.c | 1 - src/mainboard/amd/inagua/mptable.c | 2 +- src/mainboard/amd/inagua/platform_cfg.h | 2 +- src/mainboard/amd/lamar/BiosCallOuts.c | 14 +- src/mainboard/amd/lamar/mainboard.c | 3 - src/mainboard/amd/mahogany/mainboard.c | 29 -- src/mainboard/amd/mahogany/mptable.c | 1 - src/mainboard/amd/mahogany_fam10/mainboard.c | 29 -- src/mainboard/amd/mahogany_fam10/resourcemap.c | 10 +- src/mainboard/amd/mahogany_fam10/romstage.c | 27 +- src/mainboard/amd/olivehill/BiosCallOuts.c | 38 +- src/mainboard/amd/olivehill/OptionsIds.h | 10 - src/mainboard/amd/olivehill/buildOpts.c | 128 ++---- src/mainboard/amd/olivehill/mptable.c | 39 -- src/mainboard/amd/olivehillplus/BiosCallOuts.c | 42 +- src/mainboard/amd/olivehillplus/mptable.c | 1 - src/mainboard/amd/olivehillplus/romstage.c | 1 - src/mainboard/amd/parmer/BiosCallOuts.c | 10 +- src/mainboard/amd/parmer/OptionsIds.h | 10 - src/mainboard/amd/parmer/buildOpts.c | 140 ++----- src/mainboard/amd/parmer/mptable.c | 1 - src/mainboard/amd/persimmon/BiosCallOuts.c | 9 +- src/mainboard/amd/persimmon/OemCustomize.c | 25 +- src/mainboard/amd/persimmon/OptionsIds.h | 8 - .../amd/persimmon/PlatformGnbPcieComplex.h | 72 ++-- src/mainboard/amd/persimmon/buildOpts.c | 108 ++--- src/mainboard/amd/persimmon/mptable.c | 1 - src/mainboard/amd/persimmon/platform_cfg.h | 2 +- src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 16 +- src/mainboard/amd/serengeti_cheetah/fadt.c | 14 +- src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 44 +-- src/mainboard/amd/serengeti_cheetah/irq_tables.c | 9 +- src/mainboard/amd/serengeti_cheetah/mptable.c | 38 +- src/mainboard/amd/serengeti_cheetah/resourcemap.c | 4 +- src/mainboard/amd/serengeti_cheetah/romstage.c | 64 +-- .../amd/serengeti_cheetah_fam10/acpi_tables.c | 17 +- src/mainboard/amd/serengeti_cheetah_fam10/fadt.c | 27 +- .../amd/serengeti_cheetah_fam10/get_bus_conf.c | 28 +- .../amd/serengeti_cheetah_fam10/irq_tables.c | 9 +- .../amd/serengeti_cheetah_fam10/mptable.c | 34 +- .../amd/serengeti_cheetah_fam10/resourcemap.c | 12 +- .../amd/serengeti_cheetah_fam10/romstage.c | 39 +- src/mainboard/amd/south_station/BiosCallOuts.c | 14 +- src/mainboard/amd/south_station/OemCustomize.c | 17 +- src/mainboard/amd/south_station/OptionsIds.h | 8 - .../amd/south_station/PlatformGnbPcieComplex.h | 72 ++-- src/mainboard/amd/south_station/buildOpts.c | 107 ++--- src/mainboard/amd/south_station/mainboard.c | 10 +- src/mainboard/amd/south_station/mptable.c | 3 +- src/mainboard/amd/south_station/platform_cfg.h | 3 +- src/mainboard/amd/thatcher/BiosCallOuts.c | 10 +- src/mainboard/amd/thatcher/OemCustomize.c | 13 +- src/mainboard/amd/thatcher/OptionsIds.h | 10 - src/mainboard/amd/thatcher/buildOpts.c | 141 ++----- src/mainboard/amd/thatcher/mptable.c | 3 +- src/mainboard/amd/tilapia_fam10/mainboard.c | 43 +- src/mainboard/amd/tilapia_fam10/resourcemap.c | 12 +- src/mainboard/amd/tilapia_fam10/romstage.c | 27 +- src/mainboard/amd/torpedo/BiosCallOuts.c | 36 +- src/mainboard/amd/torpedo/Oem.h | 23 +- src/mainboard/amd/torpedo/OemCustomize.c | 30 +- src/mainboard/amd/torpedo/OptionsIds.h | 9 - src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h | 72 ++-- src/mainboard/amd/torpedo/buildOpts.c | 41 +- src/mainboard/amd/torpedo/fadt.c | 1 - src/mainboard/amd/torpedo/gpio.c | 437 +++++++++------------ src/mainboard/amd/torpedo/gpio.h | 418 ++++++++++---------- src/mainboard/amd/torpedo/mainboard.c | 1 - src/mainboard/amd/torpedo/mptable.c | 3 - src/mainboard/amd/torpedo/platform_cfg.h | 47 +-- src/mainboard/amd/torpedo/romstage.c | 4 +- src/mainboard/amd/union_station/BiosCallOuts.c | 14 +- src/mainboard/amd/union_station/OemCustomize.c | 25 +- src/mainboard/amd/union_station/OptionsIds.h | 8 - .../amd/union_station/PlatformGnbPcieComplex.h | 72 ++-- src/mainboard/amd/union_station/buildOpts.c | 108 ++--- src/mainboard/amd/union_station/mptable.c | 3 +- src/mainboard/amd/union_station/platform_cfg.h | 1 - 107 files changed, 1813 insertions(+), 2874 deletions(-) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index d4d4410..1804296 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -72,7 +72,6 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio; diff --git a/src/mainboard/amd/bettong/OemCustomize.c b/src/mainboard/amd/bettong/OemCustomize.c index 3300244..a32ea9a 100644 --- a/src/mainboard/amd/bettong/OemCustomize.c +++ b/src/mainboard/amd/bettong/OemCustomize.c @@ -71,7 +71,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */ { - DESCRIPTOR_TERMINATE_LIST, // Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, @@ -91,7 +91,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { }, /* DP1 */ { - 0, //DESCRIPTOR_TERMINATE_LIST, + 0, /*DESCRIPTOR_TERMINATE_LIST, */ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 20, 23), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) }, diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c index 744fd98..9e73e77 100644 --- a/src/mainboard/amd/bettong/mptable.c +++ b/src/mainboard/amd/bettong/mptable.c @@ -64,7 +64,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 3c6c2c6..c4dd21e 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -63,22 +63,11 @@ void enable_int_gfx(void) void set_pcie_dereset(void) { /* GPIO 50h reset PCIe slot */ -/* - u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50); - u8 byte = ~(1 << 5); - byte |= ~(1 << 6); - *addr = byte; -*/ } void set_pcie_reset(void) { /* GPIO 50h reset PCIe slot */ -/* - u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50); - u8 byte = ~((1 << 5) | (1 << 6)); - *addr = byte; -*/ } u8 is_dev3_present(void) @@ -86,34 +75,6 @@ u8 is_dev3_present(void) return 0; } -#if 0 /* not tested yet. */ -/******************************************************** -* bimini uses SB800 GPIO9 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 5); /* Set Gpio9 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif /* get_ide_dma66() */ /************************************************* * enable the dedicated function in bimini board. @@ -125,7 +86,6 @@ static void mainboard_enable(device_t dev) set_pcie_dereset(); enable_int_gfx(); - /* get_ide_dma66(); */ } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/bimini_fam10/resourcemap.c b/src/mainboard/amd/bimini_fam10/resourcemap.c index e23f1c1..dbd6341 100644 --- a/src/mainboard/amd/bimini_fam10/resourcemap.c +++ b/src/mainboard/amd/bimini_fam10/resourcemap.c @@ -43,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -81,7 +81,8 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -129,7 +130,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,7 +164,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -191,7 +190,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -221,7 +219,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -262,7 +259,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 9ea7e44..6fee2ed 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -100,12 +98,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -164,10 +161,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -194,8 +191,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -206,24 +201,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb800_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index f46116a..291c2d8 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -158,8 +158,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00; //6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; /*BIT0 | BIT2 | BIT5; */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00; /*6 | BIT3; */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -195,7 +195,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /*BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; @@ -230,7 +230,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /*BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; @@ -241,7 +241,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /*BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; @@ -251,7 +251,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; /*BIT0 | BIT4 |BIT8; */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, @@ -279,7 +279,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); diff --git a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c index e8146a0..bffe888 100644 --- a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c +++ b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c @@ -118,66 +118,66 @@ OemCustomizeInitEarly ( * use its default conservative settings. */ static const PSO_ENTRY ROMDATA PlatformMemoryConfiguration[] = { - // - // The following macros are supported (use comma to separate macros): - // - // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) - // - // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. - // - // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. - // - // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. - // - // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. - // - // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. - // - // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. - // - // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. - // - // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) - // - // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. - // - // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Speicifes the HW RXEN training seed for a channel of a socket - // + /* + * The following macros are supported (use comma to separate macros): + * + * MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + * The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + * AGESA will base on this value to disable unused MemClk to save power. + * Example: + * BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + * Bit AM3/S1g3 pin name + * 0 M[B,A]_CLK_H/L[0] + * 1 M[B,A]_CLK_H/L[1] + * 2 M[B,A]_CLK_H/L[2] + * 3 M[B,A]_CLK_H/L[3] + * 4 M[B,A]_CLK_H/L[4] + * 5 M[B,A]_CLK_H/L[5] + * 6 M[B,A]_CLK_H/L[6] + * 7 M[B,A]_CLK_H/L[7] + * And platform has the following routing: + * CS0 M[B,A]_CLK_H/L[4] + * CS1 M[B,A]_CLK_H/L[2] + * CS2 M[B,A]_CLK_H/L[3] + * CS3 M[B,A]_CLK_H/L[5] + * Then platform can specify the following macro: + * MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + * + * CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + * The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + * AGESA will base on this value to tristate unused CKE to save power. + * + * ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + * The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + * AGESA will base on this value to tristate unused ODT pins to save power. + * + * CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + * The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + * AGESA will base on this value to tristate unused Chip select to save power. + * + * NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + * Specifies the number of DIMM slots per channel. + * + * NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + * Specifies the number of Chip selects per channel. + * + * NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + * Specifies the number of channels per socket. + * + * OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + * Specifies DDR bus speed of channel ChannelID on socket SocketID. + * + * DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + * Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + * + * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + * Byte6Seed, Byte7Seed, ByteEccSeed) + * Specifies the write leveling seed for a channel of a socket. + * + * HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + * Byte6Seed, Byte7Seed, ByteEccSeed) + * Speicifes the HW RXEN training seed for a channel of a socket + */ #define SEED_WL 0x0E WRITE_LEVELING_SEED( diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index f69e188..5c7796f 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -81,7 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); AGESAWRAPPER(amdinitpost); - //PspMboxBiosCmdDramInfo(); post_code(0x41); AGESAWRAPPER(amdinitenv); /* diff --git a/src/mainboard/amd/dinar/OemCustomize.c b/src/mainboard/amd/dinar/OemCustomize.c index 84866de..668dd25 100644 --- a/src/mainboard/amd/dinar/OemCustomize.c +++ b/src/mainboard/amd/dinar/OemCustomize.c @@ -28,11 +28,12 @@ * use its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - // Dinar has the following routing: - // CS0 M[B,A]_CLK_H/L[0] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[1] - // CS3 M[B,A]_CLK_H/L[3] + /* Dinar has the following routing: + * CS0 M[B,A]_CLK_H/L[0] + * CS1 M[B,A]_CLK_H/L[2] + * CS2 M[B,A]_CLK_H/L[1] + * CS3 M[B,A]_CLK_H/L[3] + */ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), PSO_END diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h index d1d184d..c9e66d2 100644 --- a/src/mainboard/amd/dinar/OptionsIds.h +++ b/src/mainboard/amd/dinar/OptionsIds.h @@ -42,15 +42,6 @@ * **/ -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index 1d1717b..425647e 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -72,10 +72,10 @@ unsigned long acpi_fill_madt(unsigned long current) } current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, - 0, //BUS - 0, //SOURCE - 2, //gsirq - 0 //flags + 0, /* BUS */ + 0, /* SOURCE */ + 2, /* gsirq */ + 0 /* flags */ ); /* 0: mean bus 0--->ISA */ diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index e237ff0..ee12dfc 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -26,33 +26,32 @@ #include "AGESA.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE -//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE /* AGESA will check the OEM configuration during preprocessing stage, * coreboot enable -Wundef option, so we should make sure we have all contanstand defined */ /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ /* Select the CPU family. */ @@ -79,23 +78,9 @@ * Comment out the items wanted to be included in the build. * Uncomment those items you with to REMOVE from the build. */ -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_DDR3_SUPPORT TRUE -//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE -//#define BLDOPT_REMOVE_SRAT TRUE -//#define BLDOPT_REMOVE_SLIT TRUE #define BLDOPT_REMOVE_WHEA TRUE -//#define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 120000 @@ -136,15 +121,11 @@ #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased #define BLDCFG_PLATFORM_C1E_OPDATA 0x2000 -//#define BLDCFG_USE_ATM_MODE TRUE #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0xCB0 -#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance //BatteryLife -//#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeMsgBasedC1e -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x2000 +#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance /* BatteryLife */ -//#define IDSOPT_IDS_ENABLED TRUE #define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE #define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT TRUE #define BLDCFG_PSTATE_HPC_MODE FALSE @@ -168,15 +149,17 @@ * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ -// This is the delivery package title, "MarG34PI" -// This string MUST be exactly 8 characters long +/* This is the delivery package title, "MarG34PI" + * This string MUST be exactly 8 characters long + */ #define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'} -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long +/* This is the release version number of the AGESA component + * This string MUST be exactly 12 characters long + */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '} -// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket. +/* The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket. */ #define INSTALL_G34_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_10_SUPPORT TRUE #define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE @@ -195,9 +178,10 @@ #endif #endif -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0xFF) #define DFLT_SCRUB_L2_RATE (0x10) #define DFLT_SCRUB_L3_RATE (0x10) @@ -216,8 +200,8 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, - { //BUID Swap List - { //BUID Swaps + { /* BUID Swap List */ + { /* BUID Swaps */ /* Each Non-coherent chain may have a list of device swaps, * Each item specify a device will be swap from its current id to a new one */ @@ -233,7 +217,7 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, }, - { //The ordered final BUIDs + { /* The ordered final BUIDs */ /* Specify the final BUID to be zero, All others are non applicable */ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, @@ -251,14 +235,6 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = #define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList -// And another platform specific one ... -//CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[2] = -//{ -// HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, -// HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, -// HT_LIST_TERMINAL -//}; - CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = { { @@ -282,14 +258,14 @@ CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = #define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList -// A performance-per-watt optimization. +/* A performance-per-watt optimization. */ CONST SKIP_REGANG ROMDATA PerfPerWatt[] = { { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF }, { HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF }, { HT_LIST_TERMINAL } }; -// uncomment the line below to make Perf-per-watt enabled by default. +/* uncomment the line below to make Perf-per-watt enabled by default. */ #define BLDCFG_LINK_SKIP_REGANG_LIST &PerfPerWatt @@ -313,7 +289,7 @@ CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] = CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = { - // Source Socket, Link (4-7 are sublink 1), Target Socket + /* Source Socket, Link (4-7 are sublink 1), Target Socket */ {0, 0, 1}, {0, 1, 1}, {0, 3, 1}, @@ -329,9 +305,9 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = */ CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] = { - // Socket, Link, SecBus, SubBus - { 0, 2, 0x00, 0xBF }, // RD890 of Dinar - { 1, 0, 0xC0, 0xFF }, // HTX + /* Socket, Link, SecBus, SubBus */ + { 0, 2, 0x00, 0xBF }, /* RD890 of Dinar */ + { 1, 0, 0xC0, 0xFF }, /* HTX */ { (HT_LIST_TERMINAL) } }; @@ -346,15 +322,6 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = }; #define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList -/* - CONST SKIP_REGANG ROMDATA DinarSkipRegangMap[] = - { -// {socketA, linkA, socketB, linkB} -{0, 0, 1, 1}, -}; - -#define BLDCFG_LINK_SKIP_REGANG_LIST &DinarSkipRegangMap -*/ /* * Device Capabilities Override for disabling ID Clumping diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c index affda6f..56dfb56 100644 --- a/src/mainboard/amd/dinar/gpio.c +++ b/src/mainboard/amd/dinar/gpio.c @@ -62,11 +62,11 @@ gpioEarlyInit( u32 SmiMmioAddr = 0; u32 andMask32 = 0; - // Enable HUDSON MMIO Base (AcpiMmioAddr) + /* Enable HUDSON MMIO Base (AcpiMmioAddr) */ ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); Data8 |= BIT0; WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); - // Get HUDSON MMIO Base (AcpiMmioAddr) + /* Get HUDSON MMIO Base (AcpiMmioAddr) */ ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); Data16 = Data8 << 8; ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8); @@ -77,109 +77,109 @@ gpioEarlyInit( MiscMmioAddr = AcpiMmioAddr + MISC_BASE; Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80); if ((Data8 & BIT4) == 0) { - BoardType = 0; // external clock board + BoardType = 0; /* external clock board */ } Data8 = Mmio8_G (GpioMmioAddr, GPIO_30); StripInfo = (Data8 & BIT7) >> 7; Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); StripInfo |= (Data8 & BIT7) >> 6; - if (StripInfo < boardRevC) { // for old board. Rev B - Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 - Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 + if (StripInfo < boardRevC) { /* for old board. Rev B */ + Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); /* function 3 */ + Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); /* function 0 */ } for (Index = 0; Index < MAX_GPIO_NO; Index++) { if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { - // Configure multi-function + /* Configure multi-function */ Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); } - // Configure GPIO + /* Configure GPIO */ if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); } if (Index == GPIO_65) { if ( BoardType == 0 ) { - Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 + Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); /* function 3 */ } } } - // Configure GEVENT + /* Configure GEVENT */ if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) { SmiMmioAddr = AcpiMmioAddr + SMI_BASE; andMask32 = ~(1 << (Index - GEVENT_00)); - //EventEnable: 0-Disable, 1-Enable + /*EventEnable: 0-Disable, 1-Enable */ Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); - //SciTrig: 0-Falling Edge, 1-Rising Edge + /*SciTrig: 0-Falling Edge, 1-Rising Edge */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); - //SciLevl: 0-Edge trigger, 1-Level Trigger + /*SciLevl: 0-Edge trigger, 1-Level Trigger */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); - //SmiSciEn: 0-Not send SMI, 1-Send SMI + /*SmiSciEn: 0-Not send SMI, 1-Send SMI */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); - //SciS0En: 0-Disable, 1-Enable + /*SciS0En: 0-Disable, 1-Enable */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); - //SciMap: 00000b ~ 11111b + /*SciMap: 00000b ~ 11111b */ RegIndex8=(u8)((Index - GEVENT_00) >> 2); Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8); Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); - //SmiTrig: 0-Active Low, 1-Active High + /*SmiTrig: 0-Active Low, 1-Active High */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); - //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 + /*SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 */ RegIndex8=(u8)((Index - GEVENT_00) >> 4); Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2); Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); } } - // - // config MXM - // GPIO9: Input for MXM_PRESENT2# - // GPIO10: Input for MXM_PRESENT1# - // GPIO28: Input for MXM_PWRGD - // GPIO35: Output for MXM Reset - // GPIO45: Output for MXM Power Enable, active HIGH - // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable - // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO - // - // set INTE#/GPIO32 as GPO for PCIE_SW - RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO + /* + * config MXM + * GPIO9: Input for MXM_PRESENT2# + * GPIO10: Input for MXM_PRESENT1# + * GPIO28: Input for MXM_PWRGD + * GPIO35: Output for MXM Reset + * GPIO45: Output for MXM Power Enable, active HIGH + * GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable + * GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO + */ + /* set INTE#/GPIO32 as GPO for PCIE_SW */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); /* GPO */ RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6); - // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN - RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO + /* set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); /* GPO */ - // set AD9/GPIO9 as GPI for MXM_PRESENT2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD9/GPIO9 as GPI for MXM_PRESENT2# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set AD10/GPIO10 as GPI for MXM_PRESENT1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD10/GPIO10 as GPI for MXM_PRESENT1# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set GNT1#/GPIO44 as GPO for MXM Reset - RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO + /* set GNT1#/GPIO44 as GPO for MXM Reset */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); /* GPO */ - // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO + /* set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); /* GPO */ - // set AD28/GPIO28 as GPI for MXM_PWRGD - RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD28/GPIO28 as GPI for MXM_PWRGD */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) + /* set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); @@ -187,20 +187,13 @@ gpioEarlyInit( RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3); - // - // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). - // - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20)); - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20))); + /* [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). */ - // check if there any GFX card + /* check if there any GFX card */ Flags = 0; - // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL); - // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09); ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8); if (!(Data8 & BIT7)) { - //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10); ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8); if (!(Data8 & BIT7)) { @@ -209,241 +202,187 @@ gpioEarlyInit( } if ( Flags ) { - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 + /* [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 */ RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH */ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) SbStall (10000); - // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module + /* Write the GPIO55(MXM_PWR_EN) to enable the integrated power module */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) - // WAIT POWER READY: GPIO28 (MXM_PWRGD) - //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); while (!(Data8 & BIT7)) { ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); } - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset - // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); } else { - // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module + /* Write the GPIO55(MXM_PWR_EN) to disable the integrated power module */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) SbStall (10000); - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down */ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); } - // - // APU GPP0: On board LAN - // GPIO25: PCIE_RST#_LAN, LOW active - // GPIO63: LAN_CLKREQ# - // GPIO197: LOM_POWER, HIGH Active - // Clock: GPP_CLK3 - // - // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER - RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - - // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 - - // - // APU GPP1: WUSB - // GPIO1: MPCIE_RST2#, LOW active - // GPIO13: WU_DISABLE#, LOW active - // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) - // - // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD01/GPIO01 as GPO for MPCIE_RST2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB - // RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO - // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH - // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // - // APU GPP2: WWAN - // GPIO0: MPCIE_RST1#, LOW active - // GPIO14: WP_DISABLE#, LOW active - // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) - // - // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD00/GPIO00 as GPO for MPCIE_RST1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO - // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN - // RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO - // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); - // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3); - - // - // APU GPP3: 1394 - // GPIO59: Power control, HIGH active - // GPIO27: PCIE_RST#_1394, LOW active - // GPIO41: CLKREQ# - // Clock: GPP_CLK8 - // - // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 - RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# - - // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C - RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - // To fix glitch issue - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - // - // Enable/Disable OnBoard LAN - // + /* + * APU GPP0: On board LAN + * GPIO25: PCIE_RST#_LAN, LOW active + * GPIO63: LAN_CLKREQ# + * GPIO197: LOM_POWER, HIGH Active + * Clock: GPP_CLK3 + * + * Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER + */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + + /* set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); /* CLK_REQ3# */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); /* Enable GPP_CLK3 */ + + /* + * APU GPP1: WUSB + * GPIO1: MPCIE_RST2#, LOW active + * GPIO13: WU_DISABLE#, LOW active + * GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) + * + * Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable + */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD01/GPIO01 as GPO for MPCIE_RST2# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* + * APU GPP2: WWAN + * GPIO0: MPCIE_RST1#, LOW active + * GPIO14: WP_DISABLE#, LOW active + * GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) + * + * Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable + */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Set AD00/GPIO00 as GPO for MPCIE_RST1# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* + * APU GPP3: 1394 + * GPIO59: Power control, HIGH active + * GPIO27: PCIE_RST#_1394, LOW active + * GPIO41: CLKREQ# + * Clock: GPP_CLK8 + */ + /* Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); /* CLK_REQ2# */ + + /* set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); /* GPO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + /* To fix glitch issue */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); /* set GPIO_GATE_C to LOW */ + + /* Enable/Disable OnBoard LAN */ + if (!CONFIG_ONBOARD_LAN) - { // 1 - DISABLED - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off + { /* 1 - DISABLED */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); /* LOM_POWER off */ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3 + RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); /* PULL UP - DISABLED */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); /* Disable GPP_CLK3 */ } - // else - // { // 0 - AUTO - // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable) - // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); - // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); - // } + /* Enable/Disable 1394 */ - // - // Enable/Disable 1394 - // if (!CONFIG_ONBOARD_1394) - { // 1 - DISABLED - // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off + { /* 1 - DISABLED */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); /* 1394 power off */ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 - // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); /* pullup DISABLE */ + RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); /* DISABLE GPP_CLK8 */ } - // else - // { // 0 - AUTO - // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH) - // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); - // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); - // - // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); - // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); - // } - - // - // external USB 3.0 control: - // amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE - // GPIO26: PCIE_RST#_USB3.0 - // GPIO46: PCIE_USB30_CLKREQ# - // GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON - // Clock: GPP_CLK7 - // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE - // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { - // disable Onboard NEC USB3.0 controller + + /* + * external USB 3.0 control: + * amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO26: PCIE_RST#_USB3.0 + * GPIO46: PCIE_USB30_CLKREQ# + * GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON + * Clock: GPP_CLK7 + * GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + */ + if (!CONFIG_ONBOARD_USB30) { RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 - RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); /* PULL_UP DISABLE */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); /* DISABLE GPP_CLK7 */ + RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */ } - // } - // - // BlueTooth control: BT_ON - // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE - // GPIO07: BT_ON, 0 - OFF, 1 - ON - // + /* BlueTooth control: BT_ON + * amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO07: BT_ON, 0 - OFF, 1 - ON + */ if (!CONFIG_ONBOARD_BLUETOOTH) { - //- if (SystemConfiguration.amdBlueTooth == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); - //- } } - // - // WebCam control: - // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE - // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF - // + /* + * WebCam control: + * amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF + */ if (!CONFIG_ONBOARD_WEBCAM) { - //- if (SystemConfiguration.amdWebCam == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); - //- } } - // - // Travis enable: - // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE - // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE - // + /* + * Travis enable: + * amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE + * GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE + */ if (!CONFIG_ONBOARD_TRAVIS) { - //- if (SystemConfiguration.amdTravisCtrl == 0) { RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); - //- } } - // - // Disable Light Sensor if needed - // + /* Disable Light Sensor if needed */ + if (CONFIG_ONBOARD_LIGHTSENSOR) { - //- if (SystemConfiguration.amdLightSensor == 1) { RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); - //- } } } diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h index 3ac8bfa..64368c9 100644 --- a/src/mainboard/amd/dinar/gpio.h +++ b/src/mainboard/amd/dinar/gpio.h @@ -83,87 +83,87 @@ #define FUNCTION1 1 #define FUNCTION2 2 #define FUNCTION3 3 -#define NonGpio 0x80 // BIT7 +#define NonGpio 0x80 /* BIT7 */ -// S0-domain General Purpose I/O: GPIO 00~67 -#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT -#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT -#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT -#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED -#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT -#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT -#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED -#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF -#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level -#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 -#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 -#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 -#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default -#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. -#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) -#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) -#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE -// 1:BATTERY IS FINE(DEFAULT) -// 0:BATTERY IS LOW -#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF -#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default -#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high -#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high -#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high -#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT -#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT -#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 -#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 -// 00 - REVA -// 01 - REVB -// 10 - REVC -// 11 - REVD -#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO -#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. -// 0:USB3.0 I/F in Express CARD -// 1:PCIE I/F in Express CARD detection -#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF -#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# -#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC -#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. -#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# -#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# -#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK -#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE -#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF -#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# -#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA -#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ -#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 -#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V -#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 -#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT -#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE -#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE -#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) -// 1:ENABLE; 0:DISABLE -// DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 -#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN -#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER -#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER -#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE -#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# -#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 -#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 -#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# -#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 -#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM -#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default -#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# +/* S0-domain General Purpose I/O: GPIO 00~67 */ +#define GPIO_00_SELECT FUNCTION1+NonGpio /* MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_01_SELECT FUNCTION1+NonGpio /* MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_02_SELECT FUNCTION1 /* MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_03_SELECT FUNCTION1+NonGpio /* NOT USED */ +#define GPIO_04_SELECT FUNCTION1+NonGpio /* x1 gpp reset, for J3701, low active, HIGH DEFAULT */ +#define GPIO_05_SELECT FUNCTION1+NonGpio /* express card reset, for J2500, low active, HIGH DEFAULT */ +#define GPIO_06_SELECT FUNCTION0+NonGpio /*NOT USED */ +#define GPIO_07_SELECT FUNCTION1 /* BT_ON, 1: BT ON(DEFAULT); 0: BT OFF */ +#define GPIO_08_SELECT FUNCTION1 /* PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level */ +#define GPIO_09_SELECT FUNCTION1+NonGpio /* MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED */ +#define GPIO_10_SELECT FUNCTION1+NonGpio /* MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED */ +#define GPIO_11_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_12_SELECT FUNCTION1 /* WL_DISABLE#, DISABLE THE WALN IN J3702 */ +#define GPIO_13_SELECT FUNCTION1 /* WU_DISABLE#, DISABLE THE WUSB IN J3711 */ +#define GPIO_14_SELECT FUNCTION1 /* WP_DISABLE, DISABLE THE WWAN IN J3703 */ +#define GPIO_15_SELECT FUNCTION1+NonGpio /* NOT USED, /*FUNCTION1, Reset_CEC# Low Active, High default */ */ +#define GPIO_16_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_17_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_18_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_19_SELECT FUNCTION1 /* For LASSO_DET# detection when Gevent14# is asserted. */ +#define GPIO_20_SELECT FUNCTION1 /* PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) */ +#define GPIO_21_SELECT FUNCTION1 /* DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) */ +#define GPIO_22_SELECT FUNCTION1 /* SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE */ +/* 1:BATTERY IS FINE(DEFAULT) */ +/* 0:BATTERY IS LOW */ +#define GPIO_23_SELECT FUNCTION1 /* CODEC_ON.1: CODEC ON (default)0: CODEC OFF */ +#define GPIO_24_SELECT FUNCTION1 /* Travis reset,Low active High default */ +#define GPIO_25_SELECT FUNCTION1+NonGpio /* PCIE_RST# for LAN (AND gate with PCIE_RST#); default high */ +#define GPIO_26_SELECT FUNCTION1+NonGpio /* PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high */ +#define GPIO_27_SELECT FUNCTION1+NonGpio /* PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high */ +#define GPIO_28_SELECT FUNCTION1 /* MXM PWRGD INDICATOR, INPUT */ +#define GPIO_29_SELECT FUNCTION1 /* MEM HOT, LOW ACTIVE, OUTPUT */ +#define GPIO_30_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 0 */ +#define GPIO_31_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 1 */ +/* 00 - REVA */ +/* 01 - REVB */ +/* 10 - REVC */ +/* 11 - REVD */ +#define GPIO_32_SELECT FUNCTION1+NonGpio /* PCIE_SW - HIGH:MXM; LOW:LASSO */ +#define GPIO_33_SELECT FUNCTION1 /* USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. */ +/* 0:USB3.0 I/F in Express CARD */ +/* 1:PCIE I/F in Express CARD detection */ +#define GPIO_34_SELECT FUNCTION1 /* WEBCAM_ON#. 0: ON (default) 1: OFF */ +#define GPIO_35_SELECT FUNCTION1 /* ODD_DA_INTH# */ +#define GPIO_36_SELECT FUNCTION0+NonGpio /* PCICLK FOR KBC */ +#define GPIO_37_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_38_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_39_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_40_SELECT FUNCTION1 /* For DOCK# detection when Gevent14# is asserted. */ +#define GPIO_41_SELECT FUNCTION1+NonGpio /* 1394 CLK REQ# */ +#define GPIO_42_SELECT FUNCTION1+NonGpio /* X4 GPP CLK REQ# */ +#define GPIO_43_SELECT FUNCTION0+NonGpio /* SMBUS0, CLOCK */ +#define GPIO_44_SELECT FUNCTION1+NonGpio /* PEGPIO0, RESET THE MXM MODULE */ +#define GPIO_45_SELECT FUNCTION2+NonGpio /* PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF */ +#define GPIO_46_SELECT FUNCTION1+NonGpio /* USB3.0_CLKREQ# */ +#define GPIO_47_SELECT FUNCTION0+NonGpio /* SMBUS0, DATA */ +#define GPIO_48_SELECT FUNCTION0+NonGpio /* SERIRQ */ +#define GPIO_49_SELECT FUNCTION0+NonGpio /* LDRQ#1 */ +#define GPIO_50_SELECT FUNCTION2 /* SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V */ +#define GPIO_51_SELECT FUNCTION0+NonGpio /* back-up for SMARTVOLTAGE1 */ +#define GPIO_52_SELECT FUNCTION0+NonGpio /* CPU FAN OUT */ +#define GPIO_53_SELECT FUNCTION1 /* ODD POWER ENABLE, HIGH ACTIVE */ +#define GPIO_54_SELECT FUNCTION0+NonGpio /* SB_PROCHOT, OUTPUT, LOW ACTIVE */ +#define GPIO_55_SELECT FUNCTION2+NonGpio /* MXM POWER ENABLE(POWER ON MODULE) */ +/* 1:ENABLE; 0:DISABLE */ +/* DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 */ +#define GPIO_56_SELECT FUNCTION0+NonGpio /*HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN */ +#define GPIO_57_SELECT FUNCTION1 /* HDD0_POWER */ +#define GPIO_58_SELECT FUNCTION1 /* HDD2_POWER */ +#define GPIO_59_SELECT FUNCTION2+NonGpio /* 1394 POWER, OUTPUT, HIGH ACTIVE */ +#define GPIO_60_SELECT FUNCTION0+NonGpio /* EXPCARD_CLKREQ# */ +#define GPIO_61_SELECT FUNCTION0+NonGpio /* PE0_CLKREQ#, FROM J3700 */ +#define GPIO_62_SELECT FUNCTION0+NonGpio /* PE2_CLKREQ#, FROM J3711 */ +#define GPIO_63_SELECT FUNCTION0+NonGpio /* LAN_CLKREQ# */ +#define GPIO_64_SELECT FUNCTION0+NonGpio /* PE1_CLKREQ#, FROM J3703 */ +#define GPIO_65_SELECT FUNCTION0+NonGpio /* MXM CLK REQ#, FROM MXM */ +#define GPIO_66_SELECT FUNCTION1 /* USED AS TRAVIS_EN#; 0:ENABLE as default */ +#define GPIO_67_SELECT FUNCTION0+NonGpio /* USED AS SATA_ACT# */ #define GPIO_68_SELECT FUNCTION0+NonGpio #define GPIO_69_SELECT FUNCTION0+NonGpio #define GPIO_70_SELECT FUNCTION0+NonGpio @@ -192,40 +192,40 @@ #define GPIO_93_SELECT FUNCTION0+NonGpio #define GPIO_94_SELECT FUNCTION0+NonGpio #define GPIO_95_SELECT FUNCTION0+NonGpio -// GEVENT 00~23 are mapped to GPIO 96~119 -#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# -#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# -#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP -#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# -#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# -#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active -#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, -// there is a confliction to IR function when this pin is as a GEVENT. -#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, -// special pin difination for SB700 VGA OUTPUT, high active, -// VGA power for Hudson-M2 will be down when it was asserted. -#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active -#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) -#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 -#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 -#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active -// [option for SPI_TPM_CS# in Hudson-M2 A12)] -#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & -// USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time -#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, -// plus judge GPIO40 and GPIO19 level,low is assert. -// LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) -// DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) -#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active -#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, -// low active, when it's low, BIOS will enbale ODD_PWR -#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# -#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK -#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# -#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT -#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 -#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# -#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI +/* GEVENT 00~23 are mapped to GPIO 96~119 */ +#define GPIO_96_SELECT FUNCTION0 /* GA20IN/GEVENT0# */ +#define GPIO_97_SELECT FUNCTION0 /* KBRST#/GEVENT1# */ +#define GPIO_98_SELECT FUNCTION0 /* THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP */ +#define GPIO_99_SELECT FUNCTION1 /* LPC_PME#/GEVENT3# -> EC_SCI# */ +#define GPIO_100_SELECT FUNCTION2 /* PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# */ +#define GPIO_101_SELECT FUNCTION1 /* LPC_PD#/GEVENT5# -> hotplug of express card, low active */ +#define GPIO_102_SELECT FUNCTION0+NonGpio /* USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, */ +/* there is a confliction to IR function when this pin is as a GEVENT. */ +#define GPIO_103_SELECT FUNCTION0+NonGpio /* DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, */ +/* special pin difination for SB700 VGA OUTPUT, high active, */ +/* VGA power for Hudson-M2 will be down when it was asserted. */ +#define GPIO_104_SELECT FUNCTION0 /* WAKE#/GEVENT8# -> WAKEUP, low active */ +#define GPIO_105_SELECT FUNCTION2 /* SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) */ +#define GPIO_106_SELECT FUNCTION0 /* GBE_LED2/GEVENT10# -> GBE_LED2 */ +#define GPIO_107_SELECT FUNCTION0+NonGpio /* GBE_STAT0/GEVENT11# -> GBE_STAT0 */ +#define GPIO_108_SELECT FUNCTION2 /* USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active */ +/* [option for SPI_TPM_CS# in Hudson-M2 A12)] */ +#define GPIO_109_SELECT FUNCTION0 /* USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & */ +/* USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time */ +#define GPIO_110_SELECT FUNCTION2 /* USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, */ +/* plus judge GPIO40 and GPIO19 level,low is assert. */ +/* LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) */ +/* DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) */ +#define GPIO_111_SELECT FUNCTION1+NonGpio /* USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active */ +#define GPIO_112_SELECT FUNCTION2 /* USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, */ +/* low active, when it's low, BIOS will enbale ODD_PWR */ +#define GPIO_113_SELECT FUNCTION2 /* USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# */ +#define GPIO_114_SELECT FUNCTION2 /* BLINK/USB_OC7#/GEVENT18# -> BLINK */ +#define GPIO_115_SELECT FUNCTION0 /* SYS_RESET#/GEVENT19# -> SYS_RST# */ +#define GPIO_116_SELECT FUNCTION0 /* R_RX1/GEVENT20# -> IR INPUT */ +#define GPIO_117_SELECT FUNCTION1+NonGpio /* SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 */ +#define GPIO_118_SELECT FUNCTION1 /* RI#/GEVENT22# -> LID_CLOSED# */ +#define GPIO_119_SELECT FUNCTION0 /* LPC_SMI#/GEVENT23# -> EC_SMI */ #define GPIO_120_SELECT FUNCTION0+NonGpio #define GPIO_121_SELECT FUNCTION0+NonGpio #define GPIO_122_SELECT FUNCTION0+NonGpio @@ -268,78 +268,78 @@ #define GPIO_159_SELECT FUNCTION0+NonGpio #define GPIO_160_SELECT FUNCTION0+NonGpio -// S5-domain General Purpose I/O -#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# -#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 -#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 -#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 -#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 -#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. -#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, -#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE -#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 -#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# -#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 -#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 -#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO -#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR -#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 -#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 -#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# -#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE -#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE -// option for HDMI CEC signal OW ACTIVE -#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active -#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT -#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA -#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK -#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active -// RESERVED FOR LCD BACKLIGHT PWM -#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL -#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM -#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF -#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD +/* S5-domain General Purpose I/O */ +#define GPIO_161_SELECT FUNCTION0+NonGpio /* ROM_RST# */ +#define GPIO_162_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_163_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_164_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_165_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_166_SELECT FUNCTION1+NonGpio /* GBE_STAT2 */ +#define GPIO_167_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN0 */ +#define GPIO_168_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN1 */ +#define GPIO_169_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN2 */ +#define GPIO_170_SELECT FUNCTION1+NonGpio /* gating the power control signal for ODD, see BIOS requirements doc for detail. */ +#define GPIO_171_SELECT FUNCTION0+NonGpio /* TEMPIN0, */ +#define GPIO_172_SELECT FUNCTION1 /* used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE */ +#define GPIO_173_SELECT FUNCTION0+NonGpio /* TEMPIN3 */ +#define GPIO_174_SELECT FUNCTION1+NonGpio /* USED AS TALERT# */ +#define GPIO_175_SELECT FUNCTION1 /* WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_176_SELECT FUNCTION1+NonGpio /* WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_177_SELECT FUNCTION2+NonGpio /* WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_178_SELECT FUNCTION2 /* MEM_1V5 */ +#define GPIO_179_SELECT FUNCTION2 /* MEM_1V35 */ +#define GPIO_180_SELECT FUNCTION0+NonGpio /* Use as VIN VDDIO */ +#define GPIO_181_SELECT FUNCTION0+NonGpio /* Use as VIN VDDR */ +#define GPIO_182_SELECT FUNCTION1+NonGpio /* GBE_LED3 */ +#define GPIO_183_SELECT FUNCTION0+NonGpio /* GBE_LED0 */ +#define GPIO_184_SELECT FUNCTION1+NonGpio /* USED AS LLB# */ +#define GPIO_185_SELECT FUNCTION0+NonGpio /* USED AS USB */ +#define GPIO_186_SELECT FUNCTION0+NonGpio /* USED AS USB */ +#define GPIO_187_SELECT FUNCTION2 /* USED AS AC LED INDICATOR, LOW ACTIVE */ +#define GPIO_188_SELECT FUNCTION2 /* default used AS BATT LED INDICATOR, LOW ACTIVE */ +/* option for HDMI CEC signal OW ACTIVE */ +#define GPIO_189_SELECT FUNCTION1 /* USED AS AC_OK RECIEVER, INPUT, low active */ +#define GPIO_190_SELECT FUNCTION1 /* USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT */ +#define GPIO_191_SELECT FUNCTION0+NonGpio /* TOUCH PAD, DATA */ +#define GPIO_192_SELECT FUNCTION0+NonGpio /* TOUCH PAD, CLK */ +#define GPIO_193_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_194_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_195_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_196_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_197_SELECT FUNCTION2+NonGpio /* Default GPIO for LOM_POWER, high active */ +/* RESERVED FOR LCD BACKLIGHT PWM */ +#define GPIO_198_SELECT FUNCTION0+NonGpio /* IMC SCROLL LED CONTROL */ +#define GPIO_199_SELECT FUNCTION3 /* STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM */ +#define GPIO_200_SELECT FUNCTION2 /* NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF */ +#define GPIO_201_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_202_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_203_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_204_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_205_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_206_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_207_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_208_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_209_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_210_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_211_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_212_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_213_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_214_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_215_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_216_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_217_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_218_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_219_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_220_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_221_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_222_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_223_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_224_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_225_SELECT FUNCTION2+NonGpio /* KSO */ +#define GPIO_226_SELECT FUNCTION2+NonGpio /* KSO */ +#define GPIO_227_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_228_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_229_SELECT FUNCTION0+NonGpio /* DP1_HPD */ #define TYPE_GPI (1 << 5) #define TYPE_GPO (0 << 5) @@ -441,7 +441,7 @@ #define GPIO_94_TYPE TYPE_GPO #define GPIO_95_TYPE TYPE_GPO -// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 +/* GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 */ #define GPIO_96_TYPE TYPE_GPI #define GPIO_97_TYPE TYPE_GPI #define GPIO_98_TYPE TYPE_GPI @@ -753,13 +753,13 @@ #define GPO_169_LEVEL GPO_LOW #define GPO_170_LEVEL GPO_HI #define GPO_171_LEVEL GPO_LOW -#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +#define GPO_172_LEVEL GPO_HI /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */ #define GPO_173_LEVEL GPO_LOW #define GPO_174_LEVEL GPO_LOW #define GPO_175_LEVEL GPO_LOW #define GPO_176_LEVEL GPO_LOW #define GPO_177_LEVEL GPO_LOW -#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU +#define GPO_178_LEVEL GPO_HI /* AMD.SR BU to set VDDIO level to 1.5V for Barb BU */ #define GPO_179_LEVEL GPO_HI #define GPO_180_LEVEL GPO_HI #define GPO_181_LEVEL GPO_LOW @@ -1523,28 +1523,28 @@ #define GEVENT_00_EVENTENABLE EVENT_DISABLE #define GEVENT_01_EVENTENABLE EVENT_DISABLE -#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# -#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# -#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# -#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# +#define GEVENT_02_EVENTENABLE EVENT_ENABLE /* APU THERMTRIP# */ +#define GEVENT_03_EVENTENABLE EVENT_ENABLE /* EC_SCI# */ +#define GEVENT_04_EVENTENABLE EVENT_ENABLE /* APU_MEMHOT# */ +#define GEVENT_05_EVENTENABLE EVENT_ENABLE /* PCIE_EXPCARD_PWREN# */ #define GEVENT_06_EVENTENABLE EVENT_DISABLE #define GEVENT_07_EVENTENABLE EVENT_DISABLE #define GEVENT_08_EVENTENABLE EVENT_DISABLE -#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO +#define GEVENT_09_EVENTENABLE EVENT_ENABLE /* WF_RADIO */ #define GEVENT_10_EVENTENABLE EVENT_DISABLE #define GEVENT_11_EVENTENABLE EVENT_DISABLE -#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# +#define GEVENT_12_EVENTENABLE EVENT_ENABLE /* SMBALERT# */ #define GEVENT_13_EVENTENABLE EVENT_DISABLE -#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# -#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# -#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA -#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN +#define GEVENT_14_EVENTENABLE EVENT_ENABLE /* LASSO_DET#/DOCK# */ +#define GEVENT_15_EVENTENABLE EVENT_ENABLE /* ODD_PLUGIN# */ +#define GEVENT_16_EVENTENABLE EVENT_ENABLE /* ODD_DA */ +#define GEVENT_17_EVENTENABLE EVENT_ENABLE /* TWARN */ #define GEVENT_18_EVENTENABLE EVENT_DISABLE #define GEVENT_19_EVENTENABLE EVENT_DISABLE #define GEVENT_20_EVENTENABLE EVENT_DISABLE #define GEVENT_21_EVENTENABLE EVENT_DISABLE -#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# -#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# +#define GEVENT_22_EVENTENABLE EVENT_ENABLE /* LID_CLOSE# */ +#define GEVENT_23_EVENTENABLE EVENT_DISABLE /* EC_SMI# */ #define SCITRIG_LOW 0 #define SCITRIG_HI 1 @@ -2255,14 +2255,14 @@ typedef enum _GEVENT_COUNT typedef struct _GEVENT_SETTINGS { - u8 EventEnable; // 0: Disable, 1: Enable - u8 SciTrig; // 0: Falling Edge, 1: Rising Edge - u8 SciLevl; // 0: Edge trigger, 1: Level Trigger - u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI - u8 SciS0En; // 0: Disable, 1: Enable - u8 SciMap; // 0000b->1111b - u8 SmiTrig; // 0: Active Low, 1: Active High - u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 + u8 EventEnable; /* 0: Disable, 1: Enable */ + u8 SciTrig; /* 0: Falling Edge, 1: Rising Edge */ + u8 SciLevl; /* 0: Edge trigger, 1: Level Trigger */ + u8 SmiSciEn; /* 0: Not send SMI, 1: Send SMI */ + u8 SciS0En; /* 0: Disable, 1: Enable */ + u8 SciMap; /* 0000b->1111b */ + u8 SmiTrig; /* 0: Active Low, 1: Active High */ + u8 SmiControl; /* 0: Disable, 1: SMI 2: NMI 3: IRQ13 */ } GEVENT_SETTINGS; GEVENT_SETTINGS gevent_table[] = diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 947ec65..ae08ee1 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -22,8 +22,6 @@ #include <device/pci_def.h> #include <NbPlatform.h> -//#define SMBUS_IO_BASE 0x6000 - void set_pcie_reset(void *nbconfig); void set_pcie_dereset(void *nbconfig); @@ -42,7 +40,6 @@ void set_pcie_reset(void *nbconfig) */ void set_pcie_dereset(void *nbconfig) { - //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); u32 i; u32 val; u32 nb_addr; diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index a8b53d0..048ecaf 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -95,7 +95,6 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin)) /* SMBUS */ - //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0 /* HD Audio */ PCI_INT(0x0, 0x14, 0x2, 0x10); @@ -117,7 +116,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */ /* SATA */ - PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG + PCI_INT(0x0, 0x11, 0x0, 0x16); /*6, INTG */ /* PCI slots */ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h index f10e4d7..9afba97 100644 --- a/src/mainboard/amd/dinar/platform_cfg.h +++ b/src/mainboard/amd/dinar/platform_cfg.h @@ -21,30 +21,25 @@ /** * Max number of northbridges in the system */ -#define MAX_NB_COUNT 1 //TODO: only 1 NB tested +#define MAX_NB_COUNT 1 /* TODO: only 1 NB tested */ /** * Enable check for PCIe endpoint to be ready for PCI enumeration. * */ -//#define EPREADY_WORKAROUND_DISABLED /** * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. * */ -#define IOMMU_SUPPORT_DISABLE //TODO: enable it +#define IOMMU_SUPPORT_DISABLE /* TODO: enable it */ /** * Disable server PCIe hotplug support. */ -//#define HOTPLUG_SUPPORT_DISABLED - /** * Disable support for device number remapping for PCIe portsserver PCIe hotplug support. */ -//#define DEVICE_REMAP_DISABLE - -#endif //_PLATFORM_CFG_H_ +#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c index 5459200..733435d 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.c +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -32,7 +32,6 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) { u16 i; PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; - //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; DEFAULT_PLATFORM_CONFIG(platform_config); @@ -93,7 +92,7 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) } } } -#endif // __PRE_RAM__ +#endif /* __PRE_RAM__ */ /** * @brief Entry point of Northbridge CIMx callout/CallBack @@ -166,9 +165,9 @@ static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config) case CB_AmdSetMidPostConfig: nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR; -#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu +#ifndef IOMMU_SUPPORT_DISABLE /*TODO enable iommu */ /* SBIOS must alloc 16K memory for IOMMU MMIO */ - UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress + UINT32 MmcfgBarAddress; /*using default IOmmuBaseAddress */ LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, AccessWidth32, &MmcfgBarAddress, @@ -177,7 +176,7 @@ static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config) if (MmcfgBarAddress != 0) { nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; } - nbConfigPtr->IommuBaseAddress = 0; //disable iommu + nbConfigPtr->IommuBaseAddress = 0; /*disable iommu */ #endif break; @@ -235,10 +234,10 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON sbNode = (val >> 8) & 0x07; PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); - sbLink = (val >> 8) & 0x07; //assum ganged + sbLink = (val >> 8) & 0x07; /*assum ganged */ pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; - //TODO: other NBs + /* TODO: other NBs */ #ifndef __PRE_RAM__ /* If temporrary MMIO enable set up CPU MMIO */ diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h index 8645553..5b5a213 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.h +++ b/src/mainboard/amd/dinar/rd890_cfg.h @@ -142,7 +142,6 @@ DEFAULT_GPP2_CONFIG, \ DEFAULT_GPP3A_CONFIG, \ DEFAULT_HT_DEEMPASIES, \ - /*DEFAULT_HT_PATH,*/ \ DEFAULT_APIC_INTERRUPT_BASE, \ } @@ -150,17 +149,16 @@ * Platform configuration */ typedef struct { - UINT16 PortEnableMap; ///< Bitmap of enabled ports - UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 - UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug - UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors - UINT32 TemporaryMmio; ///< Temporary MMIO - UINT32 Gpp1Config; ///< Default PCIe GFX core configuration - UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration - UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration - UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level - // HT_PATH NbHtPath; ///< HT path to NB - UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. + UINT16 PortEnableMap; /* Bitmap of enabled ports */ + UINT16 PortGen1Map; /* Bitmap of ports to disable Gen2 */ + UINT16 PortHotplugMap; /* Bitmap of ports support hotplug */ + UINT8 PortHotplugDescriptors[8];/* Ports Hotplug descriptors */ + UINT32 TemporaryMmio; /* Temporary MMIO */ + UINT32 Gpp1Config; /* Default PCIe GFX core configuration */ + UINT32 Gpp2Config; /* Default PCIe GPP2 core configuration */ + UINT32 Gpp3aConfig; /* Default PCIe GPP3a core configuration */ + UINT8 NbTransmitterDeemphasis; /* HT transmitter de-emphasis level */ + UINT8 GlobalApicInterruptBase; /* Global APIC interrupt base that is used in MADT table for IO APIC. */ } NB_PLATFORM_CONFIG; /** @@ -168,4 +166,4 @@ typedef struct { */ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); -#endif //_RD890_CFG_H_ +#endif /* _RD890_CFG_H_ */ diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index bc5d312..a1b1e3b 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -64,7 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x33); report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); @@ -101,5 +101,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x44); copy_and_run(); - post_code(0x45); // Should never see this post code. + post_code(0x45); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c index 797bed8..2a5eae3 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.c +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -83,8 +83,8 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->SpreadSpectrum = 0; sb_config->PciClk5 = 0; sb_config->PciClks = 0x1F; - sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood - sb_config->TimerClockSource = 2; // Auto + sb_config->ResetCpuOnSyncFlood = 1; /* Do not reset CPU on sync flood */ + sb_config->TimerClockSource = 2; /* Auto */ sb_config->S3Resume = 0; sb_config->RebootRequired = 0; @@ -92,28 +92,28 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->HpetTimer = HPET_TIMER; /* USB */ - sb_config->UsbIntClock = 0; // Use external clock - sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 - sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 - sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 - sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 - sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 - sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 - sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 - sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable + sb_config->UsbIntClock = 0; /* Use external clock */ + sb_config->Usb1Ohci0 = 1; /* 0:disable 1:enable Bus 0 Dev 18 Func0 */ + sb_config->Usb1Ohci1 = 1; /* 0:disable 1:enable Bus 0 Dev 18 Func1 */ + sb_config->Usb1Ehci = 1; /* 0:disable 1:enable Bus 0 Dev 18 Func2 */ + sb_config->Usb2Ohci0 = 1; /* 0:disable 1:enable Bus 0 Dev 19 Func0 */ + sb_config->Usb2Ohci1 = 1; /* 0:disable 1:enable Bus 0 Dev 19 Func1 */ + sb_config->Usb2Ehci = 1; /* 0:disable 1:enable Bus 0 Dev 19 Func2 */ + sb_config->Usb3Ohci = 1; /* 0:disable 1:enable Bus 0 Dev 20 Func5 */ + sb_config->UsbOhciLegacyEmulation = 1; /* 0:Enable 1:Disable */ sb_config->AcpiS1Supported = 1; /* SATA */ sb_config->SataController = 1; - sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; /* 0 native, 1 raid, 2 ahci */ sb_config->SataSmbus = 0; sb_config->SataAggrLinkPmCap = 1; sb_config->SataPortMultCap = 1; sb_config->SataClkAutoOff = 1; - sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. - //TODO: set to secondary not take effect. - sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled + sb_config->SataIdeCombMdPriSecOpt = 0; /* 0 -IDE as primary, 1 -IDE as secondary. */ + /* TODO: set to secondary not take effect. */ + sb_config->SataIdeCombinedMode = 0; /* 1 IDE controlor exposed and combined mode enabled, 0 disabled */ sb_config->SataEspPort = 0; sb_config->SataClkAutoOffAhciMode = 1; sb_config->SataHpcpButNonESP = 0; @@ -134,7 +134,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->StdHeader.pCallBack = (CIM_HOOK_ENTRY)&sb700_callout_entry; } - //sb_config-> -#endif //!__PRE_RAM__ + /* sb_config-> */ +#endif /* !__PRE_RAM__ */ printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - End.\n", __func__); } diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h index 02c3934..65327bf 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.h +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -187,7 +187,6 @@ * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN -//#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN #define AZALIA_SDIN_PIN_0 0x2 #define AZALIA_SDIN_PIN_1 0x2 @@ -234,4 +233,4 @@ void sb700_cimx_config(AMDSBCFG *sb_cfg); */ u32 sb700_callout_entry(u32 func, u32 data, void* config); -#endif //_SB700_CFG_H_ +#endif /* _SB700_CFG_H_ */ diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 4b64055..4c64b47 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -135,7 +135,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -152,13 +152,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; } @@ -168,13 +168,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; } @@ -184,13 +184,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c index d1f715c..8bcf666 100644 --- a/src/mainboard/amd/inagua/OemCustomize.c +++ b/src/mainboard/amd/inagua/OemCustomize.c @@ -48,25 +48,25 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -75,13 +75,13 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS + /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1) }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA + /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), @@ -96,11 +96,10 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) &DdiList[0] }; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h index 2d8381b..7a9c03f 100644 --- a/src/mainboard/amd/inagua/OptionsIds.h +++ b/src/mainboard/amd/inagua/OptionsIds.h @@ -43,14 +43,6 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h index 60045e1..fd92667 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h @@ -20,44 +20,44 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c index 640f639..92b5931 100644 --- a/src/mainboard/amd/inagua/broadcom.c +++ b/src/mainboard/amd/inagua/broadcom.c @@ -26,28 +26,28 @@ #include <types.h> #include <console/console.h> -#include <device/device.h> //Coreboot device access +#include <device/device.h> /* Coreboot device access */ #include <device/pci.h> #include <delay.h> #include <endian.h> void broadcom_init(void); -#define be16(x) cpu_to_be16(x) //a little easier to type -#define be(x) cpu_to_be32(x) //this is used a lot! +#define be16(x) cpu_to_be16(x) /* a little easier to type */ +#define be(x) cpu_to_be32(x) /* this is used a lot! */ /* C forces us to specify these before defining struct selfboot_patch :-( */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF #define INIT1_LENGTH 9 #define INIT2_LENGTH 10 #define INIT3_LENGTH 3 -#define INIT4_LENGTH 7 //this one may be 0 +#define INIT4_LENGTH 7 /* this one may be 0 */ #define PWRDN_LENGTH 5 #else #define INIT1_LENGTH 13 #define INIT2_LENGTH 6 #define INIT3_LENGTH 3 -#define INIT4_LENGTH 11 //this one may be 0 +#define INIT4_LENGTH 11 /* this one may be 0 */ #define PWRDN_LENGTH 4 #endif @@ -106,61 +106,61 @@ void broadcom_init(void); * not supported. */ -static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! +static struct selfboot_patch { /* Watch out: all values are *BIG-ENDIAN*! */ struct { /* Global header */ - u8 signature; //0xA5 - u8 format; //bits 7-3: patch format; 2-0: revision + u8 signature; /* 0xA5 */ + u8 format; /* bits 7-3: patch format; 2-0: revision */ u8 mac_addr[6]; - u16 subsys_device; //IDs will be loaded into PCI config space + u16 subsys_device; /* IDs will be loaded into PCI config space */ u16 subsys_vendor; - u16 pci_device; //PCI device ID; vendor is always Broadcom (0x14E4) - u8 unknown1[8]; //?, noticed no effect - u16 basic_config; //?, see below - u8 checksum; //byte sum of header == 0 - u8 unknown2; //?, patch rejected if changed - u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...) + u16 pci_device; /* PCI device ID; vendor is always Broadcom (0x14E4) */ + u8 unknown1[8]; /* ?, noticed no effect */ + u16 basic_config; /* ?, see below */ + u8 checksum; /* byte sum of header == 0 */ + u8 unknown2; /* ?, patch rejected if changed */ + u16 patch_version; /* 10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...) */ } header; struct { /* Init code */ - u8 checksum; //byte sum of init == 0 - u8 unknown; //?, looks unused - u8 num_hunks; //0x60 = 3 hunks, 0x80 = 4 hunks, other values not supported - u8 size; //total size of all hunk#_code[] in bytes - u8 hunk1_when; //mark when hunk1_code gets executed - u8 hunk1_size; //sizeof(hunk1_code) + u8 checksum; /* byte sum of init == 0 */ + u8 unknown; /* ?, looks unused */ + u8 num_hunks; /* 0x60 = 3 hunks, 0x80 = 4 hunks, other values not supported */ + u8 size; /* total size of all hunk#_code[] in bytes */ + u8 hunk1_when; /* mark when hunk1_code gets executed */ + u8 hunk1_size; /* sizeof(hunk1_code) */ u8 hunk2_when; u8 hunk2_size; u8 hunk3_when; u8 hunk3_size; - u8 hunk4_when; //0x00 (padding) if only 3 hunks - u8 hunk4_size; //dito - u32 hunk1_code[INIT1_LENGTH]; //actual commands, see below + u8 hunk4_when; /* 0x00 (padding) if only 3 hunks */ + u8 hunk4_size; /* dito */ + u32 hunk1_code[INIT1_LENGTH]; /* actual commands, see below */ u32 hunk2_code[INIT2_LENGTH]; u32 hunk3_code[INIT3_LENGTH]; - u32 hunk4_code[INIT4_LENGTH]; //missing (zero length) if only 3 hunks + u32 hunk4_code[INIT4_LENGTH]; /* missing (zero length) if only 3 hunks */ } init; struct { /* Power down code */ - u8 checksum; //byte sum of powerdown == 0 - u8 unknown; //?, looks unused - u8 num_hunks; //0x20 = 1 hunk, other values not supported - u8 size; //total size of all hunk#_code[] in bytes - u8 hunk1_when; //mark when hunk1_code gets executed - u8 hunk1_size; //sizeof(hunk1_code) - u16 padding; //0x0000, hunk2 is not supported - u32 hunk1_code[PWRDN_LENGTH]; //commands, see below + u8 checksum; /* byte sum of powerdown == 0 */ + u8 unknown; /* ?, looks unused */ + u8 num_hunks; /* 0x20 = 1 hunk, other values not supported */ + u8 size; /* total size of all hunk#_code[] in bytes */ + u8 hunk1_when; /* mark when hunk1_code gets executed */ + u8 hunk1_size; /* sizeof(hunk1_code) */ + u16 padding; /* 0x0000, hunk2 is not supported */ + u32 hunk1_code[PWRDN_LENGTH]; /* commands, see below */ } powerdown; } selfboot_patch = { /* Keep the following invariant for valid Selfboot patches */ .header.signature = 0xA5, - .header.format = 0x23, //format 1 revision 3 + .header.format = 0x23, /* format 1 revision 3 */ .header.unknown1 = { 0x61, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - .header.checksum = 0, //calculated later + .header.checksum = 0, /* calculated later */ .header.unknown2 = 0x30, - .init.checksum = 0, //calculated later + .init.checksum = 0, /* calculated later */ .init.unknown = 0x00, .init.num_hunks = sizeof(selfboot_patch.init.hunk4_code) ? 0x80 : 0x60, .init.size = sizeof(selfboot_patch.init.hunk1_code) @@ -171,7 +171,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! .init.hunk2_size = sizeof(selfboot_patch.init.hunk2_code), .init.hunk3_size = sizeof(selfboot_patch.init.hunk3_code), .init.hunk4_size = sizeof(selfboot_patch.init.hunk4_code), - .powerdown.checksum = 0, //calculated later + .powerdown.checksum = 0, /* calculated later */ .powerdown.unknown = 0x00, .powerdown.num_hunks = 0x20, .powerdown.size = sizeof(selfboot_patch.powerdown.hunk1_code), @@ -180,19 +180,19 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! /* Only the lines below may be adapted to your needs ... */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - .header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, //Broadcom - .header.subsys_device = be16(0x1699), //same as pci_device - .header.subsys_vendor = be16(0x14E4), //Broadcom + .header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, /* Broadcom */ + .header.subsys_device = be16(0x1699), /* same as pci_device */ + .header.subsys_vendor = be16(0x14E4), /* Broadcom */ #else - .header.mac_addr = { 0x00, 0x20, 0x9D, 0x00, 0x00, 0x00 }, //LiPPERT - .header.subsys_device = be16(0x1699), //simply kept this - .header.subsys_vendor = be16(0x121D), //LiPPERT + .header.mac_addr = { 0x00, 0x20, 0x9D, 0x00, 0x00, 0x00 }, /* LiPPERT */ + .header.subsys_device = be16(0x1699), /* simply kept this */ + .header.subsys_vendor = be16(0x121D), /* LiPPERT */ #endif - .header.pci_device = be16(0x1699), //Broadcom 5785 with GbE PHY + .header.pci_device = be16(0x1699), /* Broadcom 5785 with GbE PHY */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - .header.patch_version = be16(0x010B), //1.11 (Broadcom's sb5785m1.11) + .header.patch_version = be16(0x010B), /* 1.11 (Broadcom's sb5785m1.11) */ #else - .header.patch_version = be16(0x110B), //1.11b, i.e. hacked :-) + .header.patch_version = be16(0x110B), /* 1.11b, i.e. hacked :-) */ #endif /* Bitfield enabling general features/codepaths in the firmware or * selecting support for one of several supported PHYs? @@ -209,9 +209,9 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! * 1 X 1 | 0x391C6140 - - - */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - .header.basic_config = be16(0x0404), //original for B50610 + .header.basic_config = be16(0x0404), /* original for B50610 */ #else - .header.basic_config = be16(0x0604), //bit 9 set so not to mess up PHY regs, kept other bits unchanged + .header.basic_config = be16(0x0604), /* bit 9 set so not to mess up PHY regs, kept other bits unchanged */ #endif /* Tag that defines when / on what occasion the commands are interpreted. @@ -223,7 +223,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! * 68, 20, 70, 80 to be interpreted in this order. * All tests were performed with .basic_config = 0x0604. */ - .init.hunk1_when = 0x10, //only once at RISC CPU reset? + .init.hunk1_when = 0x10, /* only once at RISC CPU reset? */ /* Instructions are obviously a specialized bytecode interpreted by the * main firmware, rather than MIPS machine code. Commands consist of 1-3 * 32-bit words. In the following, 0-9,A-F = hex literals, a-z,_ = variable @@ -245,69 +245,68 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! */ .init.hunk1_code = { #if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0x082B8104), //CFR-AF: PHY0B: KSZ9021 select PHY104 - be(0x082CF0F0), //CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel) - be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105 - be(0x082C3333), //CFR-AF: PHY0C: KSZ9021 RX data skew (empirical) + be(0x082B8104), /* CFR-AF: PHY0B: KSZ9021 select PHY104 */ + be(0x082CF0F0), /* CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel) */ + be(0x082B8105), /* CFR-AF: PHY0B: KSZ9021 select PHY105 */ + be(0x082C3333), /* CFR-AF: PHY0C: KSZ9021 RX data skew (empirical) */ #endif - be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12 = 1: auto-clock-switch - be(0x06100D34), be(0x00000000), //v1.03 : MemD34: clear config vars - be(0x06100D38), be(0x00000000), //v1.03 : - | - be(0x06100D3C), be(0x00000000), //v1.03 : MemD3F| - }, //-->INIT1_LENGTH! + be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), /* v1.05 : 5A0.24,12 = 1: auto-clock-switch */ + be(0x06100D34), be(0x00000000), /* v1.03 : MemD34: clear config vars */ + be(0x06100D38), be(0x00000000), /* v1.03 : - | */ + be(0x06100D3C), be(0x00000000), /* v1.03 : MemD3F| */ + }, /* -->INIT1_LENGTH! */ - .init.hunk2_when = 0x30, //after global reset, PHY reset + .init.hunk2_when = 0x30, /* after global reset, PHY reset */ .init.hunk2_code = { #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0x08370F08), //v1.06 : PHY17: B50610 select reg. 08 - be(0x08350001), //v1.06 : PHY15: B50610 slow link fix - be(0x08370F00), //v1.06 : PHY17: B50610 disable reg. 08 - be(0x083C2C00), //v1.11 : PHY1C: B50610 Shadow 0B + be(0x08370F08), /* v1.06 : PHY17: B50610 select reg. 08 */ + be(0x08350001), /* v1.06 : PHY15: B50610 slow link fix */ + be(0x08370F00), /* v1.06 : PHY17: B50610 disable reg. 08 */ + be(0x083C2C00), /* v1.11 : PHY1C: B50610 Shadow 0B */ #endif - be(0xF7F301E6), //v1.09+: ?: subroutine calls to - be(0xF7FFF0B6), be(0x0000FFE7), //v1.09+: ?| restore Port Mode ??? - be(0xF7FFF0F6), be(0x00008000), //v1.09+: ?| - be(0xF7F401E6), //v1.09+: ?| - }, //-->INIT2_LENGTH! + be(0xF7F301E6), /* v1.09+: ?: subroutine calls to */ + be(0xF7FFF0B6), be(0x0000FFE7), /* v1.09+: ?| restore Port Mode ??? */ + be(0xF7FFF0F6), be(0x00008000), /* v1.09+: ?| */ + be(0xF7F401E6), /* v1.09+: ?| */ + }, /* -->INIT2_LENGTH! */ - .init.hunk3_when = 0xA8, //?, I'd guess quite late + .init.hunk3_when = 0xA8, /* ?, I'd guess quite late */ .init.hunk3_code = { - be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), //v1.08 : 3604.20-16: 10Mb clock = 12.5MHz - }, //-->INIT3_LENGTH! + be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), /* v1.08 : 3604.20-16: 10Mb clock = 12.5MHz */ + }, /* -->INIT3_LENGTH! */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - .init.hunk4_when = 0xD8, //original for B50610 + .init.hunk4_when = 0xD8, /* original for B50610 */ #else - .init.hunk4_when = 0x80, //run last, after Linux' "ifconfig up" + .init.hunk4_when = 0x80, /* run last, after Linux' "ifconfig up" */ #endif .init.hunk4_code = { #if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0x083F4300), //CFR-AF: PHY1F: IRQ active high - be(0x083C0000), //CFR-AF: PHY1C: revert driver writes - be(0x08380000), //CFR-AF: PHY18| - be(0x083C0000), //CFR-AF: PHY1C| + be(0x083F4300), /* CFR-AF: PHY1F: IRQ active high */ + be(0x083C0000), /* CFR-AF: PHY1C: revert driver writes */ + be(0x08380000), /* CFR-AF: PHY18| */ + be(0x083C0000), /* CFR-AF: PHY1C| */ #endif - be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0 == 1 -->skip next 12 bytes + be(0xCB0005A4), be(0xF7F0000C), /* v1.01 : if 5A4.0 == 1 -->skip next 12 bytes */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode + be(0xC61005A4), be(0x3210C500), /* v1.01 : 5A4: PHY LED mode */ #else - be(0xC61005A4), be(0x331C71CE), //CFR-AF: 5A4: fake LED mode + be(0xC61005A4), be(0x331C71CE), /* CFR-AF: 5A4: fake LED mode */ #endif - be(0xF7F00008), //v1.01 : -->skip next 8 bytes - be(0xC61005A4), be(0x331C71C1), //v1.01 : 5A4: inband LED mode - //be(0xC3200454), //CFR-AF: 454.4: auto link polling - }, //-->INIT4_LENGTH! + be(0xF7F00008), /* v1.01 : -->skip next 8 bytes */ + be(0xC61005A4), be(0x331C71C1), /* v1.01 : 5A4: inband LED mode */ + }, /* -->INIT4_LENGTH! */ - .powerdown.hunk1_when = 0x50, //prior to IDDQ MAC + .powerdown.hunk1_when = 0x50, /* prior to IDDQ MAC */ .powerdown.hunk1_code = { #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY + be(0x083CB001), /* v1.10 : PHY1C: IDDQ B50610 PHY */ #endif - be(0xF7F30116), // IDDQ PHY - be(0xC40005A0), //v1.09 : 5A0.0 = 0: Port Mode = MII - be(0xC4180400), //v1.09 : 400.3 = 0| - be(0xC3100400), //v1.09 : 400.2 = 1| - }, //-->PWRDN_LENGTH! + be(0xF7F30116), /* IDDQ PHY */ + be(0xC40005A0), /* v1.09 : 5A0.0 = 0: Port Mode = MII */ + be(0xC4180400), /* v1.09 : 400.3 = 0| */ + be(0xC3100400), /* v1.09 : 400.2 = 1| */ + }, /* -->PWRDN_LENGTH! */ }; @@ -316,8 +315,8 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! */ void broadcom_init(void) { - volatile u32 *gec_base; //Gigabit Ethernet Controller base addr - u8 *gec_shadow; //base addr of shadow 'NV'RAM for GbE MAC in A55E + volatile u32 *gec_base; /* Gigabit Ethernet Controller base addr */ + u8 *gec_shadow; /* base addr of shadow 'NV'RAM for GbE MAC in A55E */ u8 sum; int i; @@ -327,8 +326,8 @@ void broadcom_init(void) /* Halt RISC CPU before uploading the firmware patch */ for (i = 10000; i > 0; i--) { - gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state - gec_base[0x5000/4] |= (1 << 10); //issue RISC halt + gec_base[0x5004/4] = 0xFFFFFFFF; /* clear CPU state */ + gec_base[0x5000/4] |= (1 << 10); /* issue RISC halt */ if (gec_base[0x5000/4] | (1 << 10)) break; udelay(10); @@ -349,10 +348,10 @@ void broadcom_init(void) /* Upload firmware patch to shadow 'NV'RAM */ for (i = 0; i < sizeof(selfboot_patch); i++) - gec_shadow[i] = ((u8*)&selfboot_patch)[i]; //access byte-wise! + gec_shadow[i] = ((u8*)&selfboot_patch)[i]; /* access byte-wise! */ /* Restart BCM5785's CPU */ - gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state - gec_base[0x5000/4] = 0x00000001; //reset RISC processor - //usually we'd have to wait for the reset bit to clear again ... + gec_base[0x5004/4] = 0xFFFFFFFF; /* clear CPU state */ + gec_base[0x5000/4] = 0x00000001; /* reset RISC processor */ + /* usually we'd have to wait for the reset bit to clear again ... */ } diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 1c5c424..883dd85 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -74,7 +74,6 @@ #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE @@ -94,10 +93,7 @@ #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE @@ -106,65 +102,24 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 #define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE #define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 + #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE @@ -172,8 +127,6 @@ #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY @@ -181,16 +134,6 @@ #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE @@ -249,41 +192,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long +/* This is the delivery package title, "BrazosPI" */ +/* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long +/* This is the release version number of the AGESA component */ +/* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -292,5 +236,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data. */ #include "PlatformInstall.h" diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index d8e4f05..d7ca419 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -88,7 +88,6 @@ static void mainboard_enable(device_t dev) /* Upload AMD A55E GbE 'NV'RAM contents. Still untested on Inagua. * After anyone can confirm it works please uncomment the call. */ - //broadcom_init(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 2deb219..6053ac4 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -86,7 +86,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index d39a3ab..ea46291 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -161,7 +161,7 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA + #define AZALIA_SDIN_PIN 0x2A /** diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c index 2c633e5..221b4b3 100644 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -175,8 +175,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; //6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5; */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /* 6 | BIT3; */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -212,7 +212,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /* BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; @@ -247,7 +247,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; @@ -258,7 +258,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; @@ -268,7 +268,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;/* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, @@ -296,7 +296,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); /* Turn on FCH GPP slots */ diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index 0fec106..25e685b 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -108,9 +108,6 @@ const u8 mainboard_intr_data[] = { * use PIC IRQ 10 if it uses PIN A for its hardware INT. */ static const struct pirq_struct mainboard_pirq_data[] = { - /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ -// {GFX_DEVFN, {PIRQ_GFX, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ -// {ACTL_DEVFN, {PIRQ_NC, PIRQ_ACTL, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J119: 02.1 */ {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J118: 03.1 */ {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J120: 03.2 */ diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 9bf3a67..09a38bd 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -56,35 +56,6 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0xA8, word); } -#if 0 /* not tested yet */ -/******************************************************** -* mahogany uses SB700 GPIO9 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 5); /* Set Gpio9 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif /* get_ide_dma66 */ - u8 is_dev3_present(void) { return 0; diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index 708ddbd..9357b42 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 8c244d4..b197d36 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -56,35 +56,6 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0xA8, word); } -#if 0 /* not tested yet. */ -/******************************************************** -* mahogany uses SB700 GPIO9 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 5); /* Set Gpio9 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif /* get_ide_dma66() */ - u8 is_dev3_present(void) { return 0; diff --git a/src/mainboard/amd/mahogany_fam10/resourcemap.c b/src/mainboard/amd/mahogany_fam10/resourcemap.c index 95d009a..013f658 100644 --- a/src/mainboard/amd/mahogany_fam10/resourcemap.c +++ b/src/mainboard/amd/mahogany_fam10/resourcemap.c @@ -45,7 +45,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -83,7 +83,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -131,7 +131,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,7 +165,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,7 +191,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -223,7 +220,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -264,7 +260,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 1ee6698..0eda964 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/*used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -102,12 +100,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -166,10 +162,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -196,8 +192,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -208,21 +202,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 2361c03..e4be6e5 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -45,20 +45,20 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); * AMD Olivehill Platform ALC272 Verb Table */ static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT + {0x11, 0x411111F0}, /* - SPDIF_OUT2 */ + {0x12, 0x411111F0}, /* - DMIC_1/2 */ + {0x13, 0x411111F0}, /* - DMIC_3/4 */ + {0x14, 0x411111F0}, /* Port D - LOUT1 */ + {0x15, 0x411111F0}, /* Port A - LOUT2 */ + {0x16, 0x411111F0}, + {0x17, 0x411111F0}, /* Port H - MONO */ + {0x18, 0x01a19840}, /* Port B - MIC1 */ + {0x19, 0x411111F0}, /* Port F - MIC2 */ + {0x1a, 0x01813030}, /* Port C - LINE1 */ + {0x1b, 0x411111F0}, /* Port E - LINE2 */ + {0x1d, 0x40130605}, /* - PCBEEP */ + {0x1e, 0x01441120}, /* - SPDIF_OUT1 */ + {0x21, 0x01214010}, /* Port I - HPOUT */ {0xff, 0xffffffff} }; @@ -126,8 +126,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5; */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; /* 6 | BIT3; */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -138,7 +138,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /* AC0 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ @@ -161,7 +161,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111; /* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, @@ -190,7 +190,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h index eaf2442..bf623f7 100644 --- a/src/mainboard/amd/olivehill/OptionsIds.h +++ b/src/mainboard/amd/olivehill/OptionsIds.h @@ -43,17 +43,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 1d3fe77..d334604 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -53,36 +53,22 @@ #endif #endif -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE /* TRUE */ +#define BLDOPT_REMOVE_SLIT FALSE /* TRUE */ +#define BLDOPT_REMOVE_WHEA FALSE /* TRUE */ #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/*This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -104,11 +90,11 @@ #define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 /* Specifies the IO addresses trapped by the */ + /* core for C-state entry requests. A value */ + /* of 0 in this field specifies that the core */ + /* does not trap any IO addresses for C-state entry. */ + /* Values greater than 0xFFF8 results in undefined behavior. */ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE @@ -149,15 +135,10 @@ #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled #define BLDCFG_IOMMU_SUPPORT FALSE #define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL #define BLDCFG_CFG_ABM_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID #ifdef PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS @@ -174,43 +155,6 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = { @@ -244,40 +188,21 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE*/ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* QUANDRANK_TYPE*/ + +/* USER_MEMORY_TIMING_MODE */ + +/* POWER_DOWN_MODE */ /* * Agesa optional capabilities selection. @@ -322,17 +247,16 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL olivehill_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, {-1} }; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 9ae75ae..a540d0d 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; @@ -102,45 +101,7 @@ static void *smp_write_config_table(void *v) outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } -#if 0 - outb(0x0B, 0xCD6); - outb(0x02, 0xCD7); - outb(0x50, 0xCD6); - outb(0x1F, 0xCD7); - - outb(0x48, 0xCD6); - outb(0xF2, 0xCD7); - - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - - outb(0xED, 0xCD6); - outb(0x17, 0xCD7); - - *(volatile u8 *) (0xFED80D00 + 0x31) = 2; - *(volatile u8 *) (0xFED80D00 + 0x32) = 2; - *(volatile u8 *) (0xFED80D00 + 0x33) = 2; - *(volatile u8 *) (0xFED80D00 + 0x34) = 2; - - *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; - *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; - *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; - - *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; - *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; - *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; - *(volatile u8 *) (0xFED80100 + 0xA6) = 0; - - *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; -#endif /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c index 9528f72..82c8911 100644 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c @@ -49,20 +49,20 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); * Realtek ALC272 CODEC Verb Table */ static const CODEC_ENTRY Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40251E05}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT + {0x11, 0x411111F0}, /* - SPDIF_OUT2 */ + {0x12, 0x411111F0}, /* - DMIC_1/2 */ + {0x13, 0x411111F0}, /* - DMIC_3/4 */ + {0x14, 0x411111F0}, /* Port D - LOUT1 */ + {0x15, 0x411111F0}, /* Port A - LOUT2 */ + {0x16, 0x411111F0}, + {0x17, 0x411111F0}, /* Port H - MONO */ + {0x18, 0x01a19840}, /* Port B - MIC1 */ + {0x19, 0x411111F0}, /* Port F - MIC2 */ + {0x1a, 0x01813030}, /* Port C - LINE1 */ + {0x1b, 0x411111F0}, /* Port E - LINE2 */ + {0x1d, 0x40251E05}, /* - PCBEEP */ + {0x1e, 0x01441120}, /* - SPDIF_OUT1 */ + {0x21, 0x01214010}, /* Port I - HPOUT */ {0xff, 0xffffffff} }; @@ -141,8 +141,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; //6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; /* 6 | BIT3 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -178,7 +178,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /* BIT0 | BIT2 | BIT5 */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; @@ -213,7 +213,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; @@ -224,7 +224,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; @@ -234,7 +234,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; /* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, @@ -262,7 +262,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index 925526c..75a5798 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 6d1e4ea..9b14013 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -91,7 +91,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); AGESAWRAPPER(amdinitpost); - //PspMboxBiosCmdDramInfo(); post_code(0x41); AGESAWRAPPER(amdinitenv); /* diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index c83e318..1a97bb7 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -126,8 +126,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;/* 6 | BIT3 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -138,7 +138,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ @@ -161,7 +161,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111; /* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, @@ -190,7 +190,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h index eaf2442..bf623f7 100644 --- a/src/mainboard/amd/parmer/OptionsIds.h +++ b/src/mainboard/amd/parmer/OptionsIds.h @@ -43,17 +43,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 8ba3c53..8f6db7a 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -50,35 +50,22 @@ #define INSTALL_FM2_SOCKET_SUPPORT FALSE -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/* This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -126,7 +113,7 @@ #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 /* PCIE Spread Spectrum default value 0.36% */ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 #define BLDOPT_REMOVE_ALIB FALSE @@ -138,16 +125,10 @@ #define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 #define BLDCFG_CFG_ABM_SUPPORT 0 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity +/* Specify the default values for the VRM controlling the VDDNB plane. + * If not specified, the values used for the core VRM will be applied + */ #define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 @@ -157,17 +138,14 @@ #if CONFIG_GFXUMA #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000/*512M */ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif #define BLDCFG_IOMMU_SUPPORT FALSE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + /* Process the options... * This file include MUST occur AFTER the user option selection settings @@ -175,43 +153,7 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = { @@ -245,40 +187,40 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define DDR2100_FREQUENCY 1050 /* DDR 2100 */ +#define DDR2133_FREQUENCY 1066 /* DDR 2133 */ +#define DDR2400_FREQUENCY 1200 /* DDR 2400 */ +#define UNSUPPORTED_DDR_FREQUENCY 1201 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ /* * Agesa optional capabilities selection. @@ -323,7 +265,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL parmer_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, @@ -331,9 +272,10 @@ GPIO_CONTROL parmer_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&parmer_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index e10fc89..b630b71 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index b0b79ab..2cf07ed 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -40,8 +40,9 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); /* Call the host environment interface to provide a user hook opportunity. */ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) { - // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. - // Make sure the right speed settings are selected. + /* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. + * Make sure the right speed settings are selected. + */ ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } @@ -60,7 +61,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -72,7 +73,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; switch (ResetInfo->ResetId) { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + case 46: /* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */ switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index 825364e..dd99fe4 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -46,31 +46,31 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -79,18 +79,18 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeLvds, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} } }; @@ -102,11 +102,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &DdiList[0] }; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h index 2d8381b..7a9c03f 100644 --- a/src/mainboard/amd/persimmon/OptionsIds.h +++ b/src/mainboard/amd/persimmon/OptionsIds.h @@ -43,14 +43,6 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index 4132c7c..40489cc 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -21,45 +21,45 @@ #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 670010d..07a52e2 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -74,7 +74,6 @@ #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE @@ -94,10 +93,7 @@ #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE @@ -106,65 +102,24 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 #define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE #define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 + #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE @@ -172,8 +127,6 @@ #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY @@ -181,16 +134,6 @@ #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE @@ -249,41 +192,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long +/* This is the delivery package title, "BrazosPI" */ +/* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long +/* This is the release version number of the AGESA component */ +/* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -292,5 +236,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data. */ #include "PlatformInstall.h" diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 8e954cd..c726875 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 660be41..648ee17 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -161,7 +161,7 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA + #define AZALIA_SDIN_PIN 0x2A /** diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index ddc232f..282222d 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -80,7 +80,7 @@ unsigned long acpi_fill_madt(unsigned long current) for(i = 1; i< sysconf.hc_possible_num; i++) { u32 d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; - // 8131 need to use +4 + /* 8131 need to use +4 */ switch (sysconf.hcid[i]) { case 1: d = 7; @@ -141,15 +141,15 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp int i; - get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; - //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table + /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ - for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; @@ -160,16 +160,16 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp c = (u8) ('A' + i - 1 - 6); } current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt + printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */ ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { - case 1: //8132 + case 1: /* 8132 */ file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; - case 2: //8151 + case 2: /* 8151 */ file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; - case 3: //8131 + case 3: /* 8131 */ file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c index 6bb03e9..6cf5197 100644 --- a/src/mainboard/amd/serengeti_cheetah/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah/fadt.c @@ -41,11 +41,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; - // disable system management mode by setting to 0: - fadt->smi_cmd = 0;//pm_base+0x2f; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0;/* pm_base+0x2f */ fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; fadt->s4bios_req = 0x0; @@ -75,10 +75,10 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->flush_stride = 0; fadt->duty_offset = 1; fadt->duty_width = 3; - fadt->day_alrm = 0; // 0x7d these have to be - fadt->mon_alrm = 0; // 0x7e added to cmos.layout - fadt->century = 0; // 0x7f to make rtc alrm work - fadt->iapc_boot_arch = 0x3; // See table 5-11 + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ fadt->flags = 0x25; fadt->res2 = 0; diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index 1eb97b5..b7f55fd 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -23,30 +23,18 @@ #include <stdlib.h> #include "mb_sysconf.h" -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ struct mb_sysconf_t mb_sysconf; -static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +static unsigned pci1234x[] = { /*Here you only need to set value in pci1234 for HT-IO that could be installed or not */ + /* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */ 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 }; -static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most +static unsigned hcdnx[] = { /* HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */ 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, }; static unsigned get_bus_conf_done = 0; @@ -64,20 +52,20 @@ static unsigned get_hcid(unsigned i) dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); switch (dev->device) { - case 0x7458: //8132 + case 0x7458: /*8132 */ id = 1; break; - case 0x7454: //8151 + case 0x7454: /*8151 */ id = 2; break; - case 0x7450: //8131 + case 0x7450: /*8131 */ id = 3; break; } - // we may need more way to find out hcid: subsystem id? GPIO read ? + /* we may need more way to find out hcid: subsystem id? GPIO read ? */ - // we need use id for 1. bus num, 2. mptable, 3. ACPI table + /* we need use id for 1. bus num, 2. mptable, 3. ACPI table */ return id; } @@ -92,7 +80,7 @@ void get_bus_conf(void) struct mb_sysconf_t *m; if (get_bus_conf_done == 1) - return; //do it only once + return; /* do it only once */ get_bus_conf_done = 1; @@ -150,13 +138,13 @@ void get_bus_conf(void) if (!(sysconf.pci1234[i] & 0x1)) continue; - // check hcid type here + /* check hcid type here */ sysconf.hcid[i] = get_hcid(i); switch (sysconf.hcid[i]) { - case 1: //8132 - case 3: //8131 + case 1: /* 8132 */ + case 3: /* 8131 */ m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; @@ -190,7 +178,7 @@ void get_bus_conf(void) break; - case 2: //8151 + case 2: /* 8151 */ m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; m->sbdn5[j] = sysconf.hcdn[i] & 0xff; @@ -202,7 +190,6 @@ void get_bus_conf(void) if (dev) { m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - // printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", @@ -215,7 +202,7 @@ void get_bus_conf(void) j++; } -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address */ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) apicid_base = get_apicid_base(3); else @@ -227,5 +214,4 @@ void get_bus_conf(void) m->apicid_8132a[i][0] = apicid_base + 3 + i * 2; m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1; } - } diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c index 3d9820f..9e2e09b 100644 --- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c @@ -55,7 +55,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct mb_sysconf_t *m; - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ m = sysconf.mb; @@ -105,7 +105,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) } } -//pci bridge +/* pci bridge */ printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n"); static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 }; pci_assign_irqs(m->bus_8111_0, sysconf.sbdn + 1, slotIrqs_1_4); @@ -123,9 +123,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info++; slot_num++; -//pcix bridge -// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; +/* pcix bridge */ int j = 0; @@ -157,5 +155,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "done.\n"); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 2ffe4c9..fc421a9 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -41,8 +41,8 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); -/*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111 +/* I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */ { device_t dev; struct resource *res; @@ -69,8 +69,8 @@ static void *smp_write_config_table(void *v) if(!(sysconf.pci1234[i] & 0x1) ) continue; switch(sysconf.hcid[i]) { - case 1: // 8132 - case 3: // 8131 + case 1: /* 8132 */ + case 3: /* 8131 */ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -97,33 +97,33 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -//??? What +/* ??? What */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); -// Onboard AMD USB +/* Onboard AMD USB */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); -//Slot 3 PCI 32 +/*Slot 3 PCI 32 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */ } -//Slot 4 PCI 32 +/* Slot 4 PCI 32 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */ } -//Slot 1 PCI-X 133/100/66 +/* Slot 1 PCI-X 133/100/66 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); } -//Slot 2 PCI-X 133/100/66 +/* Slot 2 PCI-X 133/100/66 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */ } j = 0; @@ -140,9 +140,9 @@ static void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - //Slot 1 PCI-X 133/100/66 + /* Slot 1 PCI-X 133/100/66 */ for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); } } } @@ -151,9 +151,9 @@ static void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - //Slot 2 PCI-X 133/100/66 + /* Slot 2 PCI-X 133/100/66 */ for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); /* 25 */ } } } @@ -161,7 +161,7 @@ static void *smp_write_config_table(void *v) break; case 2: - // Slot AGP + /* Slot AGP */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); break; } diff --git a/src/mainboard/amd/serengeti_cheetah/resourcemap.c b/src/mainboard/amd/serengeti_cheetah/resourcemap.c index 3126dd3..92eaa9c 100644 --- a/src/mainboard/amd/serengeti_cheetah/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah/resourcemap.c @@ -260,8 +260,8 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, // AMD 8151 on link0 of CPU 1 + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, /* AMD 8111 on link0 of CPU 0 */ + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, /* AMD 8151 on link0 of CPU 1 */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index fff950a..5179448 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -37,8 +37,8 @@ static void memreset_setup(void) { - //GPIO on amd8111 to enable MEMRST ???? - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 + /* GPIO on amd8111 to enable MEMRST ???? */ + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } @@ -49,7 +49,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 int ret,i; unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time */ i = 2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); @@ -82,19 +82,19 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node + /* first node */ RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node + /* third node */ RC2|DIMM0, RC2|DIMM2, 0, 0, RC2|DIMM1, RC2|DIMM3, 0, 0, - // four node + /* four node */ RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, #endif @@ -114,27 +114,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_mb_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram - setup_coherent_ht_domain(); // routing table and start other core0 + set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */ + setup_coherent_ht_domain(); /* routing table and start other core0 */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + /* It is said that we should start core1 after all core0 launched */ /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) @@ -144,13 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - -#if 0 - //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); -#endif + ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */ #if CONFIG_SET_FIDVID /* Check to see if processor is capable of changing FIDVID */ @@ -169,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - // show final fid and vid + /* show final fid and vid */ { msr_t msr; msr = rdmsr(0xc0010042); @@ -185,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too + /* fidvid change will issue one LDTSTOP and the HT change will be effective too */ if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); @@ -193,36 +181,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + /* It's the time to set ctrl in sysinfo now; */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); -#if 0 - int i; - for(i = 0; i < 4; i++) { - activate_spd_rom(&cpu[i]); - dump_smbus_registers(); - } -#endif - memreset_setup(); - //do we need apci timer, tsc...., only debug need it for better output + /* do we need apci timer, tsc...., only debug need it for better output */ /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID + /* Need to use TMICT to synchronize FID/VID */ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); -#if 0 - print_pci_devices(); -#endif - -#if 0 -// dump_pci_devices(); - dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); - dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); -#endif - - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); /* bsp swtich stack to RAM and copy sysinfo RAM now */ } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index d7aaff2..399c086 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -53,7 +53,6 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, res->base, gsi_base ); gsi_base+=7; - } } dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); @@ -72,7 +71,7 @@ unsigned long acpi_fill_madt(unsigned long current) for(i = 1; i < sysconf.hc_possible_num; i++) { u32 d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; - // 8131 need to use +4 + /* 8131 need to use +4 */ switch (sysconf.hcid[i]) { case 1: d = 7; @@ -100,7 +99,6 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], res->base, gsi_base ); gsi_base+=d; - } } break; @@ -133,12 +131,13 @@ unsigned long mainboard_write_acpi_tables(device_t device, int i; - get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ /* same htio, but different possition? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ + * change HCIN, and recalculate the checknum and add_table + */ - for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; @@ -149,7 +148,7 @@ unsigned long mainboard_write_acpi_tables(device_t device, c = (u8) ('A' + i - 1 - 6); } current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt + printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); /* pci0 and pci1 are in dsdt */ ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: @@ -158,11 +157,11 @@ unsigned long mainboard_write_acpi_tables(device_t device, case 2: file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; - case 3: //8131 + case 3: /* 8131 */ file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: - //HTX no io apic + /* HTX no io apic */ file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; } p = cbfs_boot_map_with_leak( diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c index 7f54896..b6bcf81 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ - /* * ACPI - create the Fixed ACPI Description Tables (FADT) */ @@ -44,16 +43,15 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; - // disable system management mode by setting to 0: - fadt->smi_cmd = 0;//pm_base+0x2f; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0;/* pm_base+0x2f */ fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x00; // SMM is not used for p-state control -// fadt->pstate_cnt = 0xe2; + fadt->pstate_cnt = 0x00; /* SMM is not used for p-state control */ fadt->pm1a_evt_blk = pm_base; fadt->pm1b_evt_blk = 0x0000; @@ -72,18 +70,17 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe1_blk_len = 8; fadt->gpe1_base = 16; - fadt->cst_cnt = 0x00;// SMM is not used for p-state control -// fadt->cst_cnt = 0xe3; + fadt->cst_cnt = 0x00;/* SMM is not used for p-state control */ fadt->p_lvl2_lat = 101; fadt->p_lvl3_lat = 1001; fadt->flush_size = 0; fadt->flush_stride = 0; fadt->duty_offset = 1; fadt->duty_width = 3; - fadt->day_alrm = 0; // 0x7d these have to be - fadt->mon_alrm = 0; // 0x7e added to cmos.layout - fadt->century = 0; // 0x7f to make rtc alrm work - fadt->iapc_boot_arch = 0x3; // See table 5-11 + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ fadt->flags = 0x25; fadt->res2 = 0; @@ -115,7 +112,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; @@ -130,7 +126,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; @@ -138,7 +133,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm2_cnt_blk.addrl = 0x0; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; @@ -146,7 +140,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm_tmr_blk.addrl = pm_base+0x08; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 32; fadt->x_gpe0_blk.bit_offset = 0; @@ -154,7 +147,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_gpe0_blk.addrl = pm_base+0x20; fadt->x_gpe0_blk.addrh = 0x0; - fadt->x_gpe1_blk.space_id = 1; fadt->x_gpe1_blk.bit_width = 64; fadt->x_gpe1_blk.bit_offset = 16; @@ -163,5 +155,4 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_gpe1_blk.addrh = 0x0; header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index 87ca672..fda2626 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -29,8 +29,9 @@ struct mb_sysconf_t mb_sysconf; /* Here you only need to set value in pci1234 for HT-IO that could be -installed or not You may need to preset pci1234 for HTIO board, please -refer to src/northbridge/amd/amdfam10/get_sblk_pci1234.c for detail */ + * installed or not You may need to preset pci1234 for HTIO board, please + * refer to src/northbridge/amd/amdfam10/get_sblk_pci1234.c for detail + */ static u32 pci1234x[] = { 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, @@ -42,7 +43,8 @@ static u32 pci1234x[] = { /* HT Chain device num, actually it is unit id base of every ht device -in chain, assume every chain only have 4 ht device at most */ + * in chain, assume every chain only have 4 ht device at most + */ static unsigned hcdnx[] = { 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, @@ -70,18 +72,18 @@ static u32 get_hcid(u32 i) dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); switch (dev->device) { - case 0x7458: //8132 + case 0x7458: /* 8132 */ id = 1; break; - case 0x7454: //8151 + case 0x7454: /* 8151 */ id = 2; break; - case 0x7450: //8131 + case 0x7450: /* 8131 */ id = 3; break; } - // we may need more way to find out hcid: subsystem id? GPIO read ? - // we need use id for 1. bus num, 2. mptable, 3. ACPI table + /* we may need more way to find out hcid: subsystem id? GPIO read ? */ + /* we need use id for 1. bus num, 2. mptable, 3. ACPI table */ return id; } @@ -94,7 +96,7 @@ void get_bus_conf(void) struct mb_sysconf_t *m; if(get_bus_conf_done == 1) - return; //do it only once + return; /* do it only once */ get_bus_conf_done = 1; @@ -145,13 +147,13 @@ void get_bus_conf(void) for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; - // check hcid type here + /* check hcid type here */ sysconf.hcid[i] = get_hcid(i); switch(sysconf.hcid[i]) { - case 1: //8132 - case 3: //8131 + case 1: /* 8132 */ + case 3: /* 8131 */ m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 12) & 0xff; @@ -175,7 +177,7 @@ void get_bus_conf(void) break; - case 2: //8151 + case 2: /* 8151 */ m->bus_8151[j][0] = (sysconf.pci1234[i] >> 12) & 0xff; m->sbdn5[j] = sysconf.hcdn[i] & 0xff; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c index 4bb03c7..1ca7f3d 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c @@ -54,7 +54,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct mb_sysconf_t *m; - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ m = sysconf.mb; @@ -86,16 +86,14 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; - //pci bridge + /* pci bridge */ write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - //pcix bridge -// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; + /* pcix bridge */ int j = 0; @@ -142,5 +140,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "done.\n"); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 8699294..d800051 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -43,8 +43,8 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); - /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111 + /* I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */ { device_t dev; struct resource *res; @@ -99,33 +99,33 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ -//??? What +/* ??? What */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); - // Onboard AMD USB + /* Onboard AMD USB */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); - //Slot 3 PCI 32 + /* Slot 3 PCI 32 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */ } - // Slot 4 PCI 32 + /* Slot 4 PCI 32 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */ } - // Slot 1 PCI-X 133/100/66 + /* Slot 1 PCI-X 133/100/66 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); } - //Slot 2 PCI-X 133/100/66 + /* Slot 2 PCI-X 133/100/66 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */ } j = 0; @@ -144,9 +144,9 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { for(jj = 0; jj < 4; jj++) { - //Slot 1 PCI-X 133/100/66 + /* Slot 1 PCI-X 133/100/66 */ for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); } } } @@ -157,9 +157,9 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { for(jj = 0; jj < 4; jj++) { - //Slot 2 PCI-X 133/100/66 + /* Slot 2 PCI-X 133/100/66 */ for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); /* 25 */ } } } @@ -168,7 +168,7 @@ static void *smp_write_config_table(void *v) break; case 2: - // Slot AGP + /* Slot AGP */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); break; } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c index 8b432ed..fd14a80 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ - - static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { @@ -45,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 + /* Don't touch it, we need it for CAR with FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -83,7 +81,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR with FAM10 + /* don't touch it, we need it for CAR with FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -131,7 +129,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,7 +163,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,7 +189,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -223,7 +218,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -264,7 +258,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 1ccdf26..fa92219 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -14,10 +14,8 @@ */ #define SYSTEM_TYPE 0 /* SERVER */ -//#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -50,8 +48,8 @@ static void memreset_setup(void) { - //GPIO on amd8111 to enable MEMRST ???? - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN = 1 + /* GPIO on amd8111 to enable MEMRST ???? */ + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } @@ -87,16 +85,16 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" static const u8 spd_addr[] = { - //first node + /* first node */ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node + /* third node */ RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // forth node + /* forth node */ RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 4 @@ -208,12 +206,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -268,10 +264,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -308,8 +304,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -320,18 +314,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 711a0d5..71af45a 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -135,7 +135,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -153,13 +153,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; } @@ -170,13 +170,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; } @@ -187,13 +187,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c index 74b0aa8..be84cb1 100644 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ b/src/mainboard/amd/south_station/OemCustomize.c @@ -48,33 +48,33 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) }, #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -104,11 +104,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &DdiList[0] }; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h index 2d8381b..7a9c03f 100644 --- a/src/mainboard/amd/south_station/OptionsIds.h +++ b/src/mainboard/amd/south_station/OptionsIds.h @@ -43,14 +43,6 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h index 001ed16..0e0255e 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -20,45 +20,45 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 38a272d..dc60b77 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -74,7 +74,6 @@ #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE @@ -94,10 +93,7 @@ #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE @@ -106,65 +102,23 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 #define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE #define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE @@ -172,8 +126,6 @@ #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY @@ -181,16 +133,6 @@ #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE @@ -249,41 +191,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -292,5 +235,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data. */ #include "PlatformInstall.h" diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index b546ed8..d090e63 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -50,9 +50,9 @@ void set_pcie_dereset(void) */ static void southstation_led_init(void) { -#define GPIO_FUNCTION 2 //GPIO function -#define SB_GPIO_REG17 17 //Red Light -#define SB_GPIO_REG18 18 //Green Light +#define GPIO_FUNCTION 2 /* GPIO function */ +#define SB_GPIO_REG17 17 /* Red Light */ +#define SB_GPIO_REG18 18 /* Green Light */ /* multi-function pins switch to GPIO0-35 */ RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1); @@ -62,10 +62,10 @@ static void southstation_led_init(void) RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION); /* Lighting test */ - RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); /* output high */ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08); mdelay(100); - RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); /* output low */ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48); } diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index c24e42c..87572c5 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -83,7 +82,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index d39a3ab..7f825fd 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -161,7 +160,7 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA + #define AZALIA_SDIN_PIN 0x2A /** diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index a6a6279..6290608 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -126,8 +126,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /* 6 | BIT3 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -138,7 +138,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ @@ -161,7 +161,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111; /* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, @@ -190,7 +190,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (FchParams->StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index 66058f2..2d72f9e 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -120,19 +120,19 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - // DP0 to HDMI0/DP0 + /* DP0 to HDMI0/DP0 */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, - // DP1 to HDMI1/DP1 + /* DP1 to HDMI1/DP1 */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) }, - // DP2 to MINI-DDI Card + /* DP2 to MINI-DDI Card */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), @@ -172,11 +172,10 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h index eaf2442..bf623f7 100644 --- a/src/mainboard/amd/thatcher/OptionsIds.h +++ b/src/mainboard/amd/thatcher/OptionsIds.h @@ -43,17 +43,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 8ed3bf2..2b723c0 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -50,35 +50,21 @@ #define INSTALL_FM2_SOCKET_SUPPORT FALSE -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/* This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -126,7 +112,7 @@ #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 /* PCIE Spread Spectrum default value 0.36% */ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 #define BLDOPT_REMOVE_ALIB FALSE @@ -138,16 +124,11 @@ #define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 #define BLDCFG_CFG_ABM_SUPPORT 0 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity +/* Specify the default values for the VRM controlling the VDDNB plane. + * If not specified, the values used for the core VRM will be applied + */ + #define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 @@ -157,17 +138,13 @@ #if CONFIG_GFXUMA #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000/* 512M */ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif #define BLDCFG_IOMMU_SUPPORT FALSE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID /* Process the options... * This file include MUST occur AFTER the user option selection settings @@ -175,43 +152,7 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = { @@ -245,40 +186,40 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define DDR2100_FREQUENCY 1050 /* DDR 2100 */ +#define DDR2133_FREQUENCY 1066 /* DDR 2133 */ +#define DDR2400_FREQUENCY 1200 /* DDR 2400 */ +#define UNSUPPORTED_DDR_FREQUENCY 1201 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ /* * Agesa optional capabilities selection. @@ -323,7 +264,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 #define FCH_NO_XHCI_SUPPORT TRUE GPIO_CONTROL thatcher_gpio[] = { {183, Function1, PullUpB}, @@ -331,9 +271,10 @@ GPIO_CONTROL thatcher_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&thatcher_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 2640284..c61979f 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; @@ -173,7 +172,7 @@ static void *smp_write_config_table(void *v) /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 6652723..f3d67e4 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -88,35 +88,6 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0x7e, word); } -#if 0 /* TODO: */ -/******************************************************** -* tilapia uses SB700 GPIO8 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 4); /* Set Gpio8 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 4) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif - /* * justify the dev3 is exist or not */ @@ -251,18 +222,7 @@ static void set_thermal_config(void) pm_iowrite(0x3c, byte); /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); - * pm_iowrite(0x67, byte); - */ + } /************************************************* @@ -274,7 +234,6 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); set_pcie_dereset(); - /* get_ide_dma66(); */ set_thermal_config(); set_gpio40_gfx(); } diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c index 95d009a..d696c4d 100644 --- a/src/mainboard/amd/tilapia_fam10/resourcemap.c +++ b/src/mainboard/amd/tilapia_fam10/resourcemap.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ - - static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { @@ -45,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -83,7 +81,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -131,7 +129,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,7 +163,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,7 +189,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -223,7 +218,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -264,7 +258,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 1faac4d..c68fccc 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -102,12 +100,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -166,10 +162,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -196,8 +192,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -208,21 +202,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 0035a27..13c22eb 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -105,7 +105,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB MMIO Base (AcpiMmioAddr) + /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -117,15 +117,15 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; if (ResetInfo->ResetControl == DeassertSlotReset) { - if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + if (ResetInfo->ResetId & (BIT2+BIT3)) { /* de-assert */ + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45); if (Data8 & BIT7) { Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); while (!(Data8 & BIT7)) { Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); } - // GPIO44: PE_GPIO0 MXM Reset + /* GPIO44: PE_GPIO0 MXM Reset */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); @@ -134,53 +134,53 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi } else { Status = AGESA_UNSUPPORTED; } - // Travis + /* Travis */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); - //DE-Assert ALL PCIE RESET - // APU GPP0 (Dev 4) + /* DE-Assert ALL PCIE RESET */ + /* APU GPP0 (Dev 4) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); - // APU GPP1 (Dev 5) + /* APU GPP1 (Dev 5) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); - // APU GPP2 (Dev 6) + /* APU GPP2 (Dev 6) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); - // APU GPP3 (Dev 7) + /* APU GPP3 (Dev 7) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); } else { - if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported - // GPIO44: PE_GPIO0 MXM Reset + if (ResetInfo->ResetId & (BIT2+BIT3)) { /* Pcie Slot Reset is supported */ + /* GPIO44: PE_GPIO0 MXM Reset */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); Status = AGESA_SUCCESS; } - // Travis + /* Travis */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); - //Assert ALL PCIE RESET - // APU GPP0 (Dev 4) + /* Assert ALL PCIE RESET */ + /* APU GPP0 (Dev 4) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); - // APU GPP1 (Dev 5) + /* APU GPP1 (Dev 5) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); - // APU GPP2 (Dev 6) + /* APU GPP2 (Dev 6) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); - // APU GPP3 (Dev 7) + /* APU GPP3 (Dev 7) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index 0910ddc..86ececc 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -13,16 +13,13 @@ * GNU General Public License for more details. */ #ifndef BIOS_SIZE - #define BIOS_SIZE 0x04 //04 - 1MB + #define BIOS_SIZE 0x04 /* 04 - 1MB */ #endif #define LEGACY_FREE 0x00 #if !CONFIG_ONBOARD_USB30 #define XHCI_SUPPORT 0x01 #endif -//#define ACPI_SLEEP_TRAP 0x01 // No sleep trap smi support in coreboot. -//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01 - /** * Module Specific Defines for platform BIOS * @@ -74,7 +71,7 @@ * */ #ifndef WATCHDOG_TIMER_BASE_ADDRESS - #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address + #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 /* Watchdog Timer Base Address */ #endif /** @@ -82,7 +79,7 @@ * */ #ifndef HPET_BASE_ADDRESS - #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address + #define HPET_BASE_ADDRESS 0xFED00000 /* HPET Base address */ #endif /** @@ -107,43 +104,43 @@ * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address * */ -#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr +#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET /* AcpiPm1EvtBlkAddr */ /** * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address * */ -#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr +#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET /* AcpiPm1CntBlkAddr */ /** * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address * */ -#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr +#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET /* AcpiPmTmrBlkAddr */ /** * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address * */ -#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr +#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET /* CpuControlBlkAddr */ /** * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address * */ -#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr +#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET /* AcpiGpe0BlkAddr */ /** * SMI_CMD_PORT - ACPI SMI Command block base address * */ -#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr +#define SMI_CMD_PORT 0xB0 /* SmiCmdPortAddr */ /** * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address * */ -#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 /* AcpiPmaCntBlkAddr */ /** * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID. diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c index 3c20047..cba36bb 100644 --- a/src/mainboard/amd/torpedo/OemCustomize.c +++ b/src/mainboard/amd/torpedo/OemCustomize.c @@ -23,58 +23,53 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) }, - // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) + /* Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) }, - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) } - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) -// { -// DESCRIPTOR_TERMINATE_LIST, -// PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8), -// PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) -// } + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) }, - // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), @@ -114,11 +109,10 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h index 45abcab..77e1e90 100644 --- a/src/mainboard/amd/torpedo/OptionsIds.h +++ b/src/mainboard/amd/torpedo/OptionsIds.h @@ -42,15 +42,6 @@ * **/ -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h index 001ed16..0e0255e 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h @@ -20,45 +20,45 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index 656102d..24213cf 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -79,7 +79,7 @@ #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE -//For revision C single-link processors +/* For revision C single-link processors */ #define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE @@ -96,12 +96,12 @@ * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "LlanoPI " - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "LlanoPI " */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '} /* The following definitions specify the default values for various parameters @@ -119,8 +119,8 @@ /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 65000 //240000 //120000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 // 0 +#define BLDCFG_VRM_CURRENT_LIMIT 65000 /* 240000 */ /*120000 */ +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 /* 0 */ #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 #define BLDCFG_PLAT_NUM_IO_APICS 3 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST @@ -128,7 +128,7 @@ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY //DDR1066_FREQUENCY +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY /* DDR1066_FREQUENCY */ #define BLDCFG_MEMORY_MODE_UNGANGED TRUE #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED @@ -161,23 +161,14 @@ #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//enable HW C1E -#define BLDCFG_PLATFORM_C1E_MODE 0 //C1eModeHardware -//#define BLDCFG_PLATFORM_C1E_OPDATA 0x415 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 //0 //CStateModeC6 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 +/* enable HW C1E */ +#define BLDCFG_PLATFORM_C1E_MODE 0 /* C1eModeHardware */ +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 /* 0 */ +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 /* Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 */ -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero. -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime per BKDG. Defaults to 5000, same as core VRM. Cannot be zero. -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Llano/Ontario -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Llano/Ontario -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 /* Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero. */ #define BLDCFG_UMA_ABOVE4G_SUPPORT TRUE #define BLDCFG_STEREO_3D_PINOUT TRUE @@ -202,12 +193,6 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] = }; #define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList -//#define OPTION_NB_LCLK_DPM_INIT FALSE -//#define OPTION_POWER_GATE FALSE -//#define OPTION_PCIE_POWER_GATE FALSE -//#define OPTION_ALIB FALSE -//#define OPTION_PCIe_MID_INIT FALSE -//#define OPTION_NB_MID_INIT FALSE #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 56a90a6..5b34b9d 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - /* * ACPI - create the Fixed ACPI Description Tables (FADT) */ diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 03ab409..d3e905c 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -56,11 +56,11 @@ void gpioEarlyInit(void) { u32 SmiMmioAddr = 0; u32 andMask32 = 0; - // Enable HUDSON MMIO Base (AcpiMmioAddr) + /* Enable HUDSON MMIO Base (AcpiMmioAddr) */ ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); Data8 |= BIT0; WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); - // Get HUDSON MMIO Base (AcpiMmioAddr) + /* Get HUDSON MMIO Base (AcpiMmioAddr) */ ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); Data16 = Data8 << 8; ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8); @@ -71,109 +71,109 @@ void gpioEarlyInit(void) { MiscMmioAddr = AcpiMmioAddr + MISC_BASE; Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80); if ((Data8 & BIT4) == 0) { - BoardType = 0; // external clock board + BoardType = 0; /* external clock board */ } Data8 = Mmio8_G (GpioMmioAddr, GPIO_30); StripInfo = (Data8 & BIT7) >> 7; Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); StripInfo |= (Data8 & BIT7) >> 6; - if (StripInfo < boardRevC) { // for old board. Rev B - Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 - Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 + if (StripInfo < boardRevC) { /* for old board. Rev B */ + Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); /* function 3 */ + Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); /* function 0 */ } for (Index = 0; Index < MAX_GPIO_NO; Index++) { if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { - // Configure multi-function + /* Configure multi-function */ Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); } - // Configure GPIO + /* Configure GPIO */ if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); } if (Index == GPIO_65) { if ( BoardType == 0 ) { - Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 + Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); /* function 3 */ } } } - // Configure GEVENT + /* Configure GEVENT */ if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) { SmiMmioAddr = AcpiMmioAddr + SMI_BASE; andMask32 = ~(1 << (Index - GEVENT_00)); - //EventEnable: 0-Disable, 1-Enable + /* EventEnable: 0-Disable, 1-Enable */ Mmio32_And_Or(SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); - //SciTrig: 0-Falling Edge, 1-Rising Edge + /* SciTrig: 0-Falling Edge, 1-Rising Edge */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); - //SciLevl: 0-Edge trigger, 1-Level Trigger + /* SciLevl: 0-Edge trigger, 1-Level Trigger */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); - //SmiSciEn: 0-Not send SMI, 1-Send SMI + /* SmiSciEn: 0-Not send SMI, 1-Send SMI */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); - //SciS0En: 0-Disable, 1-Enable + /* SciS0En: 0-Disable, 1-Enable */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); - //SciMap: 00000b ~ 11111b + /* SciMap: 00000b ~ 11111b */ RegIndex8 = (u8)((Index - GEVENT_00) >> 2); Data8 = (u8)(((Index - GEVENT_00) & 0x3) * 8); Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); - //SmiTrig: 0-Active Low, 1-Active High + /* SmiTrig: 0-Active Low, 1-Active High */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); - //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 + /* SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 */ RegIndex8 = (u8)((Index - GEVENT_00) >> 4); Data8 = (u8)(((Index - GEVENT_00) & 0xF) * 2); Mmio32_And_Or(SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); } } - // - // config MXM - // GPIO9: Input for MXM_PRESENT2# - // GPIO10: Input for MXM_PRESENT1# - // GPIO28: Input for MXM_PWRGD - // GPIO35: Output for MXM Reset - // GPIO45: Output for MXM Power Enable, active HIGH - // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable - // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO - // - // set INTE#/GPIO32 as GPO for PCIE_SW - RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO + /* + * config MXM + * GPIO9: Input for MXM_PRESENT2# + * GPIO10: Input for MXM_PRESENT1# + * GPIO28: Input for MXM_PWRGD + * GPIO35: Output for MXM Reset + * GPIO45: Output for MXM Power Enable, active HIGH + * GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable + * GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO + */ + /* set INTE#/GPIO32 as GPO for PCIE_SW */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); /* GPO */ RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6); - // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN - RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO + /* set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); /* GPO */ - // set AD9/GPIO9 as GPI for MXM_PRESENT2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD9/GPIO9 as GPI for MXM_PRESENT2# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set AD10/GPIO10 as GPI for MXM_PRESENT1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD10/GPIO10 as GPI for MXM_PRESENT1# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set GNT1#/GPIO44 as GPO for MXM Reset - RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO + /* set GNT1#/GPIO44 as GPO for MXM Reset */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); /* GPO */ - // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO + /* set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); /* GPO */ - // set AD28/GPIO28 as GPI for MXM_PWRGD - RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD28/GPIO28 as GPI for MXM_PWRGD */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) + /* set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); @@ -181,20 +181,13 @@ void gpioEarlyInit(void) { RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3); - // - // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). - // - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20)); - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20))); + /* [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). */ - // check if there any GFX card + /* check if there any GFX card */ Flags = 0; - // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL); - // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09); ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8); if (!(Data8 & BIT7)) { - //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10); ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8); if (!(Data8 & BIT7)) { @@ -203,241 +196,193 @@ void gpioEarlyInit(void) { } if (Flags) { - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 + /* [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 */ RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH */ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + /*PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) */ SbStall (10000); - // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module + /* Write the GPIO55(MXM_PWR_EN) to enable the integrated power module */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) - // WAIT POWER READY: GPIO28 (MXM_PWRGD) - //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} + /* WAIT POWER READY: GPIO28 (MXM_PWRGD) */ + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); while (!(Data8 & BIT7)) { ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); } - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset - //RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); + /* [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset */ + /* RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); */ } else { - // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module + /* Write the GPIO55(MXM_PWR_EN) to disable the integrated power module */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) SbStall (10000); - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down */ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); } - // - // APU GPP0: On board LAN - // GPIO25: PCIE_RST#_LAN, LOW active - // GPIO63: LAN_CLKREQ# - // GPIO197: LOM_POWER, HIGH Active - // Clock: GPP_CLK3 - // - // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER - RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - - // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 - - // - // APU GPP1: WUSB - // GPIO1: MPCIE_RST2#, LOW active - // GPIO13: WU_DISABLE#, LOW active - // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) - // - // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD01/GPIO01 as GPO for MPCIE_RST2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB -// RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // - // APU GPP2: WWAN - // GPIO0: MPCIE_RST1#, LOW active - // GPIO14: WP_DISABLE#, LOW active - // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) - // - // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD00/GPIO00 as GPO for MPCIE_RST1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN -// RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3); - - // - // APU GPP3: 1394 - // GPIO59: Power control, HIGH active - // GPIO27: PCIE_RST#_1394, LOW active - // GPIO41: CLKREQ# - // Clock: GPP_CLK8 - // - // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 - RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# - - // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C - RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - // To fix glitch issue - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - // - // Enable/Disable OnBoard LAN - // + /* + * APU GPP0: On board LAN + * GPIO25: PCIE_RST#_LAN, LOW active + * GPIO63: LAN_CLKREQ# + * GPIO197: LOM_POWER, HIGH Active + * Clock: GPP_CLK3 + */ + /* Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + + /* set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); /* CLK_REQ3# */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); /* Enable GPP_CLK3 */ + + /* + * APU GPP1: WUSB + * GPIO1: MPCIE_RST2#, LOW active + * GPIO13: WU_DISABLE#, LOW active + * GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) + */ + /* Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD01/GPIO01 as GPO for MPCIE_RST2# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB */ + + + /* + * APU GPP2: WWAN + * GPIO0: MPCIE_RST1#, LOW active + * GPIO14: WP_DISABLE#, LOW active + * GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) + */ + /* Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Set AD00/GPIO00 as GPO for MPCIE_RST1# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN */ + + /* + * APU GPP3: 1394 + * GPIO59: Power control, HIGH active + * GPIO27: PCIE_RST#_1394, LOW active + * GPIO41: CLKREQ# + * Clock: GPP_CLK8 + */ + /* Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); /* CLK_REQ2# */ + + /* set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); /* GPO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + /* To fix glitch issue */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); /* set GPIO_GATE_C to LOW */ + + /* Enable/Disable OnBoard LAN */ + if (!CONFIG_ONBOARD_LAN) - { // 1 - DISABLED - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off + { /* 1 - DISABLED */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); /* LOM_POWER off */ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3 + RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); /* PULL UP - DISABLED */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); /* Disable GPP_CLK3 */ } -// else -// { // 0 - AUTO -// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable) -// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); -// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); -// } + /* Enable/Disable 1394 */ - // - // Enable/Disable 1394 - // if (!CONFIG_ONBOARD_1394) - { // 1 - DISABLED -// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off + { /* 1 - DISABLED */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); /* 1394 power off */ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 -// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); /* pullup DISABLE */ + RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); /* DISABLE GPP_CLK8 */ } -// else -// { // 0 - AUTO -// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH) -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); -// -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); -// } - -// -// external USB 3.0 control: -// amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO26: PCIE_RST#_USB3.0 -// GPIO46: PCIE_USB30_CLKREQ# -// GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON -// Clock: GPP_CLK7 -// GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE -// if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { -// disable Onboard NEC USB3.0 controller + +/* + * external USB 3.0 control: + * amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO26: PCIE_RST#_USB3.0 + * GPIO46: PCIE_USB30_CLKREQ# + * GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON + * Clock: GPP_CLK7 + * GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + */ +/* disable Onboard NEC USB3.0 controller */ if (!CONFIG_ONBOARD_USB30) { RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 - RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); /* PULL_UP DISABLE */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); /* DISABLE GPP_CLK7 */ + RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */ } -// } - -// -// BlueTooth control: BT_ON -// amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO07: BT_ON, 0 - OFF, 1 - ON -// +/* + * BlueTooth control: BT_ON + * amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO07: BT_ON, 0 - OFF, 1 - ON + */ if (!CONFIG_ONBOARD_BLUETOOTH) { - //- if (SystemConfiguration.amdBlueTooth == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); - //- } } -// -// WebCam control: -// amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF -// +/* + * WebCam control: + * amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF + */ if (!CONFIG_ONBOARD_WEBCAM) { - //- if (SystemConfiguration.amdWebCam == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); - //- } } -// -// Travis enable: -// amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE -// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE -// +/* + * Travis enable: + * amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE + * GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE + */ if (!CONFIG_ONBOARD_TRAVIS) { - //- if (SystemConfiguration.amdTravisCtrl == 0) { RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); - //- } } -// -// Disable Light Sensor if needed -// + +/* Disable Light Sensor if needed */ + if (CONFIG_ONBOARD_LIGHTSENSOR) { - //- if (SystemConfiguration.amdLightSensor == 1) { RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); - //- } } - } diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h index 0df5d50..bef778d 100644 --- a/src/mainboard/amd/torpedo/gpio.h +++ b/src/mainboard/amd/torpedo/gpio.h @@ -83,87 +83,87 @@ #define FUNCTION1 1 #define FUNCTION2 2 #define FUNCTION3 3 -#define NonGpio 0x80 // BIT7 +#define NonGpio 0x80 /* BIT7 */ -// S0-domain General Purpose I/O: GPIO 00~67 -#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT -#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT -#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT -#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED -#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT -#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT -#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED -#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF -#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level -#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 -#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 -#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 -#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default -#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. -#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) -#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) -#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE - // 1:BATTERY IS FINE(DEFAULT) - // 0:BATTERY IS LOW -#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF -#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default -#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high -#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high -#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high -#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT -#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT -#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 -#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 - // 00 - REVA - // 01 - REVB - // 10 - REVC - // 11 - REVD -#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO -#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. - // 0:USB3.0 I/F in Express CARD - // 1:PCIE I/F in Express CARD detection -#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF -#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# -#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC -#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. -#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# -#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# -#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK -#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE -#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF -#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# -#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA -#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ -#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 -#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V -#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 -#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT -#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE -#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE -#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) - // 1:ENABLE; 0:DISABLE - // DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 -#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN -#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER -#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER -#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE -#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# -#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 -#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 -#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# -#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 -#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM -#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default -#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# +/* S0-domain General Purpose I/O: GPIO 00~67 */ +#define GPIO_00_SELECT FUNCTION1+NonGpio /* MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_01_SELECT FUNCTION1+NonGpio /* MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_02_SELECT FUNCTION1 /* MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_03_SELECT FUNCTION1+NonGpio /* NOT USED */ +#define GPIO_04_SELECT FUNCTION1+NonGpio /* x1 gpp reset, for J3701, low active, HIGH DEFAULT */ +#define GPIO_05_SELECT FUNCTION1+NonGpio /* express card reset, for J2500, low active, HIGH DEFAULT */ +#define GPIO_06_SELECT FUNCTION0+NonGpio /*NOT USED */ +#define GPIO_07_SELECT FUNCTION1 /* BT_ON, 1: BT ON(DEFAULT); 0: BT OFF */ +#define GPIO_08_SELECT FUNCTION1 /* PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level */ +#define GPIO_09_SELECT FUNCTION1+NonGpio /* MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED */ +#define GPIO_10_SELECT FUNCTION1+NonGpio /* MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED */ +#define GPIO_11_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_12_SELECT FUNCTION1 /* WL_DISABLE#, DISABLE THE WALN IN J3702 */ +#define GPIO_13_SELECT FUNCTION1 /* WU_DISABLE#, DISABLE THE WUSB IN J3711 */ +#define GPIO_14_SELECT FUNCTION1 /* WP_DISABLE, DISABLE THE WWAN IN J3703 */ +#define GPIO_15_SELECT FUNCTION1+NonGpio /* NOT USED, FUNCTION1, Reset_CEC# Low Active, High default */ +#define GPIO_16_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_17_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_18_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_19_SELECT FUNCTION1 /* For LASSO_DET# detection when Gevent14# is asserted. */ +#define GPIO_20_SELECT FUNCTION1 /* PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) */ +#define GPIO_21_SELECT FUNCTION1 /* DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) */ +#define GPIO_22_SELECT FUNCTION1 /* SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE */ + /* 1:BATTERY IS FINE(DEFAULT) */ + /* 0:BATTERY IS LOW */ +#define GPIO_23_SELECT FUNCTION1 /* CODEC_ON.1: CODEC ON (default)0: CODEC OFF */ +#define GPIO_24_SELECT FUNCTION1 /* Travis reset,Low active High default */ +#define GPIO_25_SELECT FUNCTION1+NonGpio /* PCIE_RST# for LAN (AND gate with PCIE_RST#); default high */ +#define GPIO_26_SELECT FUNCTION1+NonGpio /* PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high */ +#define GPIO_27_SELECT FUNCTION1+NonGpio /* PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high */ +#define GPIO_28_SELECT FUNCTION1 /* MXM PWRGD INDICATOR, INPUT */ +#define GPIO_29_SELECT FUNCTION1 /* MEM HOT, LOW ACTIVE, OUTPUT */ +#define GPIO_30_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 0 */ +#define GPIO_31_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 1 */ + /* 00 - REVA */ + /* 01 - REVB */ + /* 10 - REVC */ + /* 11 - REVD */ +#define GPIO_32_SELECT FUNCTION1+NonGpio /* PCIE_SW - HIGH:MXM; LOW:LASSO */ +#define GPIO_33_SELECT FUNCTION1 /* USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. */ + /* 0:USB3.0 I/F in Express CARD */ + /* 1:PCIE I/F in Express CARD detection */ +#define GPIO_34_SELECT FUNCTION1 /* WEBCAM_ON#. 0: ON (default) 1: OFF */ +#define GPIO_35_SELECT FUNCTION1 /* ODD_DA_INTH# */ +#define GPIO_36_SELECT FUNCTION0+NonGpio /* PCICLK FOR KBC */ +#define GPIO_37_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_38_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_39_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_40_SELECT FUNCTION1 /* For DOCK# detection when Gevent14# is asserted. */ +#define GPIO_41_SELECT FUNCTION1+NonGpio /* 1394 CLK REQ# */ +#define GPIO_42_SELECT FUNCTION1+NonGpio /* X4 GPP CLK REQ# */ +#define GPIO_43_SELECT FUNCTION0+NonGpio /* SMBUS0, CLOCK */ +#define GPIO_44_SELECT FUNCTION1+NonGpio /* PEGPIO0, RESET THE MXM MODULE */ +#define GPIO_45_SELECT FUNCTION2+NonGpio /* PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF */ +#define GPIO_46_SELECT FUNCTION1+NonGpio /* USB3.0_CLKREQ# */ +#define GPIO_47_SELECT FUNCTION0+NonGpio /* SMBUS0, DATA */ +#define GPIO_48_SELECT FUNCTION0+NonGpio /* SERIRQ */ +#define GPIO_49_SELECT FUNCTION0+NonGpio /* LDRQ#1 */ +#define GPIO_50_SELECT FUNCTION2 /* SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V */ +#define GPIO_51_SELECT FUNCTION0+NonGpio /* back-up for SMARTVOLTAGE1 */ +#define GPIO_52_SELECT FUNCTION0+NonGpio /* CPU FAN OUT */ +#define GPIO_53_SELECT FUNCTION1 /* ODD POWER ENABLE, HIGH ACTIVE */ +#define GPIO_54_SELECT FUNCTION0+NonGpio /* SB_PROCHOT, OUTPUT, LOW ACTIVE */ +#define GPIO_55_SELECT FUNCTION2+NonGpio /* MXM POWER ENABLE(POWER ON MODULE) */ + /* 1:ENABLE; 0:DISABLE */ + /* DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 */ +#define GPIO_56_SELECT FUNCTION0+NonGpio /* HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN */ +#define GPIO_57_SELECT FUNCTION1 /* HDD0_POWER */ +#define GPIO_58_SELECT FUNCTION1 /* HDD2_POWER */ +#define GPIO_59_SELECT FUNCTION2+NonGpio /* 1394 POWER, OUTPUT, HIGH ACTIVE */ +#define GPIO_60_SELECT FUNCTION0+NonGpio /* EXPCARD_CLKREQ# */ +#define GPIO_61_SELECT FUNCTION0+NonGpio /* PE0_CLKREQ#, FROM J3700 */ +#define GPIO_62_SELECT FUNCTION0+NonGpio /* PE2_CLKREQ#, FROM J3711 */ +#define GPIO_63_SELECT FUNCTION0+NonGpio /* LAN_CLKREQ# */ +#define GPIO_64_SELECT FUNCTION0+NonGpio /* PE1_CLKREQ#, FROM J3703 */ +#define GPIO_65_SELECT FUNCTION0+NonGpio /* MXM CLK REQ#, FROM MXM */ +#define GPIO_66_SELECT FUNCTION1 /* USED AS TRAVIS_EN#; 0:ENABLE as default */ +#define GPIO_67_SELECT FUNCTION0+NonGpio /* USED AS SATA_ACT# */ #define GPIO_68_SELECT FUNCTION0+NonGpio #define GPIO_69_SELECT FUNCTION0+NonGpio #define GPIO_70_SELECT FUNCTION0+NonGpio @@ -192,40 +192,40 @@ #define GPIO_93_SELECT FUNCTION0+NonGpio #define GPIO_94_SELECT FUNCTION0+NonGpio #define GPIO_95_SELECT FUNCTION0+NonGpio -// GEVENT 00~23 are mapped to GPIO 96~119 -#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# -#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# -#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP -#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# -#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# -#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active -#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, - // there is a confliction to IR function when this pin is as a GEVENT. -#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, - // special pin difination for SB900 VGA OUTPUT, high active, - // VGA power for Hudson-M2 will be down when it was asserted. -#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active -#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) -#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 -#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 -#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active - // [option for SPI_TPM_CS# in Hudson-M2 A12)] -#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & - // USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time -#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, - // plus judge GPIO40 and GPIO19 level,low is assert. - // LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) - // DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) -#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active -#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, - // low active, when it's low, BIOS will enbale ODD_PWR -#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# -#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK -#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# -#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT -#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 -#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# -#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI +/* GEVENT 00~23 are mapped to GPIO 96~119 */ +#define GPIO_96_SELECT FUNCTION0 /* GA20IN/GEVENT0# */ +#define GPIO_97_SELECT FUNCTION0 /* KBRST#/GEVENT1# */ +#define GPIO_98_SELECT FUNCTION0 /* THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP */ +#define GPIO_99_SELECT FUNCTION1 /* LPC_PME#/GEVENT3# -> EC_SCI# */ +#define GPIO_100_SELECT FUNCTION2 /* PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# */ +#define GPIO_101_SELECT FUNCTION1 /* LPC_PD#/GEVENT5# -> hotplug of express card, low active */ +#define GPIO_102_SELECT FUNCTION0+NonGpio /* USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, */ + /* there is a confliction to IR function when this pin is as a GEVENT. */ +#define GPIO_103_SELECT FUNCTION0+NonGpio /* DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, */ + /* special pin difination for SB900 VGA OUTPUT, high active, */ + /* VGA power for Hudson-M2 will be down when it was asserted. */ +#define GPIO_104_SELECT FUNCTION0 /* WAKE#/GEVENT8# -> WAKEUP, low active */ +#define GPIO_105_SELECT FUNCTION2 /* SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) */ +#define GPIO_106_SELECT FUNCTION0 /* GBE_LED2/GEVENT10# -> GBE_LED2 */ +#define GPIO_107_SELECT FUNCTION0+NonGpio /* GBE_STAT0/GEVENT11# -> GBE_STAT0 */ +#define GPIO_108_SELECT FUNCTION2 /* USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active */ + /* [option for SPI_TPM_CS# in Hudson-M2 A12)] */ +#define GPIO_109_SELECT FUNCTION0 /* USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & */ + /* USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time */ +#define GPIO_110_SELECT FUNCTION2 /* USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, */ + /* plus judge GPIO40 and GPIO19 level,low is assert. */ + /* LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) */ + /* DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) */ +#define GPIO_111_SELECT FUNCTION1+NonGpio /* USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active */ +#define GPIO_112_SELECT FUNCTION2 /* USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, */ + /* low active, when it's low, BIOS will enbale ODD_PWR */ +#define GPIO_113_SELECT FUNCTION2 /* USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# */ +#define GPIO_114_SELECT FUNCTION2 /* BLINK/USB_OC7#/GEVENT18# -> BLINK */ +#define GPIO_115_SELECT FUNCTION0 /* SYS_RESET#/GEVENT19# -> SYS_RST# */ +#define GPIO_116_SELECT FUNCTION0 /* R_RX1/GEVENT20# -> IR INPUT */ +#define GPIO_117_SELECT FUNCTION1+NonGpio /* SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 */ +#define GPIO_118_SELECT FUNCTION1 /* RI#/GEVENT22# -> LID_CLOSED# */ +#define GPIO_119_SELECT FUNCTION0 /* LPC_SMI#/GEVENT23# -> EC_SMI */ #define GPIO_120_SELECT FUNCTION0+NonGpio #define GPIO_121_SELECT FUNCTION0+NonGpio #define GPIO_122_SELECT FUNCTION0+NonGpio @@ -268,78 +268,78 @@ #define GPIO_159_SELECT FUNCTION0+NonGpio #define GPIO_160_SELECT FUNCTION0+NonGpio -// S5-domain General Purpose I/O -#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# -#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 -#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 -#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 -#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 -#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. -#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, -#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE -#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 -#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# -#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 -#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 -#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO -#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR -#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 -#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 -#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# -#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE -#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE - // option for HDMI CEC signal OW ACTIVE -#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active -#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT -#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA -#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK -#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active - // RESERVED FOR LCD BACKLIGHT PWM -#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL -#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM -#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF -#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD +/* S5-domain General Purpose I/O */ +#define GPIO_161_SELECT FUNCTION0+NonGpio /* ROM_RST# */ +#define GPIO_162_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_163_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_164_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_165_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_166_SELECT FUNCTION1+NonGpio /* GBE_STAT2 */ +#define GPIO_167_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN0 */ +#define GPIO_168_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN1 */ +#define GPIO_169_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN2 */ +#define GPIO_170_SELECT FUNCTION1+NonGpio /* gating the power control signal for ODD, see BIOS requirements doc for detail. */ +#define GPIO_171_SELECT FUNCTION0+NonGpio /* TEMPIN0, */ +#define GPIO_172_SELECT FUNCTION1 /* used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE */ +#define GPIO_173_SELECT FUNCTION0+NonGpio /* TEMPIN3 */ +#define GPIO_174_SELECT FUNCTION1+NonGpio /* USED AS TALERT# */ +#define GPIO_175_SELECT FUNCTION1 /* WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_176_SELECT FUNCTION1+NonGpio /* WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_177_SELECT FUNCTION2+NonGpio /* WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_178_SELECT FUNCTION2 /* MEM_1V5 */ +#define GPIO_179_SELECT FUNCTION2 /* MEM_1V35 */ +#define GPIO_180_SELECT FUNCTION0+NonGpio /* Use as VIN VDDIO */ +#define GPIO_181_SELECT FUNCTION0+NonGpio /* Use as VIN VDDR */ +#define GPIO_182_SELECT FUNCTION1+NonGpio /* GBE_LED3 */ +#define GPIO_183_SELECT FUNCTION0+NonGpio /* GBE_LED0 */ +#define GPIO_184_SELECT FUNCTION1+NonGpio /* USED AS LLB# */ +#define GPIO_185_SELECT FUNCTION0+NonGpio /* USED AS USB */ +#define GPIO_186_SELECT FUNCTION0+NonGpio /* USED AS USB */ +#define GPIO_187_SELECT FUNCTION2 /* USED AS AC LED INDICATOR, LOW ACTIVE */ +#define GPIO_188_SELECT FUNCTION2 /* default used AS BATT LED INDICATOR, LOW ACTIVE */ + /* option for HDMI CEC signal OW ACTIVE */ +#define GPIO_189_SELECT FUNCTION1 /* USED AS AC_OK RECIEVER, INPUT, low active */ +#define GPIO_190_SELECT FUNCTION1 /* USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT */ +#define GPIO_191_SELECT FUNCTION0+NonGpio /* TOUCH PAD, DATA */ +#define GPIO_192_SELECT FUNCTION0+NonGpio /* TOUCH PAD, CLK */ +#define GPIO_193_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_194_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_195_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_196_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_197_SELECT FUNCTION2+NonGpio /* Default GPIO for LOM_POWER, high active */ + /* RESERVED FOR LCD BACKLIGHT PWM */ +#define GPIO_198_SELECT FUNCTION0+NonGpio /* IMC SCROLL LED CONTROL */ +#define GPIO_199_SELECT FUNCTION3 /* STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM */ +#define GPIO_200_SELECT FUNCTION2 /* NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF */ +#define GPIO_201_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_202_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_203_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_204_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_205_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_206_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_207_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_208_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_209_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_210_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_211_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_212_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_213_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_214_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_215_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_216_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_217_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_218_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_219_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_220_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_221_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_222_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_223_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_224_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_225_SELECT FUNCTION2+NonGpio /* KSO */ +#define GPIO_226_SELECT FUNCTION2+NonGpio /* KSO */ +#define GPIO_227_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_228_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_229_SELECT FUNCTION0+NonGpio /* DP1_HPD */ #define TYPE_GPI (1 << 5) #define TYPE_GPO (0 << 5) @@ -441,7 +441,7 @@ #define GPIO_94_TYPE TYPE_GPO #define GPIO_95_TYPE TYPE_GPO -// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 +/* GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 */ #define GPIO_96_TYPE TYPE_GPI #define GPIO_97_TYPE TYPE_GPI #define GPIO_98_TYPE TYPE_GPI @@ -753,13 +753,13 @@ #define GPO_169_LEVEL GPO_LOW #define GPO_170_LEVEL GPO_HI #define GPO_171_LEVEL GPO_LOW -#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +#define GPO_172_LEVEL GPO_HI /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */ #define GPO_173_LEVEL GPO_LOW #define GPO_174_LEVEL GPO_LOW #define GPO_175_LEVEL GPO_LOW #define GPO_176_LEVEL GPO_LOW #define GPO_177_LEVEL GPO_LOW -#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU +#define GPO_178_LEVEL GPO_HI /* AMD.SR BU to set VDDIO level to 1.5V for Barb BU */ #define GPO_179_LEVEL GPO_HI #define GPO_180_LEVEL GPO_HI #define GPO_181_LEVEL GPO_LOW @@ -1523,28 +1523,28 @@ #define GEVENT_00_EVENTENABLE EVENT_DISABLE #define GEVENT_01_EVENTENABLE EVENT_DISABLE -#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# -#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# -#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# -#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# +#define GEVENT_02_EVENTENABLE EVENT_ENABLE /* APU THERMTRIP# */ +#define GEVENT_03_EVENTENABLE EVENT_ENABLE /* EC_SCI# */ +#define GEVENT_04_EVENTENABLE EVENT_ENABLE /* APU_MEMHOT# */ +#define GEVENT_05_EVENTENABLE EVENT_ENABLE /* PCIE_EXPCARD_PWREN# */ #define GEVENT_06_EVENTENABLE EVENT_DISABLE #define GEVENT_07_EVENTENABLE EVENT_DISABLE #define GEVENT_08_EVENTENABLE EVENT_DISABLE -#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO +#define GEVENT_09_EVENTENABLE EVENT_ENABLE /* WF_RADIO */ #define GEVENT_10_EVENTENABLE EVENT_DISABLE #define GEVENT_11_EVENTENABLE EVENT_DISABLE -#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# +#define GEVENT_12_EVENTENABLE EVENT_ENABLE /* SMBALERT# */ #define GEVENT_13_EVENTENABLE EVENT_DISABLE -#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# -#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# -#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA -#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN +#define GEVENT_14_EVENTENABLE EVENT_ENABLE /* LASSO_DET#/DOCK# */ +#define GEVENT_15_EVENTENABLE EVENT_ENABLE /* ODD_PLUGIN# */ +#define GEVENT_16_EVENTENABLE EVENT_ENABLE /* ODD_DA */ +#define GEVENT_17_EVENTENABLE EVENT_ENABLE /* TWARN */ #define GEVENT_18_EVENTENABLE EVENT_DISABLE #define GEVENT_19_EVENTENABLE EVENT_DISABLE #define GEVENT_20_EVENTENABLE EVENT_DISABLE #define GEVENT_21_EVENTENABLE EVENT_DISABLE -#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# -#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# +#define GEVENT_22_EVENTENABLE EVENT_ENABLE /* LID_CLOSE# */ +#define GEVENT_23_EVENTENABLE EVENT_DISABLE /* EC_SMI# */ #define SCITRIG_LOW 0 #define SCITRIG_HI 1 @@ -2255,14 +2255,14 @@ typedef enum _GEVENT_COUNT typedef struct _GEVENT_SETTINGS { - u8 EventEnable; // 0: Disable, 1: Enable - u8 SciTrig; // 0: Falling Edge, 1: Rising Edge - u8 SciLevl; // 0: Edge trigger, 1: Level Trigger - u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI - u8 SciS0En; // 0: Disable, 1: Enable - u8 SciMap; // 0000b->1111b - u8 SmiTrig; // 0: Active Low, 1: Active High - u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 + u8 EventEnable; /* 0: Disable, 1: Enable */ + u8 SciTrig; /* 0: Falling Edge, 1: Rising Edge */ + u8 SciLevl; /* 0: Edge trigger, 1: Level Trigger */ + u8 SmiSciEn; /* 0: Not send SMI, 1: Send SMI */ + u8 SciS0En; /* 0: Disable, 1: Enable */ + u8 SciMap; /* 0000b->1111b */ + u8 SmiTrig; /* 0: Active Low, 1: Active High */ + u8 SmiControl; /* 0: Disable, 1: SMI 2: NMI 3: IRQ13 */ } GEVENT_SETTINGS; const GEVENT_SETTINGS gevent_table[] = diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 86339ef..9bd9088 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #define ONE_MB 0x100000 -//#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void); void set_pcie_dereset(void); diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 8091ffb..8aeb250 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -95,7 +94,6 @@ static void *smp_write_config_table(void *v) cpu_flag, cpu_features, cpu_feature_flags ); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; @@ -130,7 +128,6 @@ static void *smp_write_config_table(void *v) #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0); /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb900, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb900, 0x1); diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index 0713e41..5009607 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -98,30 +97,19 @@ /** * @section Smbus0BaseAddress */ -// #ifndef SMBUS0_BASE_ADDRESS -// #define SMBUS0_BASE_ADDRESS 0xB00 -// #endif /** * @section Smbus1BaseAddress */ -// #ifndef SMBUS1_BASE_ADDRESS -// #define SMBUS1_BASE_ADDRESS 0xB21 -// #endif /** * @section SioPmeBaseAddress */ -// #ifndef SIO_PME_BASE_ADDRESS -// #define SIO_PME_BASE_ADDRESS 0xE00 -// #endif /** * @section WatchDogTimerBase */ -// #ifndef WATCHDOG_TIMER_BASE_ADDRESS -// #define WATCHDOG_TIMER_BASE_ADDRESS IO_APIC_ADDR -// #endif + /** * @section GecShadowRomAddress @@ -133,58 +121,39 @@ /** * @section SpiRomBaseAddress */ -// #ifndef SPI_BASE_ADDRESS -// #define SPI_BASE_ADDRESS 0xFEC10000 -// #endif /** * @section AcpiPm1EvtBlkAddr */ -// #ifndef PM1_EVT_BLK_ADDRESS -// #define PM1_EVT_BLK_ADDRESS 0x400 -// #endif /** * @section AcpiPm1CntBlkAddr */ -// #ifndef PM1_CNT_BLK_ADDRESS -// #define PM1_CNT_BLK_ADDRESS 0x404 -// #endif + /** * @section AcpiPmTmrBlkAddr */ -// #ifndef PM1_TMR_BLK_ADDRESS -// #define PM1_TMR_BLK_ADDRESS 0x408 -// #endif + /** * @section CpuControlBlkAddr */ -// #ifndef CPU_CNT_BLK_ADDRESS -// #define CPU_CNT_BLK_ADDRESS 0x410 -// #endif + /** * @section AcpiGpe0BlkAddr */ -// #ifndef GPE0_BLK_ADDRESS -// #define GPE0_BLK_ADDRESS 0x420 -// #endif + /** * @section SmiCmdPortAddr */ -// #ifndef SMI_CMD_PORT -// #define SMI_CMD_PORT 0xB0 -// #endif /** * @section AcpiPmaCntBlkAddr */ -// #ifndef ACPI_PMA_CNT_BLK_ADDRESS -// #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -// #endif + /** * @section InChipSataController @@ -1192,7 +1161,7 @@ #define INCHIP_STRESS_RESET_MODE 0 #ifndef SB_PCI_CLOCK_RESERVED - #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F + #define SB_PCI_CLOCK_RESERVED 0x0 /* according to CIMx change 0x1F */ #endif /** @@ -1214,7 +1183,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_cfg); */ u32 sb900_callout_entry(u32 func, u32 data, void* config); -// definition for function in gpio.c +/* definition for function in gpio.c */ void gpioEarlyInit (void); #endif diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 74402bf..e8395fa 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -61,7 +61,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x34); report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); @@ -87,5 +87,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run returned!\n"); - post_code(0x44); // Should never see this post code. + post_code(0x44); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 711a0d5..71af45a 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -135,7 +135,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -153,13 +153,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; } @@ -170,13 +170,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; } @@ -187,13 +187,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c index 6f4dbfc..5378e2d 100644 --- a/src/mainboard/amd/union_station/OemCustomize.c +++ b/src/mainboard/amd/union_station/OemCustomize.c @@ -52,33 +52,33 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) }, #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -87,18 +87,18 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + /*PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */ {ConnectorTypeHDMI, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + /*PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ {ConnectorTypeHDMI, Aux2, Hdp2} } }; @@ -110,11 +110,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &DdiList[0] }; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h index 2d8381b..7a9c03f 100644 --- a/src/mainboard/amd/union_station/OptionsIds.h +++ b/src/mainboard/amd/union_station/OptionsIds.h @@ -43,14 +43,6 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h index 001ed16..0e0255e 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h @@ -20,45 +20,45 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 38a272d..648212c 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -29,7 +29,6 @@ #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE @@ -74,7 +73,6 @@ #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE @@ -94,10 +92,7 @@ #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE @@ -106,65 +101,23 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 #define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE #define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE @@ -172,8 +125,6 @@ #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY @@ -181,16 +132,6 @@ #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE @@ -249,41 +190,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -292,5 +234,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data. */ #include "PlatformInstall.h" diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index c24e42c..87572c5 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -83,7 +82,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index d39a3ab..4e6adb1 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -161,7 +161,6 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A /**

1 0

Patch set updated for coreboot: cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E
by Arthur Heymans 06 Oct '16

06 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16901 -gerrit commit b03816bcaf28be4be7fb4822640fa83f2dcaee0b Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 6 12:14:14 2016 +0200 cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E The datasheets "Intel® Core™ Duo Processor and Intel® Core™ Solo Processor on 65 nm Process" mentions cpu C-states substates which can either be attained by adding a substate hint to the MWAIT/P_LVLx request or automatically by setting some msr bits correctly. This just sets the same msr bits as model_6fx to enable dynamic L2 cache, C2E and C4E acpi cpu states. The result is that when limiting a thinkpad x60 with a yonah T2400 cpu to the acpi cpu C2 state, the idle power usage drops from 18W to 14W. When the lowest C-state is set to C4 the idle power usage seems to remain similar. Change-Id: I6c422656ace04659f32082a5944617eda6c79ec3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/cpu/intel/model_6ex/model_6ex_init.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 91633ec..d42ff69 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -69,7 +69,7 @@ static void configure_c_states(void) msr.lo |= (1 << 15); // config lock until next reset. msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - // TODO Do we want Deep C4 and Dynamic L2 shrinking? + msr.lo |= (1 << 3); //dynamic L2 /* Number of supported C-States */ msr.lo &= ~7; @@ -103,7 +103,13 @@ static void configure_misc(void) // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - // TODO Do we want Deep C4 and Dynamic L2 shrinking? + /* Enable C2E */ + msr.lo |= (1 << 26); + + /* Enable C4E */ + msr.hi |= (1 << (32 - 32)); // C4E + msr.hi |= (1 << (33 - 32)); // Hard C4E + wrmsr(IA32_MISC_ENABLE, msr); msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */

1 0

Patch set updated for coreboot: southbridge/nvidia: Remove commented code
by HAOUAS Elyes 06 Oct '16

06 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16899 -gerrit commit dbfb69279af67d4afa1f73572e40adfbf95a22f5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 22:17:30 2016 +0200 southbridge/nvidia: Remove commented code Change-Id: Ice4a5cae1a289852895012bb55035707b54cefb5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/nvidia/ck804/early_setup.c | 4 --- src/southbridge/nvidia/ck804/lpc.c | 6 ---- src/southbridge/nvidia/ck804/pci.c | 9 ------ src/southbridge/nvidia/ck804/sata.c | 35 --------------------- src/southbridge/nvidia/ck804/smbus.h | 43 -------------------------- src/southbridge/nvidia/mcp55/bootblock.c | 7 +---- src/southbridge/nvidia/mcp55/early_setup_car.c | 19 ------------ src/southbridge/nvidia/mcp55/lpc.c | 14 --------- src/southbridge/nvidia/mcp55/mcp55.c | 11 ------- 9 files changed, 1 insertion(+), 147 deletions(-) diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index abcb913..1d4999c 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -300,10 +300,6 @@ static void ck804_early_setup(void) setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); #endif -#if 0 - dump_io_resources(ANACTRL_IO_BASE); - dump_io_resources(SYSCTRL_IO_BASE); -#endif } static int ck804_early_setup_x(void) diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index d15ef8e..2b0bdd5 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -136,12 +136,6 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on * 12) + (on >> 1), (on & 1) * 5); } -#if 0 - /* Enable Port 92 fast reset (default is enabled). */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif /* Set up NMI on errors. */ byte = inb(0x70); /* RTC70 */ diff --git a/src/southbridge/nvidia/ck804/pci.c b/src/southbridge/nvidia/ck804/pci.c index 8ccf80c..a9f0f5b 100644 --- a/src/southbridge/nvidia/ck804/pci.c +++ b/src/southbridge/nvidia/ck804/pci.c @@ -33,18 +33,9 @@ static void pci_init(struct device *dev) dword |= (1 << 30); /* Clear possible errors */ pci_write_config32(dev, 0x04, dword); -#if 0 - word = pci_read_config16(dev, 0x48); - word |= (1 << 0); /* MRL2MRM */ - word |= (1 << 2); /* MR2MRM */ - pci_write_config16(dev, 0x48, word); -#endif - -#if 1 dword = pci_read_config32(dev, 0x4c); dword |= 0x00440000; /* TABORT_SER_ENABLE Park Last Enable. */ pci_write_config32(dev, 0x4c, dword); -#endif pci_domain_dev = dev->bus->dev; while (pci_domain_dev) { diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c index b67cf28..c5dc56e 100644 --- a/src/southbridge/nvidia/ck804/sata.c +++ b/src/southbridge/nvidia/ck804/sata.c @@ -51,13 +51,6 @@ static void sata_com_reset(struct device *dev, unsigned reset) *(base + 8) = dword; *(base + 0x48) = dword; -#if 0 - udelay(1000); - dword &= ~(0xf); - *(base + 8) = dword; - *(base + 0x48) = dword; -#endif - if (reset) return; @@ -109,17 +102,6 @@ static void sata_init(struct device *dev) dword |= (1 << 1); printk(BIOS_DEBUG, "SATA P\n"); } -#if 0 - /* Write back */ - dword |= (1 << 12); - dword |= (1 << 14); -#endif - -#if 0 - /* ADMA */ - dword |= (1 << 16); - dword |= (1 << 17); -#endif #if 1 /* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */ @@ -128,23 +110,6 @@ static void sata_init(struct device *dev) #endif pci_write_config32(dev, 0x50, dword); -#if 0 - /* SLUMBER_DURING_D3 */ - dword = pci_read_config32(dev, 0x7c); - dword &= ~(1 << 4); - pci_write_config32(dev, 0x7c, dword); - - dword = pci_read_config32(dev, 0xd0); - dword &= ~(0xff << 24); - dword |= (0x68 << 24); - pci_write_config32(dev, 0xd0, dword); - - dword = pci_read_config32(dev, 0xe0); - dword &= ~(0xff << 24); - dword |= (0x68 << 24); - pci_write_config32(dev, 0xe0, dword); -#endif - dword = pci_read_config32(dev, 0xf8); dword |= 2; pci_write_config32(dev, 0xf8, dword); diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h index 6d0c510..40b8cb7 100644 --- a/src/southbridge/nvidia/ck804/smbus.h +++ b/src/southbridge/nvidia/ck804/smbus.h @@ -34,25 +34,6 @@ static inline void smbus_delay(void) outb(0x80, 0x80); } -#if 0 -/* Not needed, upon write to PRTCL, the status will be auto-cleared. */ -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) - return 0; - outb(val, smbus_io_base + SMBHSTSTAT); - } while (--loops); - return -2; -} -#endif - static int smbus_wait_until_done(unsigned smbus_io_base) { unsigned long loops; @@ -72,12 +53,6 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { unsigned char global_status_register, byte; -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - /* Set the device I'm talking to. */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); smbus_delay(); @@ -112,12 +87,6 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, { unsigned global_status_register; -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); @@ -151,12 +120,6 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, { unsigned char global_status_register, byte; -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - /* Set the device I'm talking to. */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); smbus_delay(); @@ -191,12 +154,6 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, { unsigned global_status_register; -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index b77463a..6d24f56 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -28,13 +28,8 @@ static void mcp55_enable_rom(void) pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ -#if 0 - /* Default MCP55 LPC single */ - addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0); -#else -// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0); + addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0); -#endif /* Set the 15MB enable bits. */ byte = pci_read_config8(addr, 0x88); diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 76947ec..7f1d03b 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -253,7 +253,6 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, #if CONFIG_MCP55_USE_AZA RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, - // RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1 << 14), (1 << 14), #endif #ifdef MCP55_MB_SETUP @@ -326,22 +325,6 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, PCI_DEV(busn[j], devn[j], 0), io_base[j]); } -#if 0 - for (j = 0; j < mcp55_num; j++) { - // PCI-E (XSPLL) SS table 0x40, x044, 0x48 - // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 - // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, - io_base[j] + ANACTRL_IO_BASE + 0x44, - io_base[j] + ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, - io_base[j] + ANACTRL_IO_BASE + 0xb4, - io_base[j] + ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, - io_base[j] + ANACTRL_IO_BASE + 0xc4, - io_base[j] + ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); - } -#endif } #ifndef HT_CHAIN_NUM_MAX @@ -405,7 +388,5 @@ out: mcp55_early_clear_port(mcp55_num, busn, devn, io_base); - // set_ht_link_mcp55(HT_CHAIN_NUM_MAX); - return 0; } diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 824abc5..afc6e64 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -91,11 +91,6 @@ static void lpc_init(device_t dev) lpc_common_init(dev, 1); -#if 0 - /* Posted memory write enable. */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1 << 0)); -#endif /* power after power fail */ #if 1 @@ -122,13 +117,6 @@ static void lpc_init(device_t dev) (on * 12) + (on >> 1), (on & 1) * 5); } -#if 0 - /* Enable Port 92 fast reset (default is enabled). */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif - /* Enable error reporting. */ /* Set up sync flood detected. */ byte = pci_read_config8(dev, 0x47); @@ -258,7 +246,6 @@ static struct device_operations lpc_ops = { .enable_resources = mcp55_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_lpc_bus, -// .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; static const unsigned short lpc_ids[] = { @@ -295,7 +282,6 @@ static struct device_operations lpc_slave_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_slave_init, -// .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c index cfe5e17..7c43fea 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ b/src/southbridge/nvidia/mcp55/mcp55.c @@ -68,9 +68,7 @@ void mcp55_enable(device_t dev) if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid >> 16) & 0xffff; -// vendorid &= 0xffff; } else { -// vendorid = dev->vendor; deviceid = dev->device; } @@ -200,15 +198,6 @@ void mcp55_enable(device_t dev) | (1 << 11) | (1 << 10) | (1 << 9)); pci_write_config32(sm_dev, 0xe8, final_reg); /* Enable all at first. */ -#if 0 - reg_old = reg = pci_read_config32(sm_dev, 0xe4); -// reg |= (1 << 0); - reg &= ~(0x3f << 4); - if (reg != reg_old) { - printk(BIOS_DEBUG, "mcp55.c pcie enabled\n"); - pci_write_config32(sm_dev, 0xe4, reg); - } -#endif } if (!dev->enabled) {

1 0

Patch set updated for coreboot: google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration
by Patrick Georgi 06 Oct '16

06 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16699 -gerrit commit 2522f4e29ba8aaa95398c5e67a21eff87d0d4844 Author: Jeffy Chen <jeffy.chen(a)rock-chips.com> Date: Fri Sep 2 18:16:33 2016 +0800 google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto. BUG=chrome-os-partner:56759 BRANCH=none TEST=Build Change-Id: I698fe450d48b64a06232aa44ecf91d688d9dc17a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d3edecdb135939c3264ab1b831e7821d3a3e0149 Original-Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531 Original-Signed-off-by: Jeffy Chen <jeffy.chen(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380443 Original-Commit-Ready: Alexandru Stan <amstan(a)chromium.org> Original-Tested-by: Alexandru Stan <amstan(a)chromium.org> Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org> Original-Reviewed-by: Jonathan Dixon <joth(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_rialto/sdram_configs.c | 2 +- .../sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc | 90 ++++++++++++++++++++++ 2 files changed, 91 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c index 42fa582..0e260c3 100644 --- a/src/mainboard/google/veyron_rialto/sdram_configs.c +++ b/src/mainboard/google/veyron_rialto/sdram_configs.c @@ -22,7 +22,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc" /* ram_code = 0000 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */ +#include "sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc"/* ram_code = 0001 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */ diff --git a/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc new file mode 100644 index 0000000..a0fe689 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + { + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x0, + .col = 0x0, + .bk = 0x0, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x0, + .cs1_row = 0x0 + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 1, + .stride = 22, + .odt = 0 +},

1 0

Patch set updated for coreboot: mainboard/amd: Use C89 comments style & remove commented code
by HAOUAS Elyes 06 Oct '16

06 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16907 -gerrit commit c318c57ef9a2d751198024511f3ef5b511be29ba Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Oct 6 18:37:35 2016 +0200 mainboard/amd: Use C89 comments style & remove commented code Change-Id: I137b27ffb0e54a9ca6b0bd3a454b1d99b3e1c22b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/bettong/BiosCallOuts.c | 1 - src/mainboard/amd/bettong/OemCustomize.c | 4 +- src/mainboard/amd/bettong/mptable.c | 1 - src/mainboard/amd/bimini_fam10/mainboard.c | 40 -- src/mainboard/amd/bimini_fam10/resourcemap.c | 11 +- src/mainboard/amd/bimini_fam10/romstage.c | 29 +- src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c | 13 +- src/mainboard/amd/db-ft3b-lc/OemCustomize.c | 120 +++--- src/mainboard/amd/db-ft3b-lc/romstage.c | 1 - src/mainboard/amd/dinar/OemCustomize.c | 11 +- src/mainboard/amd/dinar/OptionsIds.h | 9 - src/mainboard/amd/dinar/acpi_tables.c | 8 +- src/mainboard/amd/dinar/buildOpts.c | 107 ++--- src/mainboard/amd/dinar/gpio.c | 427 +++++++++----------- src/mainboard/amd/dinar/gpio.h | 418 ++++++++++---------- src/mainboard/amd/dinar/mainboard.c | 3 - src/mainboard/amd/dinar/mptable.c | 3 +- src/mainboard/amd/dinar/platform_cfg.h | 11 +- src/mainboard/amd/dinar/rd890_cfg.c | 13 +- src/mainboard/amd/dinar/rd890_cfg.h | 24 +- src/mainboard/amd/dinar/romstage.c | 4 +- src/mainboard/amd/dinar/sb700_cfg.c | 34 +- src/mainboard/amd/dinar/sb700_cfg.h | 3 +- src/mainboard/amd/inagua/BiosCallOuts.c | 14 +- src/mainboard/amd/inagua/OemCustomize.c | 19 +- src/mainboard/amd/inagua/OptionsIds.h | 8 - src/mainboard/amd/inagua/PlatformGnbPcieComplex.h | 82 ++-- src/mainboard/amd/inagua/broadcom.c | 197 +++++----- src/mainboard/amd/inagua/buildOpts.c | 108 ++--- src/mainboard/amd/inagua/mainboard.c | 1 - src/mainboard/amd/inagua/mptable.c | 2 +- src/mainboard/amd/inagua/platform_cfg.h | 2 +- src/mainboard/amd/lamar/BiosCallOuts.c | 14 +- src/mainboard/amd/lamar/mainboard.c | 3 - src/mainboard/amd/mahogany/mainboard.c | 29 -- src/mainboard/amd/mahogany/mptable.c | 1 - src/mainboard/amd/mahogany_fam10/mainboard.c | 29 -- src/mainboard/amd/mahogany_fam10/resourcemap.c | 10 +- src/mainboard/amd/mahogany_fam10/romstage.c | 27 +- src/mainboard/amd/olivehill/BiosCallOuts.c | 38 +- src/mainboard/amd/olivehill/OptionsIds.h | 10 - src/mainboard/amd/olivehill/buildOpts.c | 128 ++---- src/mainboard/amd/olivehill/mptable.c | 39 -- src/mainboard/amd/olivehillplus/BiosCallOuts.c | 42 +- src/mainboard/amd/olivehillplus/mptable.c | 1 - src/mainboard/amd/olivehillplus/romstage.c | 1 - src/mainboard/amd/parmer/BiosCallOuts.c | 10 +- src/mainboard/amd/parmer/OptionsIds.h | 10 - src/mainboard/amd/parmer/buildOpts.c | 140 ++----- src/mainboard/amd/parmer/mptable.c | 1 - src/mainboard/amd/persimmon/BiosCallOuts.c | 9 +- src/mainboard/amd/persimmon/OemCustomize.c | 25 +- src/mainboard/amd/persimmon/OptionsIds.h | 8 - .../amd/persimmon/PlatformGnbPcieComplex.h | 72 ++-- src/mainboard/amd/persimmon/buildOpts.c | 108 ++--- src/mainboard/amd/persimmon/mptable.c | 1 - src/mainboard/amd/persimmon/platform_cfg.h | 2 +- src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 16 +- src/mainboard/amd/serengeti_cheetah/fadt.c | 14 +- src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 44 +-- src/mainboard/amd/serengeti_cheetah/irq_tables.c | 9 +- src/mainboard/amd/serengeti_cheetah/mptable.c | 38 +- src/mainboard/amd/serengeti_cheetah/resourcemap.c | 4 +- src/mainboard/amd/serengeti_cheetah/romstage.c | 64 +-- .../amd/serengeti_cheetah_fam10/acpi_tables.c | 17 +- src/mainboard/amd/serengeti_cheetah_fam10/fadt.c | 27 +- .../amd/serengeti_cheetah_fam10/get_bus_conf.c | 28 +- .../amd/serengeti_cheetah_fam10/irq_tables.c | 9 +- .../amd/serengeti_cheetah_fam10/mptable.c | 34 +- .../amd/serengeti_cheetah_fam10/resourcemap.c | 12 +- .../amd/serengeti_cheetah_fam10/romstage.c | 39 +- src/mainboard/amd/south_station/BiosCallOuts.c | 14 +- src/mainboard/amd/south_station/OemCustomize.c | 17 +- src/mainboard/amd/south_station/OptionsIds.h | 8 - .../amd/south_station/PlatformGnbPcieComplex.h | 72 ++-- src/mainboard/amd/south_station/buildOpts.c | 107 ++--- src/mainboard/amd/south_station/mainboard.c | 10 +- src/mainboard/amd/south_station/mptable.c | 3 +- src/mainboard/amd/south_station/platform_cfg.h | 3 +- src/mainboard/amd/thatcher/BiosCallOuts.c | 10 +- src/mainboard/amd/thatcher/OemCustomize.c | 13 +- src/mainboard/amd/thatcher/OptionsIds.h | 10 - src/mainboard/amd/thatcher/buildOpts.c | 141 ++----- src/mainboard/amd/thatcher/mptable.c | 3 +- src/mainboard/amd/tilapia_fam10/mainboard.c | 43 +- src/mainboard/amd/tilapia_fam10/resourcemap.c | 12 +- src/mainboard/amd/tilapia_fam10/romstage.c | 27 +- src/mainboard/amd/torpedo/BiosCallOuts.c | 36 +- src/mainboard/amd/torpedo/Oem.h | 23 +- src/mainboard/amd/torpedo/OemCustomize.c | 30 +- src/mainboard/amd/torpedo/OptionsIds.h | 9 - src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h | 72 ++-- src/mainboard/amd/torpedo/buildOpts.c | 41 +- src/mainboard/amd/torpedo/fadt.c | 1 - src/mainboard/amd/torpedo/gpio.c | 437 +++++++++------------ src/mainboard/amd/torpedo/gpio.h | 418 ++++++++++---------- src/mainboard/amd/torpedo/mainboard.c | 1 - src/mainboard/amd/torpedo/mptable.c | 3 - src/mainboard/amd/torpedo/platform_cfg.h | 47 +-- src/mainboard/amd/torpedo/romstage.c | 4 +- src/mainboard/amd/union_station/BiosCallOuts.c | 14 +- src/mainboard/amd/union_station/OemCustomize.c | 25 +- src/mainboard/amd/union_station/OptionsIds.h | 8 - .../amd/union_station/PlatformGnbPcieComplex.h | 72 ++-- src/mainboard/amd/union_station/buildOpts.c | 108 ++--- src/mainboard/amd/union_station/mptable.c | 3 +- src/mainboard/amd/union_station/platform_cfg.h | 1 - 107 files changed, 1813 insertions(+), 2874 deletions(-) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index d4d4410..1804296 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -72,7 +72,6 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio; diff --git a/src/mainboard/amd/bettong/OemCustomize.c b/src/mainboard/amd/bettong/OemCustomize.c index 3300244..a32ea9a 100644 --- a/src/mainboard/amd/bettong/OemCustomize.c +++ b/src/mainboard/amd/bettong/OemCustomize.c @@ -71,7 +71,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */ { - DESCRIPTOR_TERMINATE_LIST, // Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, @@ -91,7 +91,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { }, /* DP1 */ { - 0, //DESCRIPTOR_TERMINATE_LIST, + 0, /*DESCRIPTOR_TERMINATE_LIST, */ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 20, 23), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) }, diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c index 744fd98..9e73e77 100644 --- a/src/mainboard/amd/bettong/mptable.c +++ b/src/mainboard/amd/bettong/mptable.c @@ -64,7 +64,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 3c6c2c6..c4dd21e 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -63,22 +63,11 @@ void enable_int_gfx(void) void set_pcie_dereset(void) { /* GPIO 50h reset PCIe slot */ -/* - u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50); - u8 byte = ~(1 << 5); - byte |= ~(1 << 6); - *addr = byte; -*/ } void set_pcie_reset(void) { /* GPIO 50h reset PCIe slot */ -/* - u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50); - u8 byte = ~((1 << 5) | (1 << 6)); - *addr = byte; -*/ } u8 is_dev3_present(void) @@ -86,34 +75,6 @@ u8 is_dev3_present(void) return 0; } -#if 0 /* not tested yet. */ -/******************************************************** -* bimini uses SB800 GPIO9 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 5); /* Set Gpio9 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif /* get_ide_dma66() */ /************************************************* * enable the dedicated function in bimini board. @@ -125,7 +86,6 @@ static void mainboard_enable(device_t dev) set_pcie_dereset(); enable_int_gfx(); - /* get_ide_dma66(); */ } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/bimini_fam10/resourcemap.c b/src/mainboard/amd/bimini_fam10/resourcemap.c index e23f1c1..dbd6341 100644 --- a/src/mainboard/amd/bimini_fam10/resourcemap.c +++ b/src/mainboard/amd/bimini_fam10/resourcemap.c @@ -43,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -81,7 +81,8 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -129,7 +130,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,7 +164,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -191,7 +190,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -221,7 +219,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -262,7 +259,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 9ea7e44..6fee2ed 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -100,12 +98,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -164,10 +161,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -194,8 +191,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -206,24 +201,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb800_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index f46116a..291c2d8 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -158,8 +158,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00; //6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; /*BIT0 | BIT2 | BIT5; */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00; /*6 | BIT3; */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -195,7 +195,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /*BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; @@ -230,7 +230,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /*BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; @@ -241,7 +241,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /*BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; @@ -251,7 +251,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; /*BIT0 | BIT4 |BIT8; */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, @@ -279,7 +279,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); diff --git a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c index e8146a0..bffe888 100644 --- a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c +++ b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c @@ -118,66 +118,66 @@ OemCustomizeInitEarly ( * use its default conservative settings. */ static const PSO_ENTRY ROMDATA PlatformMemoryConfiguration[] = { - // - // The following macros are supported (use comma to separate macros): - // - // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) - // - // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. - // - // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. - // - // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. - // - // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. - // - // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. - // - // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. - // - // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. - // - // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) - // - // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. - // - // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Speicifes the HW RXEN training seed for a channel of a socket - // + /* + * The following macros are supported (use comma to separate macros): + * + * MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + * The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + * AGESA will base on this value to disable unused MemClk to save power. + * Example: + * BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + * Bit AM3/S1g3 pin name + * 0 M[B,A]_CLK_H/L[0] + * 1 M[B,A]_CLK_H/L[1] + * 2 M[B,A]_CLK_H/L[2] + * 3 M[B,A]_CLK_H/L[3] + * 4 M[B,A]_CLK_H/L[4] + * 5 M[B,A]_CLK_H/L[5] + * 6 M[B,A]_CLK_H/L[6] + * 7 M[B,A]_CLK_H/L[7] + * And platform has the following routing: + * CS0 M[B,A]_CLK_H/L[4] + * CS1 M[B,A]_CLK_H/L[2] + * CS2 M[B,A]_CLK_H/L[3] + * CS3 M[B,A]_CLK_H/L[5] + * Then platform can specify the following macro: + * MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + * + * CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + * The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + * AGESA will base on this value to tristate unused CKE to save power. + * + * ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + * The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + * AGESA will base on this value to tristate unused ODT pins to save power. + * + * CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + * The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + * AGESA will base on this value to tristate unused Chip select to save power. + * + * NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + * Specifies the number of DIMM slots per channel. + * + * NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + * Specifies the number of Chip selects per channel. + * + * NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + * Specifies the number of channels per socket. + * + * OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + * Specifies DDR bus speed of channel ChannelID on socket SocketID. + * + * DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + * Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + * + * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + * Byte6Seed, Byte7Seed, ByteEccSeed) + * Specifies the write leveling seed for a channel of a socket. + * + * HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + * Byte6Seed, Byte7Seed, ByteEccSeed) + * Speicifes the HW RXEN training seed for a channel of a socket + */ #define SEED_WL 0x0E WRITE_LEVELING_SEED( diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index f69e188..5c7796f 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -81,7 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); AGESAWRAPPER(amdinitpost); - //PspMboxBiosCmdDramInfo(); post_code(0x41); AGESAWRAPPER(amdinitenv); /* diff --git a/src/mainboard/amd/dinar/OemCustomize.c b/src/mainboard/amd/dinar/OemCustomize.c index 84866de..668dd25 100644 --- a/src/mainboard/amd/dinar/OemCustomize.c +++ b/src/mainboard/amd/dinar/OemCustomize.c @@ -28,11 +28,12 @@ * use its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - // Dinar has the following routing: - // CS0 M[B,A]_CLK_H/L[0] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[1] - // CS3 M[B,A]_CLK_H/L[3] + /* Dinar has the following routing: + * CS0 M[B,A]_CLK_H/L[0] + * CS1 M[B,A]_CLK_H/L[2] + * CS2 M[B,A]_CLK_H/L[1] + * CS3 M[B,A]_CLK_H/L[3] + */ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), PSO_END diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h index d1d184d..c9e66d2 100644 --- a/src/mainboard/amd/dinar/OptionsIds.h +++ b/src/mainboard/amd/dinar/OptionsIds.h @@ -42,15 +42,6 @@ * **/ -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index 1d1717b..425647e 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -72,10 +72,10 @@ unsigned long acpi_fill_madt(unsigned long current) } current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, - 0, //BUS - 0, //SOURCE - 2, //gsirq - 0 //flags + 0, /* BUS */ + 0, /* SOURCE */ + 2, /* gsirq */ + 0 /* flags */ ); /* 0: mean bus 0--->ISA */ diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index e237ff0..ee12dfc 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -26,33 +26,32 @@ #include "AGESA.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE -//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE /* AGESA will check the OEM configuration during preprocessing stage, * coreboot enable -Wundef option, so we should make sure we have all contanstand defined */ /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ /* Select the CPU family. */ @@ -79,23 +78,9 @@ * Comment out the items wanted to be included in the build. * Uncomment those items you with to REMOVE from the build. */ -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_DDR3_SUPPORT TRUE -//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE -//#define BLDOPT_REMOVE_SRAT TRUE -//#define BLDOPT_REMOVE_SLIT TRUE #define BLDOPT_REMOVE_WHEA TRUE -//#define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 120000 @@ -136,15 +121,11 @@ #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased #define BLDCFG_PLATFORM_C1E_OPDATA 0x2000 -//#define BLDCFG_USE_ATM_MODE TRUE #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0xCB0 -#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance //BatteryLife -//#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeMsgBasedC1e -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x2000 +#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance /* BatteryLife */ -//#define IDSOPT_IDS_ENABLED TRUE #define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE #define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT TRUE #define BLDCFG_PSTATE_HPC_MODE FALSE @@ -168,15 +149,17 @@ * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ -// This is the delivery package title, "MarG34PI" -// This string MUST be exactly 8 characters long +/* This is the delivery package title, "MarG34PI" + * This string MUST be exactly 8 characters long + */ #define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'} -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long +/* This is the release version number of the AGESA component + * This string MUST be exactly 12 characters long + */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '} -// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket. +/* The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket. */ #define INSTALL_G34_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_10_SUPPORT TRUE #define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE @@ -195,9 +178,10 @@ #endif #endif -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0xFF) #define DFLT_SCRUB_L2_RATE (0x10) #define DFLT_SCRUB_L3_RATE (0x10) @@ -216,8 +200,8 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, - { //BUID Swap List - { //BUID Swaps + { /* BUID Swap List */ + { /* BUID Swaps */ /* Each Non-coherent chain may have a list of device swaps, * Each item specify a device will be swap from its current id to a new one */ @@ -233,7 +217,7 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, }, - { //The ordered final BUIDs + { /* The ordered final BUIDs */ /* Specify the final BUID to be zero, All others are non applicable */ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, @@ -251,14 +235,6 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = #define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList -// And another platform specific one ... -//CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[2] = -//{ -// HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, -// HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, -// HT_LIST_TERMINAL -//}; - CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = { { @@ -282,14 +258,14 @@ CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = #define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList -// A performance-per-watt optimization. +/* A performance-per-watt optimization. */ CONST SKIP_REGANG ROMDATA PerfPerWatt[] = { { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF }, { HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF }, { HT_LIST_TERMINAL } }; -// uncomment the line below to make Perf-per-watt enabled by default. +/* uncomment the line below to make Perf-per-watt enabled by default. */ #define BLDCFG_LINK_SKIP_REGANG_LIST &PerfPerWatt @@ -313,7 +289,7 @@ CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] = CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = { - // Source Socket, Link (4-7 are sublink 1), Target Socket + /* Source Socket, Link (4-7 are sublink 1), Target Socket */ {0, 0, 1}, {0, 1, 1}, {0, 3, 1}, @@ -329,9 +305,9 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = */ CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] = { - // Socket, Link, SecBus, SubBus - { 0, 2, 0x00, 0xBF }, // RD890 of Dinar - { 1, 0, 0xC0, 0xFF }, // HTX + /* Socket, Link, SecBus, SubBus */ + { 0, 2, 0x00, 0xBF }, /* RD890 of Dinar */ + { 1, 0, 0xC0, 0xFF }, /* HTX */ { (HT_LIST_TERMINAL) } }; @@ -346,15 +322,6 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = }; #define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList -/* - CONST SKIP_REGANG ROMDATA DinarSkipRegangMap[] = - { -// {socketA, linkA, socketB, linkB} -{0, 0, 1, 1}, -}; - -#define BLDCFG_LINK_SKIP_REGANG_LIST &DinarSkipRegangMap -*/ /* * Device Capabilities Override for disabling ID Clumping diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c index affda6f..56dfb56 100644 --- a/src/mainboard/amd/dinar/gpio.c +++ b/src/mainboard/amd/dinar/gpio.c @@ -62,11 +62,11 @@ gpioEarlyInit( u32 SmiMmioAddr = 0; u32 andMask32 = 0; - // Enable HUDSON MMIO Base (AcpiMmioAddr) + /* Enable HUDSON MMIO Base (AcpiMmioAddr) */ ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); Data8 |= BIT0; WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); - // Get HUDSON MMIO Base (AcpiMmioAddr) + /* Get HUDSON MMIO Base (AcpiMmioAddr) */ ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); Data16 = Data8 << 8; ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8); @@ -77,109 +77,109 @@ gpioEarlyInit( MiscMmioAddr = AcpiMmioAddr + MISC_BASE; Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80); if ((Data8 & BIT4) == 0) { - BoardType = 0; // external clock board + BoardType = 0; /* external clock board */ } Data8 = Mmio8_G (GpioMmioAddr, GPIO_30); StripInfo = (Data8 & BIT7) >> 7; Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); StripInfo |= (Data8 & BIT7) >> 6; - if (StripInfo < boardRevC) { // for old board. Rev B - Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 - Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 + if (StripInfo < boardRevC) { /* for old board. Rev B */ + Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); /* function 3 */ + Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); /* function 0 */ } for (Index = 0; Index < MAX_GPIO_NO; Index++) { if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { - // Configure multi-function + /* Configure multi-function */ Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); } - // Configure GPIO + /* Configure GPIO */ if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); } if (Index == GPIO_65) { if ( BoardType == 0 ) { - Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 + Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); /* function 3 */ } } } - // Configure GEVENT + /* Configure GEVENT */ if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) { SmiMmioAddr = AcpiMmioAddr + SMI_BASE; andMask32 = ~(1 << (Index - GEVENT_00)); - //EventEnable: 0-Disable, 1-Enable + /*EventEnable: 0-Disable, 1-Enable */ Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); - //SciTrig: 0-Falling Edge, 1-Rising Edge + /*SciTrig: 0-Falling Edge, 1-Rising Edge */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); - //SciLevl: 0-Edge trigger, 1-Level Trigger + /*SciLevl: 0-Edge trigger, 1-Level Trigger */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); - //SmiSciEn: 0-Not send SMI, 1-Send SMI + /*SmiSciEn: 0-Not send SMI, 1-Send SMI */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); - //SciS0En: 0-Disable, 1-Enable + /*SciS0En: 0-Disable, 1-Enable */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); - //SciMap: 00000b ~ 11111b + /*SciMap: 00000b ~ 11111b */ RegIndex8=(u8)((Index - GEVENT_00) >> 2); Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8); Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); - //SmiTrig: 0-Active Low, 1-Active High + /*SmiTrig: 0-Active Low, 1-Active High */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); - //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 + /*SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 */ RegIndex8=(u8)((Index - GEVENT_00) >> 4); Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2); Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); } } - // - // config MXM - // GPIO9: Input for MXM_PRESENT2# - // GPIO10: Input for MXM_PRESENT1# - // GPIO28: Input for MXM_PWRGD - // GPIO35: Output for MXM Reset - // GPIO45: Output for MXM Power Enable, active HIGH - // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable - // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO - // - // set INTE#/GPIO32 as GPO for PCIE_SW - RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO + /* + * config MXM + * GPIO9: Input for MXM_PRESENT2# + * GPIO10: Input for MXM_PRESENT1# + * GPIO28: Input for MXM_PWRGD + * GPIO35: Output for MXM Reset + * GPIO45: Output for MXM Power Enable, active HIGH + * GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable + * GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO + */ + /* set INTE#/GPIO32 as GPO for PCIE_SW */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); /* GPO */ RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6); - // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN - RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO + /* set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); /* GPO */ - // set AD9/GPIO9 as GPI for MXM_PRESENT2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD9/GPIO9 as GPI for MXM_PRESENT2# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set AD10/GPIO10 as GPI for MXM_PRESENT1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD10/GPIO10 as GPI for MXM_PRESENT1# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set GNT1#/GPIO44 as GPO for MXM Reset - RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO + /* set GNT1#/GPIO44 as GPO for MXM Reset */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); /* GPO */ - // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO + /* set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); /* GPO */ - // set AD28/GPIO28 as GPI for MXM_PWRGD - RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD28/GPIO28 as GPI for MXM_PWRGD */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) + /* set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); @@ -187,20 +187,13 @@ gpioEarlyInit( RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3); - // - // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). - // - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20)); - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20))); + /* [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). */ - // check if there any GFX card + /* check if there any GFX card */ Flags = 0; - // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL); - // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09); ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8); if (!(Data8 & BIT7)) { - //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10); ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8); if (!(Data8 & BIT7)) { @@ -209,241 +202,187 @@ gpioEarlyInit( } if ( Flags ) { - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 + /* [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 */ RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH */ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) SbStall (10000); - // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module + /* Write the GPIO55(MXM_PWR_EN) to enable the integrated power module */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) - // WAIT POWER READY: GPIO28 (MXM_PWRGD) - //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); while (!(Data8 & BIT7)) { ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); } - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset - // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); } else { - // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module + /* Write the GPIO55(MXM_PWR_EN) to disable the integrated power module */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) SbStall (10000); - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down */ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); } - // - // APU GPP0: On board LAN - // GPIO25: PCIE_RST#_LAN, LOW active - // GPIO63: LAN_CLKREQ# - // GPIO197: LOM_POWER, HIGH Active - // Clock: GPP_CLK3 - // - // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER - RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - - // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 - - // - // APU GPP1: WUSB - // GPIO1: MPCIE_RST2#, LOW active - // GPIO13: WU_DISABLE#, LOW active - // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) - // - // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD01/GPIO01 as GPO for MPCIE_RST2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB - // RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO - // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH - // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // - // APU GPP2: WWAN - // GPIO0: MPCIE_RST1#, LOW active - // GPIO14: WP_DISABLE#, LOW active - // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) - // - // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD00/GPIO00 as GPO for MPCIE_RST1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO - // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN - // RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO - // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); - // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3); - - // - // APU GPP3: 1394 - // GPIO59: Power control, HIGH active - // GPIO27: PCIE_RST#_1394, LOW active - // GPIO41: CLKREQ# - // Clock: GPP_CLK8 - // - // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 - RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# - - // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C - RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - // To fix glitch issue - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - // - // Enable/Disable OnBoard LAN - // + /* + * APU GPP0: On board LAN + * GPIO25: PCIE_RST#_LAN, LOW active + * GPIO63: LAN_CLKREQ# + * GPIO197: LOM_POWER, HIGH Active + * Clock: GPP_CLK3 + * + * Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER + */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + + /* set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); /* CLK_REQ3# */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); /* Enable GPP_CLK3 */ + + /* + * APU GPP1: WUSB + * GPIO1: MPCIE_RST2#, LOW active + * GPIO13: WU_DISABLE#, LOW active + * GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) + * + * Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable + */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD01/GPIO01 as GPO for MPCIE_RST2# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* + * APU GPP2: WWAN + * GPIO0: MPCIE_RST1#, LOW active + * GPIO14: WP_DISABLE#, LOW active + * GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) + * + * Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable + */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Set AD00/GPIO00 as GPO for MPCIE_RST1# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* + * APU GPP3: 1394 + * GPIO59: Power control, HIGH active + * GPIO27: PCIE_RST#_1394, LOW active + * GPIO41: CLKREQ# + * Clock: GPP_CLK8 + */ + /* Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); /* CLK_REQ2# */ + + /* set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); /* GPO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + /* To fix glitch issue */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); /* set GPIO_GATE_C to LOW */ + + /* Enable/Disable OnBoard LAN */ + if (!CONFIG_ONBOARD_LAN) - { // 1 - DISABLED - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off + { /* 1 - DISABLED */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); /* LOM_POWER off */ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3 + RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); /* PULL UP - DISABLED */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); /* Disable GPP_CLK3 */ } - // else - // { // 0 - AUTO - // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable) - // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); - // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); - // } + /* Enable/Disable 1394 */ - // - // Enable/Disable 1394 - // if (!CONFIG_ONBOARD_1394) - { // 1 - DISABLED - // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off + { /* 1 - DISABLED */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); /* 1394 power off */ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 - // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); /* pullup DISABLE */ + RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); /* DISABLE GPP_CLK8 */ } - // else - // { // 0 - AUTO - // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH) - // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); - // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); - // - // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); - // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); - // } - - // - // external USB 3.0 control: - // amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE - // GPIO26: PCIE_RST#_USB3.0 - // GPIO46: PCIE_USB30_CLKREQ# - // GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON - // Clock: GPP_CLK7 - // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE - // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { - // disable Onboard NEC USB3.0 controller + + /* + * external USB 3.0 control: + * amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO26: PCIE_RST#_USB3.0 + * GPIO46: PCIE_USB30_CLKREQ# + * GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON + * Clock: GPP_CLK7 + * GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + */ + if (!CONFIG_ONBOARD_USB30) { RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 - RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); /* PULL_UP DISABLE */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); /* DISABLE GPP_CLK7 */ + RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */ } - // } - // - // BlueTooth control: BT_ON - // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE - // GPIO07: BT_ON, 0 - OFF, 1 - ON - // + /* BlueTooth control: BT_ON + * amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO07: BT_ON, 0 - OFF, 1 - ON + */ if (!CONFIG_ONBOARD_BLUETOOTH) { - //- if (SystemConfiguration.amdBlueTooth == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); - //- } } - // - // WebCam control: - // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE - // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF - // + /* + * WebCam control: + * amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF + */ if (!CONFIG_ONBOARD_WEBCAM) { - //- if (SystemConfiguration.amdWebCam == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); - //- } } - // - // Travis enable: - // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE - // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE - // + /* + * Travis enable: + * amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE + * GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE + */ if (!CONFIG_ONBOARD_TRAVIS) { - //- if (SystemConfiguration.amdTravisCtrl == 0) { RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); - //- } } - // - // Disable Light Sensor if needed - // + /* Disable Light Sensor if needed */ + if (CONFIG_ONBOARD_LIGHTSENSOR) { - //- if (SystemConfiguration.amdLightSensor == 1) { RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); - //- } } } diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h index 3ac8bfa..64368c9 100644 --- a/src/mainboard/amd/dinar/gpio.h +++ b/src/mainboard/amd/dinar/gpio.h @@ -83,87 +83,87 @@ #define FUNCTION1 1 #define FUNCTION2 2 #define FUNCTION3 3 -#define NonGpio 0x80 // BIT7 +#define NonGpio 0x80 /* BIT7 */ -// S0-domain General Purpose I/O: GPIO 00~67 -#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT -#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT -#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT -#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED -#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT -#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT -#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED -#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF -#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level -#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 -#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 -#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 -#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default -#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. -#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) -#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) -#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE -// 1:BATTERY IS FINE(DEFAULT) -// 0:BATTERY IS LOW -#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF -#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default -#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high -#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high -#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high -#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT -#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT -#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 -#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 -// 00 - REVA -// 01 - REVB -// 10 - REVC -// 11 - REVD -#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO -#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. -// 0:USB3.0 I/F in Express CARD -// 1:PCIE I/F in Express CARD detection -#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF -#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# -#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC -#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. -#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# -#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# -#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK -#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE -#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF -#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# -#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA -#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ -#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 -#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V -#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 -#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT -#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE -#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE -#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) -// 1:ENABLE; 0:DISABLE -// DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 -#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN -#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER -#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER -#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE -#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# -#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 -#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 -#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# -#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 -#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM -#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default -#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# +/* S0-domain General Purpose I/O: GPIO 00~67 */ +#define GPIO_00_SELECT FUNCTION1+NonGpio /* MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_01_SELECT FUNCTION1+NonGpio /* MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_02_SELECT FUNCTION1 /* MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_03_SELECT FUNCTION1+NonGpio /* NOT USED */ +#define GPIO_04_SELECT FUNCTION1+NonGpio /* x1 gpp reset, for J3701, low active, HIGH DEFAULT */ +#define GPIO_05_SELECT FUNCTION1+NonGpio /* express card reset, for J2500, low active, HIGH DEFAULT */ +#define GPIO_06_SELECT FUNCTION0+NonGpio /*NOT USED */ +#define GPIO_07_SELECT FUNCTION1 /* BT_ON, 1: BT ON(DEFAULT); 0: BT OFF */ +#define GPIO_08_SELECT FUNCTION1 /* PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level */ +#define GPIO_09_SELECT FUNCTION1+NonGpio /* MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED */ +#define GPIO_10_SELECT FUNCTION1+NonGpio /* MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED */ +#define GPIO_11_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_12_SELECT FUNCTION1 /* WL_DISABLE#, DISABLE THE WALN IN J3702 */ +#define GPIO_13_SELECT FUNCTION1 /* WU_DISABLE#, DISABLE THE WUSB IN J3711 */ +#define GPIO_14_SELECT FUNCTION1 /* WP_DISABLE, DISABLE THE WWAN IN J3703 */ +#define GPIO_15_SELECT FUNCTION1+NonGpio /* NOT USED, /*FUNCTION1, Reset_CEC# Low Active, High default */ */ +#define GPIO_16_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_17_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_18_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_19_SELECT FUNCTION1 /* For LASSO_DET# detection when Gevent14# is asserted. */ +#define GPIO_20_SELECT FUNCTION1 /* PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) */ +#define GPIO_21_SELECT FUNCTION1 /* DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) */ +#define GPIO_22_SELECT FUNCTION1 /* SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE */ +/* 1:BATTERY IS FINE(DEFAULT) */ +/* 0:BATTERY IS LOW */ +#define GPIO_23_SELECT FUNCTION1 /* CODEC_ON.1: CODEC ON (default)0: CODEC OFF */ +#define GPIO_24_SELECT FUNCTION1 /* Travis reset,Low active High default */ +#define GPIO_25_SELECT FUNCTION1+NonGpio /* PCIE_RST# for LAN (AND gate with PCIE_RST#); default high */ +#define GPIO_26_SELECT FUNCTION1+NonGpio /* PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high */ +#define GPIO_27_SELECT FUNCTION1+NonGpio /* PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high */ +#define GPIO_28_SELECT FUNCTION1 /* MXM PWRGD INDICATOR, INPUT */ +#define GPIO_29_SELECT FUNCTION1 /* MEM HOT, LOW ACTIVE, OUTPUT */ +#define GPIO_30_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 0 */ +#define GPIO_31_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 1 */ +/* 00 - REVA */ +/* 01 - REVB */ +/* 10 - REVC */ +/* 11 - REVD */ +#define GPIO_32_SELECT FUNCTION1+NonGpio /* PCIE_SW - HIGH:MXM; LOW:LASSO */ +#define GPIO_33_SELECT FUNCTION1 /* USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. */ +/* 0:USB3.0 I/F in Express CARD */ +/* 1:PCIE I/F in Express CARD detection */ +#define GPIO_34_SELECT FUNCTION1 /* WEBCAM_ON#. 0: ON (default) 1: OFF */ +#define GPIO_35_SELECT FUNCTION1 /* ODD_DA_INTH# */ +#define GPIO_36_SELECT FUNCTION0+NonGpio /* PCICLK FOR KBC */ +#define GPIO_37_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_38_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_39_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_40_SELECT FUNCTION1 /* For DOCK# detection when Gevent14# is asserted. */ +#define GPIO_41_SELECT FUNCTION1+NonGpio /* 1394 CLK REQ# */ +#define GPIO_42_SELECT FUNCTION1+NonGpio /* X4 GPP CLK REQ# */ +#define GPIO_43_SELECT FUNCTION0+NonGpio /* SMBUS0, CLOCK */ +#define GPIO_44_SELECT FUNCTION1+NonGpio /* PEGPIO0, RESET THE MXM MODULE */ +#define GPIO_45_SELECT FUNCTION2+NonGpio /* PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF */ +#define GPIO_46_SELECT FUNCTION1+NonGpio /* USB3.0_CLKREQ# */ +#define GPIO_47_SELECT FUNCTION0+NonGpio /* SMBUS0, DATA */ +#define GPIO_48_SELECT FUNCTION0+NonGpio /* SERIRQ */ +#define GPIO_49_SELECT FUNCTION0+NonGpio /* LDRQ#1 */ +#define GPIO_50_SELECT FUNCTION2 /* SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V */ +#define GPIO_51_SELECT FUNCTION0+NonGpio /* back-up for SMARTVOLTAGE1 */ +#define GPIO_52_SELECT FUNCTION0+NonGpio /* CPU FAN OUT */ +#define GPIO_53_SELECT FUNCTION1 /* ODD POWER ENABLE, HIGH ACTIVE */ +#define GPIO_54_SELECT FUNCTION0+NonGpio /* SB_PROCHOT, OUTPUT, LOW ACTIVE */ +#define GPIO_55_SELECT FUNCTION2+NonGpio /* MXM POWER ENABLE(POWER ON MODULE) */ +/* 1:ENABLE; 0:DISABLE */ +/* DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 */ +#define GPIO_56_SELECT FUNCTION0+NonGpio /*HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN */ +#define GPIO_57_SELECT FUNCTION1 /* HDD0_POWER */ +#define GPIO_58_SELECT FUNCTION1 /* HDD2_POWER */ +#define GPIO_59_SELECT FUNCTION2+NonGpio /* 1394 POWER, OUTPUT, HIGH ACTIVE */ +#define GPIO_60_SELECT FUNCTION0+NonGpio /* EXPCARD_CLKREQ# */ +#define GPIO_61_SELECT FUNCTION0+NonGpio /* PE0_CLKREQ#, FROM J3700 */ +#define GPIO_62_SELECT FUNCTION0+NonGpio /* PE2_CLKREQ#, FROM J3711 */ +#define GPIO_63_SELECT FUNCTION0+NonGpio /* LAN_CLKREQ# */ +#define GPIO_64_SELECT FUNCTION0+NonGpio /* PE1_CLKREQ#, FROM J3703 */ +#define GPIO_65_SELECT FUNCTION0+NonGpio /* MXM CLK REQ#, FROM MXM */ +#define GPIO_66_SELECT FUNCTION1 /* USED AS TRAVIS_EN#; 0:ENABLE as default */ +#define GPIO_67_SELECT FUNCTION0+NonGpio /* USED AS SATA_ACT# */ #define GPIO_68_SELECT FUNCTION0+NonGpio #define GPIO_69_SELECT FUNCTION0+NonGpio #define GPIO_70_SELECT FUNCTION0+NonGpio @@ -192,40 +192,40 @@ #define GPIO_93_SELECT FUNCTION0+NonGpio #define GPIO_94_SELECT FUNCTION0+NonGpio #define GPIO_95_SELECT FUNCTION0+NonGpio -// GEVENT 00~23 are mapped to GPIO 96~119 -#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# -#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# -#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP -#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# -#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# -#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active -#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, -// there is a confliction to IR function when this pin is as a GEVENT. -#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, -// special pin difination for SB700 VGA OUTPUT, high active, -// VGA power for Hudson-M2 will be down when it was asserted. -#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active -#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) -#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 -#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 -#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active -// [option for SPI_TPM_CS# in Hudson-M2 A12)] -#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & -// USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time -#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, -// plus judge GPIO40 and GPIO19 level,low is assert. -// LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) -// DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) -#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active -#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, -// low active, when it's low, BIOS will enbale ODD_PWR -#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# -#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK -#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# -#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT -#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 -#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# -#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI +/* GEVENT 00~23 are mapped to GPIO 96~119 */ +#define GPIO_96_SELECT FUNCTION0 /* GA20IN/GEVENT0# */ +#define GPIO_97_SELECT FUNCTION0 /* KBRST#/GEVENT1# */ +#define GPIO_98_SELECT FUNCTION0 /* THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP */ +#define GPIO_99_SELECT FUNCTION1 /* LPC_PME#/GEVENT3# -> EC_SCI# */ +#define GPIO_100_SELECT FUNCTION2 /* PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# */ +#define GPIO_101_SELECT FUNCTION1 /* LPC_PD#/GEVENT5# -> hotplug of express card, low active */ +#define GPIO_102_SELECT FUNCTION0+NonGpio /* USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, */ +/* there is a confliction to IR function when this pin is as a GEVENT. */ +#define GPIO_103_SELECT FUNCTION0+NonGpio /* DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, */ +/* special pin difination for SB700 VGA OUTPUT, high active, */ +/* VGA power for Hudson-M2 will be down when it was asserted. */ +#define GPIO_104_SELECT FUNCTION0 /* WAKE#/GEVENT8# -> WAKEUP, low active */ +#define GPIO_105_SELECT FUNCTION2 /* SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) */ +#define GPIO_106_SELECT FUNCTION0 /* GBE_LED2/GEVENT10# -> GBE_LED2 */ +#define GPIO_107_SELECT FUNCTION0+NonGpio /* GBE_STAT0/GEVENT11# -> GBE_STAT0 */ +#define GPIO_108_SELECT FUNCTION2 /* USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active */ +/* [option for SPI_TPM_CS# in Hudson-M2 A12)] */ +#define GPIO_109_SELECT FUNCTION0 /* USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & */ +/* USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time */ +#define GPIO_110_SELECT FUNCTION2 /* USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, */ +/* plus judge GPIO40 and GPIO19 level,low is assert. */ +/* LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) */ +/* DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) */ +#define GPIO_111_SELECT FUNCTION1+NonGpio /* USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active */ +#define GPIO_112_SELECT FUNCTION2 /* USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, */ +/* low active, when it's low, BIOS will enbale ODD_PWR */ +#define GPIO_113_SELECT FUNCTION2 /* USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# */ +#define GPIO_114_SELECT FUNCTION2 /* BLINK/USB_OC7#/GEVENT18# -> BLINK */ +#define GPIO_115_SELECT FUNCTION0 /* SYS_RESET#/GEVENT19# -> SYS_RST# */ +#define GPIO_116_SELECT FUNCTION0 /* R_RX1/GEVENT20# -> IR INPUT */ +#define GPIO_117_SELECT FUNCTION1+NonGpio /* SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 */ +#define GPIO_118_SELECT FUNCTION1 /* RI#/GEVENT22# -> LID_CLOSED# */ +#define GPIO_119_SELECT FUNCTION0 /* LPC_SMI#/GEVENT23# -> EC_SMI */ #define GPIO_120_SELECT FUNCTION0+NonGpio #define GPIO_121_SELECT FUNCTION0+NonGpio #define GPIO_122_SELECT FUNCTION0+NonGpio @@ -268,78 +268,78 @@ #define GPIO_159_SELECT FUNCTION0+NonGpio #define GPIO_160_SELECT FUNCTION0+NonGpio -// S5-domain General Purpose I/O -#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# -#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 -#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 -#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 -#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 -#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. -#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, -#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE -#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 -#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# -#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 -#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 -#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO -#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR -#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 -#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 -#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# -#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE -#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE -// option for HDMI CEC signal OW ACTIVE -#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active -#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT -#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA -#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK -#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active -// RESERVED FOR LCD BACKLIGHT PWM -#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL -#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM -#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF -#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD +/* S5-domain General Purpose I/O */ +#define GPIO_161_SELECT FUNCTION0+NonGpio /* ROM_RST# */ +#define GPIO_162_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_163_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_164_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_165_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_166_SELECT FUNCTION1+NonGpio /* GBE_STAT2 */ +#define GPIO_167_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN0 */ +#define GPIO_168_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN1 */ +#define GPIO_169_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN2 */ +#define GPIO_170_SELECT FUNCTION1+NonGpio /* gating the power control signal for ODD, see BIOS requirements doc for detail. */ +#define GPIO_171_SELECT FUNCTION0+NonGpio /* TEMPIN0, */ +#define GPIO_172_SELECT FUNCTION1 /* used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE */ +#define GPIO_173_SELECT FUNCTION0+NonGpio /* TEMPIN3 */ +#define GPIO_174_SELECT FUNCTION1+NonGpio /* USED AS TALERT# */ +#define GPIO_175_SELECT FUNCTION1 /* WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_176_SELECT FUNCTION1+NonGpio /* WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_177_SELECT FUNCTION2+NonGpio /* WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_178_SELECT FUNCTION2 /* MEM_1V5 */ +#define GPIO_179_SELECT FUNCTION2 /* MEM_1V35 */ +#define GPIO_180_SELECT FUNCTION0+NonGpio /* Use as VIN VDDIO */ +#define GPIO_181_SELECT FUNCTION0+NonGpio /* Use as VIN VDDR */ +#define GPIO_182_SELECT FUNCTION1+NonGpio /* GBE_LED3 */ +#define GPIO_183_SELECT FUNCTION0+NonGpio /* GBE_LED0 */ +#define GPIO_184_SELECT FUNCTION1+NonGpio /* USED AS LLB# */ +#define GPIO_185_SELECT FUNCTION0+NonGpio /* USED AS USB */ +#define GPIO_186_SELECT FUNCTION0+NonGpio /* USED AS USB */ +#define GPIO_187_SELECT FUNCTION2 /* USED AS AC LED INDICATOR, LOW ACTIVE */ +#define GPIO_188_SELECT FUNCTION2 /* default used AS BATT LED INDICATOR, LOW ACTIVE */ +/* option for HDMI CEC signal OW ACTIVE */ +#define GPIO_189_SELECT FUNCTION1 /* USED AS AC_OK RECIEVER, INPUT, low active */ +#define GPIO_190_SELECT FUNCTION1 /* USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT */ +#define GPIO_191_SELECT FUNCTION0+NonGpio /* TOUCH PAD, DATA */ +#define GPIO_192_SELECT FUNCTION0+NonGpio /* TOUCH PAD, CLK */ +#define GPIO_193_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_194_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_195_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_196_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_197_SELECT FUNCTION2+NonGpio /* Default GPIO for LOM_POWER, high active */ +/* RESERVED FOR LCD BACKLIGHT PWM */ +#define GPIO_198_SELECT FUNCTION0+NonGpio /* IMC SCROLL LED CONTROL */ +#define GPIO_199_SELECT FUNCTION3 /* STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM */ +#define GPIO_200_SELECT FUNCTION2 /* NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF */ +#define GPIO_201_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_202_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_203_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_204_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_205_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_206_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_207_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_208_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_209_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_210_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_211_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_212_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_213_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_214_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_215_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_216_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_217_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_218_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_219_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_220_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_221_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_222_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_223_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_224_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_225_SELECT FUNCTION2+NonGpio /* KSO */ +#define GPIO_226_SELECT FUNCTION2+NonGpio /* KSO */ +#define GPIO_227_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_228_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_229_SELECT FUNCTION0+NonGpio /* DP1_HPD */ #define TYPE_GPI (1 << 5) #define TYPE_GPO (0 << 5) @@ -441,7 +441,7 @@ #define GPIO_94_TYPE TYPE_GPO #define GPIO_95_TYPE TYPE_GPO -// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 +/* GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 */ #define GPIO_96_TYPE TYPE_GPI #define GPIO_97_TYPE TYPE_GPI #define GPIO_98_TYPE TYPE_GPI @@ -753,13 +753,13 @@ #define GPO_169_LEVEL GPO_LOW #define GPO_170_LEVEL GPO_HI #define GPO_171_LEVEL GPO_LOW -#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +#define GPO_172_LEVEL GPO_HI /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */ #define GPO_173_LEVEL GPO_LOW #define GPO_174_LEVEL GPO_LOW #define GPO_175_LEVEL GPO_LOW #define GPO_176_LEVEL GPO_LOW #define GPO_177_LEVEL GPO_LOW -#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU +#define GPO_178_LEVEL GPO_HI /* AMD.SR BU to set VDDIO level to 1.5V for Barb BU */ #define GPO_179_LEVEL GPO_HI #define GPO_180_LEVEL GPO_HI #define GPO_181_LEVEL GPO_LOW @@ -1523,28 +1523,28 @@ #define GEVENT_00_EVENTENABLE EVENT_DISABLE #define GEVENT_01_EVENTENABLE EVENT_DISABLE -#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# -#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# -#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# -#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# +#define GEVENT_02_EVENTENABLE EVENT_ENABLE /* APU THERMTRIP# */ +#define GEVENT_03_EVENTENABLE EVENT_ENABLE /* EC_SCI# */ +#define GEVENT_04_EVENTENABLE EVENT_ENABLE /* APU_MEMHOT# */ +#define GEVENT_05_EVENTENABLE EVENT_ENABLE /* PCIE_EXPCARD_PWREN# */ #define GEVENT_06_EVENTENABLE EVENT_DISABLE #define GEVENT_07_EVENTENABLE EVENT_DISABLE #define GEVENT_08_EVENTENABLE EVENT_DISABLE -#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO +#define GEVENT_09_EVENTENABLE EVENT_ENABLE /* WF_RADIO */ #define GEVENT_10_EVENTENABLE EVENT_DISABLE #define GEVENT_11_EVENTENABLE EVENT_DISABLE -#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# +#define GEVENT_12_EVENTENABLE EVENT_ENABLE /* SMBALERT# */ #define GEVENT_13_EVENTENABLE EVENT_DISABLE -#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# -#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# -#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA -#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN +#define GEVENT_14_EVENTENABLE EVENT_ENABLE /* LASSO_DET#/DOCK# */ +#define GEVENT_15_EVENTENABLE EVENT_ENABLE /* ODD_PLUGIN# */ +#define GEVENT_16_EVENTENABLE EVENT_ENABLE /* ODD_DA */ +#define GEVENT_17_EVENTENABLE EVENT_ENABLE /* TWARN */ #define GEVENT_18_EVENTENABLE EVENT_DISABLE #define GEVENT_19_EVENTENABLE EVENT_DISABLE #define GEVENT_20_EVENTENABLE EVENT_DISABLE #define GEVENT_21_EVENTENABLE EVENT_DISABLE -#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# -#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# +#define GEVENT_22_EVENTENABLE EVENT_ENABLE /* LID_CLOSE# */ +#define GEVENT_23_EVENTENABLE EVENT_DISABLE /* EC_SMI# */ #define SCITRIG_LOW 0 #define SCITRIG_HI 1 @@ -2255,14 +2255,14 @@ typedef enum _GEVENT_COUNT typedef struct _GEVENT_SETTINGS { - u8 EventEnable; // 0: Disable, 1: Enable - u8 SciTrig; // 0: Falling Edge, 1: Rising Edge - u8 SciLevl; // 0: Edge trigger, 1: Level Trigger - u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI - u8 SciS0En; // 0: Disable, 1: Enable - u8 SciMap; // 0000b->1111b - u8 SmiTrig; // 0: Active Low, 1: Active High - u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 + u8 EventEnable; /* 0: Disable, 1: Enable */ + u8 SciTrig; /* 0: Falling Edge, 1: Rising Edge */ + u8 SciLevl; /* 0: Edge trigger, 1: Level Trigger */ + u8 SmiSciEn; /* 0: Not send SMI, 1: Send SMI */ + u8 SciS0En; /* 0: Disable, 1: Enable */ + u8 SciMap; /* 0000b->1111b */ + u8 SmiTrig; /* 0: Active Low, 1: Active High */ + u8 SmiControl; /* 0: Disable, 1: SMI 2: NMI 3: IRQ13 */ } GEVENT_SETTINGS; GEVENT_SETTINGS gevent_table[] = diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 947ec65..ae08ee1 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -22,8 +22,6 @@ #include <device/pci_def.h> #include <NbPlatform.h> -//#define SMBUS_IO_BASE 0x6000 - void set_pcie_reset(void *nbconfig); void set_pcie_dereset(void *nbconfig); @@ -42,7 +40,6 @@ void set_pcie_reset(void *nbconfig) */ void set_pcie_dereset(void *nbconfig) { - //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); u32 i; u32 val; u32 nb_addr; diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index a8b53d0..048ecaf 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -95,7 +95,6 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin)) /* SMBUS */ - //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0 /* HD Audio */ PCI_INT(0x0, 0x14, 0x2, 0x10); @@ -117,7 +116,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */ /* SATA */ - PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG + PCI_INT(0x0, 0x11, 0x0, 0x16); /*6, INTG */ /* PCI slots */ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h index f10e4d7..9afba97 100644 --- a/src/mainboard/amd/dinar/platform_cfg.h +++ b/src/mainboard/amd/dinar/platform_cfg.h @@ -21,30 +21,25 @@ /** * Max number of northbridges in the system */ -#define MAX_NB_COUNT 1 //TODO: only 1 NB tested +#define MAX_NB_COUNT 1 /* TODO: only 1 NB tested */ /** * Enable check for PCIe endpoint to be ready for PCI enumeration. * */ -//#define EPREADY_WORKAROUND_DISABLED /** * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. * */ -#define IOMMU_SUPPORT_DISABLE //TODO: enable it +#define IOMMU_SUPPORT_DISABLE /* TODO: enable it */ /** * Disable server PCIe hotplug support. */ -//#define HOTPLUG_SUPPORT_DISABLED - /** * Disable support for device number remapping for PCIe portsserver PCIe hotplug support. */ -//#define DEVICE_REMAP_DISABLE - -#endif //_PLATFORM_CFG_H_ +#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c index 5459200..733435d 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.c +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -32,7 +32,6 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) { u16 i; PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; - //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; DEFAULT_PLATFORM_CONFIG(platform_config); @@ -93,7 +92,7 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) } } } -#endif // __PRE_RAM__ +#endif /* __PRE_RAM__ */ /** * @brief Entry point of Northbridge CIMx callout/CallBack @@ -166,9 +165,9 @@ static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config) case CB_AmdSetMidPostConfig: nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR; -#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu +#ifndef IOMMU_SUPPORT_DISABLE /*TODO enable iommu */ /* SBIOS must alloc 16K memory for IOMMU MMIO */ - UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress + UINT32 MmcfgBarAddress; /*using default IOmmuBaseAddress */ LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, AccessWidth32, &MmcfgBarAddress, @@ -177,7 +176,7 @@ static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config) if (MmcfgBarAddress != 0) { nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; } - nbConfigPtr->IommuBaseAddress = 0; //disable iommu + nbConfigPtr->IommuBaseAddress = 0; /*disable iommu */ #endif break; @@ -235,10 +234,10 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON sbNode = (val >> 8) & 0x07; PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); - sbLink = (val >> 8) & 0x07; //assum ganged + sbLink = (val >> 8) & 0x07; /*assum ganged */ pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; - //TODO: other NBs + /* TODO: other NBs */ #ifndef __PRE_RAM__ /* If temporrary MMIO enable set up CPU MMIO */ diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h index 8645553..5b5a213 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.h +++ b/src/mainboard/amd/dinar/rd890_cfg.h @@ -142,7 +142,6 @@ DEFAULT_GPP2_CONFIG, \ DEFAULT_GPP3A_CONFIG, \ DEFAULT_HT_DEEMPASIES, \ - /*DEFAULT_HT_PATH,*/ \ DEFAULT_APIC_INTERRUPT_BASE, \ } @@ -150,17 +149,16 @@ * Platform configuration */ typedef struct { - UINT16 PortEnableMap; ///< Bitmap of enabled ports - UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 - UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug - UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors - UINT32 TemporaryMmio; ///< Temporary MMIO - UINT32 Gpp1Config; ///< Default PCIe GFX core configuration - UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration - UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration - UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level - // HT_PATH NbHtPath; ///< HT path to NB - UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. + UINT16 PortEnableMap; /* Bitmap of enabled ports */ + UINT16 PortGen1Map; /* Bitmap of ports to disable Gen2 */ + UINT16 PortHotplugMap; /* Bitmap of ports support hotplug */ + UINT8 PortHotplugDescriptors[8];/* Ports Hotplug descriptors */ + UINT32 TemporaryMmio; /* Temporary MMIO */ + UINT32 Gpp1Config; /* Default PCIe GFX core configuration */ + UINT32 Gpp2Config; /* Default PCIe GPP2 core configuration */ + UINT32 Gpp3aConfig; /* Default PCIe GPP3a core configuration */ + UINT8 NbTransmitterDeemphasis; /* HT transmitter de-emphasis level */ + UINT8 GlobalApicInterruptBase; /* Global APIC interrupt base that is used in MADT table for IO APIC. */ } NB_PLATFORM_CONFIG; /** @@ -168,4 +166,4 @@ typedef struct { */ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); -#endif //_RD890_CFG_H_ +#endif /* _RD890_CFG_H_ */ diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index bc5d312..a1b1e3b 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -64,7 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x33); report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); @@ -101,5 +101,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x44); copy_and_run(); - post_code(0x45); // Should never see this post code. + post_code(0x45); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c index 797bed8..2a5eae3 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.c +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -83,8 +83,8 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->SpreadSpectrum = 0; sb_config->PciClk5 = 0; sb_config->PciClks = 0x1F; - sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood - sb_config->TimerClockSource = 2; // Auto + sb_config->ResetCpuOnSyncFlood = 1; /* Do not reset CPU on sync flood */ + sb_config->TimerClockSource = 2; /* Auto */ sb_config->S3Resume = 0; sb_config->RebootRequired = 0; @@ -92,28 +92,28 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->HpetTimer = HPET_TIMER; /* USB */ - sb_config->UsbIntClock = 0; // Use external clock - sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 - sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 - sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 - sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 - sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 - sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 - sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 - sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable + sb_config->UsbIntClock = 0; /* Use external clock */ + sb_config->Usb1Ohci0 = 1; /* 0:disable 1:enable Bus 0 Dev 18 Func0 */ + sb_config->Usb1Ohci1 = 1; /* 0:disable 1:enable Bus 0 Dev 18 Func1 */ + sb_config->Usb1Ehci = 1; /* 0:disable 1:enable Bus 0 Dev 18 Func2 */ + sb_config->Usb2Ohci0 = 1; /* 0:disable 1:enable Bus 0 Dev 19 Func0 */ + sb_config->Usb2Ohci1 = 1; /* 0:disable 1:enable Bus 0 Dev 19 Func1 */ + sb_config->Usb2Ehci = 1; /* 0:disable 1:enable Bus 0 Dev 19 Func2 */ + sb_config->Usb3Ohci = 1; /* 0:disable 1:enable Bus 0 Dev 20 Func5 */ + sb_config->UsbOhciLegacyEmulation = 1; /* 0:Enable 1:Disable */ sb_config->AcpiS1Supported = 1; /* SATA */ sb_config->SataController = 1; - sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; /* 0 native, 1 raid, 2 ahci */ sb_config->SataSmbus = 0; sb_config->SataAggrLinkPmCap = 1; sb_config->SataPortMultCap = 1; sb_config->SataClkAutoOff = 1; - sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. - //TODO: set to secondary not take effect. - sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled + sb_config->SataIdeCombMdPriSecOpt = 0; /* 0 -IDE as primary, 1 -IDE as secondary. */ + /* TODO: set to secondary not take effect. */ + sb_config->SataIdeCombinedMode = 0; /* 1 IDE controlor exposed and combined mode enabled, 0 disabled */ sb_config->SataEspPort = 0; sb_config->SataClkAutoOffAhciMode = 1; sb_config->SataHpcpButNonESP = 0; @@ -134,7 +134,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->StdHeader.pCallBack = (CIM_HOOK_ENTRY)&sb700_callout_entry; } - //sb_config-> -#endif //!__PRE_RAM__ + /* sb_config-> */ +#endif /* !__PRE_RAM__ */ printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - End.\n", __func__); } diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h index 02c3934..65327bf 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.h +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -187,7 +187,6 @@ * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN -//#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN #define AZALIA_SDIN_PIN_0 0x2 #define AZALIA_SDIN_PIN_1 0x2 @@ -234,4 +233,4 @@ void sb700_cimx_config(AMDSBCFG *sb_cfg); */ u32 sb700_callout_entry(u32 func, u32 data, void* config); -#endif //_SB700_CFG_H_ +#endif /* _SB700_CFG_H_ */ diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 4b64055..4c64b47 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -135,7 +135,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -152,13 +152,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; } @@ -168,13 +168,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; } @@ -184,13 +184,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c index d1f715c..8bcf666 100644 --- a/src/mainboard/amd/inagua/OemCustomize.c +++ b/src/mainboard/amd/inagua/OemCustomize.c @@ -48,25 +48,25 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -75,13 +75,13 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS + /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1) }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA + /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), @@ -96,11 +96,10 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) &DdiList[0] }; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h index 2d8381b..7a9c03f 100644 --- a/src/mainboard/amd/inagua/OptionsIds.h +++ b/src/mainboard/amd/inagua/OptionsIds.h @@ -43,14 +43,6 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h index 60045e1..fd92667 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h @@ -20,44 +20,44 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c index 640f639..92b5931 100644 --- a/src/mainboard/amd/inagua/broadcom.c +++ b/src/mainboard/amd/inagua/broadcom.c @@ -26,28 +26,28 @@ #include <types.h> #include <console/console.h> -#include <device/device.h> //Coreboot device access +#include <device/device.h> /* Coreboot device access */ #include <device/pci.h> #include <delay.h> #include <endian.h> void broadcom_init(void); -#define be16(x) cpu_to_be16(x) //a little easier to type -#define be(x) cpu_to_be32(x) //this is used a lot! +#define be16(x) cpu_to_be16(x) /* a little easier to type */ +#define be(x) cpu_to_be32(x) /* this is used a lot! */ /* C forces us to specify these before defining struct selfboot_patch :-( */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF #define INIT1_LENGTH 9 #define INIT2_LENGTH 10 #define INIT3_LENGTH 3 -#define INIT4_LENGTH 7 //this one may be 0 +#define INIT4_LENGTH 7 /* this one may be 0 */ #define PWRDN_LENGTH 5 #else #define INIT1_LENGTH 13 #define INIT2_LENGTH 6 #define INIT3_LENGTH 3 -#define INIT4_LENGTH 11 //this one may be 0 +#define INIT4_LENGTH 11 /* this one may be 0 */ #define PWRDN_LENGTH 4 #endif @@ -106,61 +106,61 @@ void broadcom_init(void); * not supported. */ -static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! +static struct selfboot_patch { /* Watch out: all values are *BIG-ENDIAN*! */ struct { /* Global header */ - u8 signature; //0xA5 - u8 format; //bits 7-3: patch format; 2-0: revision + u8 signature; /* 0xA5 */ + u8 format; /* bits 7-3: patch format; 2-0: revision */ u8 mac_addr[6]; - u16 subsys_device; //IDs will be loaded into PCI config space + u16 subsys_device; /* IDs will be loaded into PCI config space */ u16 subsys_vendor; - u16 pci_device; //PCI device ID; vendor is always Broadcom (0x14E4) - u8 unknown1[8]; //?, noticed no effect - u16 basic_config; //?, see below - u8 checksum; //byte sum of header == 0 - u8 unknown2; //?, patch rejected if changed - u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...) + u16 pci_device; /* PCI device ID; vendor is always Broadcom (0x14E4) */ + u8 unknown1[8]; /* ?, noticed no effect */ + u16 basic_config; /* ?, see below */ + u8 checksum; /* byte sum of header == 0 */ + u8 unknown2; /* ?, patch rejected if changed */ + u16 patch_version; /* 10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...) */ } header; struct { /* Init code */ - u8 checksum; //byte sum of init == 0 - u8 unknown; //?, looks unused - u8 num_hunks; //0x60 = 3 hunks, 0x80 = 4 hunks, other values not supported - u8 size; //total size of all hunk#_code[] in bytes - u8 hunk1_when; //mark when hunk1_code gets executed - u8 hunk1_size; //sizeof(hunk1_code) + u8 checksum; /* byte sum of init == 0 */ + u8 unknown; /* ?, looks unused */ + u8 num_hunks; /* 0x60 = 3 hunks, 0x80 = 4 hunks, other values not supported */ + u8 size; /* total size of all hunk#_code[] in bytes */ + u8 hunk1_when; /* mark when hunk1_code gets executed */ + u8 hunk1_size; /* sizeof(hunk1_code) */ u8 hunk2_when; u8 hunk2_size; u8 hunk3_when; u8 hunk3_size; - u8 hunk4_when; //0x00 (padding) if only 3 hunks - u8 hunk4_size; //dito - u32 hunk1_code[INIT1_LENGTH]; //actual commands, see below + u8 hunk4_when; /* 0x00 (padding) if only 3 hunks */ + u8 hunk4_size; /* dito */ + u32 hunk1_code[INIT1_LENGTH]; /* actual commands, see below */ u32 hunk2_code[INIT2_LENGTH]; u32 hunk3_code[INIT3_LENGTH]; - u32 hunk4_code[INIT4_LENGTH]; //missing (zero length) if only 3 hunks + u32 hunk4_code[INIT4_LENGTH]; /* missing (zero length) if only 3 hunks */ } init; struct { /* Power down code */ - u8 checksum; //byte sum of powerdown == 0 - u8 unknown; //?, looks unused - u8 num_hunks; //0x20 = 1 hunk, other values not supported - u8 size; //total size of all hunk#_code[] in bytes - u8 hunk1_when; //mark when hunk1_code gets executed - u8 hunk1_size; //sizeof(hunk1_code) - u16 padding; //0x0000, hunk2 is not supported - u32 hunk1_code[PWRDN_LENGTH]; //commands, see below + u8 checksum; /* byte sum of powerdown == 0 */ + u8 unknown; /* ?, looks unused */ + u8 num_hunks; /* 0x20 = 1 hunk, other values not supported */ + u8 size; /* total size of all hunk#_code[] in bytes */ + u8 hunk1_when; /* mark when hunk1_code gets executed */ + u8 hunk1_size; /* sizeof(hunk1_code) */ + u16 padding; /* 0x0000, hunk2 is not supported */ + u32 hunk1_code[PWRDN_LENGTH]; /* commands, see below */ } powerdown; } selfboot_patch = { /* Keep the following invariant for valid Selfboot patches */ .header.signature = 0xA5, - .header.format = 0x23, //format 1 revision 3 + .header.format = 0x23, /* format 1 revision 3 */ .header.unknown1 = { 0x61, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - .header.checksum = 0, //calculated later + .header.checksum = 0, /* calculated later */ .header.unknown2 = 0x30, - .init.checksum = 0, //calculated later + .init.checksum = 0, /* calculated later */ .init.unknown = 0x00, .init.num_hunks = sizeof(selfboot_patch.init.hunk4_code) ? 0x80 : 0x60, .init.size = sizeof(selfboot_patch.init.hunk1_code) @@ -171,7 +171,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! .init.hunk2_size = sizeof(selfboot_patch.init.hunk2_code), .init.hunk3_size = sizeof(selfboot_patch.init.hunk3_code), .init.hunk4_size = sizeof(selfboot_patch.init.hunk4_code), - .powerdown.checksum = 0, //calculated later + .powerdown.checksum = 0, /* calculated later */ .powerdown.unknown = 0x00, .powerdown.num_hunks = 0x20, .powerdown.size = sizeof(selfboot_patch.powerdown.hunk1_code), @@ -180,19 +180,19 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! /* Only the lines below may be adapted to your needs ... */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - .header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, //Broadcom - .header.subsys_device = be16(0x1699), //same as pci_device - .header.subsys_vendor = be16(0x14E4), //Broadcom + .header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, /* Broadcom */ + .header.subsys_device = be16(0x1699), /* same as pci_device */ + .header.subsys_vendor = be16(0x14E4), /* Broadcom */ #else - .header.mac_addr = { 0x00, 0x20, 0x9D, 0x00, 0x00, 0x00 }, //LiPPERT - .header.subsys_device = be16(0x1699), //simply kept this - .header.subsys_vendor = be16(0x121D), //LiPPERT + .header.mac_addr = { 0x00, 0x20, 0x9D, 0x00, 0x00, 0x00 }, /* LiPPERT */ + .header.subsys_device = be16(0x1699), /* simply kept this */ + .header.subsys_vendor = be16(0x121D), /* LiPPERT */ #endif - .header.pci_device = be16(0x1699), //Broadcom 5785 with GbE PHY + .header.pci_device = be16(0x1699), /* Broadcom 5785 with GbE PHY */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - .header.patch_version = be16(0x010B), //1.11 (Broadcom's sb5785m1.11) + .header.patch_version = be16(0x010B), /* 1.11 (Broadcom's sb5785m1.11) */ #else - .header.patch_version = be16(0x110B), //1.11b, i.e. hacked :-) + .header.patch_version = be16(0x110B), /* 1.11b, i.e. hacked :-) */ #endif /* Bitfield enabling general features/codepaths in the firmware or * selecting support for one of several supported PHYs? @@ -209,9 +209,9 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! * 1 X 1 | 0x391C6140 - - - */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - .header.basic_config = be16(0x0404), //original for B50610 + .header.basic_config = be16(0x0404), /* original for B50610 */ #else - .header.basic_config = be16(0x0604), //bit 9 set so not to mess up PHY regs, kept other bits unchanged + .header.basic_config = be16(0x0604), /* bit 9 set so not to mess up PHY regs, kept other bits unchanged */ #endif /* Tag that defines when / on what occasion the commands are interpreted. @@ -223,7 +223,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! * 68, 20, 70, 80 to be interpreted in this order. * All tests were performed with .basic_config = 0x0604. */ - .init.hunk1_when = 0x10, //only once at RISC CPU reset? + .init.hunk1_when = 0x10, /* only once at RISC CPU reset? */ /* Instructions are obviously a specialized bytecode interpreted by the * main firmware, rather than MIPS machine code. Commands consist of 1-3 * 32-bit words. In the following, 0-9,A-F = hex literals, a-z,_ = variable @@ -245,69 +245,68 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! */ .init.hunk1_code = { #if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0x082B8104), //CFR-AF: PHY0B: KSZ9021 select PHY104 - be(0x082CF0F0), //CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel) - be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105 - be(0x082C3333), //CFR-AF: PHY0C: KSZ9021 RX data skew (empirical) + be(0x082B8104), /* CFR-AF: PHY0B: KSZ9021 select PHY104 */ + be(0x082CF0F0), /* CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel) */ + be(0x082B8105), /* CFR-AF: PHY0B: KSZ9021 select PHY105 */ + be(0x082C3333), /* CFR-AF: PHY0C: KSZ9021 RX data skew (empirical) */ #endif - be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12 = 1: auto-clock-switch - be(0x06100D34), be(0x00000000), //v1.03 : MemD34: clear config vars - be(0x06100D38), be(0x00000000), //v1.03 : - | - be(0x06100D3C), be(0x00000000), //v1.03 : MemD3F| - }, //-->INIT1_LENGTH! + be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), /* v1.05 : 5A0.24,12 = 1: auto-clock-switch */ + be(0x06100D34), be(0x00000000), /* v1.03 : MemD34: clear config vars */ + be(0x06100D38), be(0x00000000), /* v1.03 : - | */ + be(0x06100D3C), be(0x00000000), /* v1.03 : MemD3F| */ + }, /* -->INIT1_LENGTH! */ - .init.hunk2_when = 0x30, //after global reset, PHY reset + .init.hunk2_when = 0x30, /* after global reset, PHY reset */ .init.hunk2_code = { #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0x08370F08), //v1.06 : PHY17: B50610 select reg. 08 - be(0x08350001), //v1.06 : PHY15: B50610 slow link fix - be(0x08370F00), //v1.06 : PHY17: B50610 disable reg. 08 - be(0x083C2C00), //v1.11 : PHY1C: B50610 Shadow 0B + be(0x08370F08), /* v1.06 : PHY17: B50610 select reg. 08 */ + be(0x08350001), /* v1.06 : PHY15: B50610 slow link fix */ + be(0x08370F00), /* v1.06 : PHY17: B50610 disable reg. 08 */ + be(0x083C2C00), /* v1.11 : PHY1C: B50610 Shadow 0B */ #endif - be(0xF7F301E6), //v1.09+: ?: subroutine calls to - be(0xF7FFF0B6), be(0x0000FFE7), //v1.09+: ?| restore Port Mode ??? - be(0xF7FFF0F6), be(0x00008000), //v1.09+: ?| - be(0xF7F401E6), //v1.09+: ?| - }, //-->INIT2_LENGTH! + be(0xF7F301E6), /* v1.09+: ?: subroutine calls to */ + be(0xF7FFF0B6), be(0x0000FFE7), /* v1.09+: ?| restore Port Mode ??? */ + be(0xF7FFF0F6), be(0x00008000), /* v1.09+: ?| */ + be(0xF7F401E6), /* v1.09+: ?| */ + }, /* -->INIT2_LENGTH! */ - .init.hunk3_when = 0xA8, //?, I'd guess quite late + .init.hunk3_when = 0xA8, /* ?, I'd guess quite late */ .init.hunk3_code = { - be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), //v1.08 : 3604.20-16: 10Mb clock = 12.5MHz - }, //-->INIT3_LENGTH! + be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), /* v1.08 : 3604.20-16: 10Mb clock = 12.5MHz */ + }, /* -->INIT3_LENGTH! */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - .init.hunk4_when = 0xD8, //original for B50610 + .init.hunk4_when = 0xD8, /* original for B50610 */ #else - .init.hunk4_when = 0x80, //run last, after Linux' "ifconfig up" + .init.hunk4_when = 0x80, /* run last, after Linux' "ifconfig up" */ #endif .init.hunk4_code = { #if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0x083F4300), //CFR-AF: PHY1F: IRQ active high - be(0x083C0000), //CFR-AF: PHY1C: revert driver writes - be(0x08380000), //CFR-AF: PHY18| - be(0x083C0000), //CFR-AF: PHY1C| + be(0x083F4300), /* CFR-AF: PHY1F: IRQ active high */ + be(0x083C0000), /* CFR-AF: PHY1C: revert driver writes */ + be(0x08380000), /* CFR-AF: PHY18| */ + be(0x083C0000), /* CFR-AF: PHY1C| */ #endif - be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0 == 1 -->skip next 12 bytes + be(0xCB0005A4), be(0xF7F0000C), /* v1.01 : if 5A4.0 == 1 -->skip next 12 bytes */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode + be(0xC61005A4), be(0x3210C500), /* v1.01 : 5A4: PHY LED mode */ #else - be(0xC61005A4), be(0x331C71CE), //CFR-AF: 5A4: fake LED mode + be(0xC61005A4), be(0x331C71CE), /* CFR-AF: 5A4: fake LED mode */ #endif - be(0xF7F00008), //v1.01 : -->skip next 8 bytes - be(0xC61005A4), be(0x331C71C1), //v1.01 : 5A4: inband LED mode - //be(0xC3200454), //CFR-AF: 454.4: auto link polling - }, //-->INIT4_LENGTH! + be(0xF7F00008), /* v1.01 : -->skip next 8 bytes */ + be(0xC61005A4), be(0x331C71C1), /* v1.01 : 5A4: inband LED mode */ + }, /* -->INIT4_LENGTH! */ - .powerdown.hunk1_when = 0x50, //prior to IDDQ MAC + .powerdown.hunk1_when = 0x50, /* prior to IDDQ MAC */ .powerdown.hunk1_code = { #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY + be(0x083CB001), /* v1.10 : PHY1C: IDDQ B50610 PHY */ #endif - be(0xF7F30116), // IDDQ PHY - be(0xC40005A0), //v1.09 : 5A0.0 = 0: Port Mode = MII - be(0xC4180400), //v1.09 : 400.3 = 0| - be(0xC3100400), //v1.09 : 400.2 = 1| - }, //-->PWRDN_LENGTH! + be(0xF7F30116), /* IDDQ PHY */ + be(0xC40005A0), /* v1.09 : 5A0.0 = 0: Port Mode = MII */ + be(0xC4180400), /* v1.09 : 400.3 = 0| */ + be(0xC3100400), /* v1.09 : 400.2 = 1| */ + }, /* -->PWRDN_LENGTH! */ }; @@ -316,8 +315,8 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! */ void broadcom_init(void) { - volatile u32 *gec_base; //Gigabit Ethernet Controller base addr - u8 *gec_shadow; //base addr of shadow 'NV'RAM for GbE MAC in A55E + volatile u32 *gec_base; /* Gigabit Ethernet Controller base addr */ + u8 *gec_shadow; /* base addr of shadow 'NV'RAM for GbE MAC in A55E */ u8 sum; int i; @@ -327,8 +326,8 @@ void broadcom_init(void) /* Halt RISC CPU before uploading the firmware patch */ for (i = 10000; i > 0; i--) { - gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state - gec_base[0x5000/4] |= (1 << 10); //issue RISC halt + gec_base[0x5004/4] = 0xFFFFFFFF; /* clear CPU state */ + gec_base[0x5000/4] |= (1 << 10); /* issue RISC halt */ if (gec_base[0x5000/4] | (1 << 10)) break; udelay(10); @@ -349,10 +348,10 @@ void broadcom_init(void) /* Upload firmware patch to shadow 'NV'RAM */ for (i = 0; i < sizeof(selfboot_patch); i++) - gec_shadow[i] = ((u8*)&selfboot_patch)[i]; //access byte-wise! + gec_shadow[i] = ((u8*)&selfboot_patch)[i]; /* access byte-wise! */ /* Restart BCM5785's CPU */ - gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state - gec_base[0x5000/4] = 0x00000001; //reset RISC processor - //usually we'd have to wait for the reset bit to clear again ... + gec_base[0x5004/4] = 0xFFFFFFFF; /* clear CPU state */ + gec_base[0x5000/4] = 0x00000001; /* reset RISC processor */ + /* usually we'd have to wait for the reset bit to clear again ... */ } diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 1c5c424..883dd85 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -74,7 +74,6 @@ #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE @@ -94,10 +93,7 @@ #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE @@ -106,65 +102,24 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 #define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE #define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 + #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE @@ -172,8 +127,6 @@ #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY @@ -181,16 +134,6 @@ #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE @@ -249,41 +192,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long +/* This is the delivery package title, "BrazosPI" */ +/* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long +/* This is the release version number of the AGESA component */ +/* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -292,5 +236,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data. */ #include "PlatformInstall.h" diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index d8e4f05..d7ca419 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -88,7 +88,6 @@ static void mainboard_enable(device_t dev) /* Upload AMD A55E GbE 'NV'RAM contents. Still untested on Inagua. * After anyone can confirm it works please uncomment the call. */ - //broadcom_init(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 2deb219..6053ac4 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -86,7 +86,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index d39a3ab..ea46291 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -161,7 +161,7 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA + #define AZALIA_SDIN_PIN 0x2A /** diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c index 2c633e5..221b4b3 100644 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -175,8 +175,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; //6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5; */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /* 6 | BIT3; */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -212,7 +212,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /* BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; @@ -247,7 +247,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; @@ -258,7 +258,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; @@ -268,7 +268,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;/* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, @@ -296,7 +296,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); /* Turn on FCH GPP slots */ diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index 0fec106..25e685b 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -108,9 +108,6 @@ const u8 mainboard_intr_data[] = { * use PIC IRQ 10 if it uses PIN A for its hardware INT. */ static const struct pirq_struct mainboard_pirq_data[] = { - /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ -// {GFX_DEVFN, {PIRQ_GFX, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ -// {ACTL_DEVFN, {PIRQ_NC, PIRQ_ACTL, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J119: 02.1 */ {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J118: 03.1 */ {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J120: 03.2 */ diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 9bf3a67..09a38bd 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -56,35 +56,6 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0xA8, word); } -#if 0 /* not tested yet */ -/******************************************************** -* mahogany uses SB700 GPIO9 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 5); /* Set Gpio9 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif /* get_ide_dma66 */ - u8 is_dev3_present(void) { return 0; diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index 708ddbd..9357b42 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 8c244d4..b197d36 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -56,35 +56,6 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0xA8, word); } -#if 0 /* not tested yet. */ -/******************************************************** -* mahogany uses SB700 GPIO9 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 5); /* Set Gpio9 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif /* get_ide_dma66() */ - u8 is_dev3_present(void) { return 0; diff --git a/src/mainboard/amd/mahogany_fam10/resourcemap.c b/src/mainboard/amd/mahogany_fam10/resourcemap.c index 95d009a..013f658 100644 --- a/src/mainboard/amd/mahogany_fam10/resourcemap.c +++ b/src/mainboard/amd/mahogany_fam10/resourcemap.c @@ -45,7 +45,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -83,7 +83,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -131,7 +131,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,7 +165,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,7 +191,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -223,7 +220,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -264,7 +260,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 1ee6698..0eda964 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/*used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -102,12 +100,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -166,10 +162,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -196,8 +192,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -208,21 +202,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 2361c03..e4be6e5 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -45,20 +45,20 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); * AMD Olivehill Platform ALC272 Verb Table */ static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT + {0x11, 0x411111F0}, /* - SPDIF_OUT2 */ + {0x12, 0x411111F0}, /* - DMIC_1/2 */ + {0x13, 0x411111F0}, /* - DMIC_3/4 */ + {0x14, 0x411111F0}, /* Port D - LOUT1 */ + {0x15, 0x411111F0}, /* Port A - LOUT2 */ + {0x16, 0x411111F0}, + {0x17, 0x411111F0}, /* Port H - MONO */ + {0x18, 0x01a19840}, /* Port B - MIC1 */ + {0x19, 0x411111F0}, /* Port F - MIC2 */ + {0x1a, 0x01813030}, /* Port C - LINE1 */ + {0x1b, 0x411111F0}, /* Port E - LINE2 */ + {0x1d, 0x40130605}, /* - PCBEEP */ + {0x1e, 0x01441120}, /* - SPDIF_OUT1 */ + {0x21, 0x01214010}, /* Port I - HPOUT */ {0xff, 0xffffffff} }; @@ -126,8 +126,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5; */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; /* 6 | BIT3; */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -138,7 +138,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /* AC0 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ @@ -161,7 +161,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111; /* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, @@ -190,7 +190,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h index eaf2442..bf623f7 100644 --- a/src/mainboard/amd/olivehill/OptionsIds.h +++ b/src/mainboard/amd/olivehill/OptionsIds.h @@ -43,17 +43,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 1d3fe77..d334604 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -53,36 +53,22 @@ #endif #endif -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE /* TRUE */ +#define BLDOPT_REMOVE_SLIT FALSE /* TRUE */ +#define BLDOPT_REMOVE_WHEA FALSE /* TRUE */ #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/*This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -104,11 +90,11 @@ #define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 /* Specifies the IO addresses trapped by the */ + /* core for C-state entry requests. A value */ + /* of 0 in this field specifies that the core */ + /* does not trap any IO addresses for C-state entry. */ + /* Values greater than 0xFFF8 results in undefined behavior. */ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE @@ -149,15 +135,10 @@ #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled #define BLDCFG_IOMMU_SUPPORT FALSE #define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL #define BLDCFG_CFG_ABM_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID #ifdef PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS @@ -174,43 +155,6 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = { @@ -244,40 +188,21 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE*/ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* QUANDRANK_TYPE*/ + +/* USER_MEMORY_TIMING_MODE */ + +/* POWER_DOWN_MODE */ /* * Agesa optional capabilities selection. @@ -322,17 +247,16 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL olivehill_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, {-1} }; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 9ae75ae..a540d0d 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; @@ -102,45 +101,7 @@ static void *smp_write_config_table(void *v) outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } -#if 0 - outb(0x0B, 0xCD6); - outb(0x02, 0xCD7); - outb(0x50, 0xCD6); - outb(0x1F, 0xCD7); - - outb(0x48, 0xCD6); - outb(0xF2, 0xCD7); - - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - - outb(0xED, 0xCD6); - outb(0x17, 0xCD7); - - *(volatile u8 *) (0xFED80D00 + 0x31) = 2; - *(volatile u8 *) (0xFED80D00 + 0x32) = 2; - *(volatile u8 *) (0xFED80D00 + 0x33) = 2; - *(volatile u8 *) (0xFED80D00 + 0x34) = 2; - - *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; - *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; - *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; - - *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; - *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; - *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; - *(volatile u8 *) (0xFED80100 + 0xA6) = 0; - - *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; -#endif /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c index 9528f72..82c8911 100644 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c @@ -49,20 +49,20 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); * Realtek ALC272 CODEC Verb Table */ static const CODEC_ENTRY Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40251E05}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT + {0x11, 0x411111F0}, /* - SPDIF_OUT2 */ + {0x12, 0x411111F0}, /* - DMIC_1/2 */ + {0x13, 0x411111F0}, /* - DMIC_3/4 */ + {0x14, 0x411111F0}, /* Port D - LOUT1 */ + {0x15, 0x411111F0}, /* Port A - LOUT2 */ + {0x16, 0x411111F0}, + {0x17, 0x411111F0}, /* Port H - MONO */ + {0x18, 0x01a19840}, /* Port B - MIC1 */ + {0x19, 0x411111F0}, /* Port F - MIC2 */ + {0x1a, 0x01813030}, /* Port C - LINE1 */ + {0x1b, 0x411111F0}, /* Port E - LINE2 */ + {0x1d, 0x40251E05}, /* - PCBEEP */ + {0x1e, 0x01441120}, /* - SPDIF_OUT1 */ + {0x21, 0x01214010}, /* Port I - HPOUT */ {0xff, 0xffffffff} }; @@ -141,8 +141,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; //6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; /* 6 | BIT3 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -178,7 +178,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /* BIT0 | BIT2 | BIT5 */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; @@ -213,7 +213,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; @@ -224,7 +224,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; @@ -234,7 +234,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; /* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, @@ -262,7 +262,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index 925526c..75a5798 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 6d1e4ea..9b14013 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -91,7 +91,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); AGESAWRAPPER(amdinitpost); - //PspMboxBiosCmdDramInfo(); post_code(0x41); AGESAWRAPPER(amdinitenv); /* diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index c83e318..1a97bb7 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -126,8 +126,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;/* 6 | BIT3 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -138,7 +138,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ @@ -161,7 +161,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111; /* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, @@ -190,7 +190,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h index eaf2442..bf623f7 100644 --- a/src/mainboard/amd/parmer/OptionsIds.h +++ b/src/mainboard/amd/parmer/OptionsIds.h @@ -43,17 +43,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 8ba3c53..8f6db7a 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -50,35 +50,22 @@ #define INSTALL_FM2_SOCKET_SUPPORT FALSE -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/* This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -126,7 +113,7 @@ #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 /* PCIE Spread Spectrum default value 0.36% */ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 #define BLDOPT_REMOVE_ALIB FALSE @@ -138,16 +125,10 @@ #define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 #define BLDCFG_CFG_ABM_SUPPORT 0 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity +/* Specify the default values for the VRM controlling the VDDNB plane. + * If not specified, the values used for the core VRM will be applied + */ #define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 @@ -157,17 +138,14 @@ #if CONFIG_GFXUMA #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000/*512M */ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif #define BLDCFG_IOMMU_SUPPORT FALSE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + /* Process the options... * This file include MUST occur AFTER the user option selection settings @@ -175,43 +153,7 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = { @@ -245,40 +187,40 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define DDR2100_FREQUENCY 1050 /* DDR 2100 */ +#define DDR2133_FREQUENCY 1066 /* DDR 2133 */ +#define DDR2400_FREQUENCY 1200 /* DDR 2400 */ +#define UNSUPPORTED_DDR_FREQUENCY 1201 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ /* * Agesa optional capabilities selection. @@ -323,7 +265,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL parmer_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, @@ -331,9 +272,10 @@ GPIO_CONTROL parmer_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&parmer_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index e10fc89..b630b71 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index b0b79ab..2cf07ed 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -40,8 +40,9 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); /* Call the host environment interface to provide a user hook opportunity. */ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) { - // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. - // Make sure the right speed settings are selected. + /* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. + * Make sure the right speed settings are selected. + */ ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } @@ -60,7 +61,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -72,7 +73,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; switch (ResetInfo->ResetId) { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + case 46: /* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */ switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index 825364e..dd99fe4 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -46,31 +46,31 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -79,18 +79,18 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeLvds, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} } }; @@ -102,11 +102,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &DdiList[0] }; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h index 2d8381b..7a9c03f 100644 --- a/src/mainboard/amd/persimmon/OptionsIds.h +++ b/src/mainboard/amd/persimmon/OptionsIds.h @@ -43,14 +43,6 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index 4132c7c..40489cc 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -21,45 +21,45 @@ #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 670010d..07a52e2 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -74,7 +74,6 @@ #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE @@ -94,10 +93,7 @@ #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE @@ -106,65 +102,24 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 #define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE #define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 + #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE @@ -172,8 +127,6 @@ #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY @@ -181,16 +134,6 @@ #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE @@ -249,41 +192,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long +/* This is the delivery package title, "BrazosPI" */ +/* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long +/* This is the release version number of the AGESA component */ +/* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -292,5 +236,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data. */ #include "PlatformInstall.h" diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 8e954cd..c726875 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 660be41..648ee17 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -161,7 +161,7 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA + #define AZALIA_SDIN_PIN 0x2A /** diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index ddc232f..282222d 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -80,7 +80,7 @@ unsigned long acpi_fill_madt(unsigned long current) for(i = 1; i< sysconf.hc_possible_num; i++) { u32 d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; - // 8131 need to use +4 + /* 8131 need to use +4 */ switch (sysconf.hcid[i]) { case 1: d = 7; @@ -141,15 +141,15 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp int i; - get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; - //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table + /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ - for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; @@ -160,16 +160,16 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp c = (u8) ('A' + i - 1 - 6); } current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt + printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */ ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { - case 1: //8132 + case 1: /* 8132 */ file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; - case 2: //8151 + case 2: /* 8151 */ file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; - case 3: //8131 + case 3: /* 8131 */ file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c index 6bb03e9..6cf5197 100644 --- a/src/mainboard/amd/serengeti_cheetah/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah/fadt.c @@ -41,11 +41,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; - // disable system management mode by setting to 0: - fadt->smi_cmd = 0;//pm_base+0x2f; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0;/* pm_base+0x2f */ fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; fadt->s4bios_req = 0x0; @@ -75,10 +75,10 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->flush_stride = 0; fadt->duty_offset = 1; fadt->duty_width = 3; - fadt->day_alrm = 0; // 0x7d these have to be - fadt->mon_alrm = 0; // 0x7e added to cmos.layout - fadt->century = 0; // 0x7f to make rtc alrm work - fadt->iapc_boot_arch = 0x3; // See table 5-11 + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ fadt->flags = 0x25; fadt->res2 = 0; diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index 1eb97b5..b7f55fd 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -23,30 +23,18 @@ #include <stdlib.h> #include "mb_sysconf.h" -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ struct mb_sysconf_t mb_sysconf; -static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +static unsigned pci1234x[] = { /*Here you only need to set value in pci1234 for HT-IO that could be installed or not */ + /* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */ 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 }; -static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most +static unsigned hcdnx[] = { /* HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */ 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, }; static unsigned get_bus_conf_done = 0; @@ -64,20 +52,20 @@ static unsigned get_hcid(unsigned i) dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); switch (dev->device) { - case 0x7458: //8132 + case 0x7458: /*8132 */ id = 1; break; - case 0x7454: //8151 + case 0x7454: /*8151 */ id = 2; break; - case 0x7450: //8131 + case 0x7450: /*8131 */ id = 3; break; } - // we may need more way to find out hcid: subsystem id? GPIO read ? + /* we may need more way to find out hcid: subsystem id? GPIO read ? */ - // we need use id for 1. bus num, 2. mptable, 3. ACPI table + /* we need use id for 1. bus num, 2. mptable, 3. ACPI table */ return id; } @@ -92,7 +80,7 @@ void get_bus_conf(void) struct mb_sysconf_t *m; if (get_bus_conf_done == 1) - return; //do it only once + return; /* do it only once */ get_bus_conf_done = 1; @@ -150,13 +138,13 @@ void get_bus_conf(void) if (!(sysconf.pci1234[i] & 0x1)) continue; - // check hcid type here + /* check hcid type here */ sysconf.hcid[i] = get_hcid(i); switch (sysconf.hcid[i]) { - case 1: //8132 - case 3: //8131 + case 1: /* 8132 */ + case 3: /* 8131 */ m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; @@ -190,7 +178,7 @@ void get_bus_conf(void) break; - case 2: //8151 + case 2: /* 8151 */ m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; m->sbdn5[j] = sysconf.hcdn[i] & 0xff; @@ -202,7 +190,6 @@ void get_bus_conf(void) if (dev) { m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - // printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", @@ -215,7 +202,7 @@ void get_bus_conf(void) j++; } -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address */ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) apicid_base = get_apicid_base(3); else @@ -227,5 +214,4 @@ void get_bus_conf(void) m->apicid_8132a[i][0] = apicid_base + 3 + i * 2; m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1; } - } diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c index 3d9820f..9e2e09b 100644 --- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c @@ -55,7 +55,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct mb_sysconf_t *m; - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ m = sysconf.mb; @@ -105,7 +105,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) } } -//pci bridge +/* pci bridge */ printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n"); static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 }; pci_assign_irqs(m->bus_8111_0, sysconf.sbdn + 1, slotIrqs_1_4); @@ -123,9 +123,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info++; slot_num++; -//pcix bridge -// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; +/* pcix bridge */ int j = 0; @@ -157,5 +155,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "done.\n"); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 2ffe4c9..fc421a9 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -41,8 +41,8 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); -/*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111 +/* I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */ { device_t dev; struct resource *res; @@ -69,8 +69,8 @@ static void *smp_write_config_table(void *v) if(!(sysconf.pci1234[i] & 0x1) ) continue; switch(sysconf.hcid[i]) { - case 1: // 8132 - case 3: // 8131 + case 1: /* 8132 */ + case 3: /* 8131 */ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -97,33 +97,33 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -//??? What +/* ??? What */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); -// Onboard AMD USB +/* Onboard AMD USB */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); -//Slot 3 PCI 32 +/*Slot 3 PCI 32 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */ } -//Slot 4 PCI 32 +/* Slot 4 PCI 32 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */ } -//Slot 1 PCI-X 133/100/66 +/* Slot 1 PCI-X 133/100/66 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); } -//Slot 2 PCI-X 133/100/66 +/* Slot 2 PCI-X 133/100/66 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */ } j = 0; @@ -140,9 +140,9 @@ static void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - //Slot 1 PCI-X 133/100/66 + /* Slot 1 PCI-X 133/100/66 */ for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); } } } @@ -151,9 +151,9 @@ static void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - //Slot 2 PCI-X 133/100/66 + /* Slot 2 PCI-X 133/100/66 */ for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); /* 25 */ } } } @@ -161,7 +161,7 @@ static void *smp_write_config_table(void *v) break; case 2: - // Slot AGP + /* Slot AGP */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); break; } diff --git a/src/mainboard/amd/serengeti_cheetah/resourcemap.c b/src/mainboard/amd/serengeti_cheetah/resourcemap.c index 3126dd3..92eaa9c 100644 --- a/src/mainboard/amd/serengeti_cheetah/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah/resourcemap.c @@ -260,8 +260,8 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, // AMD 8151 on link0 of CPU 1 + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, /* AMD 8111 on link0 of CPU 0 */ + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, /* AMD 8151 on link0 of CPU 1 */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index fff950a..5179448 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -37,8 +37,8 @@ static void memreset_setup(void) { - //GPIO on amd8111 to enable MEMRST ???? - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 + /* GPIO on amd8111 to enable MEMRST ???? */ + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } @@ -49,7 +49,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 int ret,i; unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time */ i = 2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); @@ -82,19 +82,19 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node + /* first node */ RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node + /* third node */ RC2|DIMM0, RC2|DIMM2, 0, 0, RC2|DIMM1, RC2|DIMM3, 0, 0, - // four node + /* four node */ RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, #endif @@ -114,27 +114,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_mb_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram - setup_coherent_ht_domain(); // routing table and start other core0 + set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */ + setup_coherent_ht_domain(); /* routing table and start other core0 */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + /* It is said that we should start core1 after all core0 launched */ /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) @@ -144,13 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - -#if 0 - //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); -#endif + ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */ #if CONFIG_SET_FIDVID /* Check to see if processor is capable of changing FIDVID */ @@ -169,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - // show final fid and vid + /* show final fid and vid */ { msr_t msr; msr = rdmsr(0xc0010042); @@ -185,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too + /* fidvid change will issue one LDTSTOP and the HT change will be effective too */ if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); @@ -193,36 +181,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + /* It's the time to set ctrl in sysinfo now; */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); -#if 0 - int i; - for(i = 0; i < 4; i++) { - activate_spd_rom(&cpu[i]); - dump_smbus_registers(); - } -#endif - memreset_setup(); - //do we need apci timer, tsc...., only debug need it for better output + /* do we need apci timer, tsc...., only debug need it for better output */ /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID + /* Need to use TMICT to synchronize FID/VID */ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); -#if 0 - print_pci_devices(); -#endif - -#if 0 -// dump_pci_devices(); - dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); - dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); -#endif - - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); /* bsp swtich stack to RAM and copy sysinfo RAM now */ } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index d7aaff2..399c086 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -53,7 +53,6 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, res->base, gsi_base ); gsi_base+=7; - } } dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); @@ -72,7 +71,7 @@ unsigned long acpi_fill_madt(unsigned long current) for(i = 1; i < sysconf.hc_possible_num; i++) { u32 d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; - // 8131 need to use +4 + /* 8131 need to use +4 */ switch (sysconf.hcid[i]) { case 1: d = 7; @@ -100,7 +99,6 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], res->base, gsi_base ); gsi_base+=d; - } } break; @@ -133,12 +131,13 @@ unsigned long mainboard_write_acpi_tables(device_t device, int i; - get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ /* same htio, but different possition? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ + * change HCIN, and recalculate the checknum and add_table + */ - for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; @@ -149,7 +148,7 @@ unsigned long mainboard_write_acpi_tables(device_t device, c = (u8) ('A' + i - 1 - 6); } current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt + printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); /* pci0 and pci1 are in dsdt */ ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: @@ -158,11 +157,11 @@ unsigned long mainboard_write_acpi_tables(device_t device, case 2: file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; - case 3: //8131 + case 3: /* 8131 */ file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: - //HTX no io apic + /* HTX no io apic */ file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; } p = cbfs_boot_map_with_leak( diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c index 7f54896..b6bcf81 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ - /* * ACPI - create the Fixed ACPI Description Tables (FADT) */ @@ -44,16 +43,15 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; - // disable system management mode by setting to 0: - fadt->smi_cmd = 0;//pm_base+0x2f; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0;/* pm_base+0x2f */ fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x00; // SMM is not used for p-state control -// fadt->pstate_cnt = 0xe2; + fadt->pstate_cnt = 0x00; /* SMM is not used for p-state control */ fadt->pm1a_evt_blk = pm_base; fadt->pm1b_evt_blk = 0x0000; @@ -72,18 +70,17 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe1_blk_len = 8; fadt->gpe1_base = 16; - fadt->cst_cnt = 0x00;// SMM is not used for p-state control -// fadt->cst_cnt = 0xe3; + fadt->cst_cnt = 0x00;/* SMM is not used for p-state control */ fadt->p_lvl2_lat = 101; fadt->p_lvl3_lat = 1001; fadt->flush_size = 0; fadt->flush_stride = 0; fadt->duty_offset = 1; fadt->duty_width = 3; - fadt->day_alrm = 0; // 0x7d these have to be - fadt->mon_alrm = 0; // 0x7e added to cmos.layout - fadt->century = 0; // 0x7f to make rtc alrm work - fadt->iapc_boot_arch = 0x3; // See table 5-11 + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ fadt->flags = 0x25; fadt->res2 = 0; @@ -115,7 +112,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; @@ -130,7 +126,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; @@ -138,7 +133,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm2_cnt_blk.addrl = 0x0; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; @@ -146,7 +140,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm_tmr_blk.addrl = pm_base+0x08; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 32; fadt->x_gpe0_blk.bit_offset = 0; @@ -154,7 +147,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_gpe0_blk.addrl = pm_base+0x20; fadt->x_gpe0_blk.addrh = 0x0; - fadt->x_gpe1_blk.space_id = 1; fadt->x_gpe1_blk.bit_width = 64; fadt->x_gpe1_blk.bit_offset = 16; @@ -163,5 +155,4 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_gpe1_blk.addrh = 0x0; header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index 87ca672..fda2626 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -29,8 +29,9 @@ struct mb_sysconf_t mb_sysconf; /* Here you only need to set value in pci1234 for HT-IO that could be -installed or not You may need to preset pci1234 for HTIO board, please -refer to src/northbridge/amd/amdfam10/get_sblk_pci1234.c for detail */ + * installed or not You may need to preset pci1234 for HTIO board, please + * refer to src/northbridge/amd/amdfam10/get_sblk_pci1234.c for detail + */ static u32 pci1234x[] = { 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, @@ -42,7 +43,8 @@ static u32 pci1234x[] = { /* HT Chain device num, actually it is unit id base of every ht device -in chain, assume every chain only have 4 ht device at most */ + * in chain, assume every chain only have 4 ht device at most + */ static unsigned hcdnx[] = { 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, @@ -70,18 +72,18 @@ static u32 get_hcid(u32 i) dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); switch (dev->device) { - case 0x7458: //8132 + case 0x7458: /* 8132 */ id = 1; break; - case 0x7454: //8151 + case 0x7454: /* 8151 */ id = 2; break; - case 0x7450: //8131 + case 0x7450: /* 8131 */ id = 3; break; } - // we may need more way to find out hcid: subsystem id? GPIO read ? - // we need use id for 1. bus num, 2. mptable, 3. ACPI table + /* we may need more way to find out hcid: subsystem id? GPIO read ? */ + /* we need use id for 1. bus num, 2. mptable, 3. ACPI table */ return id; } @@ -94,7 +96,7 @@ void get_bus_conf(void) struct mb_sysconf_t *m; if(get_bus_conf_done == 1) - return; //do it only once + return; /* do it only once */ get_bus_conf_done = 1; @@ -145,13 +147,13 @@ void get_bus_conf(void) for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; - // check hcid type here + /* check hcid type here */ sysconf.hcid[i] = get_hcid(i); switch(sysconf.hcid[i]) { - case 1: //8132 - case 3: //8131 + case 1: /* 8132 */ + case 3: /* 8131 */ m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 12) & 0xff; @@ -175,7 +177,7 @@ void get_bus_conf(void) break; - case 2: //8151 + case 2: /* 8151 */ m->bus_8151[j][0] = (sysconf.pci1234[i] >> 12) & 0xff; m->sbdn5[j] = sysconf.hcdn[i] & 0xff; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c index 4bb03c7..1ca7f3d 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c @@ -54,7 +54,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct mb_sysconf_t *m; - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ m = sysconf.mb; @@ -86,16 +86,14 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; - //pci bridge + /* pci bridge */ write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - //pcix bridge -// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; + /* pcix bridge */ int j = 0; @@ -142,5 +140,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "done.\n"); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 8699294..d800051 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -43,8 +43,8 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); - /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111 + /* I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */ { device_t dev; struct resource *res; @@ -99,33 +99,33 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ -//??? What +/* ??? What */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); - // Onboard AMD USB + /* Onboard AMD USB */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); - //Slot 3 PCI 32 + /* Slot 3 PCI 32 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */ } - // Slot 4 PCI 32 + /* Slot 4 PCI 32 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */ } - // Slot 1 PCI-X 133/100/66 + /* Slot 1 PCI-X 133/100/66 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); } - //Slot 2 PCI-X 133/100/66 + /* Slot 2 PCI-X 133/100/66 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */ } j = 0; @@ -144,9 +144,9 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { for(jj = 0; jj < 4; jj++) { - //Slot 1 PCI-X 133/100/66 + /* Slot 1 PCI-X 133/100/66 */ for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); } } } @@ -157,9 +157,9 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { for(jj = 0; jj < 4; jj++) { - //Slot 2 PCI-X 133/100/66 + /* Slot 2 PCI-X 133/100/66 */ for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); /* 25 */ } } } @@ -168,7 +168,7 @@ static void *smp_write_config_table(void *v) break; case 2: - // Slot AGP + /* Slot AGP */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); break; } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c index 8b432ed..fd14a80 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ - - static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { @@ -45,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 + /* Don't touch it, we need it for CAR with FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -83,7 +81,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR with FAM10 + /* don't touch it, we need it for CAR with FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -131,7 +129,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,7 +163,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,7 +189,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -223,7 +218,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -264,7 +258,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 1ccdf26..fa92219 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -14,10 +14,8 @@ */ #define SYSTEM_TYPE 0 /* SERVER */ -//#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -50,8 +48,8 @@ static void memreset_setup(void) { - //GPIO on amd8111 to enable MEMRST ???? - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN = 1 + /* GPIO on amd8111 to enable MEMRST ???? */ + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } @@ -87,16 +85,16 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" static const u8 spd_addr[] = { - //first node + /* first node */ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node + /* third node */ RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // forth node + /* forth node */ RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 4 @@ -208,12 +206,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -268,10 +264,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -308,8 +304,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -320,18 +314,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 711a0d5..71af45a 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -135,7 +135,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -153,13 +153,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; } @@ -170,13 +170,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; } @@ -187,13 +187,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c index 74b0aa8..be84cb1 100644 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ b/src/mainboard/amd/south_station/OemCustomize.c @@ -48,33 +48,33 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) }, #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -104,11 +104,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &DdiList[0] }; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h index 2d8381b..7a9c03f 100644 --- a/src/mainboard/amd/south_station/OptionsIds.h +++ b/src/mainboard/amd/south_station/OptionsIds.h @@ -43,14 +43,6 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h index 001ed16..0e0255e 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -20,45 +20,45 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 38a272d..dc60b77 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -74,7 +74,6 @@ #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE @@ -94,10 +93,7 @@ #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE @@ -106,65 +102,23 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 #define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE #define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE @@ -172,8 +126,6 @@ #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY @@ -181,16 +133,6 @@ #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE @@ -249,41 +191,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -292,5 +235,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data. */ #include "PlatformInstall.h" diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index b546ed8..d090e63 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -50,9 +50,9 @@ void set_pcie_dereset(void) */ static void southstation_led_init(void) { -#define GPIO_FUNCTION 2 //GPIO function -#define SB_GPIO_REG17 17 //Red Light -#define SB_GPIO_REG18 18 //Green Light +#define GPIO_FUNCTION 2 /* GPIO function */ +#define SB_GPIO_REG17 17 /* Red Light */ +#define SB_GPIO_REG18 18 /* Green Light */ /* multi-function pins switch to GPIO0-35 */ RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1); @@ -62,10 +62,10 @@ static void southstation_led_init(void) RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION); /* Lighting test */ - RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); /* output high */ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08); mdelay(100); - RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); /* output low */ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48); } diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index c24e42c..87572c5 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -83,7 +82,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index d39a3ab..7f825fd 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -161,7 +160,7 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA + #define AZALIA_SDIN_PIN 0x2A /** diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index a6a6279..6290608 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -126,8 +126,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /* 6 | BIT3 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -138,7 +138,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ @@ -161,7 +161,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111; /* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, @@ -190,7 +190,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (FchParams->StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index 66058f2..2d72f9e 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -120,19 +120,19 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - // DP0 to HDMI0/DP0 + /* DP0 to HDMI0/DP0 */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, - // DP1 to HDMI1/DP1 + /* DP1 to HDMI1/DP1 */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) }, - // DP2 to MINI-DDI Card + /* DP2 to MINI-DDI Card */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), @@ -172,11 +172,10 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h index eaf2442..bf623f7 100644 --- a/src/mainboard/amd/thatcher/OptionsIds.h +++ b/src/mainboard/amd/thatcher/OptionsIds.h @@ -43,17 +43,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 8ed3bf2..2b723c0 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -50,35 +50,21 @@ #define INSTALL_FM2_SOCKET_SUPPORT FALSE -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/* This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -126,7 +112,7 @@ #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 /* PCIE Spread Spectrum default value 0.36% */ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 #define BLDOPT_REMOVE_ALIB FALSE @@ -138,16 +124,11 @@ #define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 #define BLDCFG_CFG_ABM_SUPPORT 0 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity +/* Specify the default values for the VRM controlling the VDDNB plane. + * If not specified, the values used for the core VRM will be applied + */ + #define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 @@ -157,17 +138,13 @@ #if CONFIG_GFXUMA #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000/* 512M */ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif #define BLDCFG_IOMMU_SUPPORT FALSE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID /* Process the options... * This file include MUST occur AFTER the user option selection settings @@ -175,43 +152,7 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = { @@ -245,40 +186,40 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define DDR2100_FREQUENCY 1050 /* DDR 2100 */ +#define DDR2133_FREQUENCY 1066 /* DDR 2133 */ +#define DDR2400_FREQUENCY 1200 /* DDR 2400 */ +#define UNSUPPORTED_DDR_FREQUENCY 1201 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ /* * Agesa optional capabilities selection. @@ -323,7 +264,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 #define FCH_NO_XHCI_SUPPORT TRUE GPIO_CONTROL thatcher_gpio[] = { {183, Function1, PullUpB}, @@ -331,9 +271,10 @@ GPIO_CONTROL thatcher_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&thatcher_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 2640284..c61979f 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; @@ -173,7 +172,7 @@ static void *smp_write_config_table(void *v) /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 6652723..f3d67e4 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -88,35 +88,6 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0x7e, word); } -#if 0 /* TODO: */ -/******************************************************** -* tilapia uses SB700 GPIO8 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 4); /* Set Gpio8 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 4) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif - /* * justify the dev3 is exist or not */ @@ -251,18 +222,7 @@ static void set_thermal_config(void) pm_iowrite(0x3c, byte); /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); - * pm_iowrite(0x67, byte); - */ + } /************************************************* @@ -274,7 +234,6 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); set_pcie_dereset(); - /* get_ide_dma66(); */ set_thermal_config(); set_gpio40_gfx(); } diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c index 95d009a..d696c4d 100644 --- a/src/mainboard/amd/tilapia_fam10/resourcemap.c +++ b/src/mainboard/amd/tilapia_fam10/resourcemap.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ - - static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { @@ -45,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -83,7 +81,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -131,7 +129,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,7 +163,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,7 +189,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -223,7 +218,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -264,7 +258,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 1faac4d..c68fccc 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -102,12 +100,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -166,10 +162,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -196,8 +192,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -208,21 +202,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 0035a27..13c22eb 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -105,7 +105,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB MMIO Base (AcpiMmioAddr) + /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -117,15 +117,15 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; if (ResetInfo->ResetControl == DeassertSlotReset) { - if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + if (ResetInfo->ResetId & (BIT2+BIT3)) { /* de-assert */ + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45); if (Data8 & BIT7) { Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); while (!(Data8 & BIT7)) { Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); } - // GPIO44: PE_GPIO0 MXM Reset + /* GPIO44: PE_GPIO0 MXM Reset */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); @@ -134,53 +134,53 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi } else { Status = AGESA_UNSUPPORTED; } - // Travis + /* Travis */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); - //DE-Assert ALL PCIE RESET - // APU GPP0 (Dev 4) + /* DE-Assert ALL PCIE RESET */ + /* APU GPP0 (Dev 4) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); - // APU GPP1 (Dev 5) + /* APU GPP1 (Dev 5) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); - // APU GPP2 (Dev 6) + /* APU GPP2 (Dev 6) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); - // APU GPP3 (Dev 7) + /* APU GPP3 (Dev 7) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); } else { - if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported - // GPIO44: PE_GPIO0 MXM Reset + if (ResetInfo->ResetId & (BIT2+BIT3)) { /* Pcie Slot Reset is supported */ + /* GPIO44: PE_GPIO0 MXM Reset */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); Status = AGESA_SUCCESS; } - // Travis + /* Travis */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); - //Assert ALL PCIE RESET - // APU GPP0 (Dev 4) + /* Assert ALL PCIE RESET */ + /* APU GPP0 (Dev 4) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); - // APU GPP1 (Dev 5) + /* APU GPP1 (Dev 5) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); - // APU GPP2 (Dev 6) + /* APU GPP2 (Dev 6) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); - // APU GPP3 (Dev 7) + /* APU GPP3 (Dev 7) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index 0910ddc..86ececc 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -13,16 +13,13 @@ * GNU General Public License for more details. */ #ifndef BIOS_SIZE - #define BIOS_SIZE 0x04 //04 - 1MB + #define BIOS_SIZE 0x04 /* 04 - 1MB */ #endif #define LEGACY_FREE 0x00 #if !CONFIG_ONBOARD_USB30 #define XHCI_SUPPORT 0x01 #endif -//#define ACPI_SLEEP_TRAP 0x01 // No sleep trap smi support in coreboot. -//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01 - /** * Module Specific Defines for platform BIOS * @@ -74,7 +71,7 @@ * */ #ifndef WATCHDOG_TIMER_BASE_ADDRESS - #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address + #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 /* Watchdog Timer Base Address */ #endif /** @@ -82,7 +79,7 @@ * */ #ifndef HPET_BASE_ADDRESS - #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address + #define HPET_BASE_ADDRESS 0xFED00000 /* HPET Base address */ #endif /** @@ -107,43 +104,43 @@ * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address * */ -#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr +#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET /* AcpiPm1EvtBlkAddr */ /** * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address * */ -#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr +#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET /* AcpiPm1CntBlkAddr */ /** * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address * */ -#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr +#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET /* AcpiPmTmrBlkAddr */ /** * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address * */ -#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr +#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET /* CpuControlBlkAddr */ /** * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address * */ -#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr +#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET /* AcpiGpe0BlkAddr */ /** * SMI_CMD_PORT - ACPI SMI Command block base address * */ -#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr +#define SMI_CMD_PORT 0xB0 /* SmiCmdPortAddr */ /** * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address * */ -#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 /* AcpiPmaCntBlkAddr */ /** * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID. diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c index 3c20047..cba36bb 100644 --- a/src/mainboard/amd/torpedo/OemCustomize.c +++ b/src/mainboard/amd/torpedo/OemCustomize.c @@ -23,58 +23,53 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) }, - // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) + /* Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) }, - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) } - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) -// { -// DESCRIPTOR_TERMINATE_LIST, -// PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8), -// PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) -// } + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) }, - // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), @@ -114,11 +109,10 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h index 45abcab..77e1e90 100644 --- a/src/mainboard/amd/torpedo/OptionsIds.h +++ b/src/mainboard/amd/torpedo/OptionsIds.h @@ -42,15 +42,6 @@ * **/ -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h index 001ed16..0e0255e 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h @@ -20,45 +20,45 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index 656102d..24213cf 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -79,7 +79,7 @@ #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE -//For revision C single-link processors +/* For revision C single-link processors */ #define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE @@ -96,12 +96,12 @@ * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "LlanoPI " - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "LlanoPI " */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '} /* The following definitions specify the default values for various parameters @@ -119,8 +119,8 @@ /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 65000 //240000 //120000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 // 0 +#define BLDCFG_VRM_CURRENT_LIMIT 65000 /* 240000 */ /*120000 */ +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 /* 0 */ #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 #define BLDCFG_PLAT_NUM_IO_APICS 3 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST @@ -128,7 +128,7 @@ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY //DDR1066_FREQUENCY +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY /* DDR1066_FREQUENCY */ #define BLDCFG_MEMORY_MODE_UNGANGED TRUE #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED @@ -161,23 +161,14 @@ #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//enable HW C1E -#define BLDCFG_PLATFORM_C1E_MODE 0 //C1eModeHardware -//#define BLDCFG_PLATFORM_C1E_OPDATA 0x415 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 //0 //CStateModeC6 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 +/* enable HW C1E */ +#define BLDCFG_PLATFORM_C1E_MODE 0 /* C1eModeHardware */ +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 /* 0 */ +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 /* Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 */ -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero. -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime per BKDG. Defaults to 5000, same as core VRM. Cannot be zero. -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Llano/Ontario -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Llano/Ontario -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 /* Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero. */ #define BLDCFG_UMA_ABOVE4G_SUPPORT TRUE #define BLDCFG_STEREO_3D_PINOUT TRUE @@ -202,12 +193,6 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] = }; #define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList -//#define OPTION_NB_LCLK_DPM_INIT FALSE -//#define OPTION_POWER_GATE FALSE -//#define OPTION_PCIE_POWER_GATE FALSE -//#define OPTION_ALIB FALSE -//#define OPTION_PCIe_MID_INIT FALSE -//#define OPTION_NB_MID_INIT FALSE #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 56a90a6..5b34b9d 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - /* * ACPI - create the Fixed ACPI Description Tables (FADT) */ diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 03ab409..d3e905c 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -56,11 +56,11 @@ void gpioEarlyInit(void) { u32 SmiMmioAddr = 0; u32 andMask32 = 0; - // Enable HUDSON MMIO Base (AcpiMmioAddr) + /* Enable HUDSON MMIO Base (AcpiMmioAddr) */ ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); Data8 |= BIT0; WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); - // Get HUDSON MMIO Base (AcpiMmioAddr) + /* Get HUDSON MMIO Base (AcpiMmioAddr) */ ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); Data16 = Data8 << 8; ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8); @@ -71,109 +71,109 @@ void gpioEarlyInit(void) { MiscMmioAddr = AcpiMmioAddr + MISC_BASE; Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80); if ((Data8 & BIT4) == 0) { - BoardType = 0; // external clock board + BoardType = 0; /* external clock board */ } Data8 = Mmio8_G (GpioMmioAddr, GPIO_30); StripInfo = (Data8 & BIT7) >> 7; Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); StripInfo |= (Data8 & BIT7) >> 6; - if (StripInfo < boardRevC) { // for old board. Rev B - Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 - Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 + if (StripInfo < boardRevC) { /* for old board. Rev B */ + Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); /* function 3 */ + Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); /* function 0 */ } for (Index = 0; Index < MAX_GPIO_NO; Index++) { if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { - // Configure multi-function + /* Configure multi-function */ Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); } - // Configure GPIO + /* Configure GPIO */ if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); } if (Index == GPIO_65) { if ( BoardType == 0 ) { - Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 + Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); /* function 3 */ } } } - // Configure GEVENT + /* Configure GEVENT */ if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) { SmiMmioAddr = AcpiMmioAddr + SMI_BASE; andMask32 = ~(1 << (Index - GEVENT_00)); - //EventEnable: 0-Disable, 1-Enable + /* EventEnable: 0-Disable, 1-Enable */ Mmio32_And_Or(SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); - //SciTrig: 0-Falling Edge, 1-Rising Edge + /* SciTrig: 0-Falling Edge, 1-Rising Edge */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); - //SciLevl: 0-Edge trigger, 1-Level Trigger + /* SciLevl: 0-Edge trigger, 1-Level Trigger */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); - //SmiSciEn: 0-Not send SMI, 1-Send SMI + /* SmiSciEn: 0-Not send SMI, 1-Send SMI */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); - //SciS0En: 0-Disable, 1-Enable + /* SciS0En: 0-Disable, 1-Enable */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); - //SciMap: 00000b ~ 11111b + /* SciMap: 00000b ~ 11111b */ RegIndex8 = (u8)((Index - GEVENT_00) >> 2); Data8 = (u8)(((Index - GEVENT_00) & 0x3) * 8); Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); - //SmiTrig: 0-Active Low, 1-Active High + /* SmiTrig: 0-Active Low, 1-Active High */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); - //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 + /* SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 */ RegIndex8 = (u8)((Index - GEVENT_00) >> 4); Data8 = (u8)(((Index - GEVENT_00) & 0xF) * 2); Mmio32_And_Or(SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); } } - // - // config MXM - // GPIO9: Input for MXM_PRESENT2# - // GPIO10: Input for MXM_PRESENT1# - // GPIO28: Input for MXM_PWRGD - // GPIO35: Output for MXM Reset - // GPIO45: Output for MXM Power Enable, active HIGH - // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable - // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO - // - // set INTE#/GPIO32 as GPO for PCIE_SW - RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO + /* + * config MXM + * GPIO9: Input for MXM_PRESENT2# + * GPIO10: Input for MXM_PRESENT1# + * GPIO28: Input for MXM_PWRGD + * GPIO35: Output for MXM Reset + * GPIO45: Output for MXM Power Enable, active HIGH + * GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable + * GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO + */ + /* set INTE#/GPIO32 as GPO for PCIE_SW */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); /* GPO */ RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6); - // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN - RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO + /* set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); /* GPO */ - // set AD9/GPIO9 as GPI for MXM_PRESENT2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD9/GPIO9 as GPI for MXM_PRESENT2# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set AD10/GPIO10 as GPI for MXM_PRESENT1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD10/GPIO10 as GPI for MXM_PRESENT1# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set GNT1#/GPIO44 as GPO for MXM Reset - RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO + /* set GNT1#/GPIO44 as GPO for MXM Reset */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); /* GPO */ - // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO + /* set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); /* GPO */ - // set AD28/GPIO28 as GPI for MXM_PWRGD - RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD28/GPIO28 as GPI for MXM_PWRGD */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) + /* set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); @@ -181,20 +181,13 @@ void gpioEarlyInit(void) { RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3); - // - // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). - // - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20)); - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20))); + /* [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). */ - // check if there any GFX card + /* check if there any GFX card */ Flags = 0; - // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL); - // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09); ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8); if (!(Data8 & BIT7)) { - //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10); ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8); if (!(Data8 & BIT7)) { @@ -203,241 +196,193 @@ void gpioEarlyInit(void) { } if (Flags) { - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 + /* [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 */ RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH */ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + /*PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) */ SbStall (10000); - // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module + /* Write the GPIO55(MXM_PWR_EN) to enable the integrated power module */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) - // WAIT POWER READY: GPIO28 (MXM_PWRGD) - //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} + /* WAIT POWER READY: GPIO28 (MXM_PWRGD) */ + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); while (!(Data8 & BIT7)) { ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); } - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset - //RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); + /* [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset */ + /* RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); */ } else { - // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module + /* Write the GPIO55(MXM_PWR_EN) to disable the integrated power module */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) SbStall (10000); - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down */ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); } - // - // APU GPP0: On board LAN - // GPIO25: PCIE_RST#_LAN, LOW active - // GPIO63: LAN_CLKREQ# - // GPIO197: LOM_POWER, HIGH Active - // Clock: GPP_CLK3 - // - // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER - RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - - // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 - - // - // APU GPP1: WUSB - // GPIO1: MPCIE_RST2#, LOW active - // GPIO13: WU_DISABLE#, LOW active - // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) - // - // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD01/GPIO01 as GPO for MPCIE_RST2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB -// RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // - // APU GPP2: WWAN - // GPIO0: MPCIE_RST1#, LOW active - // GPIO14: WP_DISABLE#, LOW active - // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) - // - // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD00/GPIO00 as GPO for MPCIE_RST1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN -// RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3); - - // - // APU GPP3: 1394 - // GPIO59: Power control, HIGH active - // GPIO27: PCIE_RST#_1394, LOW active - // GPIO41: CLKREQ# - // Clock: GPP_CLK8 - // - // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 - RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# - - // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C - RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - // To fix glitch issue - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - // - // Enable/Disable OnBoard LAN - // + /* + * APU GPP0: On board LAN + * GPIO25: PCIE_RST#_LAN, LOW active + * GPIO63: LAN_CLKREQ# + * GPIO197: LOM_POWER, HIGH Active + * Clock: GPP_CLK3 + */ + /* Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + + /* set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); /* CLK_REQ3# */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); /* Enable GPP_CLK3 */ + + /* + * APU GPP1: WUSB + * GPIO1: MPCIE_RST2#, LOW active + * GPIO13: WU_DISABLE#, LOW active + * GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) + */ + /* Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD01/GPIO01 as GPO for MPCIE_RST2# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB */ + + + /* + * APU GPP2: WWAN + * GPIO0: MPCIE_RST1#, LOW active + * GPIO14: WP_DISABLE#, LOW active + * GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) + */ + /* Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Set AD00/GPIO00 as GPO for MPCIE_RST1# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN */ + + /* + * APU GPP3: 1394 + * GPIO59: Power control, HIGH active + * GPIO27: PCIE_RST#_1394, LOW active + * GPIO41: CLKREQ# + * Clock: GPP_CLK8 + */ + /* Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); /* CLK_REQ2# */ + + /* set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); /* GPO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + /* To fix glitch issue */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); /* set GPIO_GATE_C to LOW */ + + /* Enable/Disable OnBoard LAN */ + if (!CONFIG_ONBOARD_LAN) - { // 1 - DISABLED - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off + { /* 1 - DISABLED */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); /* LOM_POWER off */ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3 + RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); /* PULL UP - DISABLED */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); /* Disable GPP_CLK3 */ } -// else -// { // 0 - AUTO -// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable) -// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); -// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); -// } + /* Enable/Disable 1394 */ - // - // Enable/Disable 1394 - // if (!CONFIG_ONBOARD_1394) - { // 1 - DISABLED -// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off + { /* 1 - DISABLED */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); /* 1394 power off */ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 -// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); /* pullup DISABLE */ + RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); /* DISABLE GPP_CLK8 */ } -// else -// { // 0 - AUTO -// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH) -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); -// -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); -// } - -// -// external USB 3.0 control: -// amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO26: PCIE_RST#_USB3.0 -// GPIO46: PCIE_USB30_CLKREQ# -// GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON -// Clock: GPP_CLK7 -// GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE -// if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { -// disable Onboard NEC USB3.0 controller + +/* + * external USB 3.0 control: + * amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO26: PCIE_RST#_USB3.0 + * GPIO46: PCIE_USB30_CLKREQ# + * GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON + * Clock: GPP_CLK7 + * GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + */ +/* disable Onboard NEC USB3.0 controller */ if (!CONFIG_ONBOARD_USB30) { RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 - RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); /* PULL_UP DISABLE */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); /* DISABLE GPP_CLK7 */ + RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */ } -// } - -// -// BlueTooth control: BT_ON -// amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO07: BT_ON, 0 - OFF, 1 - ON -// +/* + * BlueTooth control: BT_ON + * amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO07: BT_ON, 0 - OFF, 1 - ON + */ if (!CONFIG_ONBOARD_BLUETOOTH) { - //- if (SystemConfiguration.amdBlueTooth == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); - //- } } -// -// WebCam control: -// amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF -// +/* + * WebCam control: + * amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF + */ if (!CONFIG_ONBOARD_WEBCAM) { - //- if (SystemConfiguration.amdWebCam == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); - //- } } -// -// Travis enable: -// amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE -// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE -// +/* + * Travis enable: + * amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE + * GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE + */ if (!CONFIG_ONBOARD_TRAVIS) { - //- if (SystemConfiguration.amdTravisCtrl == 0) { RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); - //- } } -// -// Disable Light Sensor if needed -// + +/* Disable Light Sensor if needed */ + if (CONFIG_ONBOARD_LIGHTSENSOR) { - //- if (SystemConfiguration.amdLightSensor == 1) { RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); - //- } } - } diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h index 0df5d50..0e64abd 100644 --- a/src/mainboard/amd/torpedo/gpio.h +++ b/src/mainboard/amd/torpedo/gpio.h @@ -83,87 +83,87 @@ #define FUNCTION1 1 #define FUNCTION2 2 #define FUNCTION3 3 -#define NonGpio 0x80 // BIT7 +#define NonGpio 0x80 /* BIT7 */ -// S0-domain General Purpose I/O: GPIO 00~67 -#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT -#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT -#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT -#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED -#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT -#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT -#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED -#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF -#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level -#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 -#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 -#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 -#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default -#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. -#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) -#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) -#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE - // 1:BATTERY IS FINE(DEFAULT) - // 0:BATTERY IS LOW -#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF -#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default -#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high -#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high -#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high -#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT -#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT -#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 -#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 - // 00 - REVA - // 01 - REVB - // 10 - REVC - // 11 - REVD -#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO -#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. - // 0:USB3.0 I/F in Express CARD - // 1:PCIE I/F in Express CARD detection -#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF -#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# -#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC -#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. -#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# -#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# -#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK -#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE -#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF -#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# -#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA -#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ -#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 -#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V -#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 -#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT -#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE -#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE -#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) - // 1:ENABLE; 0:DISABLE - // DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 -#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN -#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER -#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER -#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE -#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# -#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 -#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 -#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# -#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 -#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM -#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default -#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# +/* S0-domain General Purpose I/O: GPIO 00~67 */ +#define GPIO_00_SELECT FUNCTION1+NonGpio /* MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_01_SELECT FUNCTION1+NonGpio /* MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_02_SELECT FUNCTION1 /* MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_03_SELECT FUNCTION1+NonGpio /* NOT USED */ +#define GPIO_04_SELECT FUNCTION1+NonGpio /* x1 gpp reset, for J3701, low active, HIGH DEFAULT */ +#define GPIO_05_SELECT FUNCTION1+NonGpio /* express card reset, for J2500, low active, HIGH DEFAULT */ +#define GPIO_06_SELECT FUNCTION0+NonGpio /*NOT USED */ +#define GPIO_07_SELECT FUNCTION1 /* BT_ON, 1: BT ON(DEFAULT); 0: BT OFF */ +#define GPIO_08_SELECT FUNCTION1 /* PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level */ +#define GPIO_09_SELECT FUNCTION1+NonGpio /* MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED */ +#define GPIO_10_SELECT FUNCTION1+NonGpio /* MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED */ +#define GPIO_11_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_12_SELECT FUNCTION1 /* WL_DISABLE#, DISABLE THE WALN IN J3702 */ +#define GPIO_13_SELECT FUNCTION1 /* WU_DISABLE#, DISABLE THE WUSB IN J3711 */ +#define GPIO_14_SELECT FUNCTION1 /* WP_DISABLE, DISABLE THE WWAN IN J3703 */ +#define GPIO_15_SELECT FUNCTION1+NonGpio /* NOT USED, /*FUNCTION1, Reset_CEC# Low Active, High default */ */ +#define GPIO_16_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_17_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_18_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_19_SELECT FUNCTION1 /* For LASSO_DET# detection when Gevent14# is asserted. */ +#define GPIO_20_SELECT FUNCTION1 /* PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) */ +#define GPIO_21_SELECT FUNCTION1 /* DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) */ +#define GPIO_22_SELECT FUNCTION1 /* SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE */ + /* 1:BATTERY IS FINE(DEFAULT) */ + /* 0:BATTERY IS LOW */ +#define GPIO_23_SELECT FUNCTION1 /* CODEC_ON.1: CODEC ON (default)0: CODEC OFF */ +#define GPIO_24_SELECT FUNCTION1 /* Travis reset,Low active High default */ +#define GPIO_25_SELECT FUNCTION1+NonGpio /* PCIE_RST# for LAN (AND gate with PCIE_RST#); default high */ +#define GPIO_26_SELECT FUNCTION1+NonGpio /* PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high */ +#define GPIO_27_SELECT FUNCTION1+NonGpio /* PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high */ +#define GPIO_28_SELECT FUNCTION1 /* MXM PWRGD INDICATOR, INPUT */ +#define GPIO_29_SELECT FUNCTION1 /* MEM HOT, LOW ACTIVE, OUTPUT */ +#define GPIO_30_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 0 */ +#define GPIO_31_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 1 */ + /* 00 - REVA */ + /* 01 - REVB */ + /* 10 - REVC */ + /* 11 - REVD */ +#define GPIO_32_SELECT FUNCTION1+NonGpio /* PCIE_SW - HIGH:MXM; LOW:LASSO */ +#define GPIO_33_SELECT FUNCTION1 /* USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. */ + /* 0:USB3.0 I/F in Express CARD */ + /* 1:PCIE I/F in Express CARD detection */ +#define GPIO_34_SELECT FUNCTION1 /* WEBCAM_ON#. 0: ON (default) 1: OFF */ +#define GPIO_35_SELECT FUNCTION1 /* ODD_DA_INTH# */ +#define GPIO_36_SELECT FUNCTION0+NonGpio /* PCICLK FOR KBC */ +#define GPIO_37_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_38_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_39_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_40_SELECT FUNCTION1 /* For DOCK# detection when Gevent14# is asserted. */ +#define GPIO_41_SELECT FUNCTION1+NonGpio /* 1394 CLK REQ# */ +#define GPIO_42_SELECT FUNCTION1+NonGpio /* X4 GPP CLK REQ# */ +#define GPIO_43_SELECT FUNCTION0+NonGpio /* SMBUS0, CLOCK */ +#define GPIO_44_SELECT FUNCTION1+NonGpio /* PEGPIO0, RESET THE MXM MODULE */ +#define GPIO_45_SELECT FUNCTION2+NonGpio /* PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF */ +#define GPIO_46_SELECT FUNCTION1+NonGpio /* USB3.0_CLKREQ# */ +#define GPIO_47_SELECT FUNCTION0+NonGpio /* SMBUS0, DATA */ +#define GPIO_48_SELECT FUNCTION0+NonGpio /* SERIRQ */ +#define GPIO_49_SELECT FUNCTION0+NonGpio /* LDRQ#1 */ +#define GPIO_50_SELECT FUNCTION2 /* SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V */ +#define GPIO_51_SELECT FUNCTION0+NonGpio /* back-up for SMARTVOLTAGE1 */ +#define GPIO_52_SELECT FUNCTION0+NonGpio /* CPU FAN OUT */ +#define GPIO_53_SELECT FUNCTION1 /* ODD POWER ENABLE, HIGH ACTIVE */ +#define GPIO_54_SELECT FUNCTION0+NonGpio /* SB_PROCHOT, OUTPUT, LOW ACTIVE */ +#define GPIO_55_SELECT FUNCTION2+NonGpio /* MXM POWER ENABLE(POWER ON MODULE) */ + /* 1:ENABLE; 0:DISABLE */ + /* DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 */ +#define GPIO_56_SELECT FUNCTION0+NonGpio /* HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN */ +#define GPIO_57_SELECT FUNCTION1 /* HDD0_POWER */ +#define GPIO_58_SELECT FUNCTION1 /* HDD2_POWER */ +#define GPIO_59_SELECT FUNCTION2+NonGpio /* 1394 POWER, OUTPUT, HIGH ACTIVE */ +#define GPIO_60_SELECT FUNCTION0+NonGpio /* EXPCARD_CLKREQ# */ +#define GPIO_61_SELECT FUNCTION0+NonGpio /* PE0_CLKREQ#, FROM J3700 */ +#define GPIO_62_SELECT FUNCTION0+NonGpio /* PE2_CLKREQ#, FROM J3711 */ +#define GPIO_63_SELECT FUNCTION0+NonGpio /* LAN_CLKREQ# */ +#define GPIO_64_SELECT FUNCTION0+NonGpio /* PE1_CLKREQ#, FROM J3703 */ +#define GPIO_65_SELECT FUNCTION0+NonGpio /* MXM CLK REQ#, FROM MXM */ +#define GPIO_66_SELECT FUNCTION1 /* USED AS TRAVIS_EN#; 0:ENABLE as default */ +#define GPIO_67_SELECT FUNCTION0+NonGpio /* USED AS SATA_ACT# */ #define GPIO_68_SELECT FUNCTION0+NonGpio #define GPIO_69_SELECT FUNCTION0+NonGpio #define GPIO_70_SELECT FUNCTION0+NonGpio @@ -192,40 +192,40 @@ #define GPIO_93_SELECT FUNCTION0+NonGpio #define GPIO_94_SELECT FUNCTION0+NonGpio #define GPIO_95_SELECT FUNCTION0+NonGpio -// GEVENT 00~23 are mapped to GPIO 96~119 -#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# -#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# -#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP -#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# -#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# -#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active -#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, - // there is a confliction to IR function when this pin is as a GEVENT. -#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, - // special pin difination for SB900 VGA OUTPUT, high active, - // VGA power for Hudson-M2 will be down when it was asserted. -#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active -#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) -#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 -#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 -#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active - // [option for SPI_TPM_CS# in Hudson-M2 A12)] -#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & - // USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time -#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, - // plus judge GPIO40 and GPIO19 level,low is assert. - // LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) - // DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) -#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active -#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, - // low active, when it's low, BIOS will enbale ODD_PWR -#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# -#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK -#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# -#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT -#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 -#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# -#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI +/* GEVENT 00~23 are mapped to GPIO 96~119 */ +#define GPIO_96_SELECT FUNCTION0 /* GA20IN/GEVENT0# */ +#define GPIO_97_SELECT FUNCTION0 /* KBRST#/GEVENT1# */ +#define GPIO_98_SELECT FUNCTION0 /* THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP */ +#define GPIO_99_SELECT FUNCTION1 /* LPC_PME#/GEVENT3# -> EC_SCI# */ +#define GPIO_100_SELECT FUNCTION2 /* PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# */ +#define GPIO_101_SELECT FUNCTION1 /* LPC_PD#/GEVENT5# -> hotplug of express card, low active */ +#define GPIO_102_SELECT FUNCTION0+NonGpio /* USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, */ + /* there is a confliction to IR function when this pin is as a GEVENT. */ +#define GPIO_103_SELECT FUNCTION0+NonGpio /* DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, */ + /* special pin difination for SB900 VGA OUTPUT, high active, */ + /* VGA power for Hudson-M2 will be down when it was asserted. */ +#define GPIO_104_SELECT FUNCTION0 /* WAKE#/GEVENT8# -> WAKEUP, low active */ +#define GPIO_105_SELECT FUNCTION2 /* SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) */ +#define GPIO_106_SELECT FUNCTION0 /* GBE_LED2/GEVENT10# -> GBE_LED2 */ +#define GPIO_107_SELECT FUNCTION0+NonGpio /* GBE_STAT0/GEVENT11# -> GBE_STAT0 */ +#define GPIO_108_SELECT FUNCTION2 /* USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active */ + /* [option for SPI_TPM_CS# in Hudson-M2 A12)] */ +#define GPIO_109_SELECT FUNCTION0 /* USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & */ + /* USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time */ +#define GPIO_110_SELECT FUNCTION2 /* USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, */ + /* plus judge GPIO40 and GPIO19 level,low is assert. */ + /* LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) */ + /* DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) */ +#define GPIO_111_SELECT FUNCTION1+NonGpio /* USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active */ +#define GPIO_112_SELECT FUNCTION2 /* USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, */ + /* low active, when it's low, BIOS will enbale ODD_PWR */ +#define GPIO_113_SELECT FUNCTION2 /* USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# */ +#define GPIO_114_SELECT FUNCTION2 /* BLINK/USB_OC7#/GEVENT18# -> BLINK */ +#define GPIO_115_SELECT FUNCTION0 /* SYS_RESET#/GEVENT19# -> SYS_RST# */ +#define GPIO_116_SELECT FUNCTION0 /* R_RX1/GEVENT20# -> IR INPUT */ +#define GPIO_117_SELECT FUNCTION1+NonGpio /* SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 */ +#define GPIO_118_SELECT FUNCTION1 /* RI#/GEVENT22# -> LID_CLOSED# */ +#define GPIO_119_SELECT FUNCTION0 /* LPC_SMI#/GEVENT23# -> EC_SMI */ #define GPIO_120_SELECT FUNCTION0+NonGpio #define GPIO_121_SELECT FUNCTION0+NonGpio #define GPIO_122_SELECT FUNCTION0+NonGpio @@ -268,78 +268,78 @@ #define GPIO_159_SELECT FUNCTION0+NonGpio #define GPIO_160_SELECT FUNCTION0+NonGpio -// S5-domain General Purpose I/O -#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# -#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 -#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 -#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 -#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 -#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. -#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, -#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE -#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 -#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# -#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 -#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 -#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO -#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR -#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 -#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 -#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# -#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE -#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE - // option for HDMI CEC signal OW ACTIVE -#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active -#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT -#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA -#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK -#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active - // RESERVED FOR LCD BACKLIGHT PWM -#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL -#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM -#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF -#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD +/* S5-domain General Purpose I/O */ +#define GPIO_161_SELECT FUNCTION0+NonGpio /* ROM_RST# */ +#define GPIO_162_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_163_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_164_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_165_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_166_SELECT FUNCTION1+NonGpio /* GBE_STAT2 */ +#define GPIO_167_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN0 */ +#define GPIO_168_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN1 */ +#define GPIO_169_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN2 */ +#define GPIO_170_SELECT FUNCTION1+NonGpio /* gating the power control signal for ODD, see BIOS requirements doc for detail. */ +#define GPIO_171_SELECT FUNCTION0+NonGpio /* TEMPIN0, */ +#define GPIO_172_SELECT FUNCTION1 /* used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE */ +#define GPIO_173_SELECT FUNCTION0+NonGpio /* TEMPIN3 */ +#define GPIO_174_SELECT FUNCTION1+NonGpio /* USED AS TALERT# */ +#define GPIO_175_SELECT FUNCTION1 /* WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_176_SELECT FUNCTION1+NonGpio /* WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_177_SELECT FUNCTION2+NonGpio /* WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_178_SELECT FUNCTION2 /* MEM_1V5 */ +#define GPIO_179_SELECT FUNCTION2 /* MEM_1V35 */ +#define GPIO_180_SELECT FUNCTION0+NonGpio /* Use as VIN VDDIO */ +#define GPIO_181_SELECT FUNCTION0+NonGpio /* Use as VIN VDDR */ +#define GPIO_182_SELECT FUNCTION1+NonGpio /* GBE_LED3 */ +#define GPIO_183_SELECT FUNCTION0+NonGpio /* GBE_LED0 */ +#define GPIO_184_SELECT FUNCTION1+NonGpio /* USED AS LLB# */ +#define GPIO_185_SELECT FUNCTION0+NonGpio /* USED AS USB */ +#define GPIO_186_SELECT FUNCTION0+NonGpio /* USED AS USB */ +#define GPIO_187_SELECT FUNCTION2 /* USED AS AC LED INDICATOR, LOW ACTIVE */ +#define GPIO_188_SELECT FUNCTION2 /* default used AS BATT LED INDICATOR, LOW ACTIVE */ + /* option for HDMI CEC signal OW ACTIVE */ +#define GPIO_189_SELECT FUNCTION1 /* USED AS AC_OK RECIEVER, INPUT, low active */ +#define GPIO_190_SELECT FUNCTION1 /* USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT */ +#define GPIO_191_SELECT FUNCTION0+NonGpio /* TOUCH PAD, DATA */ +#define GPIO_192_SELECT FUNCTION0+NonGpio /* TOUCH PAD, CLK */ +#define GPIO_193_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_194_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_195_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_196_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_197_SELECT FUNCTION2+NonGpio /* Default GPIO for LOM_POWER, high active */ + /* RESERVED FOR LCD BACKLIGHT PWM */ +#define GPIO_198_SELECT FUNCTION0+NonGpio /* IMC SCROLL LED CONTROL */ +#define GPIO_199_SELECT FUNCTION3 /* STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM */ +#define GPIO_200_SELECT FUNCTION2 /* NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF */ +#define GPIO_201_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_202_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_203_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_204_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_205_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_206_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_207_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_208_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_209_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_210_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_211_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_212_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_213_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_214_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_215_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_216_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_217_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_218_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_219_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_220_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_221_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_222_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_223_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_224_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_225_SELECT FUNCTION2+NonGpio /* KSO */ +#define GPIO_226_SELECT FUNCTION2+NonGpio /* KSO */ +#define GPIO_227_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_228_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_229_SELECT FUNCTION0+NonGpio /* DP1_HPD */ #define TYPE_GPI (1 << 5) #define TYPE_GPO (0 << 5) @@ -441,7 +441,7 @@ #define GPIO_94_TYPE TYPE_GPO #define GPIO_95_TYPE TYPE_GPO -// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 +/* GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 */ #define GPIO_96_TYPE TYPE_GPI #define GPIO_97_TYPE TYPE_GPI #define GPIO_98_TYPE TYPE_GPI @@ -753,13 +753,13 @@ #define GPO_169_LEVEL GPO_LOW #define GPO_170_LEVEL GPO_HI #define GPO_171_LEVEL GPO_LOW -#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +#define GPO_172_LEVEL GPO_HI /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */ #define GPO_173_LEVEL GPO_LOW #define GPO_174_LEVEL GPO_LOW #define GPO_175_LEVEL GPO_LOW #define GPO_176_LEVEL GPO_LOW #define GPO_177_LEVEL GPO_LOW -#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU +#define GPO_178_LEVEL GPO_HI /* AMD.SR BU to set VDDIO level to 1.5V for Barb BU */ #define GPO_179_LEVEL GPO_HI #define GPO_180_LEVEL GPO_HI #define GPO_181_LEVEL GPO_LOW @@ -1523,28 +1523,28 @@ #define GEVENT_00_EVENTENABLE EVENT_DISABLE #define GEVENT_01_EVENTENABLE EVENT_DISABLE -#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# -#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# -#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# -#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# +#define GEVENT_02_EVENTENABLE EVENT_ENABLE /* APU THERMTRIP# */ +#define GEVENT_03_EVENTENABLE EVENT_ENABLE /* EC_SCI# */ +#define GEVENT_04_EVENTENABLE EVENT_ENABLE /* APU_MEMHOT# */ +#define GEVENT_05_EVENTENABLE EVENT_ENABLE /* PCIE_EXPCARD_PWREN# */ #define GEVENT_06_EVENTENABLE EVENT_DISABLE #define GEVENT_07_EVENTENABLE EVENT_DISABLE #define GEVENT_08_EVENTENABLE EVENT_DISABLE -#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO +#define GEVENT_09_EVENTENABLE EVENT_ENABLE /* WF_RADIO */ #define GEVENT_10_EVENTENABLE EVENT_DISABLE #define GEVENT_11_EVENTENABLE EVENT_DISABLE -#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# +#define GEVENT_12_EVENTENABLE EVENT_ENABLE /* SMBALERT# */ #define GEVENT_13_EVENTENABLE EVENT_DISABLE -#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# -#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# -#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA -#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN +#define GEVENT_14_EVENTENABLE EVENT_ENABLE /* LASSO_DET#/DOCK# */ +#define GEVENT_15_EVENTENABLE EVENT_ENABLE /* ODD_PLUGIN# */ +#define GEVENT_16_EVENTENABLE EVENT_ENABLE /* ODD_DA */ +#define GEVENT_17_EVENTENABLE EVENT_ENABLE /* TWARN */ #define GEVENT_18_EVENTENABLE EVENT_DISABLE #define GEVENT_19_EVENTENABLE EVENT_DISABLE #define GEVENT_20_EVENTENABLE EVENT_DISABLE #define GEVENT_21_EVENTENABLE EVENT_DISABLE -#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# -#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# +#define GEVENT_22_EVENTENABLE EVENT_ENABLE /* LID_CLOSE# */ +#define GEVENT_23_EVENTENABLE EVENT_DISABLE /* EC_SMI# */ #define SCITRIG_LOW 0 #define SCITRIG_HI 1 @@ -2255,14 +2255,14 @@ typedef enum _GEVENT_COUNT typedef struct _GEVENT_SETTINGS { - u8 EventEnable; // 0: Disable, 1: Enable - u8 SciTrig; // 0: Falling Edge, 1: Rising Edge - u8 SciLevl; // 0: Edge trigger, 1: Level Trigger - u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI - u8 SciS0En; // 0: Disable, 1: Enable - u8 SciMap; // 0000b->1111b - u8 SmiTrig; // 0: Active Low, 1: Active High - u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 + u8 EventEnable; /* 0: Disable, 1: Enable */ + u8 SciTrig; /* 0: Falling Edge, 1: Rising Edge */ + u8 SciLevl; /* 0: Edge trigger, 1: Level Trigger */ + u8 SmiSciEn; /* 0: Not send SMI, 1: Send SMI */ + u8 SciS0En; /* 0: Disable, 1: Enable */ + u8 SciMap; /* 0000b->1111b */ + u8 SmiTrig; /* 0: Active Low, 1: Active High */ + u8 SmiControl; /* 0: Disable, 1: SMI 2: NMI 3: IRQ13 */ } GEVENT_SETTINGS; const GEVENT_SETTINGS gevent_table[] = diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 86339ef..9bd9088 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #define ONE_MB 0x100000 -//#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void); void set_pcie_dereset(void); diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 8091ffb..8aeb250 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -95,7 +94,6 @@ static void *smp_write_config_table(void *v) cpu_flag, cpu_features, cpu_feature_flags ); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; @@ -130,7 +128,6 @@ static void *smp_write_config_table(void *v) #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0); /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb900, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb900, 0x1); diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index 0713e41..5009607 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -98,30 +97,19 @@ /** * @section Smbus0BaseAddress */ -// #ifndef SMBUS0_BASE_ADDRESS -// #define SMBUS0_BASE_ADDRESS 0xB00 -// #endif /** * @section Smbus1BaseAddress */ -// #ifndef SMBUS1_BASE_ADDRESS -// #define SMBUS1_BASE_ADDRESS 0xB21 -// #endif /** * @section SioPmeBaseAddress */ -// #ifndef SIO_PME_BASE_ADDRESS -// #define SIO_PME_BASE_ADDRESS 0xE00 -// #endif /** * @section WatchDogTimerBase */ -// #ifndef WATCHDOG_TIMER_BASE_ADDRESS -// #define WATCHDOG_TIMER_BASE_ADDRESS IO_APIC_ADDR -// #endif + /** * @section GecShadowRomAddress @@ -133,58 +121,39 @@ /** * @section SpiRomBaseAddress */ -// #ifndef SPI_BASE_ADDRESS -// #define SPI_BASE_ADDRESS 0xFEC10000 -// #endif /** * @section AcpiPm1EvtBlkAddr */ -// #ifndef PM1_EVT_BLK_ADDRESS -// #define PM1_EVT_BLK_ADDRESS 0x400 -// #endif /** * @section AcpiPm1CntBlkAddr */ -// #ifndef PM1_CNT_BLK_ADDRESS -// #define PM1_CNT_BLK_ADDRESS 0x404 -// #endif + /** * @section AcpiPmTmrBlkAddr */ -// #ifndef PM1_TMR_BLK_ADDRESS -// #define PM1_TMR_BLK_ADDRESS 0x408 -// #endif + /** * @section CpuControlBlkAddr */ -// #ifndef CPU_CNT_BLK_ADDRESS -// #define CPU_CNT_BLK_ADDRESS 0x410 -// #endif + /** * @section AcpiGpe0BlkAddr */ -// #ifndef GPE0_BLK_ADDRESS -// #define GPE0_BLK_ADDRESS 0x420 -// #endif + /** * @section SmiCmdPortAddr */ -// #ifndef SMI_CMD_PORT -// #define SMI_CMD_PORT 0xB0 -// #endif /** * @section AcpiPmaCntBlkAddr */ -// #ifndef ACPI_PMA_CNT_BLK_ADDRESS -// #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -// #endif + /** * @section InChipSataController @@ -1192,7 +1161,7 @@ #define INCHIP_STRESS_RESET_MODE 0 #ifndef SB_PCI_CLOCK_RESERVED - #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F + #define SB_PCI_CLOCK_RESERVED 0x0 /* according to CIMx change 0x1F */ #endif /** @@ -1214,7 +1183,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_cfg); */ u32 sb900_callout_entry(u32 func, u32 data, void* config); -// definition for function in gpio.c +/* definition for function in gpio.c */ void gpioEarlyInit (void); #endif diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 74402bf..e8395fa 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -61,7 +61,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x34); report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); @@ -87,5 +87,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run returned!\n"); - post_code(0x44); // Should never see this post code. + post_code(0x44); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 711a0d5..71af45a 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -135,7 +135,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -153,13 +153,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; } @@ -170,13 +170,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; } @@ -187,13 +187,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c index 6f4dbfc..5378e2d 100644 --- a/src/mainboard/amd/union_station/OemCustomize.c +++ b/src/mainboard/amd/union_station/OemCustomize.c @@ -52,33 +52,33 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) }, #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -87,18 +87,18 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + /*PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */ {ConnectorTypeHDMI, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + /*PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ {ConnectorTypeHDMI, Aux2, Hdp2} } }; @@ -110,11 +110,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &DdiList[0] }; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h index 2d8381b..7a9c03f 100644 --- a/src/mainboard/amd/union_station/OptionsIds.h +++ b/src/mainboard/amd/union_station/OptionsIds.h @@ -43,14 +43,6 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h index 001ed16..0e0255e 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h @@ -20,45 +20,45 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 38a272d..648212c 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -29,7 +29,6 @@ #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE @@ -74,7 +73,6 @@ #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE @@ -94,10 +92,7 @@ #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE @@ -106,65 +101,23 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 #define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE #define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE @@ -172,8 +125,6 @@ #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY @@ -181,16 +132,6 @@ #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE @@ -249,41 +190,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -292,5 +234,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data. */ #include "PlatformInstall.h" diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index c24e42c..87572c5 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -83,7 +82,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index d39a3ab..4e6adb1 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -161,7 +161,6 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A /**

1 0

New patch to review for coreboot: mainboard/amd: Use C89 comments style & remove commented code
by HAOUAS Elyes 06 Oct '16

06 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16907 -gerrit commit d4e18ad3df65ca0080e19d0076178e0856167357 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Oct 6 18:37:35 2016 +0200 mainboard/amd: Use C89 comments style & remove commented code Change-Id: I137b27ffb0e54a9ca6b0bd3a454b1d99b3e1c22b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/bettong/BiosCallOuts.c | 1 - src/mainboard/amd/bettong/OemCustomize.c | 4 +- src/mainboard/amd/bettong/mptable.c | 1 - src/mainboard/amd/bimini_fam10/mainboard.c | 40 -- src/mainboard/amd/bimini_fam10/resourcemap.c | 11 +- src/mainboard/amd/bimini_fam10/romstage.c | 29 +- src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c | 13 +- src/mainboard/amd/db-ft3b-lc/OemCustomize.c | 120 +++--- src/mainboard/amd/db-ft3b-lc/romstage.c | 1 - src/mainboard/amd/dinar/OemCustomize.c | 11 +- src/mainboard/amd/dinar/OptionsIds.h | 9 - src/mainboard/amd/dinar/acpi_tables.c | 8 +- src/mainboard/amd/dinar/buildOpts.c | 107 ++--- src/mainboard/amd/dinar/gpio.c | 427 +++++++++----------- src/mainboard/amd/dinar/gpio.h | 418 ++++++++++---------- src/mainboard/amd/dinar/mainboard.c | 3 - src/mainboard/amd/dinar/mptable.c | 3 +- src/mainboard/amd/dinar/platform_cfg.h | 11 +- src/mainboard/amd/dinar/rd890_cfg.c | 13 +- src/mainboard/amd/dinar/rd890_cfg.h | 24 +- src/mainboard/amd/dinar/romstage.c | 4 +- src/mainboard/amd/dinar/sb700_cfg.c | 34 +- src/mainboard/amd/dinar/sb700_cfg.h | 3 +- src/mainboard/amd/inagua/BiosCallOuts.c | 14 +- src/mainboard/amd/inagua/OemCustomize.c | 19 +- src/mainboard/amd/inagua/OptionsIds.h | 8 - src/mainboard/amd/inagua/PlatformGnbPcieComplex.h | 82 ++-- src/mainboard/amd/inagua/broadcom.c | 197 +++++----- src/mainboard/amd/inagua/buildOpts.c | 108 ++--- src/mainboard/amd/inagua/mainboard.c | 1 - src/mainboard/amd/inagua/mptable.c | 2 +- src/mainboard/amd/inagua/platform_cfg.h | 2 +- src/mainboard/amd/lamar/BiosCallOuts.c | 14 +- src/mainboard/amd/lamar/mainboard.c | 3 - src/mainboard/amd/mahogany/mainboard.c | 29 -- src/mainboard/amd/mahogany/mptable.c | 1 - src/mainboard/amd/mahogany_fam10/mainboard.c | 29 -- src/mainboard/amd/mahogany_fam10/resourcemap.c | 10 +- src/mainboard/amd/mahogany_fam10/romstage.c | 27 +- src/mainboard/amd/olivehill/BiosCallOuts.c | 38 +- src/mainboard/amd/olivehill/OptionsIds.h | 10 - src/mainboard/amd/olivehill/buildOpts.c | 128 ++---- src/mainboard/amd/olivehill/mptable.c | 39 -- src/mainboard/amd/olivehillplus/BiosCallOuts.c | 42 +- src/mainboard/amd/olivehillplus/mptable.c | 1 - src/mainboard/amd/olivehillplus/romstage.c | 1 - src/mainboard/amd/parmer/BiosCallOuts.c | 10 +- src/mainboard/amd/parmer/OptionsIds.h | 10 - src/mainboard/amd/parmer/buildOpts.c | 140 ++----- src/mainboard/amd/parmer/mptable.c | 1 - src/mainboard/amd/persimmon/BiosCallOuts.c | 9 +- src/mainboard/amd/persimmon/OemCustomize.c | 25 +- src/mainboard/amd/persimmon/OptionsIds.h | 8 - .../amd/persimmon/PlatformGnbPcieComplex.h | 72 ++-- src/mainboard/amd/persimmon/buildOpts.c | 108 ++--- src/mainboard/amd/persimmon/mptable.c | 1 - src/mainboard/amd/persimmon/platform_cfg.h | 2 +- src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 16 +- src/mainboard/amd/serengeti_cheetah/fadt.c | 14 +- src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 44 +-- src/mainboard/amd/serengeti_cheetah/irq_tables.c | 9 +- src/mainboard/amd/serengeti_cheetah/mptable.c | 38 +- src/mainboard/amd/serengeti_cheetah/resourcemap.c | 4 +- src/mainboard/amd/serengeti_cheetah/romstage.c | 64 +-- .../amd/serengeti_cheetah_fam10/acpi_tables.c | 17 +- src/mainboard/amd/serengeti_cheetah_fam10/fadt.c | 27 +- .../amd/serengeti_cheetah_fam10/get_bus_conf.c | 28 +- .../amd/serengeti_cheetah_fam10/irq_tables.c | 9 +- .../amd/serengeti_cheetah_fam10/mptable.c | 34 +- .../amd/serengeti_cheetah_fam10/resourcemap.c | 12 +- .../amd/serengeti_cheetah_fam10/romstage.c | 39 +- src/mainboard/amd/south_station/BiosCallOuts.c | 14 +- src/mainboard/amd/south_station/OemCustomize.c | 17 +- src/mainboard/amd/south_station/OptionsIds.h | 8 - .../amd/south_station/PlatformGnbPcieComplex.h | 72 ++-- src/mainboard/amd/south_station/buildOpts.c | 107 ++--- src/mainboard/amd/south_station/mainboard.c | 10 +- src/mainboard/amd/south_station/mptable.c | 3 +- src/mainboard/amd/south_station/platform_cfg.h | 3 +- src/mainboard/amd/thatcher/BiosCallOuts.c | 10 +- src/mainboard/amd/thatcher/OemCustomize.c | 13 +- src/mainboard/amd/thatcher/OptionsIds.h | 10 - src/mainboard/amd/thatcher/buildOpts.c | 141 ++----- src/mainboard/amd/thatcher/mptable.c | 3 +- src/mainboard/amd/tilapia_fam10/mainboard.c | 43 +- src/mainboard/amd/tilapia_fam10/resourcemap.c | 12 +- src/mainboard/amd/tilapia_fam10/romstage.c | 27 +- src/mainboard/amd/torpedo/BiosCallOuts.c | 36 +- src/mainboard/amd/torpedo/Oem.h | 23 +- src/mainboard/amd/torpedo/OemCustomize.c | 30 +- src/mainboard/amd/torpedo/OptionsIds.h | 9 - src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h | 72 ++-- src/mainboard/amd/torpedo/buildOpts.c | 41 +- src/mainboard/amd/torpedo/fadt.c | 1 - src/mainboard/amd/torpedo/gpio.c | 437 +++++++++------------ src/mainboard/amd/torpedo/gpio.h | 418 ++++++++++---------- src/mainboard/amd/torpedo/mainboard.c | 1 - src/mainboard/amd/torpedo/mptable.c | 3 - src/mainboard/amd/torpedo/platform_cfg.h | 47 +-- src/mainboard/amd/torpedo/romstage.c | 4 +- src/mainboard/amd/union_station/BiosCallOuts.c | 14 +- src/mainboard/amd/union_station/OemCustomize.c | 25 +- src/mainboard/amd/union_station/OptionsIds.h | 8 - .../amd/union_station/PlatformGnbPcieComplex.h | 72 ++-- src/mainboard/amd/union_station/buildOpts.c | 108 ++--- src/mainboard/amd/union_station/mptable.c | 3 +- src/mainboard/amd/union_station/platform_cfg.h | 1 - 107 files changed, 1815 insertions(+), 2872 deletions(-) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index d4d4410..1804296 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -72,7 +72,6 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio; diff --git a/src/mainboard/amd/bettong/OemCustomize.c b/src/mainboard/amd/bettong/OemCustomize.c index 3300244..a32ea9a 100644 --- a/src/mainboard/amd/bettong/OemCustomize.c +++ b/src/mainboard/amd/bettong/OemCustomize.c @@ -71,7 +71,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }, /* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */ { - DESCRIPTOR_TERMINATE_LIST, // Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, @@ -91,7 +91,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { }, /* DP1 */ { - 0, //DESCRIPTOR_TERMINATE_LIST, + 0, /*DESCRIPTOR_TERMINATE_LIST, */ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 20, 23), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) }, diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c index 744fd98..9e73e77 100644 --- a/src/mainboard/amd/bettong/mptable.c +++ b/src/mainboard/amd/bettong/mptable.c @@ -64,7 +64,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 3c6c2c6..c4dd21e 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -63,22 +63,11 @@ void enable_int_gfx(void) void set_pcie_dereset(void) { /* GPIO 50h reset PCIe slot */ -/* - u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50); - u8 byte = ~(1 << 5); - byte |= ~(1 << 6); - *addr = byte; -*/ } void set_pcie_reset(void) { /* GPIO 50h reset PCIe slot */ -/* - u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50); - u8 byte = ~((1 << 5) | (1 << 6)); - *addr = byte; -*/ } u8 is_dev3_present(void) @@ -86,34 +75,6 @@ u8 is_dev3_present(void) return 0; } -#if 0 /* not tested yet. */ -/******************************************************** -* bimini uses SB800 GPIO9 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 5); /* Set Gpio9 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif /* get_ide_dma66() */ /************************************************* * enable the dedicated function in bimini board. @@ -125,7 +86,6 @@ static void mainboard_enable(device_t dev) set_pcie_dereset(); enable_int_gfx(); - /* get_ide_dma66(); */ } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/bimini_fam10/resourcemap.c b/src/mainboard/amd/bimini_fam10/resourcemap.c index e23f1c1..dbd6341 100644 --- a/src/mainboard/amd/bimini_fam10/resourcemap.c +++ b/src/mainboard/amd/bimini_fam10/resourcemap.c @@ -43,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -81,7 +81,8 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -129,7 +130,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,7 +164,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -191,7 +190,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -221,7 +219,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -262,7 +259,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 9ea7e44..8920560 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/*used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -100,12 +98,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -164,10 +161,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -194,8 +191,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -206,24 +201,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb800_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index f46116a..291c2d8 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -158,8 +158,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00; //6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; /*BIT0 | BIT2 | BIT5; */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00; /*6 | BIT3; */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -195,7 +195,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /*BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; @@ -230,7 +230,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /*BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; @@ -241,7 +241,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /*BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; @@ -251,7 +251,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; /*BIT0 | BIT4 |BIT8; */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, @@ -279,7 +279,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); diff --git a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c index e8146a0..bffe888 100644 --- a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c +++ b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c @@ -118,66 +118,66 @@ OemCustomizeInitEarly ( * use its default conservative settings. */ static const PSO_ENTRY ROMDATA PlatformMemoryConfiguration[] = { - // - // The following macros are supported (use comma to separate macros): - // - // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) - // - // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. - // - // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. - // - // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. - // - // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. - // - // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. - // - // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. - // - // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. - // - // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) - // - // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. - // - // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Speicifes the HW RXEN training seed for a channel of a socket - // + /* + * The following macros are supported (use comma to separate macros): + * + * MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + * The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + * AGESA will base on this value to disable unused MemClk to save power. + * Example: + * BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + * Bit AM3/S1g3 pin name + * 0 M[B,A]_CLK_H/L[0] + * 1 M[B,A]_CLK_H/L[1] + * 2 M[B,A]_CLK_H/L[2] + * 3 M[B,A]_CLK_H/L[3] + * 4 M[B,A]_CLK_H/L[4] + * 5 M[B,A]_CLK_H/L[5] + * 6 M[B,A]_CLK_H/L[6] + * 7 M[B,A]_CLK_H/L[7] + * And platform has the following routing: + * CS0 M[B,A]_CLK_H/L[4] + * CS1 M[B,A]_CLK_H/L[2] + * CS2 M[B,A]_CLK_H/L[3] + * CS3 M[B,A]_CLK_H/L[5] + * Then platform can specify the following macro: + * MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + * + * CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + * The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + * AGESA will base on this value to tristate unused CKE to save power. + * + * ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + * The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + * AGESA will base on this value to tristate unused ODT pins to save power. + * + * CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + * The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + * AGESA will base on this value to tristate unused Chip select to save power. + * + * NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + * Specifies the number of DIMM slots per channel. + * + * NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + * Specifies the number of Chip selects per channel. + * + * NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + * Specifies the number of channels per socket. + * + * OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + * Specifies DDR bus speed of channel ChannelID on socket SocketID. + * + * DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + * Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + * + * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + * Byte6Seed, Byte7Seed, ByteEccSeed) + * Specifies the write leveling seed for a channel of a socket. + * + * HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + * Byte6Seed, Byte7Seed, ByteEccSeed) + * Speicifes the HW RXEN training seed for a channel of a socket + */ #define SEED_WL 0x0E WRITE_LEVELING_SEED( diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index f69e188..5c7796f 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -81,7 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); AGESAWRAPPER(amdinitpost); - //PspMboxBiosCmdDramInfo(); post_code(0x41); AGESAWRAPPER(amdinitenv); /* diff --git a/src/mainboard/amd/dinar/OemCustomize.c b/src/mainboard/amd/dinar/OemCustomize.c index 84866de..668dd25 100644 --- a/src/mainboard/amd/dinar/OemCustomize.c +++ b/src/mainboard/amd/dinar/OemCustomize.c @@ -28,11 +28,12 @@ * use its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - // Dinar has the following routing: - // CS0 M[B,A]_CLK_H/L[0] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[1] - // CS3 M[B,A]_CLK_H/L[3] + /* Dinar has the following routing: + * CS0 M[B,A]_CLK_H/L[0] + * CS1 M[B,A]_CLK_H/L[2] + * CS2 M[B,A]_CLK_H/L[1] + * CS3 M[B,A]_CLK_H/L[3] + */ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), PSO_END diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h index d1d184d..c9e66d2 100644 --- a/src/mainboard/amd/dinar/OptionsIds.h +++ b/src/mainboard/amd/dinar/OptionsIds.h @@ -42,15 +42,6 @@ * **/ -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index 1d1717b..425647e 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -72,10 +72,10 @@ unsigned long acpi_fill_madt(unsigned long current) } current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, - 0, //BUS - 0, //SOURCE - 2, //gsirq - 0 //flags + 0, /* BUS */ + 0, /* SOURCE */ + 2, /* gsirq */ + 0 /* flags */ ); /* 0: mean bus 0--->ISA */ diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index e237ff0..ee12dfc 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -26,33 +26,32 @@ #include "AGESA.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE -//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE /* AGESA will check the OEM configuration during preprocessing stage, * coreboot enable -Wundef option, so we should make sure we have all contanstand defined */ /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ /* Select the CPU family. */ @@ -79,23 +78,9 @@ * Comment out the items wanted to be included in the build. * Uncomment those items you with to REMOVE from the build. */ -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_DDR3_SUPPORT TRUE -//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE -//#define BLDOPT_REMOVE_SRAT TRUE -//#define BLDOPT_REMOVE_SLIT TRUE #define BLDOPT_REMOVE_WHEA TRUE -//#define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 120000 @@ -136,15 +121,11 @@ #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased #define BLDCFG_PLATFORM_C1E_OPDATA 0x2000 -//#define BLDCFG_USE_ATM_MODE TRUE #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0xCB0 -#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance //BatteryLife -//#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeMsgBasedC1e -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x2000 +#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance /* BatteryLife */ -//#define IDSOPT_IDS_ENABLED TRUE #define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE #define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT TRUE #define BLDCFG_PSTATE_HPC_MODE FALSE @@ -168,15 +149,17 @@ * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ -// This is the delivery package title, "MarG34PI" -// This string MUST be exactly 8 characters long +/* This is the delivery package title, "MarG34PI" + * This string MUST be exactly 8 characters long + */ #define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'} -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long +/* This is the release version number of the AGESA component + * This string MUST be exactly 12 characters long + */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '} -// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket. +/* The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket. */ #define INSTALL_G34_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_10_SUPPORT TRUE #define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE @@ -195,9 +178,10 @@ #endif #endif -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0xFF) #define DFLT_SCRUB_L2_RATE (0x10) #define DFLT_SCRUB_L3_RATE (0x10) @@ -216,8 +200,8 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, - { //BUID Swap List - { //BUID Swaps + { /* BUID Swap List */ + { /* BUID Swaps */ /* Each Non-coherent chain may have a list of device swaps, * Each item specify a device will be swap from its current id to a new one */ @@ -233,7 +217,7 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, }, - { //The ordered final BUIDs + { /* The ordered final BUIDs */ /* Specify the final BUID to be zero, All others are non applicable */ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, @@ -251,14 +235,6 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = #define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList -// And another platform specific one ... -//CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[2] = -//{ -// HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, -// HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, -// HT_LIST_TERMINAL -//}; - CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = { { @@ -282,14 +258,14 @@ CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = #define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList -// A performance-per-watt optimization. +/* A performance-per-watt optimization. */ CONST SKIP_REGANG ROMDATA PerfPerWatt[] = { { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF }, { HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF }, { HT_LIST_TERMINAL } }; -// uncomment the line below to make Perf-per-watt enabled by default. +/* uncomment the line below to make Perf-per-watt enabled by default. */ #define BLDCFG_LINK_SKIP_REGANG_LIST &PerfPerWatt @@ -313,7 +289,7 @@ CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] = CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = { - // Source Socket, Link (4-7 are sublink 1), Target Socket + /* Source Socket, Link (4-7 are sublink 1), Target Socket */ {0, 0, 1}, {0, 1, 1}, {0, 3, 1}, @@ -329,9 +305,9 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = */ CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] = { - // Socket, Link, SecBus, SubBus - { 0, 2, 0x00, 0xBF }, // RD890 of Dinar - { 1, 0, 0xC0, 0xFF }, // HTX + /* Socket, Link, SecBus, SubBus */ + { 0, 2, 0x00, 0xBF }, /* RD890 of Dinar */ + { 1, 0, 0xC0, 0xFF }, /* HTX */ { (HT_LIST_TERMINAL) } }; @@ -346,15 +322,6 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = }; #define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList -/* - CONST SKIP_REGANG ROMDATA DinarSkipRegangMap[] = - { -// {socketA, linkA, socketB, linkB} -{0, 0, 1, 1}, -}; - -#define BLDCFG_LINK_SKIP_REGANG_LIST &DinarSkipRegangMap -*/ /* * Device Capabilities Override for disabling ID Clumping diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c index affda6f..56dfb56 100644 --- a/src/mainboard/amd/dinar/gpio.c +++ b/src/mainboard/amd/dinar/gpio.c @@ -62,11 +62,11 @@ gpioEarlyInit( u32 SmiMmioAddr = 0; u32 andMask32 = 0; - // Enable HUDSON MMIO Base (AcpiMmioAddr) + /* Enable HUDSON MMIO Base (AcpiMmioAddr) */ ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); Data8 |= BIT0; WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); - // Get HUDSON MMIO Base (AcpiMmioAddr) + /* Get HUDSON MMIO Base (AcpiMmioAddr) */ ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); Data16 = Data8 << 8; ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8); @@ -77,109 +77,109 @@ gpioEarlyInit( MiscMmioAddr = AcpiMmioAddr + MISC_BASE; Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80); if ((Data8 & BIT4) == 0) { - BoardType = 0; // external clock board + BoardType = 0; /* external clock board */ } Data8 = Mmio8_G (GpioMmioAddr, GPIO_30); StripInfo = (Data8 & BIT7) >> 7; Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); StripInfo |= (Data8 & BIT7) >> 6; - if (StripInfo < boardRevC) { // for old board. Rev B - Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 - Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 + if (StripInfo < boardRevC) { /* for old board. Rev B */ + Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); /* function 3 */ + Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); /* function 0 */ } for (Index = 0; Index < MAX_GPIO_NO; Index++) { if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { - // Configure multi-function + /* Configure multi-function */ Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); } - // Configure GPIO + /* Configure GPIO */ if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); } if (Index == GPIO_65) { if ( BoardType == 0 ) { - Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 + Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); /* function 3 */ } } } - // Configure GEVENT + /* Configure GEVENT */ if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) { SmiMmioAddr = AcpiMmioAddr + SMI_BASE; andMask32 = ~(1 << (Index - GEVENT_00)); - //EventEnable: 0-Disable, 1-Enable + /*EventEnable: 0-Disable, 1-Enable */ Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); - //SciTrig: 0-Falling Edge, 1-Rising Edge + /*SciTrig: 0-Falling Edge, 1-Rising Edge */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); - //SciLevl: 0-Edge trigger, 1-Level Trigger + /*SciLevl: 0-Edge trigger, 1-Level Trigger */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); - //SmiSciEn: 0-Not send SMI, 1-Send SMI + /*SmiSciEn: 0-Not send SMI, 1-Send SMI */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); - //SciS0En: 0-Disable, 1-Enable + /*SciS0En: 0-Disable, 1-Enable */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); - //SciMap: 00000b ~ 11111b + /*SciMap: 00000b ~ 11111b */ RegIndex8=(u8)((Index - GEVENT_00) >> 2); Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8); Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); - //SmiTrig: 0-Active Low, 1-Active High + /*SmiTrig: 0-Active Low, 1-Active High */ Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); - //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 + /*SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 */ RegIndex8=(u8)((Index - GEVENT_00) >> 4); Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2); Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); } } - // - // config MXM - // GPIO9: Input for MXM_PRESENT2# - // GPIO10: Input for MXM_PRESENT1# - // GPIO28: Input for MXM_PWRGD - // GPIO35: Output for MXM Reset - // GPIO45: Output for MXM Power Enable, active HIGH - // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable - // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO - // - // set INTE#/GPIO32 as GPO for PCIE_SW - RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO + /* + * config MXM + * GPIO9: Input for MXM_PRESENT2# + * GPIO10: Input for MXM_PRESENT1# + * GPIO28: Input for MXM_PWRGD + * GPIO35: Output for MXM Reset + * GPIO45: Output for MXM Power Enable, active HIGH + * GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable + * GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO + */ + /* set INTE#/GPIO32 as GPO for PCIE_SW */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); /* GPO */ RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6); - // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN - RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO + /* set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); /* GPO */ - // set AD9/GPIO9 as GPI for MXM_PRESENT2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD9/GPIO9 as GPI for MXM_PRESENT2# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set AD10/GPIO10 as GPI for MXM_PRESENT1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD10/GPIO10 as GPI for MXM_PRESENT1# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set GNT1#/GPIO44 as GPO for MXM Reset - RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO + /* set GNT1#/GPIO44 as GPO for MXM Reset */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); /* GPO */ - // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO + /* set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); /* GPO */ - // set AD28/GPIO28 as GPI for MXM_PWRGD - RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD28/GPIO28 as GPI for MXM_PWRGD */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) + /* set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); @@ -187,20 +187,13 @@ gpioEarlyInit( RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3); - // - // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). - // - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20)); - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20))); + /* [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). */ - // check if there any GFX card + /* check if there any GFX card */ Flags = 0; - // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL); - // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09); ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8); if (!(Data8 & BIT7)) { - //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10); ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8); if (!(Data8 & BIT7)) { @@ -209,241 +202,187 @@ gpioEarlyInit( } if ( Flags ) { - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 + /* [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 */ RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH */ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) SbStall (10000); - // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module + /* Write the GPIO55(MXM_PWR_EN) to enable the integrated power module */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) - // WAIT POWER READY: GPIO28 (MXM_PWRGD) - //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); while (!(Data8 & BIT7)) { ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); } - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset - // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); } else { - // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module + /* Write the GPIO55(MXM_PWR_EN) to disable the integrated power module */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) SbStall (10000); - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down */ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); } - // - // APU GPP0: On board LAN - // GPIO25: PCIE_RST#_LAN, LOW active - // GPIO63: LAN_CLKREQ# - // GPIO197: LOM_POWER, HIGH Active - // Clock: GPP_CLK3 - // - // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER - RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - - // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 - - // - // APU GPP1: WUSB - // GPIO1: MPCIE_RST2#, LOW active - // GPIO13: WU_DISABLE#, LOW active - // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) - // - // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD01/GPIO01 as GPO for MPCIE_RST2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB - // RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO - // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH - // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // - // APU GPP2: WWAN - // GPIO0: MPCIE_RST1#, LOW active - // GPIO14: WP_DISABLE#, LOW active - // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) - // - // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD00/GPIO00 as GPO for MPCIE_RST1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO - // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN - // RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO - // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); - // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3); - - // - // APU GPP3: 1394 - // GPIO59: Power control, HIGH active - // GPIO27: PCIE_RST#_1394, LOW active - // GPIO41: CLKREQ# - // Clock: GPP_CLK8 - // - // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 - RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# - - // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C - RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - // To fix glitch issue - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - // - // Enable/Disable OnBoard LAN - // + /* + * APU GPP0: On board LAN + * GPIO25: PCIE_RST#_LAN, LOW active + * GPIO63: LAN_CLKREQ# + * GPIO197: LOM_POWER, HIGH Active + * Clock: GPP_CLK3 + * + * Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER + */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + + /* set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); /* CLK_REQ3# */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); /* Enable GPP_CLK3 */ + + /* + * APU GPP1: WUSB + * GPIO1: MPCIE_RST2#, LOW active + * GPIO13: WU_DISABLE#, LOW active + * GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) + * + * Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable + */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD01/GPIO01 as GPO for MPCIE_RST2# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* + * APU GPP2: WWAN + * GPIO0: MPCIE_RST1#, LOW active + * GPIO14: WP_DISABLE#, LOW active + * GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) + * + * Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable + */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Set AD00/GPIO00 as GPO for MPCIE_RST1# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* + * APU GPP3: 1394 + * GPIO59: Power control, HIGH active + * GPIO27: PCIE_RST#_1394, LOW active + * GPIO41: CLKREQ# + * Clock: GPP_CLK8 + */ + /* Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); /* CLK_REQ2# */ + + /* set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); /* GPO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + /* To fix glitch issue */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); /* set GPIO_GATE_C to LOW */ + + /* Enable/Disable OnBoard LAN */ + if (!CONFIG_ONBOARD_LAN) - { // 1 - DISABLED - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off + { /* 1 - DISABLED */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); /* LOM_POWER off */ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3 + RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); /* PULL UP - DISABLED */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); /* Disable GPP_CLK3 */ } - // else - // { // 0 - AUTO - // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable) - // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); - // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); - // } + /* Enable/Disable 1394 */ - // - // Enable/Disable 1394 - // if (!CONFIG_ONBOARD_1394) - { // 1 - DISABLED - // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off + { /* 1 - DISABLED */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); /* 1394 power off */ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 - // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); /* pullup DISABLE */ + RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); /* DISABLE GPP_CLK8 */ } - // else - // { // 0 - AUTO - // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH) - // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); - // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); - // - // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); - // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); - // } - - // - // external USB 3.0 control: - // amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE - // GPIO26: PCIE_RST#_USB3.0 - // GPIO46: PCIE_USB30_CLKREQ# - // GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON - // Clock: GPP_CLK7 - // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE - // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { - // disable Onboard NEC USB3.0 controller + + /* + * external USB 3.0 control: + * amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO26: PCIE_RST#_USB3.0 + * GPIO46: PCIE_USB30_CLKREQ# + * GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON + * Clock: GPP_CLK7 + * GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + */ + if (!CONFIG_ONBOARD_USB30) { RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 - RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); /* PULL_UP DISABLE */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); /* DISABLE GPP_CLK7 */ + RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */ } - // } - // - // BlueTooth control: BT_ON - // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE - // GPIO07: BT_ON, 0 - OFF, 1 - ON - // + /* BlueTooth control: BT_ON + * amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO07: BT_ON, 0 - OFF, 1 - ON + */ if (!CONFIG_ONBOARD_BLUETOOTH) { - //- if (SystemConfiguration.amdBlueTooth == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); - //- } } - // - // WebCam control: - // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE - // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF - // + /* + * WebCam control: + * amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF + */ if (!CONFIG_ONBOARD_WEBCAM) { - //- if (SystemConfiguration.amdWebCam == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); - //- } } - // - // Travis enable: - // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE - // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE - // + /* + * Travis enable: + * amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE + * GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE + */ if (!CONFIG_ONBOARD_TRAVIS) { - //- if (SystemConfiguration.amdTravisCtrl == 0) { RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); - //- } } - // - // Disable Light Sensor if needed - // + /* Disable Light Sensor if needed */ + if (CONFIG_ONBOARD_LIGHTSENSOR) { - //- if (SystemConfiguration.amdLightSensor == 1) { RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); - //- } } } diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h index 3ac8bfa..64368c9 100644 --- a/src/mainboard/amd/dinar/gpio.h +++ b/src/mainboard/amd/dinar/gpio.h @@ -83,87 +83,87 @@ #define FUNCTION1 1 #define FUNCTION2 2 #define FUNCTION3 3 -#define NonGpio 0x80 // BIT7 +#define NonGpio 0x80 /* BIT7 */ -// S0-domain General Purpose I/O: GPIO 00~67 -#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT -#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT -#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT -#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED -#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT -#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT -#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED -#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF -#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level -#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 -#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 -#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 -#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default -#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. -#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) -#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) -#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE -// 1:BATTERY IS FINE(DEFAULT) -// 0:BATTERY IS LOW -#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF -#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default -#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high -#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high -#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high -#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT -#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT -#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 -#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 -// 00 - REVA -// 01 - REVB -// 10 - REVC -// 11 - REVD -#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO -#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. -// 0:USB3.0 I/F in Express CARD -// 1:PCIE I/F in Express CARD detection -#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF -#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# -#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC -#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. -#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# -#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# -#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK -#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE -#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF -#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# -#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA -#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ -#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 -#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V -#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 -#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT -#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE -#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE -#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) -// 1:ENABLE; 0:DISABLE -// DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 -#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN -#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER -#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER -#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE -#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# -#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 -#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 -#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# -#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 -#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM -#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default -#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# +/* S0-domain General Purpose I/O: GPIO 00~67 */ +#define GPIO_00_SELECT FUNCTION1+NonGpio /* MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_01_SELECT FUNCTION1+NonGpio /* MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_02_SELECT FUNCTION1 /* MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_03_SELECT FUNCTION1+NonGpio /* NOT USED */ +#define GPIO_04_SELECT FUNCTION1+NonGpio /* x1 gpp reset, for J3701, low active, HIGH DEFAULT */ +#define GPIO_05_SELECT FUNCTION1+NonGpio /* express card reset, for J2500, low active, HIGH DEFAULT */ +#define GPIO_06_SELECT FUNCTION0+NonGpio /*NOT USED */ +#define GPIO_07_SELECT FUNCTION1 /* BT_ON, 1: BT ON(DEFAULT); 0: BT OFF */ +#define GPIO_08_SELECT FUNCTION1 /* PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level */ +#define GPIO_09_SELECT FUNCTION1+NonGpio /* MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED */ +#define GPIO_10_SELECT FUNCTION1+NonGpio /* MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED */ +#define GPIO_11_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_12_SELECT FUNCTION1 /* WL_DISABLE#, DISABLE THE WALN IN J3702 */ +#define GPIO_13_SELECT FUNCTION1 /* WU_DISABLE#, DISABLE THE WUSB IN J3711 */ +#define GPIO_14_SELECT FUNCTION1 /* WP_DISABLE, DISABLE THE WWAN IN J3703 */ +#define GPIO_15_SELECT FUNCTION1+NonGpio /* NOT USED, /*FUNCTION1, Reset_CEC# Low Active, High default */ */ +#define GPIO_16_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_17_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_18_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_19_SELECT FUNCTION1 /* For LASSO_DET# detection when Gevent14# is asserted. */ +#define GPIO_20_SELECT FUNCTION1 /* PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) */ +#define GPIO_21_SELECT FUNCTION1 /* DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) */ +#define GPIO_22_SELECT FUNCTION1 /* SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE */ +/* 1:BATTERY IS FINE(DEFAULT) */ +/* 0:BATTERY IS LOW */ +#define GPIO_23_SELECT FUNCTION1 /* CODEC_ON.1: CODEC ON (default)0: CODEC OFF */ +#define GPIO_24_SELECT FUNCTION1 /* Travis reset,Low active High default */ +#define GPIO_25_SELECT FUNCTION1+NonGpio /* PCIE_RST# for LAN (AND gate with PCIE_RST#); default high */ +#define GPIO_26_SELECT FUNCTION1+NonGpio /* PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high */ +#define GPIO_27_SELECT FUNCTION1+NonGpio /* PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high */ +#define GPIO_28_SELECT FUNCTION1 /* MXM PWRGD INDICATOR, INPUT */ +#define GPIO_29_SELECT FUNCTION1 /* MEM HOT, LOW ACTIVE, OUTPUT */ +#define GPIO_30_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 0 */ +#define GPIO_31_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 1 */ +/* 00 - REVA */ +/* 01 - REVB */ +/* 10 - REVC */ +/* 11 - REVD */ +#define GPIO_32_SELECT FUNCTION1+NonGpio /* PCIE_SW - HIGH:MXM; LOW:LASSO */ +#define GPIO_33_SELECT FUNCTION1 /* USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. */ +/* 0:USB3.0 I/F in Express CARD */ +/* 1:PCIE I/F in Express CARD detection */ +#define GPIO_34_SELECT FUNCTION1 /* WEBCAM_ON#. 0: ON (default) 1: OFF */ +#define GPIO_35_SELECT FUNCTION1 /* ODD_DA_INTH# */ +#define GPIO_36_SELECT FUNCTION0+NonGpio /* PCICLK FOR KBC */ +#define GPIO_37_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_38_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_39_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_40_SELECT FUNCTION1 /* For DOCK# detection when Gevent14# is asserted. */ +#define GPIO_41_SELECT FUNCTION1+NonGpio /* 1394 CLK REQ# */ +#define GPIO_42_SELECT FUNCTION1+NonGpio /* X4 GPP CLK REQ# */ +#define GPIO_43_SELECT FUNCTION0+NonGpio /* SMBUS0, CLOCK */ +#define GPIO_44_SELECT FUNCTION1+NonGpio /* PEGPIO0, RESET THE MXM MODULE */ +#define GPIO_45_SELECT FUNCTION2+NonGpio /* PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF */ +#define GPIO_46_SELECT FUNCTION1+NonGpio /* USB3.0_CLKREQ# */ +#define GPIO_47_SELECT FUNCTION0+NonGpio /* SMBUS0, DATA */ +#define GPIO_48_SELECT FUNCTION0+NonGpio /* SERIRQ */ +#define GPIO_49_SELECT FUNCTION0+NonGpio /* LDRQ#1 */ +#define GPIO_50_SELECT FUNCTION2 /* SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V */ +#define GPIO_51_SELECT FUNCTION0+NonGpio /* back-up for SMARTVOLTAGE1 */ +#define GPIO_52_SELECT FUNCTION0+NonGpio /* CPU FAN OUT */ +#define GPIO_53_SELECT FUNCTION1 /* ODD POWER ENABLE, HIGH ACTIVE */ +#define GPIO_54_SELECT FUNCTION0+NonGpio /* SB_PROCHOT, OUTPUT, LOW ACTIVE */ +#define GPIO_55_SELECT FUNCTION2+NonGpio /* MXM POWER ENABLE(POWER ON MODULE) */ +/* 1:ENABLE; 0:DISABLE */ +/* DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 */ +#define GPIO_56_SELECT FUNCTION0+NonGpio /*HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN */ +#define GPIO_57_SELECT FUNCTION1 /* HDD0_POWER */ +#define GPIO_58_SELECT FUNCTION1 /* HDD2_POWER */ +#define GPIO_59_SELECT FUNCTION2+NonGpio /* 1394 POWER, OUTPUT, HIGH ACTIVE */ +#define GPIO_60_SELECT FUNCTION0+NonGpio /* EXPCARD_CLKREQ# */ +#define GPIO_61_SELECT FUNCTION0+NonGpio /* PE0_CLKREQ#, FROM J3700 */ +#define GPIO_62_SELECT FUNCTION0+NonGpio /* PE2_CLKREQ#, FROM J3711 */ +#define GPIO_63_SELECT FUNCTION0+NonGpio /* LAN_CLKREQ# */ +#define GPIO_64_SELECT FUNCTION0+NonGpio /* PE1_CLKREQ#, FROM J3703 */ +#define GPIO_65_SELECT FUNCTION0+NonGpio /* MXM CLK REQ#, FROM MXM */ +#define GPIO_66_SELECT FUNCTION1 /* USED AS TRAVIS_EN#; 0:ENABLE as default */ +#define GPIO_67_SELECT FUNCTION0+NonGpio /* USED AS SATA_ACT# */ #define GPIO_68_SELECT FUNCTION0+NonGpio #define GPIO_69_SELECT FUNCTION0+NonGpio #define GPIO_70_SELECT FUNCTION0+NonGpio @@ -192,40 +192,40 @@ #define GPIO_93_SELECT FUNCTION0+NonGpio #define GPIO_94_SELECT FUNCTION0+NonGpio #define GPIO_95_SELECT FUNCTION0+NonGpio -// GEVENT 00~23 are mapped to GPIO 96~119 -#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# -#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# -#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP -#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# -#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# -#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active -#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, -// there is a confliction to IR function when this pin is as a GEVENT. -#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, -// special pin difination for SB700 VGA OUTPUT, high active, -// VGA power for Hudson-M2 will be down when it was asserted. -#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active -#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) -#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 -#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 -#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active -// [option for SPI_TPM_CS# in Hudson-M2 A12)] -#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & -// USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time -#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, -// plus judge GPIO40 and GPIO19 level,low is assert. -// LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) -// DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) -#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active -#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, -// low active, when it's low, BIOS will enbale ODD_PWR -#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# -#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK -#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# -#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT -#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 -#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# -#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI +/* GEVENT 00~23 are mapped to GPIO 96~119 */ +#define GPIO_96_SELECT FUNCTION0 /* GA20IN/GEVENT0# */ +#define GPIO_97_SELECT FUNCTION0 /* KBRST#/GEVENT1# */ +#define GPIO_98_SELECT FUNCTION0 /* THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP */ +#define GPIO_99_SELECT FUNCTION1 /* LPC_PME#/GEVENT3# -> EC_SCI# */ +#define GPIO_100_SELECT FUNCTION2 /* PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# */ +#define GPIO_101_SELECT FUNCTION1 /* LPC_PD#/GEVENT5# -> hotplug of express card, low active */ +#define GPIO_102_SELECT FUNCTION0+NonGpio /* USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, */ +/* there is a confliction to IR function when this pin is as a GEVENT. */ +#define GPIO_103_SELECT FUNCTION0+NonGpio /* DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, */ +/* special pin difination for SB700 VGA OUTPUT, high active, */ +/* VGA power for Hudson-M2 will be down when it was asserted. */ +#define GPIO_104_SELECT FUNCTION0 /* WAKE#/GEVENT8# -> WAKEUP, low active */ +#define GPIO_105_SELECT FUNCTION2 /* SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) */ +#define GPIO_106_SELECT FUNCTION0 /* GBE_LED2/GEVENT10# -> GBE_LED2 */ +#define GPIO_107_SELECT FUNCTION0+NonGpio /* GBE_STAT0/GEVENT11# -> GBE_STAT0 */ +#define GPIO_108_SELECT FUNCTION2 /* USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active */ +/* [option for SPI_TPM_CS# in Hudson-M2 A12)] */ +#define GPIO_109_SELECT FUNCTION0 /* USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & */ +/* USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time */ +#define GPIO_110_SELECT FUNCTION2 /* USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, */ +/* plus judge GPIO40 and GPIO19 level,low is assert. */ +/* LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) */ +/* DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) */ +#define GPIO_111_SELECT FUNCTION1+NonGpio /* USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active */ +#define GPIO_112_SELECT FUNCTION2 /* USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, */ +/* low active, when it's low, BIOS will enbale ODD_PWR */ +#define GPIO_113_SELECT FUNCTION2 /* USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# */ +#define GPIO_114_SELECT FUNCTION2 /* BLINK/USB_OC7#/GEVENT18# -> BLINK */ +#define GPIO_115_SELECT FUNCTION0 /* SYS_RESET#/GEVENT19# -> SYS_RST# */ +#define GPIO_116_SELECT FUNCTION0 /* R_RX1/GEVENT20# -> IR INPUT */ +#define GPIO_117_SELECT FUNCTION1+NonGpio /* SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 */ +#define GPIO_118_SELECT FUNCTION1 /* RI#/GEVENT22# -> LID_CLOSED# */ +#define GPIO_119_SELECT FUNCTION0 /* LPC_SMI#/GEVENT23# -> EC_SMI */ #define GPIO_120_SELECT FUNCTION0+NonGpio #define GPIO_121_SELECT FUNCTION0+NonGpio #define GPIO_122_SELECT FUNCTION0+NonGpio @@ -268,78 +268,78 @@ #define GPIO_159_SELECT FUNCTION0+NonGpio #define GPIO_160_SELECT FUNCTION0+NonGpio -// S5-domain General Purpose I/O -#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# -#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 -#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 -#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 -#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 -#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. -#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, -#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE -#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 -#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# -#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 -#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 -#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO -#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR -#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 -#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 -#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# -#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE -#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE -// option for HDMI CEC signal OW ACTIVE -#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active -#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT -#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA -#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK -#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active -// RESERVED FOR LCD BACKLIGHT PWM -#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL -#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM -#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF -#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD +/* S5-domain General Purpose I/O */ +#define GPIO_161_SELECT FUNCTION0+NonGpio /* ROM_RST# */ +#define GPIO_162_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_163_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_164_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_165_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_166_SELECT FUNCTION1+NonGpio /* GBE_STAT2 */ +#define GPIO_167_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN0 */ +#define GPIO_168_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN1 */ +#define GPIO_169_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN2 */ +#define GPIO_170_SELECT FUNCTION1+NonGpio /* gating the power control signal for ODD, see BIOS requirements doc for detail. */ +#define GPIO_171_SELECT FUNCTION0+NonGpio /* TEMPIN0, */ +#define GPIO_172_SELECT FUNCTION1 /* used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE */ +#define GPIO_173_SELECT FUNCTION0+NonGpio /* TEMPIN3 */ +#define GPIO_174_SELECT FUNCTION1+NonGpio /* USED AS TALERT# */ +#define GPIO_175_SELECT FUNCTION1 /* WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_176_SELECT FUNCTION1+NonGpio /* WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_177_SELECT FUNCTION2+NonGpio /* WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_178_SELECT FUNCTION2 /* MEM_1V5 */ +#define GPIO_179_SELECT FUNCTION2 /* MEM_1V35 */ +#define GPIO_180_SELECT FUNCTION0+NonGpio /* Use as VIN VDDIO */ +#define GPIO_181_SELECT FUNCTION0+NonGpio /* Use as VIN VDDR */ +#define GPIO_182_SELECT FUNCTION1+NonGpio /* GBE_LED3 */ +#define GPIO_183_SELECT FUNCTION0+NonGpio /* GBE_LED0 */ +#define GPIO_184_SELECT FUNCTION1+NonGpio /* USED AS LLB# */ +#define GPIO_185_SELECT FUNCTION0+NonGpio /* USED AS USB */ +#define GPIO_186_SELECT FUNCTION0+NonGpio /* USED AS USB */ +#define GPIO_187_SELECT FUNCTION2 /* USED AS AC LED INDICATOR, LOW ACTIVE */ +#define GPIO_188_SELECT FUNCTION2 /* default used AS BATT LED INDICATOR, LOW ACTIVE */ +/* option for HDMI CEC signal OW ACTIVE */ +#define GPIO_189_SELECT FUNCTION1 /* USED AS AC_OK RECIEVER, INPUT, low active */ +#define GPIO_190_SELECT FUNCTION1 /* USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT */ +#define GPIO_191_SELECT FUNCTION0+NonGpio /* TOUCH PAD, DATA */ +#define GPIO_192_SELECT FUNCTION0+NonGpio /* TOUCH PAD, CLK */ +#define GPIO_193_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_194_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_195_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_196_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_197_SELECT FUNCTION2+NonGpio /* Default GPIO for LOM_POWER, high active */ +/* RESERVED FOR LCD BACKLIGHT PWM */ +#define GPIO_198_SELECT FUNCTION0+NonGpio /* IMC SCROLL LED CONTROL */ +#define GPIO_199_SELECT FUNCTION3 /* STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM */ +#define GPIO_200_SELECT FUNCTION2 /* NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF */ +#define GPIO_201_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_202_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_203_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_204_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_205_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_206_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_207_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_208_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_209_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_210_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_211_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_212_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_213_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_214_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_215_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_216_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_217_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_218_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_219_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_220_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_221_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_222_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_223_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_224_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_225_SELECT FUNCTION2+NonGpio /* KSO */ +#define GPIO_226_SELECT FUNCTION2+NonGpio /* KSO */ +#define GPIO_227_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_228_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_229_SELECT FUNCTION0+NonGpio /* DP1_HPD */ #define TYPE_GPI (1 << 5) #define TYPE_GPO (0 << 5) @@ -441,7 +441,7 @@ #define GPIO_94_TYPE TYPE_GPO #define GPIO_95_TYPE TYPE_GPO -// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 +/* GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 */ #define GPIO_96_TYPE TYPE_GPI #define GPIO_97_TYPE TYPE_GPI #define GPIO_98_TYPE TYPE_GPI @@ -753,13 +753,13 @@ #define GPO_169_LEVEL GPO_LOW #define GPO_170_LEVEL GPO_HI #define GPO_171_LEVEL GPO_LOW -#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +#define GPO_172_LEVEL GPO_HI /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */ #define GPO_173_LEVEL GPO_LOW #define GPO_174_LEVEL GPO_LOW #define GPO_175_LEVEL GPO_LOW #define GPO_176_LEVEL GPO_LOW #define GPO_177_LEVEL GPO_LOW -#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU +#define GPO_178_LEVEL GPO_HI /* AMD.SR BU to set VDDIO level to 1.5V for Barb BU */ #define GPO_179_LEVEL GPO_HI #define GPO_180_LEVEL GPO_HI #define GPO_181_LEVEL GPO_LOW @@ -1523,28 +1523,28 @@ #define GEVENT_00_EVENTENABLE EVENT_DISABLE #define GEVENT_01_EVENTENABLE EVENT_DISABLE -#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# -#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# -#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# -#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# +#define GEVENT_02_EVENTENABLE EVENT_ENABLE /* APU THERMTRIP# */ +#define GEVENT_03_EVENTENABLE EVENT_ENABLE /* EC_SCI# */ +#define GEVENT_04_EVENTENABLE EVENT_ENABLE /* APU_MEMHOT# */ +#define GEVENT_05_EVENTENABLE EVENT_ENABLE /* PCIE_EXPCARD_PWREN# */ #define GEVENT_06_EVENTENABLE EVENT_DISABLE #define GEVENT_07_EVENTENABLE EVENT_DISABLE #define GEVENT_08_EVENTENABLE EVENT_DISABLE -#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO +#define GEVENT_09_EVENTENABLE EVENT_ENABLE /* WF_RADIO */ #define GEVENT_10_EVENTENABLE EVENT_DISABLE #define GEVENT_11_EVENTENABLE EVENT_DISABLE -#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# +#define GEVENT_12_EVENTENABLE EVENT_ENABLE /* SMBALERT# */ #define GEVENT_13_EVENTENABLE EVENT_DISABLE -#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# -#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# -#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA -#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN +#define GEVENT_14_EVENTENABLE EVENT_ENABLE /* LASSO_DET#/DOCK# */ +#define GEVENT_15_EVENTENABLE EVENT_ENABLE /* ODD_PLUGIN# */ +#define GEVENT_16_EVENTENABLE EVENT_ENABLE /* ODD_DA */ +#define GEVENT_17_EVENTENABLE EVENT_ENABLE /* TWARN */ #define GEVENT_18_EVENTENABLE EVENT_DISABLE #define GEVENT_19_EVENTENABLE EVENT_DISABLE #define GEVENT_20_EVENTENABLE EVENT_DISABLE #define GEVENT_21_EVENTENABLE EVENT_DISABLE -#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# -#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# +#define GEVENT_22_EVENTENABLE EVENT_ENABLE /* LID_CLOSE# */ +#define GEVENT_23_EVENTENABLE EVENT_DISABLE /* EC_SMI# */ #define SCITRIG_LOW 0 #define SCITRIG_HI 1 @@ -2255,14 +2255,14 @@ typedef enum _GEVENT_COUNT typedef struct _GEVENT_SETTINGS { - u8 EventEnable; // 0: Disable, 1: Enable - u8 SciTrig; // 0: Falling Edge, 1: Rising Edge - u8 SciLevl; // 0: Edge trigger, 1: Level Trigger - u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI - u8 SciS0En; // 0: Disable, 1: Enable - u8 SciMap; // 0000b->1111b - u8 SmiTrig; // 0: Active Low, 1: Active High - u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 + u8 EventEnable; /* 0: Disable, 1: Enable */ + u8 SciTrig; /* 0: Falling Edge, 1: Rising Edge */ + u8 SciLevl; /* 0: Edge trigger, 1: Level Trigger */ + u8 SmiSciEn; /* 0: Not send SMI, 1: Send SMI */ + u8 SciS0En; /* 0: Disable, 1: Enable */ + u8 SciMap; /* 0000b->1111b */ + u8 SmiTrig; /* 0: Active Low, 1: Active High */ + u8 SmiControl; /* 0: Disable, 1: SMI 2: NMI 3: IRQ13 */ } GEVENT_SETTINGS; GEVENT_SETTINGS gevent_table[] = diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 947ec65..ae08ee1 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -22,8 +22,6 @@ #include <device/pci_def.h> #include <NbPlatform.h> -//#define SMBUS_IO_BASE 0x6000 - void set_pcie_reset(void *nbconfig); void set_pcie_dereset(void *nbconfig); @@ -42,7 +40,6 @@ void set_pcie_reset(void *nbconfig) */ void set_pcie_dereset(void *nbconfig) { - //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); u32 i; u32 val; u32 nb_addr; diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index a8b53d0..048ecaf 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -95,7 +95,6 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin)) /* SMBUS */ - //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0 /* HD Audio */ PCI_INT(0x0, 0x14, 0x2, 0x10); @@ -117,7 +116,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */ /* SATA */ - PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG + PCI_INT(0x0, 0x11, 0x0, 0x16); /*6, INTG */ /* PCI slots */ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h index f10e4d7..9afba97 100644 --- a/src/mainboard/amd/dinar/platform_cfg.h +++ b/src/mainboard/amd/dinar/platform_cfg.h @@ -21,30 +21,25 @@ /** * Max number of northbridges in the system */ -#define MAX_NB_COUNT 1 //TODO: only 1 NB tested +#define MAX_NB_COUNT 1 /* TODO: only 1 NB tested */ /** * Enable check for PCIe endpoint to be ready for PCI enumeration. * */ -//#define EPREADY_WORKAROUND_DISABLED /** * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. * */ -#define IOMMU_SUPPORT_DISABLE //TODO: enable it +#define IOMMU_SUPPORT_DISABLE /* TODO: enable it */ /** * Disable server PCIe hotplug support. */ -//#define HOTPLUG_SUPPORT_DISABLED - /** * Disable support for device number remapping for PCIe portsserver PCIe hotplug support. */ -//#define DEVICE_REMAP_DISABLE - -#endif //_PLATFORM_CFG_H_ +#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c index 5459200..733435d 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.c +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -32,7 +32,6 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) { u16 i; PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; - //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; DEFAULT_PLATFORM_CONFIG(platform_config); @@ -93,7 +92,7 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) } } } -#endif // __PRE_RAM__ +#endif /* __PRE_RAM__ */ /** * @brief Entry point of Northbridge CIMx callout/CallBack @@ -166,9 +165,9 @@ static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config) case CB_AmdSetMidPostConfig: nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR; -#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu +#ifndef IOMMU_SUPPORT_DISABLE /*TODO enable iommu */ /* SBIOS must alloc 16K memory for IOMMU MMIO */ - UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress + UINT32 MmcfgBarAddress; /*using default IOmmuBaseAddress */ LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, AccessWidth32, &MmcfgBarAddress, @@ -177,7 +176,7 @@ static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config) if (MmcfgBarAddress != 0) { nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; } - nbConfigPtr->IommuBaseAddress = 0; //disable iommu + nbConfigPtr->IommuBaseAddress = 0; /*disable iommu */ #endif break; @@ -235,10 +234,10 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON sbNode = (val >> 8) & 0x07; PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); - sbLink = (val >> 8) & 0x07; //assum ganged + sbLink = (val >> 8) & 0x07; /*assum ganged */ pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; - //TODO: other NBs + /* TODO: other NBs */ #ifndef __PRE_RAM__ /* If temporrary MMIO enable set up CPU MMIO */ diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h index 8645553..5b5a213 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.h +++ b/src/mainboard/amd/dinar/rd890_cfg.h @@ -142,7 +142,6 @@ DEFAULT_GPP2_CONFIG, \ DEFAULT_GPP3A_CONFIG, \ DEFAULT_HT_DEEMPASIES, \ - /*DEFAULT_HT_PATH,*/ \ DEFAULT_APIC_INTERRUPT_BASE, \ } @@ -150,17 +149,16 @@ * Platform configuration */ typedef struct { - UINT16 PortEnableMap; ///< Bitmap of enabled ports - UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 - UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug - UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors - UINT32 TemporaryMmio; ///< Temporary MMIO - UINT32 Gpp1Config; ///< Default PCIe GFX core configuration - UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration - UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration - UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level - // HT_PATH NbHtPath; ///< HT path to NB - UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. + UINT16 PortEnableMap; /* Bitmap of enabled ports */ + UINT16 PortGen1Map; /* Bitmap of ports to disable Gen2 */ + UINT16 PortHotplugMap; /* Bitmap of ports support hotplug */ + UINT8 PortHotplugDescriptors[8];/* Ports Hotplug descriptors */ + UINT32 TemporaryMmio; /* Temporary MMIO */ + UINT32 Gpp1Config; /* Default PCIe GFX core configuration */ + UINT32 Gpp2Config; /* Default PCIe GPP2 core configuration */ + UINT32 Gpp3aConfig; /* Default PCIe GPP3a core configuration */ + UINT8 NbTransmitterDeemphasis; /* HT transmitter de-emphasis level */ + UINT8 GlobalApicInterruptBase; /* Global APIC interrupt base that is used in MADT table for IO APIC. */ } NB_PLATFORM_CONFIG; /** @@ -168,4 +166,4 @@ typedef struct { */ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); -#endif //_RD890_CFG_H_ +#endif /* _RD890_CFG_H_ */ diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index bc5d312..a1b1e3b 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -64,7 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x33); report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); @@ -101,5 +101,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x44); copy_and_run(); - post_code(0x45); // Should never see this post code. + post_code(0x45); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c index 797bed8..2a5eae3 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.c +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -83,8 +83,8 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->SpreadSpectrum = 0; sb_config->PciClk5 = 0; sb_config->PciClks = 0x1F; - sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood - sb_config->TimerClockSource = 2; // Auto + sb_config->ResetCpuOnSyncFlood = 1; /* Do not reset CPU on sync flood */ + sb_config->TimerClockSource = 2; /* Auto */ sb_config->S3Resume = 0; sb_config->RebootRequired = 0; @@ -92,28 +92,28 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->HpetTimer = HPET_TIMER; /* USB */ - sb_config->UsbIntClock = 0; // Use external clock - sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 - sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 - sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 - sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 - sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 - sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 - sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 - sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable + sb_config->UsbIntClock = 0; /* Use external clock */ + sb_config->Usb1Ohci0 = 1; /* 0:disable 1:enable Bus 0 Dev 18 Func0 */ + sb_config->Usb1Ohci1 = 1; /* 0:disable 1:enable Bus 0 Dev 18 Func1 */ + sb_config->Usb1Ehci = 1; /* 0:disable 1:enable Bus 0 Dev 18 Func2 */ + sb_config->Usb2Ohci0 = 1; /* 0:disable 1:enable Bus 0 Dev 19 Func0 */ + sb_config->Usb2Ohci1 = 1; /* 0:disable 1:enable Bus 0 Dev 19 Func1 */ + sb_config->Usb2Ehci = 1; /* 0:disable 1:enable Bus 0 Dev 19 Func2 */ + sb_config->Usb3Ohci = 1; /* 0:disable 1:enable Bus 0 Dev 20 Func5 */ + sb_config->UsbOhciLegacyEmulation = 1; /* 0:Enable 1:Disable */ sb_config->AcpiS1Supported = 1; /* SATA */ sb_config->SataController = 1; - sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; /* 0 native, 1 raid, 2 ahci */ sb_config->SataSmbus = 0; sb_config->SataAggrLinkPmCap = 1; sb_config->SataPortMultCap = 1; sb_config->SataClkAutoOff = 1; - sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. - //TODO: set to secondary not take effect. - sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled + sb_config->SataIdeCombMdPriSecOpt = 0; /* 0 -IDE as primary, 1 -IDE as secondary. */ + /* TODO: set to secondary not take effect. */ + sb_config->SataIdeCombinedMode = 0; /* 1 IDE controlor exposed and combined mode enabled, 0 disabled */ sb_config->SataEspPort = 0; sb_config->SataClkAutoOffAhciMode = 1; sb_config->SataHpcpButNonESP = 0; @@ -134,7 +134,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->StdHeader.pCallBack = (CIM_HOOK_ENTRY)&sb700_callout_entry; } - //sb_config-> -#endif //!__PRE_RAM__ + /* sb_config-> */ +#endif /* !__PRE_RAM__ */ printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - End.\n", __func__); } diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h index 02c3934..65327bf 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.h +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -187,7 +187,6 @@ * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN -//#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN #define AZALIA_SDIN_PIN_0 0x2 #define AZALIA_SDIN_PIN_1 0x2 @@ -234,4 +233,4 @@ void sb700_cimx_config(AMDSBCFG *sb_cfg); */ u32 sb700_callout_entry(u32 func, u32 data, void* config); -#endif //_SB700_CFG_H_ +#endif /* _SB700_CFG_H_ */ diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 4b64055..4c64b47 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -135,7 +135,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -152,13 +152,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; } @@ -168,13 +168,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; } @@ -184,13 +184,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c index d1f715c..8bcf666 100644 --- a/src/mainboard/amd/inagua/OemCustomize.c +++ b/src/mainboard/amd/inagua/OemCustomize.c @@ -48,25 +48,25 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -75,13 +75,13 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS + /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1) }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA + /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), @@ -96,11 +96,10 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) &DdiList[0] }; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h index 2d8381b..7a9c03f 100644 --- a/src/mainboard/amd/inagua/OptionsIds.h +++ b/src/mainboard/amd/inagua/OptionsIds.h @@ -43,14 +43,6 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h index 60045e1..fd92667 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h @@ -20,44 +20,44 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ +/* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ + +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c index 640f639..92b5931 100644 --- a/src/mainboard/amd/inagua/broadcom.c +++ b/src/mainboard/amd/inagua/broadcom.c @@ -26,28 +26,28 @@ #include <types.h> #include <console/console.h> -#include <device/device.h> //Coreboot device access +#include <device/device.h> /* Coreboot device access */ #include <device/pci.h> #include <delay.h> #include <endian.h> void broadcom_init(void); -#define be16(x) cpu_to_be16(x) //a little easier to type -#define be(x) cpu_to_be32(x) //this is used a lot! +#define be16(x) cpu_to_be16(x) /* a little easier to type */ +#define be(x) cpu_to_be32(x) /* this is used a lot! */ /* C forces us to specify these before defining struct selfboot_patch :-( */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF #define INIT1_LENGTH 9 #define INIT2_LENGTH 10 #define INIT3_LENGTH 3 -#define INIT4_LENGTH 7 //this one may be 0 +#define INIT4_LENGTH 7 /* this one may be 0 */ #define PWRDN_LENGTH 5 #else #define INIT1_LENGTH 13 #define INIT2_LENGTH 6 #define INIT3_LENGTH 3 -#define INIT4_LENGTH 11 //this one may be 0 +#define INIT4_LENGTH 11 /* this one may be 0 */ #define PWRDN_LENGTH 4 #endif @@ -106,61 +106,61 @@ void broadcom_init(void); * not supported. */ -static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! +static struct selfboot_patch { /* Watch out: all values are *BIG-ENDIAN*! */ struct { /* Global header */ - u8 signature; //0xA5 - u8 format; //bits 7-3: patch format; 2-0: revision + u8 signature; /* 0xA5 */ + u8 format; /* bits 7-3: patch format; 2-0: revision */ u8 mac_addr[6]; - u16 subsys_device; //IDs will be loaded into PCI config space + u16 subsys_device; /* IDs will be loaded into PCI config space */ u16 subsys_vendor; - u16 pci_device; //PCI device ID; vendor is always Broadcom (0x14E4) - u8 unknown1[8]; //?, noticed no effect - u16 basic_config; //?, see below - u8 checksum; //byte sum of header == 0 - u8 unknown2; //?, patch rejected if changed - u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...) + u16 pci_device; /* PCI device ID; vendor is always Broadcom (0x14E4) */ + u8 unknown1[8]; /* ?, noticed no effect */ + u16 basic_config; /* ?, see below */ + u8 checksum; /* byte sum of header == 0 */ + u8 unknown2; /* ?, patch rejected if changed */ + u16 patch_version; /* 10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...) */ } header; struct { /* Init code */ - u8 checksum; //byte sum of init == 0 - u8 unknown; //?, looks unused - u8 num_hunks; //0x60 = 3 hunks, 0x80 = 4 hunks, other values not supported - u8 size; //total size of all hunk#_code[] in bytes - u8 hunk1_when; //mark when hunk1_code gets executed - u8 hunk1_size; //sizeof(hunk1_code) + u8 checksum; /* byte sum of init == 0 */ + u8 unknown; /* ?, looks unused */ + u8 num_hunks; /* 0x60 = 3 hunks, 0x80 = 4 hunks, other values not supported */ + u8 size; /* total size of all hunk#_code[] in bytes */ + u8 hunk1_when; /* mark when hunk1_code gets executed */ + u8 hunk1_size; /* sizeof(hunk1_code) */ u8 hunk2_when; u8 hunk2_size; u8 hunk3_when; u8 hunk3_size; - u8 hunk4_when; //0x00 (padding) if only 3 hunks - u8 hunk4_size; //dito - u32 hunk1_code[INIT1_LENGTH]; //actual commands, see below + u8 hunk4_when; /* 0x00 (padding) if only 3 hunks */ + u8 hunk4_size; /* dito */ + u32 hunk1_code[INIT1_LENGTH]; /* actual commands, see below */ u32 hunk2_code[INIT2_LENGTH]; u32 hunk3_code[INIT3_LENGTH]; - u32 hunk4_code[INIT4_LENGTH]; //missing (zero length) if only 3 hunks + u32 hunk4_code[INIT4_LENGTH]; /* missing (zero length) if only 3 hunks */ } init; struct { /* Power down code */ - u8 checksum; //byte sum of powerdown == 0 - u8 unknown; //?, looks unused - u8 num_hunks; //0x20 = 1 hunk, other values not supported - u8 size; //total size of all hunk#_code[] in bytes - u8 hunk1_when; //mark when hunk1_code gets executed - u8 hunk1_size; //sizeof(hunk1_code) - u16 padding; //0x0000, hunk2 is not supported - u32 hunk1_code[PWRDN_LENGTH]; //commands, see below + u8 checksum; /* byte sum of powerdown == 0 */ + u8 unknown; /* ?, looks unused */ + u8 num_hunks; /* 0x20 = 1 hunk, other values not supported */ + u8 size; /* total size of all hunk#_code[] in bytes */ + u8 hunk1_when; /* mark when hunk1_code gets executed */ + u8 hunk1_size; /* sizeof(hunk1_code) */ + u16 padding; /* 0x0000, hunk2 is not supported */ + u32 hunk1_code[PWRDN_LENGTH]; /* commands, see below */ } powerdown; } selfboot_patch = { /* Keep the following invariant for valid Selfboot patches */ .header.signature = 0xA5, - .header.format = 0x23, //format 1 revision 3 + .header.format = 0x23, /* format 1 revision 3 */ .header.unknown1 = { 0x61, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - .header.checksum = 0, //calculated later + .header.checksum = 0, /* calculated later */ .header.unknown2 = 0x30, - .init.checksum = 0, //calculated later + .init.checksum = 0, /* calculated later */ .init.unknown = 0x00, .init.num_hunks = sizeof(selfboot_patch.init.hunk4_code) ? 0x80 : 0x60, .init.size = sizeof(selfboot_patch.init.hunk1_code) @@ -171,7 +171,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! .init.hunk2_size = sizeof(selfboot_patch.init.hunk2_code), .init.hunk3_size = sizeof(selfboot_patch.init.hunk3_code), .init.hunk4_size = sizeof(selfboot_patch.init.hunk4_code), - .powerdown.checksum = 0, //calculated later + .powerdown.checksum = 0, /* calculated later */ .powerdown.unknown = 0x00, .powerdown.num_hunks = 0x20, .powerdown.size = sizeof(selfboot_patch.powerdown.hunk1_code), @@ -180,19 +180,19 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! /* Only the lines below may be adapted to your needs ... */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - .header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, //Broadcom - .header.subsys_device = be16(0x1699), //same as pci_device - .header.subsys_vendor = be16(0x14E4), //Broadcom + .header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, /* Broadcom */ + .header.subsys_device = be16(0x1699), /* same as pci_device */ + .header.subsys_vendor = be16(0x14E4), /* Broadcom */ #else - .header.mac_addr = { 0x00, 0x20, 0x9D, 0x00, 0x00, 0x00 }, //LiPPERT - .header.subsys_device = be16(0x1699), //simply kept this - .header.subsys_vendor = be16(0x121D), //LiPPERT + .header.mac_addr = { 0x00, 0x20, 0x9D, 0x00, 0x00, 0x00 }, /* LiPPERT */ + .header.subsys_device = be16(0x1699), /* simply kept this */ + .header.subsys_vendor = be16(0x121D), /* LiPPERT */ #endif - .header.pci_device = be16(0x1699), //Broadcom 5785 with GbE PHY + .header.pci_device = be16(0x1699), /* Broadcom 5785 with GbE PHY */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - .header.patch_version = be16(0x010B), //1.11 (Broadcom's sb5785m1.11) + .header.patch_version = be16(0x010B), /* 1.11 (Broadcom's sb5785m1.11) */ #else - .header.patch_version = be16(0x110B), //1.11b, i.e. hacked :-) + .header.patch_version = be16(0x110B), /* 1.11b, i.e. hacked :-) */ #endif /* Bitfield enabling general features/codepaths in the firmware or * selecting support for one of several supported PHYs? @@ -209,9 +209,9 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! * 1 X 1 | 0x391C6140 - - - */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - .header.basic_config = be16(0x0404), //original for B50610 + .header.basic_config = be16(0x0404), /* original for B50610 */ #else - .header.basic_config = be16(0x0604), //bit 9 set so not to mess up PHY regs, kept other bits unchanged + .header.basic_config = be16(0x0604), /* bit 9 set so not to mess up PHY regs, kept other bits unchanged */ #endif /* Tag that defines when / on what occasion the commands are interpreted. @@ -223,7 +223,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! * 68, 20, 70, 80 to be interpreted in this order. * All tests were performed with .basic_config = 0x0604. */ - .init.hunk1_when = 0x10, //only once at RISC CPU reset? + .init.hunk1_when = 0x10, /* only once at RISC CPU reset? */ /* Instructions are obviously a specialized bytecode interpreted by the * main firmware, rather than MIPS machine code. Commands consist of 1-3 * 32-bit words. In the following, 0-9,A-F = hex literals, a-z,_ = variable @@ -245,69 +245,68 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! */ .init.hunk1_code = { #if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0x082B8104), //CFR-AF: PHY0B: KSZ9021 select PHY104 - be(0x082CF0F0), //CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel) - be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105 - be(0x082C3333), //CFR-AF: PHY0C: KSZ9021 RX data skew (empirical) + be(0x082B8104), /* CFR-AF: PHY0B: KSZ9021 select PHY104 */ + be(0x082CF0F0), /* CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel) */ + be(0x082B8105), /* CFR-AF: PHY0B: KSZ9021 select PHY105 */ + be(0x082C3333), /* CFR-AF: PHY0C: KSZ9021 RX data skew (empirical) */ #endif - be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12 = 1: auto-clock-switch - be(0x06100D34), be(0x00000000), //v1.03 : MemD34: clear config vars - be(0x06100D38), be(0x00000000), //v1.03 : - | - be(0x06100D3C), be(0x00000000), //v1.03 : MemD3F| - }, //-->INIT1_LENGTH! + be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), /* v1.05 : 5A0.24,12 = 1: auto-clock-switch */ + be(0x06100D34), be(0x00000000), /* v1.03 : MemD34: clear config vars */ + be(0x06100D38), be(0x00000000), /* v1.03 : - | */ + be(0x06100D3C), be(0x00000000), /* v1.03 : MemD3F| */ + }, /* -->INIT1_LENGTH! */ - .init.hunk2_when = 0x30, //after global reset, PHY reset + .init.hunk2_when = 0x30, /* after global reset, PHY reset */ .init.hunk2_code = { #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0x08370F08), //v1.06 : PHY17: B50610 select reg. 08 - be(0x08350001), //v1.06 : PHY15: B50610 slow link fix - be(0x08370F00), //v1.06 : PHY17: B50610 disable reg. 08 - be(0x083C2C00), //v1.11 : PHY1C: B50610 Shadow 0B + be(0x08370F08), /* v1.06 : PHY17: B50610 select reg. 08 */ + be(0x08350001), /* v1.06 : PHY15: B50610 slow link fix */ + be(0x08370F00), /* v1.06 : PHY17: B50610 disable reg. 08 */ + be(0x083C2C00), /* v1.11 : PHY1C: B50610 Shadow 0B */ #endif - be(0xF7F301E6), //v1.09+: ?: subroutine calls to - be(0xF7FFF0B6), be(0x0000FFE7), //v1.09+: ?| restore Port Mode ??? - be(0xF7FFF0F6), be(0x00008000), //v1.09+: ?| - be(0xF7F401E6), //v1.09+: ?| - }, //-->INIT2_LENGTH! + be(0xF7F301E6), /* v1.09+: ?: subroutine calls to */ + be(0xF7FFF0B6), be(0x0000FFE7), /* v1.09+: ?| restore Port Mode ??? */ + be(0xF7FFF0F6), be(0x00008000), /* v1.09+: ?| */ + be(0xF7F401E6), /* v1.09+: ?| */ + }, /* -->INIT2_LENGTH! */ - .init.hunk3_when = 0xA8, //?, I'd guess quite late + .init.hunk3_when = 0xA8, /* ?, I'd guess quite late */ .init.hunk3_code = { - be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), //v1.08 : 3604.20-16: 10Mb clock = 12.5MHz - }, //-->INIT3_LENGTH! + be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), /* v1.08 : 3604.20-16: 10Mb clock = 12.5MHz */ + }, /* -->INIT3_LENGTH! */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - .init.hunk4_when = 0xD8, //original for B50610 + .init.hunk4_when = 0xD8, /* original for B50610 */ #else - .init.hunk4_when = 0x80, //run last, after Linux' "ifconfig up" + .init.hunk4_when = 0x80, /* run last, after Linux' "ifconfig up" */ #endif .init.hunk4_code = { #if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0x083F4300), //CFR-AF: PHY1F: IRQ active high - be(0x083C0000), //CFR-AF: PHY1C: revert driver writes - be(0x08380000), //CFR-AF: PHY18| - be(0x083C0000), //CFR-AF: PHY1C| + be(0x083F4300), /* CFR-AF: PHY1F: IRQ active high */ + be(0x083C0000), /* CFR-AF: PHY1C: revert driver writes */ + be(0x08380000), /* CFR-AF: PHY18| */ + be(0x083C0000), /* CFR-AF: PHY1C| */ #endif - be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0 == 1 -->skip next 12 bytes + be(0xCB0005A4), be(0xF7F0000C), /* v1.01 : if 5A4.0 == 1 -->skip next 12 bytes */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode + be(0xC61005A4), be(0x3210C500), /* v1.01 : 5A4: PHY LED mode */ #else - be(0xC61005A4), be(0x331C71CE), //CFR-AF: 5A4: fake LED mode + be(0xC61005A4), be(0x331C71CE), /* CFR-AF: 5A4: fake LED mode */ #endif - be(0xF7F00008), //v1.01 : -->skip next 8 bytes - be(0xC61005A4), be(0x331C71C1), //v1.01 : 5A4: inband LED mode - //be(0xC3200454), //CFR-AF: 454.4: auto link polling - }, //-->INIT4_LENGTH! + be(0xF7F00008), /* v1.01 : -->skip next 8 bytes */ + be(0xC61005A4), be(0x331C71C1), /* v1.01 : 5A4: inband LED mode */ + }, /* -->INIT4_LENGTH! */ - .powerdown.hunk1_when = 0x50, //prior to IDDQ MAC + .powerdown.hunk1_when = 0x50, /* prior to IDDQ MAC */ .powerdown.hunk1_code = { #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF - be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY + be(0x083CB001), /* v1.10 : PHY1C: IDDQ B50610 PHY */ #endif - be(0xF7F30116), // IDDQ PHY - be(0xC40005A0), //v1.09 : 5A0.0 = 0: Port Mode = MII - be(0xC4180400), //v1.09 : 400.3 = 0| - be(0xC3100400), //v1.09 : 400.2 = 1| - }, //-->PWRDN_LENGTH! + be(0xF7F30116), /* IDDQ PHY */ + be(0xC40005A0), /* v1.09 : 5A0.0 = 0: Port Mode = MII */ + be(0xC4180400), /* v1.09 : 400.3 = 0| */ + be(0xC3100400), /* v1.09 : 400.2 = 1| */ + }, /* -->PWRDN_LENGTH! */ }; @@ -316,8 +315,8 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! */ void broadcom_init(void) { - volatile u32 *gec_base; //Gigabit Ethernet Controller base addr - u8 *gec_shadow; //base addr of shadow 'NV'RAM for GbE MAC in A55E + volatile u32 *gec_base; /* Gigabit Ethernet Controller base addr */ + u8 *gec_shadow; /* base addr of shadow 'NV'RAM for GbE MAC in A55E */ u8 sum; int i; @@ -327,8 +326,8 @@ void broadcom_init(void) /* Halt RISC CPU before uploading the firmware patch */ for (i = 10000; i > 0; i--) { - gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state - gec_base[0x5000/4] |= (1 << 10); //issue RISC halt + gec_base[0x5004/4] = 0xFFFFFFFF; /* clear CPU state */ + gec_base[0x5000/4] |= (1 << 10); /* issue RISC halt */ if (gec_base[0x5000/4] | (1 << 10)) break; udelay(10); @@ -349,10 +348,10 @@ void broadcom_init(void) /* Upload firmware patch to shadow 'NV'RAM */ for (i = 0; i < sizeof(selfboot_patch); i++) - gec_shadow[i] = ((u8*)&selfboot_patch)[i]; //access byte-wise! + gec_shadow[i] = ((u8*)&selfboot_patch)[i]; /* access byte-wise! */ /* Restart BCM5785's CPU */ - gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state - gec_base[0x5000/4] = 0x00000001; //reset RISC processor - //usually we'd have to wait for the reset bit to clear again ... + gec_base[0x5004/4] = 0xFFFFFFFF; /* clear CPU state */ + gec_base[0x5000/4] = 0x00000001; /* reset RISC processor */ + /* usually we'd have to wait for the reset bit to clear again ... */ } diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 1c5c424..883dd85 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -74,7 +74,6 @@ #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE @@ -94,10 +93,7 @@ #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE @@ -106,65 +102,24 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 #define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE #define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 + #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE @@ -172,8 +127,6 @@ #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY @@ -181,16 +134,6 @@ #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE @@ -249,41 +192,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long +/* This is the delivery package title, "BrazosPI" */ +/* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long +/* This is the release version number of the AGESA component */ +/* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -292,5 +236,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data. */ #include "PlatformInstall.h" diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index d8e4f05..d7ca419 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -88,7 +88,6 @@ static void mainboard_enable(device_t dev) /* Upload AMD A55E GbE 'NV'RAM contents. Still untested on Inagua. * After anyone can confirm it works please uncomment the call. */ - //broadcom_init(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 2deb219..6053ac4 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -86,7 +86,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index d39a3ab..ea46291 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -161,7 +161,7 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA + #define AZALIA_SDIN_PIN 0x2A /** diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c index 2c633e5..221b4b3 100644 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -175,8 +175,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; //6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5; */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /* 6 | BIT3; */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -212,7 +212,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /* BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; @@ -247,7 +247,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; @@ -258,7 +258,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5; */ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; @@ -268,7 +268,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;/* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, @@ -296,7 +296,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); /* Turn on FCH GPP slots */ diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index 0fec106..25e685b 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -108,9 +108,6 @@ const u8 mainboard_intr_data[] = { * use PIC IRQ 10 if it uses PIN A for its hardware INT. */ static const struct pirq_struct mainboard_pirq_data[] = { - /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ -// {GFX_DEVFN, {PIRQ_GFX, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ -// {ACTL_DEVFN, {PIRQ_NC, PIRQ_ACTL, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J119: 02.1 */ {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J118: 03.1 */ {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J120: 03.2 */ diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 9bf3a67..09a38bd 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -56,35 +56,6 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0xA8, word); } -#if 0 /* not tested yet */ -/******************************************************** -* mahogany uses SB700 GPIO9 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 5); /* Set Gpio9 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif /* get_ide_dma66 */ - u8 is_dev3_present(void) { return 0; diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index 708ddbd..9357b42 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 8c244d4..b197d36 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -56,35 +56,6 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0xA8, word); } -#if 0 /* not tested yet. */ -/******************************************************** -* mahogany uses SB700 GPIO9 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 5); /* Set Gpio9 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif /* get_ide_dma66() */ - u8 is_dev3_present(void) { return 0; diff --git a/src/mainboard/amd/mahogany_fam10/resourcemap.c b/src/mainboard/amd/mahogany_fam10/resourcemap.c index 95d009a..013f658 100644 --- a/src/mainboard/amd/mahogany_fam10/resourcemap.c +++ b/src/mainboard/amd/mahogany_fam10/resourcemap.c @@ -45,7 +45,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -83,7 +83,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -131,7 +131,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,7 +165,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,7 +191,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -223,7 +220,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -264,7 +260,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 1ee6698..ca7f3e5 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/*used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -102,12 +100,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); +/* dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); */ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -166,10 +164,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -196,8 +194,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -208,21 +204,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 2361c03..e4be6e5 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -45,20 +45,20 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); * AMD Olivehill Platform ALC272 Verb Table */ static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT + {0x11, 0x411111F0}, /* - SPDIF_OUT2 */ + {0x12, 0x411111F0}, /* - DMIC_1/2 */ + {0x13, 0x411111F0}, /* - DMIC_3/4 */ + {0x14, 0x411111F0}, /* Port D - LOUT1 */ + {0x15, 0x411111F0}, /* Port A - LOUT2 */ + {0x16, 0x411111F0}, + {0x17, 0x411111F0}, /* Port H - MONO */ + {0x18, 0x01a19840}, /* Port B - MIC1 */ + {0x19, 0x411111F0}, /* Port F - MIC2 */ + {0x1a, 0x01813030}, /* Port C - LINE1 */ + {0x1b, 0x411111F0}, /* Port E - LINE2 */ + {0x1d, 0x40130605}, /* - PCBEEP */ + {0x1e, 0x01441120}, /* - SPDIF_OUT1 */ + {0x21, 0x01214010}, /* Port I - HPOUT */ {0xff, 0xffffffff} }; @@ -126,8 +126,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5; */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; /* 6 | BIT3; */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -138,7 +138,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /* AC0 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ @@ -161,7 +161,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111; /* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, @@ -190,7 +190,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h index eaf2442..bf623f7 100644 --- a/src/mainboard/amd/olivehill/OptionsIds.h +++ b/src/mainboard/amd/olivehill/OptionsIds.h @@ -43,17 +43,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 1d3fe77..d334604 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -53,36 +53,22 @@ #endif #endif -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE /* TRUE */ +#define BLDOPT_REMOVE_SLIT FALSE /* TRUE */ +#define BLDOPT_REMOVE_WHEA FALSE /* TRUE */ #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/*This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -104,11 +90,11 @@ #define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 /* Specifies the IO addresses trapped by the */ + /* core for C-state entry requests. A value */ + /* of 0 in this field specifies that the core */ + /* does not trap any IO addresses for C-state entry. */ + /* Values greater than 0xFFF8 results in undefined behavior. */ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE @@ -149,15 +135,10 @@ #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled #define BLDCFG_IOMMU_SUPPORT FALSE #define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL #define BLDCFG_CFG_ABM_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID #ifdef PCIEX_BASE_ADDRESS #define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS @@ -174,43 +155,6 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = { @@ -244,40 +188,21 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE*/ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* QUANDRANK_TYPE*/ + +/* USER_MEMORY_TIMING_MODE */ + +/* POWER_DOWN_MODE */ /* * Agesa optional capabilities selection. @@ -322,17 +247,16 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL olivehill_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, {-1} }; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 9ae75ae..a540d0d 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; @@ -102,45 +101,7 @@ static void *smp_write_config_table(void *v) outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } -#if 0 - outb(0x0B, 0xCD6); - outb(0x02, 0xCD7); - outb(0x50, 0xCD6); - outb(0x1F, 0xCD7); - - outb(0x48, 0xCD6); - outb(0xF2, 0xCD7); - - //outb(0xBE, 0xCD6); - //outb(0x52, 0xCD7); - - outb(0xED, 0xCD6); - outb(0x17, 0xCD7); - - *(volatile u8 *) (0xFED80D00 + 0x31) = 2; - *(volatile u8 *) (0xFED80D00 + 0x32) = 2; - *(volatile u8 *) (0xFED80D00 + 0x33) = 2; - *(volatile u8 *) (0xFED80D00 + 0x34) = 2; - - *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; - *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; - *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; - *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; - - *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; - *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; - *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; - - *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; - *(volatile u8 *) (0xFED80100 + 0xA6) = 0; - - *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; -#endif /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c index 9528f72..82c8911 100644 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c @@ -49,20 +49,20 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); * Realtek ALC272 CODEC Verb Table */ static const CODEC_ENTRY Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40251E05}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT + {0x11, 0x411111F0}, /* - SPDIF_OUT2 */ + {0x12, 0x411111F0}, /* - DMIC_1/2 */ + {0x13, 0x411111F0}, /* - DMIC_3/4 */ + {0x14, 0x411111F0}, /* Port D - LOUT1 */ + {0x15, 0x411111F0}, /* Port A - LOUT2 */ + {0x16, 0x411111F0}, + {0x17, 0x411111F0}, /* Port H - MONO */ + {0x18, 0x01a19840}, /* Port B - MIC1 */ + {0x19, 0x411111F0}, /* Port F - MIC2 */ + {0x1a, 0x01813030}, /* Port C - LINE1 */ + {0x1b, 0x411111F0}, /* Port E - LINE2 */ + {0x1d, 0x40251E05}, /* - PCBEEP */ + {0x1e, 0x01441120}, /* - SPDIF_OUT1 */ + {0x21, 0x01214010}, /* Port I - HPOUT */ {0xff, 0xffffffff} }; @@ -141,8 +141,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; //6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; /* 6 | BIT3 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -178,7 +178,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /* BIT0 | BIT2 | BIT5 */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; @@ -213,7 +213,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; @@ -224,7 +224,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; @@ -234,7 +234,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; /* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, @@ -262,7 +262,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable(); diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index 925526c..75a5798 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 6d1e4ea..9b14013 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -91,7 +91,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); AGESAWRAPPER(amdinitpost); - //PspMboxBiosCmdDramInfo(); post_code(0x41); AGESAWRAPPER(amdinitenv); /* diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index c83e318..1a97bb7 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -126,8 +126,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;/* 6 | BIT3 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -138,7 +138,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ @@ -161,7 +161,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111; /* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, @@ -190,7 +190,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h index eaf2442..bf623f7 100644 --- a/src/mainboard/amd/parmer/OptionsIds.h +++ b/src/mainboard/amd/parmer/OptionsIds.h @@ -43,17 +43,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 8ba3c53..b030e2d 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -50,35 +50,22 @@ #define INSTALL_FM2_SOCKET_SUPPORT FALSE -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/* This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -126,7 +113,7 @@ #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 /* PCIE Spread Spectrum default value 0.36% */ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 #define BLDOPT_REMOVE_ALIB FALSE @@ -138,16 +125,10 @@ #define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 #define BLDCFG_CFG_ABM_SUPPORT 0 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity +/* Specify the default values for the VRM controlling the VDDNB plane. + * If not specified, the values used for the core VRM will be applied + */ #define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 @@ -157,17 +138,14 @@ #if CONFIG_GFXUMA #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000/*512M */ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif #define BLDCFG_IOMMU_SUPPORT FALSE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + /* Process the options... * This file include MUST occur AFTER the user option selection settings @@ -175,43 +153,7 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = { @@ -245,40 +187,40 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define DDR2100_FREQUENCY 1050 /* DDR 2100 */ +#define DDR2133_FREQUENCY 1066 /* DDR 2133 */ +#define DDR2400_FREQUENCY 1200 /* DDR 2400 */ +#define UNSUPPORTED_DDR_FREQUENCY 1201 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ /* * Agesa optional capabilities selection. @@ -323,7 +265,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL parmer_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, @@ -331,9 +272,10 @@ GPIO_CONTROL parmer_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&parmer_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index e10fc89..b630b71 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index b0b79ab..2cf07ed 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -40,8 +40,9 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); /* Call the host environment interface to provide a user hook opportunity. */ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) { - // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. - // Make sure the right speed settings are selected. + /* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. + * Make sure the right speed settings are selected. + */ ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } @@ -60,7 +61,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -72,7 +73,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; switch (ResetInfo->ResetId) { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + case 46: /* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */ switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index 825364e..2b811fd 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -46,31 +46,31 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -79,18 +79,18 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeLvds, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} } }; @@ -102,11 +102,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &DdiList[0] }; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h index 2d8381b..7a9c03f 100644 --- a/src/mainboard/amd/persimmon/OptionsIds.h +++ b/src/mainboard/amd/persimmon/OptionsIds.h @@ -43,14 +43,6 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index 4132c7c..40489cc 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -21,45 +21,45 @@ #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 670010d..07a52e2 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -74,7 +74,6 @@ #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE @@ -94,10 +93,7 @@ #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE @@ -106,65 +102,24 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 #define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE #define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 + #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE @@ -172,8 +127,6 @@ #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY @@ -181,16 +134,6 @@ #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE @@ -249,41 +192,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long +/* This is the delivery package title, "BrazosPI" */ +/* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long +/* This is the release version number of the AGESA component */ +/* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -292,5 +236,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data. */ #include "PlatformInstall.h" diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 8e954cd..c726875 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 660be41..648ee17 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -161,7 +161,7 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA + #define AZALIA_SDIN_PIN 0x2A /** diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index ddc232f..282222d 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -80,7 +80,7 @@ unsigned long acpi_fill_madt(unsigned long current) for(i = 1; i< sysconf.hc_possible_num; i++) { u32 d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; - // 8131 need to use +4 + /* 8131 need to use +4 */ switch (sysconf.hcid[i]) { case 1: d = 7; @@ -141,15 +141,15 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp int i; - get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ /* Align ACPI tables to 16 bytes */ start = ALIGN(start, 16); current = start; - //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table + /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ - for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; @@ -160,16 +160,16 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp c = (u8) ('A' + i - 1 - 6); } current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt + printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */ ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { - case 1: //8132 + case 1: /* 8132 */ file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; - case 2: //8151 + case 2: /* 8151 */ file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; - case 3: //8131 + case 3: /* 8131 */ file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c index 6bb03e9..6cf5197 100644 --- a/src/mainboard/amd/serengeti_cheetah/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah/fadt.c @@ -41,11 +41,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; - // disable system management mode by setting to 0: - fadt->smi_cmd = 0;//pm_base+0x2f; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0;/* pm_base+0x2f */ fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; fadt->s4bios_req = 0x0; @@ -75,10 +75,10 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->flush_stride = 0; fadt->duty_offset = 1; fadt->duty_width = 3; - fadt->day_alrm = 0; // 0x7d these have to be - fadt->mon_alrm = 0; // 0x7e added to cmos.layout - fadt->century = 0; // 0x7f to make rtc alrm work - fadt->iapc_boot_arch = 0x3; // See table 5-11 + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ fadt->flags = 0x25; fadt->res2 = 0; diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index 1eb97b5..b7f55fd 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -23,30 +23,18 @@ #include <stdlib.h> #include "mb_sysconf.h" -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */ struct mb_sysconf_t mb_sysconf; -static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +static unsigned pci1234x[] = { /*Here you only need to set value in pci1234 for HT-IO that could be installed or not */ + /* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */ 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 }; -static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most +static unsigned hcdnx[] = { /* HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */ 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, }; static unsigned get_bus_conf_done = 0; @@ -64,20 +52,20 @@ static unsigned get_hcid(unsigned i) dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); switch (dev->device) { - case 0x7458: //8132 + case 0x7458: /*8132 */ id = 1; break; - case 0x7454: //8151 + case 0x7454: /*8151 */ id = 2; break; - case 0x7450: //8131 + case 0x7450: /*8131 */ id = 3; break; } - // we may need more way to find out hcid: subsystem id? GPIO read ? + /* we may need more way to find out hcid: subsystem id? GPIO read ? */ - // we need use id for 1. bus num, 2. mptable, 3. ACPI table + /* we need use id for 1. bus num, 2. mptable, 3. ACPI table */ return id; } @@ -92,7 +80,7 @@ void get_bus_conf(void) struct mb_sysconf_t *m; if (get_bus_conf_done == 1) - return; //do it only once + return; /* do it only once */ get_bus_conf_done = 1; @@ -150,13 +138,13 @@ void get_bus_conf(void) if (!(sysconf.pci1234[i] & 0x1)) continue; - // check hcid type here + /* check hcid type here */ sysconf.hcid[i] = get_hcid(i); switch (sysconf.hcid[i]) { - case 1: //8132 - case 3: //8131 + case 1: /* 8132 */ + case 3: /* 8131 */ m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; @@ -190,7 +178,7 @@ void get_bus_conf(void) break; - case 2: //8151 + case 2: /* 8151 */ m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; m->sbdn5[j] = sysconf.hcdn[i] & 0xff; @@ -202,7 +190,6 @@ void get_bus_conf(void) if (dev) { m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - // printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", @@ -215,7 +202,7 @@ void get_bus_conf(void) j++; } -/*I/O APICs: APIC ID Version State Address*/ +/* I/O APICs: APIC ID Version State Address */ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) apicid_base = get_apicid_base(3); else @@ -227,5 +214,4 @@ void get_bus_conf(void) m->apicid_8132a[i][0] = apicid_base + 3 + i * 2; m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1; } - } diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c index 3d9820f..9e2e09b 100644 --- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c @@ -55,7 +55,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct mb_sysconf_t *m; - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ m = sysconf.mb; @@ -105,7 +105,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) } } -//pci bridge +/* pci bridge */ printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n"); static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 }; pci_assign_irqs(m->bus_8111_0, sysconf.sbdn + 1, slotIrqs_1_4); @@ -123,9 +123,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info++; slot_num++; -//pcix bridge -// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; +/* pcix bridge */ int j = 0; @@ -157,5 +155,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "done.\n"); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 2ffe4c9..fc421a9 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -41,8 +41,8 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); -/*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111 +/* I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */ { device_t dev; struct resource *res; @@ -69,8 +69,8 @@ static void *smp_write_config_table(void *v) if(!(sysconf.pci1234[i] & 0x1) ) continue; switch(sysconf.hcid[i]) { - case 1: // 8132 - case 3: // 8131 + case 1: /* 8132 */ + case 3: /* 8131 */ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -97,33 +97,33 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -//??? What +/* ??? What */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); -// Onboard AMD USB +/* Onboard AMD USB */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); -//Slot 3 PCI 32 +/*Slot 3 PCI 32 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */ } -//Slot 4 PCI 32 +/* Slot 4 PCI 32 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */ } -//Slot 1 PCI-X 133/100/66 +/* Slot 1 PCI-X 133/100/66 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); } -//Slot 2 PCI-X 133/100/66 +/* Slot 2 PCI-X 133/100/66 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */ } j = 0; @@ -140,9 +140,9 @@ static void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - //Slot 1 PCI-X 133/100/66 + /* Slot 1 PCI-X 133/100/66 */ for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); } } } @@ -151,9 +151,9 @@ static void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - //Slot 2 PCI-X 133/100/66 + /* Slot 2 PCI-X 133/100/66 */ for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); /* 25 */ } } } @@ -161,7 +161,7 @@ static void *smp_write_config_table(void *v) break; case 2: - // Slot AGP + /* Slot AGP */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); break; } diff --git a/src/mainboard/amd/serengeti_cheetah/resourcemap.c b/src/mainboard/amd/serengeti_cheetah/resourcemap.c index 3126dd3..92eaa9c 100644 --- a/src/mainboard/amd/serengeti_cheetah/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah/resourcemap.c @@ -260,8 +260,8 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, // AMD 8151 on link0 of CPU 1 + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, /* AMD 8111 on link0 of CPU 0 */ + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, /* AMD 8151 on link0 of CPU 1 */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index fff950a..5179448 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -37,8 +37,8 @@ static void memreset_setup(void) { - //GPIO on amd8111 to enable MEMRST ???? - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 + /* GPIO on amd8111 to enable MEMRST ???? */ + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } @@ -49,7 +49,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 int ret,i; unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time */ i = 2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); @@ -82,19 +82,19 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node + /* first node */ RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node + /* third node */ RC2|DIMM0, RC2|DIMM2, 0, 0, RC2|DIMM1, RC2|DIMM3, 0, 0, - // four node + /* four node */ RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, #endif @@ -114,27 +114,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_mb_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram - setup_coherent_ht_domain(); // routing table and start other core0 + set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */ + setup_coherent_ht_domain(); /* routing table and start other core0 */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + /* It is said that we should start core1 after all core0 launched */ /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) @@ -144,13 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - -#if 0 - //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); -#endif + ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */ #if CONFIG_SET_FIDVID /* Check to see if processor is capable of changing FIDVID */ @@ -169,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - // show final fid and vid + /* show final fid and vid */ { msr_t msr; msr = rdmsr(0xc0010042); @@ -185,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too + /* fidvid change will issue one LDTSTOP and the HT change will be effective too */ if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); @@ -193,36 +181,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + /* It's the time to set ctrl in sysinfo now; */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); -#if 0 - int i; - for(i = 0; i < 4; i++) { - activate_spd_rom(&cpu[i]); - dump_smbus_registers(); - } -#endif - memreset_setup(); - //do we need apci timer, tsc...., only debug need it for better output + /* do we need apci timer, tsc...., only debug need it for better output */ /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID + /* Need to use TMICT to synchronize FID/VID */ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); -#if 0 - print_pci_devices(); -#endif - -#if 0 -// dump_pci_devices(); - dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); - dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); -#endif - - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); /* bsp swtich stack to RAM and copy sysinfo RAM now */ } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index d7aaff2..399c086 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -53,7 +53,6 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, res->base, gsi_base ); gsi_base+=7; - } } dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); @@ -72,7 +71,7 @@ unsigned long acpi_fill_madt(unsigned long current) for(i = 1; i < sysconf.hc_possible_num; i++) { u32 d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; - // 8131 need to use +4 + /* 8131 need to use +4 */ switch (sysconf.hcid[i]) { case 1: d = 7; @@ -100,7 +99,6 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], res->base, gsi_base ); gsi_base+=d; - } } break; @@ -133,12 +131,13 @@ unsigned long mainboard_write_acpi_tables(device_t device, int i; - get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ /* same htio, but different possition? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ + * change HCIN, and recalculate the checknum and add_table + */ - for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; @@ -149,7 +148,7 @@ unsigned long mainboard_write_acpi_tables(device_t device, c = (u8) ('A' + i - 1 - 6); } current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt + printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); /* pci0 and pci1 are in dsdt */ ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: @@ -158,11 +157,11 @@ unsigned long mainboard_write_acpi_tables(device_t device, case 2: file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; - case 3: //8131 + case 3: /* 8131 */ file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: - //HTX no io apic + /* HTX no io apic */ file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; } p = cbfs_boot_map_with_leak( diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c index 7f54896..b6bcf81 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ - /* * ACPI - create the Fixed ACPI Description Tables (FADT) */ @@ -44,16 +43,15 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; - // disable system management mode by setting to 0: - fadt->smi_cmd = 0;//pm_base+0x2f; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0;/* pm_base+0x2f */ fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x00; // SMM is not used for p-state control -// fadt->pstate_cnt = 0xe2; + fadt->pstate_cnt = 0x00; /* SMM is not used for p-state control */ fadt->pm1a_evt_blk = pm_base; fadt->pm1b_evt_blk = 0x0000; @@ -72,18 +70,17 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe1_blk_len = 8; fadt->gpe1_base = 16; - fadt->cst_cnt = 0x00;// SMM is not used for p-state control -// fadt->cst_cnt = 0xe3; + fadt->cst_cnt = 0x00;/* SMM is not used for p-state control */ fadt->p_lvl2_lat = 101; fadt->p_lvl3_lat = 1001; fadt->flush_size = 0; fadt->flush_stride = 0; fadt->duty_offset = 1; fadt->duty_width = 3; - fadt->day_alrm = 0; // 0x7d these have to be - fadt->mon_alrm = 0; // 0x7e added to cmos.layout - fadt->century = 0; // 0x7f to make rtc alrm work - fadt->iapc_boot_arch = 0x3; // See table 5-11 + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ fadt->flags = 0x25; fadt->res2 = 0; @@ -115,7 +112,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; @@ -130,7 +126,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; @@ -138,7 +133,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm2_cnt_blk.addrl = 0x0; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; @@ -146,7 +140,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_pm_tmr_blk.addrl = pm_base+0x08; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 32; fadt->x_gpe0_blk.bit_offset = 0; @@ -154,7 +147,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_gpe0_blk.addrl = pm_base+0x20; fadt->x_gpe0_blk.addrh = 0x0; - fadt->x_gpe1_blk.space_id = 1; fadt->x_gpe1_blk.bit_width = 64; fadt->x_gpe1_blk.bit_offset = 16; @@ -163,5 +155,4 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->x_gpe1_blk.addrh = 0x0; header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index 87ca672..fda2626 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -29,8 +29,9 @@ struct mb_sysconf_t mb_sysconf; /* Here you only need to set value in pci1234 for HT-IO that could be -installed or not You may need to preset pci1234 for HTIO board, please -refer to src/northbridge/amd/amdfam10/get_sblk_pci1234.c for detail */ + * installed or not You may need to preset pci1234 for HTIO board, please + * refer to src/northbridge/amd/amdfam10/get_sblk_pci1234.c for detail + */ static u32 pci1234x[] = { 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, @@ -42,7 +43,8 @@ static u32 pci1234x[] = { /* HT Chain device num, actually it is unit id base of every ht device -in chain, assume every chain only have 4 ht device at most */ + * in chain, assume every chain only have 4 ht device at most + */ static unsigned hcdnx[] = { 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, @@ -70,18 +72,18 @@ static u32 get_hcid(u32 i) dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); switch (dev->device) { - case 0x7458: //8132 + case 0x7458: /* 8132 */ id = 1; break; - case 0x7454: //8151 + case 0x7454: /* 8151 */ id = 2; break; - case 0x7450: //8131 + case 0x7450: /* 8131 */ id = 3; break; } - // we may need more way to find out hcid: subsystem id? GPIO read ? - // we need use id for 1. bus num, 2. mptable, 3. ACPI table + /* we may need more way to find out hcid: subsystem id? GPIO read ? */ + /* we need use id for 1. bus num, 2. mptable, 3. ACPI table */ return id; } @@ -94,7 +96,7 @@ void get_bus_conf(void) struct mb_sysconf_t *m; if(get_bus_conf_done == 1) - return; //do it only once + return; /* do it only once */ get_bus_conf_done = 1; @@ -145,13 +147,13 @@ void get_bus_conf(void) for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; - // check hcid type here + /* check hcid type here */ sysconf.hcid[i] = get_hcid(i); switch(sysconf.hcid[i]) { - case 1: //8132 - case 3: //8131 + case 1: /* 8132 */ + case 3: /* 8131 */ m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 12) & 0xff; @@ -175,7 +177,7 @@ void get_bus_conf(void) break; - case 2: //8151 + case 2: /* 8151 */ m->bus_8151[j][0] = (sysconf.pci1234[i] >> 12) & 0xff; m->sbdn5[j] = sysconf.hcdn[i] & 0xff; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c index 4bb03c7..1ca7f3d 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c @@ -54,7 +54,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct mb_sysconf_t *m; - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ m = sysconf.mb; @@ -86,16 +86,14 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; - //pci bridge + /* pci bridge */ write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - //pcix bridge -// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; + /* pcix bridge */ int j = 0; @@ -142,5 +140,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "done.\n"); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 8699294..d800051 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -43,8 +43,8 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); - /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111 + /* I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */ { device_t dev; struct resource *res; @@ -99,33 +99,33 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ -//??? What +/* ??? What */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); - // Onboard AMD USB + /* Onboard AMD USB */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); - //Slot 3 PCI 32 + /* Slot 3 PCI 32 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */ } - // Slot 4 PCI 32 + /* Slot 4 PCI 32 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */ } - // Slot 1 PCI-X 133/100/66 + /* Slot 1 PCI-X 133/100/66 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); } - //Slot 2 PCI-X 133/100/66 + /* Slot 2 PCI-X 133/100/66 */ for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */ } j = 0; @@ -144,9 +144,9 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { for(jj = 0; jj < 4; jj++) { - //Slot 1 PCI-X 133/100/66 + /* Slot 1 PCI-X 133/100/66 */ for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); } } } @@ -157,9 +157,9 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { for(jj = 0; jj < 4; jj++) { - //Slot 2 PCI-X 133/100/66 + /* Slot 2 PCI-X 133/100/66 */ for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); /* 25 */ } } } @@ -168,7 +168,7 @@ static void *smp_write_config_table(void *v) break; case 2: - // Slot AGP + /* Slot AGP */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); break; } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c index 8b432ed..fd14a80 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ - - static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { @@ -45,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 + /* Don't touch it, we need it for CAR with FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -83,7 +81,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR with FAM10 + /* don't touch it, we need it for CAR with FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -131,7 +129,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,7 +163,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,7 +189,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -223,7 +218,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -264,7 +258,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 1ccdf26..1aed1fb 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -14,10 +14,8 @@ */ #define SYSTEM_TYPE 0 /* SERVER */ -//#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -50,8 +48,8 @@ static void memreset_setup(void) { - //GPIO on amd8111 to enable MEMRST ???? - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN = 1 + /* GPIO on amd8111 to enable MEMRST ???? */ + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } @@ -87,16 +85,16 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" static const u8 spd_addr[] = { - //first node + /* first node */ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node + /* third node */ RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // forth node + /* forth node */ RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 4 @@ -208,12 +206,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); +/* dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); */ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -268,10 +266,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -308,8 +306,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -320,18 +316,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 711a0d5..71af45a 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -135,7 +135,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -153,13 +153,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; } @@ -170,13 +170,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; } @@ -187,13 +187,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c index 74b0aa8..be84cb1 100644 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ b/src/mainboard/amd/south_station/OemCustomize.c @@ -48,33 +48,33 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) }, #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -104,11 +104,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &DdiList[0] }; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h index 2d8381b..7a9c03f 100644 --- a/src/mainboard/amd/south_station/OptionsIds.h +++ b/src/mainboard/amd/south_station/OptionsIds.h @@ -43,14 +43,6 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h index 001ed16..0e0255e 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -20,45 +20,45 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 38a272d..dc60b77 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -74,7 +74,6 @@ #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE @@ -94,10 +93,7 @@ #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE @@ -106,65 +102,23 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 #define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE #define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE @@ -172,8 +126,6 @@ #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY @@ -181,16 +133,6 @@ #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE @@ -249,41 +191,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -292,5 +235,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data. */ #include "PlatformInstall.h" diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index b546ed8..d090e63 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -50,9 +50,9 @@ void set_pcie_dereset(void) */ static void southstation_led_init(void) { -#define GPIO_FUNCTION 2 //GPIO function -#define SB_GPIO_REG17 17 //Red Light -#define SB_GPIO_REG18 18 //Green Light +#define GPIO_FUNCTION 2 /* GPIO function */ +#define SB_GPIO_REG17 17 /* Red Light */ +#define SB_GPIO_REG18 18 /* Green Light */ /* multi-function pins switch to GPIO0-35 */ RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1); @@ -62,10 +62,10 @@ static void southstation_led_init(void) RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION); /* Lighting test */ - RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); /* output high */ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08); mdelay(100); - RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low + RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); /* output low */ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48); } diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index c24e42c..87572c5 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -83,7 +82,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index d39a3ab..7f825fd 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -161,7 +160,7 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA + #define AZALIA_SDIN_PIN 0x2A /** diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index a6a6279..6290608 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -126,8 +126,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /* BIT0 | BIT2 | BIT5 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /* 6 | BIT3 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ @@ -138,7 +138,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ @@ -161,7 +161,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111; /* BIT0 | BIT4 |BIT8 */ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, @@ -190,7 +190,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) if (FchParams->StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index 66058f2..2d72f9e 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -120,19 +120,19 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - // DP0 to HDMI0/DP0 + /* DP0 to HDMI0/DP0 */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, - // DP1 to HDMI1/DP1 + /* DP1 to HDMI1/DP1 */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) }, - // DP2 to MINI-DDI Card + /* DP2 to MINI-DDI Card */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), @@ -172,11 +172,10 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h index eaf2442..bf623f7 100644 --- a/src/mainboard/amd/thatcher/OptionsIds.h +++ b/src/mainboard/amd/thatcher/OptionsIds.h @@ -43,17 +43,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 #endif diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 8ed3bf2..2b723c0 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -50,35 +50,21 @@ #define INSTALL_FM2_SOCKET_SUPPORT FALSE -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +/* This element selects whether P-States should be forced to be independent, + * as reported by the ACPI _PSD object. For single-link processors, + * setting TRUE for OS to support this feature. + */ #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -126,7 +112,7 @@ #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 /* PCIE Spread Spectrum default value 0.36% */ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 #define BLDOPT_REMOVE_ALIB FALSE @@ -138,16 +124,11 @@ #define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 #define BLDCFG_CFG_ABM_SUPPORT 0 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity +/* Specify the default values for the VRM controlling the VDDNB plane. + * If not specified, the values used for the core VRM will be applied + */ + #define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 @@ -157,17 +138,13 @@ #if CONFIG_GFXUMA #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000/* 512M */ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif #define BLDCFG_IOMMU_SUPPORT FALSE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID /* Process the options... * This file include MUST occur AFTER the user option selection settings @@ -175,43 +152,7 @@ /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = { @@ -245,40 +186,40 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define DDR2100_FREQUENCY 1050 /* DDR 2100 */ +#define DDR2133_FREQUENCY 1066 /* DDR 2133 */ +#define DDR2400_FREQUENCY 1200 /* DDR 2400 */ +#define UNSUPPORTED_DDR_FREQUENCY 1201 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ /* * Agesa optional capabilities selection. @@ -323,7 +264,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 #define FCH_NO_XHCI_SUPPORT TRUE GPIO_CONTROL thatcher_gpio[] = { {183, Function1, PullUpB}, @@ -331,9 +271,10 @@ GPIO_CONTROL thatcher_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&thatcher_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 2640284..c61979f 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; @@ -173,7 +172,7 @@ static void *smp_write_config_table(void *v) /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 6652723..f3d67e4 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -88,35 +88,6 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0x7e, word); } -#if 0 /* TODO: */ -/******************************************************** -* tilapia uses SB700 GPIO8 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 4); /* Set Gpio8 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 4) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif - /* * justify the dev3 is exist or not */ @@ -251,18 +222,7 @@ static void set_thermal_config(void) pm_iowrite(0x3c, byte); /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); - * pm_iowrite(0x67, byte); - */ + } /************************************************* @@ -274,7 +234,6 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); set_pcie_dereset(); - /* get_ide_dma66(); */ set_thermal_config(); set_gpio40_gfx(); } diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c index 95d009a..d696c4d 100644 --- a/src/mainboard/amd/tilapia_fam10/resourcemap.c +++ b/src/mainboard/amd/tilapia_fam10/resourcemap.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ - - static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { @@ -45,7 +43,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + /* Don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -83,7 +81,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + /* don't touch it, we need it for CONFIG_CAR_FAM10 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, @@ -131,7 +129,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -166,7 +163,6 @@ static void setup_mb_resource_map(void) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -193,7 +189,6 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -223,7 +218,6 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, @@ -264,7 +258,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + /* AMD 8111 on link0 of CPU 0 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 1faac4d..c68fccc 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -13,11 +13,9 @@ * GNU General Public License for more details. */ -//#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -102,12 +100,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -166,10 +162,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -196,8 +192,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -208,21 +202,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 0035a27..13c22eb 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -105,7 +105,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB MMIO Base (AcpiMmioAddr) + /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -117,15 +117,15 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; if (ResetInfo->ResetControl == DeassertSlotReset) { - if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + if (ResetInfo->ResetId & (BIT2+BIT3)) { /* de-assert */ + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45); if (Data8 & BIT7) { Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); while (!(Data8 & BIT7)) { Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); } - // GPIO44: PE_GPIO0 MXM Reset + /* GPIO44: PE_GPIO0 MXM Reset */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); @@ -134,53 +134,53 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi } else { Status = AGESA_UNSUPPORTED; } - // Travis + /* Travis */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); - //DE-Assert ALL PCIE RESET - // APU GPP0 (Dev 4) + /* DE-Assert ALL PCIE RESET */ + /* APU GPP0 (Dev 4) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); - // APU GPP1 (Dev 5) + /* APU GPP1 (Dev 5) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); - // APU GPP2 (Dev 6) + /* APU GPP2 (Dev 6) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); - // APU GPP3 (Dev 7) + /* APU GPP3 (Dev 7) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); } else { - if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported - // GPIO44: PE_GPIO0 MXM Reset + if (ResetInfo->ResetId & (BIT2+BIT3)) { /* Pcie Slot Reset is supported */ + /* GPIO44: PE_GPIO0 MXM Reset */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); Status = AGESA_SUCCESS; } - // Travis + /* Travis */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); - //Assert ALL PCIE RESET - // APU GPP0 (Dev 4) + /* Assert ALL PCIE RESET */ + /* APU GPP0 (Dev 4) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); - // APU GPP1 (Dev 5) + /* APU GPP1 (Dev 5) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8); - // APU GPP2 (Dev 6) + /* APU GPP2 (Dev 6) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8); - // APU GPP3 (Dev 7) + /* APU GPP3 (Dev 7) */ Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8); diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index 0910ddc..86ececc 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -13,16 +13,13 @@ * GNU General Public License for more details. */ #ifndef BIOS_SIZE - #define BIOS_SIZE 0x04 //04 - 1MB + #define BIOS_SIZE 0x04 /* 04 - 1MB */ #endif #define LEGACY_FREE 0x00 #if !CONFIG_ONBOARD_USB30 #define XHCI_SUPPORT 0x01 #endif -//#define ACPI_SLEEP_TRAP 0x01 // No sleep trap smi support in coreboot. -//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01 - /** * Module Specific Defines for platform BIOS * @@ -74,7 +71,7 @@ * */ #ifndef WATCHDOG_TIMER_BASE_ADDRESS - #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address + #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 /* Watchdog Timer Base Address */ #endif /** @@ -82,7 +79,7 @@ * */ #ifndef HPET_BASE_ADDRESS - #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address + #define HPET_BASE_ADDRESS 0xFED00000 /* HPET Base address */ #endif /** @@ -107,43 +104,43 @@ * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address * */ -#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr +#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET /* AcpiPm1EvtBlkAddr */ /** * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address * */ -#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr +#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET /* AcpiPm1CntBlkAddr */ /** * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address * */ -#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr +#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET /* AcpiPmTmrBlkAddr */ /** * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address * */ -#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr +#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET /* CpuControlBlkAddr */ /** * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address * */ -#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr +#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET /* AcpiGpe0BlkAddr */ /** * SMI_CMD_PORT - ACPI SMI Command block base address * */ -#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr +#define SMI_CMD_PORT 0xB0 /* SmiCmdPortAddr */ /** * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address * */ -#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 /* AcpiPmaCntBlkAddr */ /** * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID. diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c index 3c20047..9bfaab8 100644 --- a/src/mainboard/amd/torpedo/OemCustomize.c +++ b/src/mainboard/amd/torpedo/OemCustomize.c @@ -23,58 +23,53 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) }, - // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) + /* Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) }, - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) } - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) -// { -// DESCRIPTOR_TERMINATE_LIST, -// PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8), -// PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) -// } + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) }, - // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), @@ -114,11 +109,10 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ + AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h index 45abcab..77e1e90 100644 --- a/src/mainboard/amd/torpedo/OptionsIds.h +++ b/src/mainboard/amd/torpedo/OptionsIds.h @@ -42,15 +42,6 @@ * **/ -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h index 001ed16..0e0255e 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h @@ -20,45 +20,45 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index 656102d..24213cf 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -79,7 +79,7 @@ #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE -//For revision C single-link processors +/* For revision C single-link processors */ #define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE @@ -96,12 +96,12 @@ * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "LlanoPI " - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "LlanoPI " */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '} /* The following definitions specify the default values for various parameters @@ -119,8 +119,8 @@ /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 65000 //240000 //120000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 // 0 +#define BLDCFG_VRM_CURRENT_LIMIT 65000 /* 240000 */ /*120000 */ +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 /* 0 */ #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 #define BLDCFG_PLAT_NUM_IO_APICS 3 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST @@ -128,7 +128,7 @@ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY //DDR1066_FREQUENCY +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY /* DDR1066_FREQUENCY */ #define BLDCFG_MEMORY_MODE_UNGANGED TRUE #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED @@ -161,23 +161,14 @@ #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//enable HW C1E -#define BLDCFG_PLATFORM_C1E_MODE 0 //C1eModeHardware -//#define BLDCFG_PLATFORM_C1E_OPDATA 0x415 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 //0 //CStateModeC6 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 +/* enable HW C1E */ +#define BLDCFG_PLATFORM_C1E_MODE 0 /* C1eModeHardware */ +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 /* 0 */ +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 /* Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 */ -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero. -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime per BKDG. Defaults to 5000, same as core VRM. Cannot be zero. -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Llano/Ontario -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Llano/Ontario -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 /* Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero. */ #define BLDCFG_UMA_ABOVE4G_SUPPORT TRUE #define BLDCFG_STEREO_3D_PINOUT TRUE @@ -202,12 +193,6 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] = }; #define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList -//#define OPTION_NB_LCLK_DPM_INIT FALSE -//#define OPTION_POWER_GATE FALSE -//#define OPTION_PCIE_POWER_GATE FALSE -//#define OPTION_ALIB FALSE -//#define OPTION_PCIe_MID_INIT FALSE -//#define OPTION_NB_MID_INIT FALSE #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 56a90a6..5b34b9d 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - /* * ACPI - create the Fixed ACPI Description Tables (FADT) */ diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 03ab409..d3e905c 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -56,11 +56,11 @@ void gpioEarlyInit(void) { u32 SmiMmioAddr = 0; u32 andMask32 = 0; - // Enable HUDSON MMIO Base (AcpiMmioAddr) + /* Enable HUDSON MMIO Base (AcpiMmioAddr) */ ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); Data8 |= BIT0; WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); - // Get HUDSON MMIO Base (AcpiMmioAddr) + /* Get HUDSON MMIO Base (AcpiMmioAddr) */ ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); Data16 = Data8 << 8; ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8); @@ -71,109 +71,109 @@ void gpioEarlyInit(void) { MiscMmioAddr = AcpiMmioAddr + MISC_BASE; Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80); if ((Data8 & BIT4) == 0) { - BoardType = 0; // external clock board + BoardType = 0; /* external clock board */ } Data8 = Mmio8_G (GpioMmioAddr, GPIO_30); StripInfo = (Data8 & BIT7) >> 7; Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); StripInfo |= (Data8 & BIT7) >> 6; - if (StripInfo < boardRevC) { // for old board. Rev B - Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 - Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 + if (StripInfo < boardRevC) { /* for old board. Rev B */ + Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); /* function 3 */ + Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); /* function 0 */ } for (Index = 0; Index < MAX_GPIO_NO; Index++) { if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { - // Configure multi-function + /* Configure multi-function */ Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); } - // Configure GPIO + /* Configure GPIO */ if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); } if (Index == GPIO_65) { if ( BoardType == 0 ) { - Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 + Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); /* function 3 */ } } } - // Configure GEVENT + /* Configure GEVENT */ if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) { SmiMmioAddr = AcpiMmioAddr + SMI_BASE; andMask32 = ~(1 << (Index - GEVENT_00)); - //EventEnable: 0-Disable, 1-Enable + /* EventEnable: 0-Disable, 1-Enable */ Mmio32_And_Or(SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); - //SciTrig: 0-Falling Edge, 1-Rising Edge + /* SciTrig: 0-Falling Edge, 1-Rising Edge */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); - //SciLevl: 0-Edge trigger, 1-Level Trigger + /* SciLevl: 0-Edge trigger, 1-Level Trigger */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); - //SmiSciEn: 0-Not send SMI, 1-Send SMI + /* SmiSciEn: 0-Not send SMI, 1-Send SMI */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); - //SciS0En: 0-Disable, 1-Enable + /* SciS0En: 0-Disable, 1-Enable */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); - //SciMap: 00000b ~ 11111b + /* SciMap: 00000b ~ 11111b */ RegIndex8 = (u8)((Index - GEVENT_00) >> 2); Data8 = (u8)(((Index - GEVENT_00) & 0x3) * 8); Mmio32_And_Or(SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); - //SmiTrig: 0-Active Low, 1-Active High + /* SmiTrig: 0-Active Low, 1-Active High */ Mmio32_And_Or(SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); - //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 + /* SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 */ RegIndex8 = (u8)((Index - GEVENT_00) >> 4); Data8 = (u8)(((Index - GEVENT_00) & 0xF) * 2); Mmio32_And_Or(SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); } } - // - // config MXM - // GPIO9: Input for MXM_PRESENT2# - // GPIO10: Input for MXM_PRESENT1# - // GPIO28: Input for MXM_PWRGD - // GPIO35: Output for MXM Reset - // GPIO45: Output for MXM Power Enable, active HIGH - // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable - // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO - // - // set INTE#/GPIO32 as GPO for PCIE_SW - RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO + /* + * config MXM + * GPIO9: Input for MXM_PRESENT2# + * GPIO10: Input for MXM_PRESENT1# + * GPIO28: Input for MXM_PWRGD + * GPIO35: Output for MXM Reset + * GPIO45: Output for MXM Power Enable, active HIGH + * GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable + * GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO + */ + /* set INTE#/GPIO32 as GPO for PCIE_SW */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); /* GPO */ RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6); - // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN - RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO + /* set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); /* GPO */ - // set AD9/GPIO9 as GPI for MXM_PRESENT2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD9/GPIO9 as GPI for MXM_PRESENT2# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set AD10/GPIO10 as GPI for MXM_PRESENT1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD10/GPIO10 as GPI for MXM_PRESENT1# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set GNT1#/GPIO44 as GPO for MXM Reset - RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO + /* set GNT1#/GPIO44 as GPO for MXM Reset */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); /* GPO */ - // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO + /* set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); /* GPO */ - // set AD28/GPIO28 as GPI for MXM_PWRGD - RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI + /* set AD28/GPIO28 as GPI for MXM_PWRGD */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); /* GPI */ - // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) + /* set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); @@ -181,20 +181,13 @@ void gpioEarlyInit(void) { RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3); - // - // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). - // - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20)); - //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20))); + /* [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). */ - // check if there any GFX card + /* check if there any GFX card */ Flags = 0; - // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL); - // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09); ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8); if (!(Data8 & BIT7)) { - //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10); ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8); if (!(Data8 & BIT7)) { @@ -203,241 +196,193 @@ void gpioEarlyInit(void) { } if (Flags) { - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 + /* [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 */ RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH */ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + /*PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) */ SbStall (10000); - // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module + /* Write the GPIO55(MXM_PWR_EN) to enable the integrated power module */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) - // WAIT POWER READY: GPIO28 (MXM_PWRGD) - //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} + /* WAIT POWER READY: GPIO28 (MXM_PWRGD) */ + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); while (!(Data8 & BIT7)) { ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); } - // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset - //RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); + /* [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset */ + /* RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); */ } else { - // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module + /* Write the GPIO55(MXM_PWR_EN) to disable the integrated power module */ RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0); - //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) SbStall (10000); - // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down + /* [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down */ RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); } - // - // APU GPP0: On board LAN - // GPIO25: PCIE_RST#_LAN, LOW active - // GPIO63: LAN_CLKREQ# - // GPIO197: LOM_POWER, HIGH Active - // Clock: GPP_CLK3 - // - // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER - RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - - // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 - - // - // APU GPP1: WUSB - // GPIO1: MPCIE_RST2#, LOW active - // GPIO13: WU_DISABLE#, LOW active - // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) - // - // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD01/GPIO01 as GPO for MPCIE_RST2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB -// RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // - // APU GPP2: WWAN - // GPIO0: MPCIE_RST1#, LOW active - // GPIO14: WP_DISABLE#, LOW active - // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) - // - // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD00/GPIO00 as GPO for MPCIE_RST1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN -// RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3); - - // - // APU GPP3: 1394 - // GPIO59: Power control, HIGH active - // GPIO27: PCIE_RST#_1394, LOW active - // GPIO41: CLKREQ# - // Clock: GPP_CLK8 - // - // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 - RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - - // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# - - // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C - RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE - // To fix glitch issue - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - // - // Enable/Disable OnBoard LAN - // + /* + * APU GPP0: On board LAN + * GPIO25: PCIE_RST#_LAN, LOW active + * GPIO63: LAN_CLKREQ# + * GPIO197: LOM_POWER, HIGH Active + * Clock: GPP_CLK3 + */ + /* Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + + /* set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); /* CLK_REQ3# */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); /* Enable GPP_CLK3 */ + + /* + * APU GPP1: WUSB + * GPIO1: MPCIE_RST2#, LOW active + * GPIO13: WU_DISABLE#, LOW active + * GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) + */ + /* Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD01/GPIO01 as GPO for MPCIE_RST2# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB */ + + + /* + * APU GPP2: WWAN + * GPIO0: MPCIE_RST1#, LOW active + * GPIO14: WP_DISABLE#, LOW active + * GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) + */ + /* Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); /* output LOW */ + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Set AD00/GPIO00 as GPO for MPCIE_RST1# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN */ + + /* + * APU GPP3: 1394 + * GPIO59: Power control, HIGH active + * GPIO27: PCIE_RST#_1394, LOW active + * GPIO41: CLKREQ# + * Clock: GPP_CLK8 + */ + /* Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + + /* set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); /* CLK_REQ2# */ + + /* set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C */ + RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); /* GPIO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); /* GPO */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); /* output HIGH */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); /* pullup DISABLE */ + /* To fix glitch issue */ + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); /* set GPIO_GATE_C to LOW */ + + /* Enable/Disable OnBoard LAN */ + if (!CONFIG_ONBOARD_LAN) - { // 1 - DISABLED - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off + { /* 1 - DISABLED */ + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); /* LOM_POWER off */ RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3 + RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); /* PULL UP - DISABLED */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); /* Disable GPP_CLK3 */ } -// else -// { // 0 - AUTO -// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable) -// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); -// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); -// } + /* Enable/Disable 1394 */ - // - // Enable/Disable 1394 - // if (!CONFIG_ONBOARD_1394) - { // 1 - DISABLED -// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off + { /* 1 - DISABLED */ + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); /* 1394 power off */ RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 -// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); /* pullup DISABLE */ + RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); /* DISABLE GPP_CLK8 */ } -// else -// { // 0 - AUTO -// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH) -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); -// -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); -// } - -// -// external USB 3.0 control: -// amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO26: PCIE_RST#_USB3.0 -// GPIO46: PCIE_USB30_CLKREQ# -// GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON -// Clock: GPP_CLK7 -// GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE -// if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { -// disable Onboard NEC USB3.0 controller + +/* + * external USB 3.0 control: + * amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO26: PCIE_RST#_USB3.0 + * GPIO46: PCIE_USB30_CLKREQ# + * GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON + * Clock: GPP_CLK7 + * GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + */ +/* disable Onboard NEC USB3.0 controller */ if (!CONFIG_ONBOARD_USB30) { RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); - RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 - RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); /* PULL_UP DISABLE */ + RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); /* DISABLE GPP_CLK7 */ + RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */ } -// } - -// -// BlueTooth control: BT_ON -// amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO07: BT_ON, 0 - OFF, 1 - ON -// +/* + * BlueTooth control: BT_ON + * amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO07: BT_ON, 0 - OFF, 1 - ON + */ if (!CONFIG_ONBOARD_BLUETOOTH) { - //- if (SystemConfiguration.amdBlueTooth == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); - //- } } -// -// WebCam control: -// amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF -// +/* + * WebCam control: + * amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE + * GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF + */ if (!CONFIG_ONBOARD_WEBCAM) { - //- if (SystemConfiguration.amdWebCam == 1) { RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); - //- } } -// -// Travis enable: -// amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE -// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE -// +/* + * Travis enable: + * amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE + * GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE + */ if (!CONFIG_ONBOARD_TRAVIS) { - //- if (SystemConfiguration.amdTravisCtrl == 0) { RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); - //- } } -// -// Disable Light Sensor if needed -// + +/* Disable Light Sensor if needed */ + if (CONFIG_ONBOARD_LIGHTSENSOR) { - //- if (SystemConfiguration.amdLightSensor == 1) { RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); - //- } } - } diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h index 0df5d50..0e64abd 100644 --- a/src/mainboard/amd/torpedo/gpio.h +++ b/src/mainboard/amd/torpedo/gpio.h @@ -83,87 +83,87 @@ #define FUNCTION1 1 #define FUNCTION2 2 #define FUNCTION3 3 -#define NonGpio 0x80 // BIT7 +#define NonGpio 0x80 /* BIT7 */ -// S0-domain General Purpose I/O: GPIO 00~67 -#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT -#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT -#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT -#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED -#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT -#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT -#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED -#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF -#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level -#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 -#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 -#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 -#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default -#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. -#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) -#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) -#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE - // 1:BATTERY IS FINE(DEFAULT) - // 0:BATTERY IS LOW -#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF -#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default -#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high -#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high -#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high -#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT -#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT -#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 -#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 - // 00 - REVA - // 01 - REVB - // 10 - REVC - // 11 - REVD -#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO -#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. - // 0:USB3.0 I/F in Express CARD - // 1:PCIE I/F in Express CARD detection -#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF -#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# -#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC -#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. -#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# -#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# -#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK -#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE -#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF -#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# -#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA -#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ -#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 -#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V -#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 -#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT -#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE -#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE -#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) - // 1:ENABLE; 0:DISABLE - // DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 -#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN -#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER -#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER -#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE -#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# -#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 -#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 -#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# -#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 -#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM -#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default -#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# +/* S0-domain General Purpose I/O: GPIO 00~67 */ +#define GPIO_00_SELECT FUNCTION1+NonGpio /* MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_01_SELECT FUNCTION1+NonGpio /* MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_02_SELECT FUNCTION1 /* MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT */ +#define GPIO_03_SELECT FUNCTION1+NonGpio /* NOT USED */ +#define GPIO_04_SELECT FUNCTION1+NonGpio /* x1 gpp reset, for J3701, low active, HIGH DEFAULT */ +#define GPIO_05_SELECT FUNCTION1+NonGpio /* express card reset, for J2500, low active, HIGH DEFAULT */ +#define GPIO_06_SELECT FUNCTION0+NonGpio /*NOT USED */ +#define GPIO_07_SELECT FUNCTION1 /* BT_ON, 1: BT ON(DEFAULT); 0: BT OFF */ +#define GPIO_08_SELECT FUNCTION1 /* PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level */ +#define GPIO_09_SELECT FUNCTION1+NonGpio /* MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED */ +#define GPIO_10_SELECT FUNCTION1+NonGpio /* MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED */ +#define GPIO_11_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_12_SELECT FUNCTION1 /* WL_DISABLE#, DISABLE THE WALN IN J3702 */ +#define GPIO_13_SELECT FUNCTION1 /* WU_DISABLE#, DISABLE THE WUSB IN J3711 */ +#define GPIO_14_SELECT FUNCTION1 /* WP_DISABLE, DISABLE THE WWAN IN J3703 */ +#define GPIO_15_SELECT FUNCTION1+NonGpio /* NOT USED, /*FUNCTION1, Reset_CEC# Low Active, High default */ */ +#define GPIO_16_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_17_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_18_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_19_SELECT FUNCTION1 /* For LASSO_DET# detection when Gevent14# is asserted. */ +#define GPIO_20_SELECT FUNCTION1 /* PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) */ +#define GPIO_21_SELECT FUNCTION1 /* DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) */ +#define GPIO_22_SELECT FUNCTION1 /* SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE */ + /* 1:BATTERY IS FINE(DEFAULT) */ + /* 0:BATTERY IS LOW */ +#define GPIO_23_SELECT FUNCTION1 /* CODEC_ON.1: CODEC ON (default)0: CODEC OFF */ +#define GPIO_24_SELECT FUNCTION1 /* Travis reset,Low active High default */ +#define GPIO_25_SELECT FUNCTION1+NonGpio /* PCIE_RST# for LAN (AND gate with PCIE_RST#); default high */ +#define GPIO_26_SELECT FUNCTION1+NonGpio /* PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high */ +#define GPIO_27_SELECT FUNCTION1+NonGpio /* PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high */ +#define GPIO_28_SELECT FUNCTION1 /* MXM PWRGD INDICATOR, INPUT */ +#define GPIO_29_SELECT FUNCTION1 /* MEM HOT, LOW ACTIVE, OUTPUT */ +#define GPIO_30_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 0 */ +#define GPIO_31_SELECT FUNCTION1 /* INPUT, DEFINE THE BOARD REVISION 1 */ + /* 00 - REVA */ + /* 01 - REVB */ + /* 10 - REVC */ + /* 11 - REVD */ +#define GPIO_32_SELECT FUNCTION1+NonGpio /* PCIE_SW - HIGH:MXM; LOW:LASSO */ +#define GPIO_33_SELECT FUNCTION1 /* USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. */ + /* 0:USB3.0 I/F in Express CARD */ + /* 1:PCIE I/F in Express CARD detection */ +#define GPIO_34_SELECT FUNCTION1 /* WEBCAM_ON#. 0: ON (default) 1: OFF */ +#define GPIO_35_SELECT FUNCTION1 /* ODD_DA_INTH# */ +#define GPIO_36_SELECT FUNCTION0+NonGpio /* PCICLK FOR KBC */ +#define GPIO_37_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_38_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_39_SELECT FUNCTION0+NonGpio /* NOT USED */ +#define GPIO_40_SELECT FUNCTION1 /* For DOCK# detection when Gevent14# is asserted. */ +#define GPIO_41_SELECT FUNCTION1+NonGpio /* 1394 CLK REQ# */ +#define GPIO_42_SELECT FUNCTION1+NonGpio /* X4 GPP CLK REQ# */ +#define GPIO_43_SELECT FUNCTION0+NonGpio /* SMBUS0, CLOCK */ +#define GPIO_44_SELECT FUNCTION1+NonGpio /* PEGPIO0, RESET THE MXM MODULE */ +#define GPIO_45_SELECT FUNCTION2+NonGpio /* PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF */ +#define GPIO_46_SELECT FUNCTION1+NonGpio /* USB3.0_CLKREQ# */ +#define GPIO_47_SELECT FUNCTION0+NonGpio /* SMBUS0, DATA */ +#define GPIO_48_SELECT FUNCTION0+NonGpio /* SERIRQ */ +#define GPIO_49_SELECT FUNCTION0+NonGpio /* LDRQ#1 */ +#define GPIO_50_SELECT FUNCTION2 /* SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V */ +#define GPIO_51_SELECT FUNCTION0+NonGpio /* back-up for SMARTVOLTAGE1 */ +#define GPIO_52_SELECT FUNCTION0+NonGpio /* CPU FAN OUT */ +#define GPIO_53_SELECT FUNCTION1 /* ODD POWER ENABLE, HIGH ACTIVE */ +#define GPIO_54_SELECT FUNCTION0+NonGpio /* SB_PROCHOT, OUTPUT, LOW ACTIVE */ +#define GPIO_55_SELECT FUNCTION2+NonGpio /* MXM POWER ENABLE(POWER ON MODULE) */ + /* 1:ENABLE; 0:DISABLE */ + /* DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 */ +#define GPIO_56_SELECT FUNCTION0+NonGpio /* HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN */ +#define GPIO_57_SELECT FUNCTION1 /* HDD0_POWER */ +#define GPIO_58_SELECT FUNCTION1 /* HDD2_POWER */ +#define GPIO_59_SELECT FUNCTION2+NonGpio /* 1394 POWER, OUTPUT, HIGH ACTIVE */ +#define GPIO_60_SELECT FUNCTION0+NonGpio /* EXPCARD_CLKREQ# */ +#define GPIO_61_SELECT FUNCTION0+NonGpio /* PE0_CLKREQ#, FROM J3700 */ +#define GPIO_62_SELECT FUNCTION0+NonGpio /* PE2_CLKREQ#, FROM J3711 */ +#define GPIO_63_SELECT FUNCTION0+NonGpio /* LAN_CLKREQ# */ +#define GPIO_64_SELECT FUNCTION0+NonGpio /* PE1_CLKREQ#, FROM J3703 */ +#define GPIO_65_SELECT FUNCTION0+NonGpio /* MXM CLK REQ#, FROM MXM */ +#define GPIO_66_SELECT FUNCTION1 /* USED AS TRAVIS_EN#; 0:ENABLE as default */ +#define GPIO_67_SELECT FUNCTION0+NonGpio /* USED AS SATA_ACT# */ #define GPIO_68_SELECT FUNCTION0+NonGpio #define GPIO_69_SELECT FUNCTION0+NonGpio #define GPIO_70_SELECT FUNCTION0+NonGpio @@ -192,40 +192,40 @@ #define GPIO_93_SELECT FUNCTION0+NonGpio #define GPIO_94_SELECT FUNCTION0+NonGpio #define GPIO_95_SELECT FUNCTION0+NonGpio -// GEVENT 00~23 are mapped to GPIO 96~119 -#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# -#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# -#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP -#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# -#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# -#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active -#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, - // there is a confliction to IR function when this pin is as a GEVENT. -#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, - // special pin difination for SB900 VGA OUTPUT, high active, - // VGA power for Hudson-M2 will be down when it was asserted. -#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active -#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) -#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 -#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 -#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active - // [option for SPI_TPM_CS# in Hudson-M2 A12)] -#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & - // USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time -#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, - // plus judge GPIO40 and GPIO19 level,low is assert. - // LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) - // DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) -#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active -#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, - // low active, when it's low, BIOS will enbale ODD_PWR -#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# -#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK -#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# -#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT -#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 -#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# -#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI +/* GEVENT 00~23 are mapped to GPIO 96~119 */ +#define GPIO_96_SELECT FUNCTION0 /* GA20IN/GEVENT0# */ +#define GPIO_97_SELECT FUNCTION0 /* KBRST#/GEVENT1# */ +#define GPIO_98_SELECT FUNCTION0 /* THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP */ +#define GPIO_99_SELECT FUNCTION1 /* LPC_PME#/GEVENT3# -> EC_SCI# */ +#define GPIO_100_SELECT FUNCTION2 /* PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# */ +#define GPIO_101_SELECT FUNCTION1 /* LPC_PD#/GEVENT5# -> hotplug of express card, low active */ +#define GPIO_102_SELECT FUNCTION0+NonGpio /* USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, */ + /* there is a confliction to IR function when this pin is as a GEVENT. */ +#define GPIO_103_SELECT FUNCTION0+NonGpio /* DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, */ + /* special pin difination for SB900 VGA OUTPUT, high active, */ + /* VGA power for Hudson-M2 will be down when it was asserted. */ +#define GPIO_104_SELECT FUNCTION0 /* WAKE#/GEVENT8# -> WAKEUP, low active */ +#define GPIO_105_SELECT FUNCTION2 /* SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) */ +#define GPIO_106_SELECT FUNCTION0 /* GBE_LED2/GEVENT10# -> GBE_LED2 */ +#define GPIO_107_SELECT FUNCTION0+NonGpio /* GBE_STAT0/GEVENT11# -> GBE_STAT0 */ +#define GPIO_108_SELECT FUNCTION2 /* USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active */ + /* [option for SPI_TPM_CS# in Hudson-M2 A12)] */ +#define GPIO_109_SELECT FUNCTION0 /* USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & */ + /* USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time */ +#define GPIO_110_SELECT FUNCTION2 /* USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, */ + /* plus judge GPIO40 and GPIO19 level,low is assert. */ + /* LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) */ + /* DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) */ +#define GPIO_111_SELECT FUNCTION1+NonGpio /* USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active */ +#define GPIO_112_SELECT FUNCTION2 /* USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, */ + /* low active, when it's low, BIOS will enbale ODD_PWR */ +#define GPIO_113_SELECT FUNCTION2 /* USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# */ +#define GPIO_114_SELECT FUNCTION2 /* BLINK/USB_OC7#/GEVENT18# -> BLINK */ +#define GPIO_115_SELECT FUNCTION0 /* SYS_RESET#/GEVENT19# -> SYS_RST# */ +#define GPIO_116_SELECT FUNCTION0 /* R_RX1/GEVENT20# -> IR INPUT */ +#define GPIO_117_SELECT FUNCTION1+NonGpio /* SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 */ +#define GPIO_118_SELECT FUNCTION1 /* RI#/GEVENT22# -> LID_CLOSED# */ +#define GPIO_119_SELECT FUNCTION0 /* LPC_SMI#/GEVENT23# -> EC_SMI */ #define GPIO_120_SELECT FUNCTION0+NonGpio #define GPIO_121_SELECT FUNCTION0+NonGpio #define GPIO_122_SELECT FUNCTION0+NonGpio @@ -268,78 +268,78 @@ #define GPIO_159_SELECT FUNCTION0+NonGpio #define GPIO_160_SELECT FUNCTION0+NonGpio -// S5-domain General Purpose I/O -#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# -#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 -#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 -#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 -#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 -#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. -#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, -#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE -#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 -#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# -#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 -#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 -#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO -#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR -#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 -#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 -#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# -#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE -#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE - // option for HDMI CEC signal OW ACTIVE -#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active -#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT -#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA -#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK -#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active - // RESERVED FOR LCD BACKLIGHT PWM -#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL -#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM -#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF -#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD +/* S5-domain General Purpose I/O */ +#define GPIO_161_SELECT FUNCTION0+NonGpio /* ROM_RST# */ +#define GPIO_162_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_163_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_164_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_165_SELECT FUNCTION0+NonGpio /* SPI ROM */ +#define GPIO_166_SELECT FUNCTION1+NonGpio /* GBE_STAT2 */ +#define GPIO_167_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN0 */ +#define GPIO_168_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN1 */ +#define GPIO_169_SELECT FUNCTION0+NonGpio /* AZ_SDATA_IN2 */ +#define GPIO_170_SELECT FUNCTION1+NonGpio /* gating the power control signal for ODD, see BIOS requirements doc for detail. */ +#define GPIO_171_SELECT FUNCTION0+NonGpio /* TEMPIN0, */ +#define GPIO_172_SELECT FUNCTION1 /* used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE */ +#define GPIO_173_SELECT FUNCTION0+NonGpio /* TEMPIN3 */ +#define GPIO_174_SELECT FUNCTION1+NonGpio /* USED AS TALERT# */ +#define GPIO_175_SELECT FUNCTION1 /* WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_176_SELECT FUNCTION1+NonGpio /* WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_177_SELECT FUNCTION2+NonGpio /* WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE */ +#define GPIO_178_SELECT FUNCTION2 /* MEM_1V5 */ +#define GPIO_179_SELECT FUNCTION2 /* MEM_1V35 */ +#define GPIO_180_SELECT FUNCTION0+NonGpio /* Use as VIN VDDIO */ +#define GPIO_181_SELECT FUNCTION0+NonGpio /* Use as VIN VDDR */ +#define GPIO_182_SELECT FUNCTION1+NonGpio /* GBE_LED3 */ +#define GPIO_183_SELECT FUNCTION0+NonGpio /* GBE_LED0 */ +#define GPIO_184_SELECT FUNCTION1+NonGpio /* USED AS LLB# */ +#define GPIO_185_SELECT FUNCTION0+NonGpio /* USED AS USB */ +#define GPIO_186_SELECT FUNCTION0+NonGpio /* USED AS USB */ +#define GPIO_187_SELECT FUNCTION2 /* USED AS AC LED INDICATOR, LOW ACTIVE */ +#define GPIO_188_SELECT FUNCTION2 /* default used AS BATT LED INDICATOR, LOW ACTIVE */ + /* option for HDMI CEC signal OW ACTIVE */ +#define GPIO_189_SELECT FUNCTION1 /* USED AS AC_OK RECIEVER, INPUT, low active */ +#define GPIO_190_SELECT FUNCTION1 /* USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT */ +#define GPIO_191_SELECT FUNCTION0+NonGpio /* TOUCH PAD, DATA */ +#define GPIO_192_SELECT FUNCTION0+NonGpio /* TOUCH PAD, CLK */ +#define GPIO_193_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_194_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_195_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_196_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_197_SELECT FUNCTION2+NonGpio /* Default GPIO for LOM_POWER, high active */ + /* RESERVED FOR LCD BACKLIGHT PWM */ +#define GPIO_198_SELECT FUNCTION0+NonGpio /* IMC SCROLL LED CONTROL */ +#define GPIO_199_SELECT FUNCTION3 /* STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM */ +#define GPIO_200_SELECT FUNCTION2 /* NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF */ +#define GPIO_201_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_202_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_203_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_204_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_205_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_206_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_207_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_208_SELECT FUNCTION0+NonGpio /* KSI */ +#define GPIO_209_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_210_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_211_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_212_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_213_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_214_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_215_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_216_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_217_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_218_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_219_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_220_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_221_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_222_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_223_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_224_SELECT FUNCTION0+NonGpio /* KSO */ +#define GPIO_225_SELECT FUNCTION2+NonGpio /* KSO */ +#define GPIO_226_SELECT FUNCTION2+NonGpio /* KSO */ +#define GPIO_227_SELECT FUNCTION0+NonGpio /* SMBUS CLK, */ +#define GPIO_228_SELECT FUNCTION0+NonGpio /* SMBUS, DATA */ +#define GPIO_229_SELECT FUNCTION0+NonGpio /* DP1_HPD */ #define TYPE_GPI (1 << 5) #define TYPE_GPO (0 << 5) @@ -441,7 +441,7 @@ #define GPIO_94_TYPE TYPE_GPO #define GPIO_95_TYPE TYPE_GPO -// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 +/* GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 */ #define GPIO_96_TYPE TYPE_GPI #define GPIO_97_TYPE TYPE_GPI #define GPIO_98_TYPE TYPE_GPI @@ -753,13 +753,13 @@ #define GPO_169_LEVEL GPO_LOW #define GPO_170_LEVEL GPO_HI #define GPO_171_LEVEL GPO_LOW -#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +#define GPO_172_LEVEL GPO_HI /* FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE */ #define GPO_173_LEVEL GPO_LOW #define GPO_174_LEVEL GPO_LOW #define GPO_175_LEVEL GPO_LOW #define GPO_176_LEVEL GPO_LOW #define GPO_177_LEVEL GPO_LOW -#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU +#define GPO_178_LEVEL GPO_HI /* AMD.SR BU to set VDDIO level to 1.5V for Barb BU */ #define GPO_179_LEVEL GPO_HI #define GPO_180_LEVEL GPO_HI #define GPO_181_LEVEL GPO_LOW @@ -1523,28 +1523,28 @@ #define GEVENT_00_EVENTENABLE EVENT_DISABLE #define GEVENT_01_EVENTENABLE EVENT_DISABLE -#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# -#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# -#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# -#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# +#define GEVENT_02_EVENTENABLE EVENT_ENABLE /* APU THERMTRIP# */ +#define GEVENT_03_EVENTENABLE EVENT_ENABLE /* EC_SCI# */ +#define GEVENT_04_EVENTENABLE EVENT_ENABLE /* APU_MEMHOT# */ +#define GEVENT_05_EVENTENABLE EVENT_ENABLE /* PCIE_EXPCARD_PWREN# */ #define GEVENT_06_EVENTENABLE EVENT_DISABLE #define GEVENT_07_EVENTENABLE EVENT_DISABLE #define GEVENT_08_EVENTENABLE EVENT_DISABLE -#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO +#define GEVENT_09_EVENTENABLE EVENT_ENABLE /* WF_RADIO */ #define GEVENT_10_EVENTENABLE EVENT_DISABLE #define GEVENT_11_EVENTENABLE EVENT_DISABLE -#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# +#define GEVENT_12_EVENTENABLE EVENT_ENABLE /* SMBALERT# */ #define GEVENT_13_EVENTENABLE EVENT_DISABLE -#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# -#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# -#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA -#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN +#define GEVENT_14_EVENTENABLE EVENT_ENABLE /* LASSO_DET#/DOCK# */ +#define GEVENT_15_EVENTENABLE EVENT_ENABLE /* ODD_PLUGIN# */ +#define GEVENT_16_EVENTENABLE EVENT_ENABLE /* ODD_DA */ +#define GEVENT_17_EVENTENABLE EVENT_ENABLE /* TWARN */ #define GEVENT_18_EVENTENABLE EVENT_DISABLE #define GEVENT_19_EVENTENABLE EVENT_DISABLE #define GEVENT_20_EVENTENABLE EVENT_DISABLE #define GEVENT_21_EVENTENABLE EVENT_DISABLE -#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# -#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# +#define GEVENT_22_EVENTENABLE EVENT_ENABLE /* LID_CLOSE# */ +#define GEVENT_23_EVENTENABLE EVENT_DISABLE /* EC_SMI# */ #define SCITRIG_LOW 0 #define SCITRIG_HI 1 @@ -2255,14 +2255,14 @@ typedef enum _GEVENT_COUNT typedef struct _GEVENT_SETTINGS { - u8 EventEnable; // 0: Disable, 1: Enable - u8 SciTrig; // 0: Falling Edge, 1: Rising Edge - u8 SciLevl; // 0: Edge trigger, 1: Level Trigger - u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI - u8 SciS0En; // 0: Disable, 1: Enable - u8 SciMap; // 0000b->1111b - u8 SmiTrig; // 0: Active Low, 1: Active High - u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 + u8 EventEnable; /* 0: Disable, 1: Enable */ + u8 SciTrig; /* 0: Falling Edge, 1: Rising Edge */ + u8 SciLevl; /* 0: Edge trigger, 1: Level Trigger */ + u8 SmiSciEn; /* 0: Not send SMI, 1: Send SMI */ + u8 SciS0En; /* 0: Disable, 1: Enable */ + u8 SciMap; /* 0000b->1111b */ + u8 SmiTrig; /* 0: Active Low, 1: Active High */ + u8 SmiControl; /* 0: Disable, 1: SMI 2: NMI 3: IRQ13 */ } GEVENT_SETTINGS; const GEVENT_SETTINGS gevent_table[] = diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 86339ef..9bd9088 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #define ONE_MB 0x100000 -//#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void); void set_pcie_dereset(void); diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 8091ffb..8aeb250 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -95,7 +94,6 @@ static void *smp_write_config_table(void *v) cpu_flag, cpu_features, cpu_feature_flags ); - //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; @@ -130,7 +128,6 @@ static void *smp_write_config_table(void *v) #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0); /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb900, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb900, 0x1); diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index 0713e41..5009607 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -98,30 +97,19 @@ /** * @section Smbus0BaseAddress */ -// #ifndef SMBUS0_BASE_ADDRESS -// #define SMBUS0_BASE_ADDRESS 0xB00 -// #endif /** * @section Smbus1BaseAddress */ -// #ifndef SMBUS1_BASE_ADDRESS -// #define SMBUS1_BASE_ADDRESS 0xB21 -// #endif /** * @section SioPmeBaseAddress */ -// #ifndef SIO_PME_BASE_ADDRESS -// #define SIO_PME_BASE_ADDRESS 0xE00 -// #endif /** * @section WatchDogTimerBase */ -// #ifndef WATCHDOG_TIMER_BASE_ADDRESS -// #define WATCHDOG_TIMER_BASE_ADDRESS IO_APIC_ADDR -// #endif + /** * @section GecShadowRomAddress @@ -133,58 +121,39 @@ /** * @section SpiRomBaseAddress */ -// #ifndef SPI_BASE_ADDRESS -// #define SPI_BASE_ADDRESS 0xFEC10000 -// #endif /** * @section AcpiPm1EvtBlkAddr */ -// #ifndef PM1_EVT_BLK_ADDRESS -// #define PM1_EVT_BLK_ADDRESS 0x400 -// #endif /** * @section AcpiPm1CntBlkAddr */ -// #ifndef PM1_CNT_BLK_ADDRESS -// #define PM1_CNT_BLK_ADDRESS 0x404 -// #endif + /** * @section AcpiPmTmrBlkAddr */ -// #ifndef PM1_TMR_BLK_ADDRESS -// #define PM1_TMR_BLK_ADDRESS 0x408 -// #endif + /** * @section CpuControlBlkAddr */ -// #ifndef CPU_CNT_BLK_ADDRESS -// #define CPU_CNT_BLK_ADDRESS 0x410 -// #endif + /** * @section AcpiGpe0BlkAddr */ -// #ifndef GPE0_BLK_ADDRESS -// #define GPE0_BLK_ADDRESS 0x420 -// #endif + /** * @section SmiCmdPortAddr */ -// #ifndef SMI_CMD_PORT -// #define SMI_CMD_PORT 0xB0 -// #endif /** * @section AcpiPmaCntBlkAddr */ -// #ifndef ACPI_PMA_CNT_BLK_ADDRESS -// #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -// #endif + /** * @section InChipSataController @@ -1192,7 +1161,7 @@ #define INCHIP_STRESS_RESET_MODE 0 #ifndef SB_PCI_CLOCK_RESERVED - #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F + #define SB_PCI_CLOCK_RESERVED 0x0 /* according to CIMx change 0x1F */ #endif /** @@ -1214,7 +1183,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_cfg); */ u32 sb900_callout_entry(u32 func, u32 data, void* config); -// definition for function in gpio.c +/* definition for function in gpio.c */ void gpioEarlyInit (void); #endif diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 74402bf..e8395fa 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -61,7 +61,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x34); report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); @@ -87,5 +87,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run returned!\n"); - post_code(0x44); // Should never see this post code. + post_code(0x44); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 711a0d5..71af45a 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -135,7 +135,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8 << 8; @@ -153,13 +153,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); /* MXM_GPIO0. GPIO21 */ Status = AGESA_SUCCESS; break; } @@ -170,13 +170,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); /* PCIE_RST#_LAN, GPIO25 */ Status = AGESA_SUCCESS; break; } @@ -187,13 +187,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); /* MPCIE_RST0, GPIO02 */ Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c index 6f4dbfc..5378e2d 100644 --- a/src/mainboard/amd/union_station/OemCustomize.c +++ b/src/mainboard/amd/union_station/OemCustomize.c @@ -52,33 +52,33 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) }, #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), @@ -87,18 +87,18 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + /*PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */ {ConnectorTypeHDMI, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + /*PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ {ConnectorTypeHDMI, Aux2, Hdp2} } }; @@ -110,11 +110,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &DdiList[0] }; - // GNB PCIe topology Porting + /* GNB PCIe topology Porting */ + + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h index 2d8381b..7a9c03f 100644 --- a/src/mainboard/amd/union_station/OptionsIds.h +++ b/src/mainboard/amd/union_station/OptionsIds.h @@ -43,14 +43,6 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - #endif diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h index 001ed16..0e0255e 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h @@ -20,45 +20,45 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT4_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT4_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT5_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT5_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT6_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT6_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT7_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT7_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP Port8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 /* 0:Disable 1:Enable */ +#define GNB_GPP_PORT8_SPEED_MODE 2 /* 0:Auto 1:GEN1 2:GEN2 */ +#define GNB_GPP_PORT8_LINK_ASPM 3 /* 0:Disable 1:L0s 2:L1 3:L0s+L1 */ +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 /* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) */ + /* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) */ +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 /* 0:Disable 1:Basic 3:Enhanced */ -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 38a272d..648212c 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -29,7 +29,6 @@ #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE @@ -74,7 +73,6 @@ #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE @@ -94,10 +92,7 @@ #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE @@ -106,65 +101,23 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 #define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE #define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE @@ -172,8 +125,6 @@ #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY @@ -181,16 +132,6 @@ #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE @@ -249,41 +190,42 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + /* This is the delivery package title, "BrazosPI" */ + /* This string MUST be exactly 8 characters long */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + /* This is the release version number of the AGESA component */ + /* This string MUST be exactly 12 characters long */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /* DDR 400 */ +#define DDR533_FREQUENCY 266 /* DDR 533 */ +#define DDR667_FREQUENCY 333 /* DDR 667 */ +#define DDR800_FREQUENCY 400 /* DDR 800 */ +#define DDR1066_FREQUENCY 533 /* DDR 1066 */ +#define DDR1333_FREQUENCY 667 /* DDR 1333 */ +#define DDR1600_FREQUENCY 800 /* DDR 1600 */ +#define DDR1866_FREQUENCY 933 /* DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /* Highest limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /* Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /* Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters in which there are + * no clearly defined defaults to be used in the common file. The values below are based on product + * and BKDG content, please consult the AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -292,5 +234,5 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data. */ #include "PlatformInstall.h" diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index c24e42c..87572c5 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -83,7 +82,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ + /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index d39a3ab..4e6adb1 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -161,7 +161,6 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A /**

1 0

Patch set updated for coreboot: soc/intel/skylake: Implement Global Reset MEI message
by Rizwan Qureshi 06 Oct '16

06 Oct '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16902 -gerrit commit b0133f9a69e93def021d6a4df381b122112c67e9 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Fri Aug 19 12:33:42 2016 +0530 soc/intel/skylake: Implement Global Reset MEI message As per ME BWG, there are two mechanism to generate a Global Reset (resets both host and Intel ME), one is through CF9h IO write of 6h or Eh with "CF9h Global Reset" (CF9GR) bit set, PMC PCI offset ACh[20]. Another is to issue the Global Reset MEI message. Because any attempts to cause global reset without synchronizing the two sides might cause unwanted side effects, such as unwritten flash data that will get destroyed if the host were to cause a global reset without informing Intel ME firmware, the recommended method is to send a Global Reset MEI message when the following conditions are met: The PCH chipset firmware just needs to complete the Intel ME Interface #1 initialization and check the Intel ME HFSTS state if Intel ME is not in ERROR state and is accepting MEI commands then firmware should be able to use Global Reset MEI message to trigger global reset. Furthermore, if Intel ME is in ERROR state, BIOS can use I/O 0xCF9 write of 0x06 or 0x0E command with PCH ETR3 register bit [20] to perform the global reset. BUG=none BRANCH=none TEST=Verified Global Reset MEI message is able to perform platform global issue in ME good state. Change-Id: If326a137eeadaa695668b76b84c510e12c546024 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 3 +- src/soc/intel/skylake/include/soc/iomap.h | 2 + src/soc/intel/skylake/include/soc/me.h | 66 +++ src/soc/intel/skylake/me.c | 694 ++++++++++++++++++++++++++++++ src/soc/intel/skylake/me_status.c | 324 -------------- 5 files changed, 764 insertions(+), 325 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ccd38ab..bf429ef 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -36,6 +36,7 @@ romstage-y += flash_controller.c romstage-y += gpio.c romstage-y += memmap.c romstage-y += monotonic_timer.c +romstage-y += me.c romstage-y += pch.c romstage-y += pcr.c romstage-y += pei_data.c @@ -59,7 +60,7 @@ ramstage-y += i2c.c ramstage-y += igd.c ramstage-y += irq.c ramstage-y += lpc.c -ramstage-y += me_status.c +ramstage-y += me.c ramstage-y += memmap.c ramstage-y += monotonic_timer.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index feba302..e736d3b 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -56,6 +56,8 @@ #define GPIO_BASE_SIZE 0x10000 +#define HECI1_BASE_ADDRESS 0xfed1a000 + /* * I/O port address space */ diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 423e9d1..b726711 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -21,6 +21,10 @@ /* * Management Engine PCI registers */ +#define PCI_ME_CMDSTS 0x04 +#define ME_CMDSTS_MSE 2 +#define ME_CMDSTS_BME 4 +#define PCI_ME_BAR 0x10 #define PCI_ME_HFSTS1 0x40 #define ME_HFS_CWS_RESET 0 #define ME_HFS_CWS_INIT 1 @@ -177,6 +181,68 @@ struct me_hfs3 { u32 power_down_mitigation: 1; } __attribute__ ((packed)); +/* + * Management Engine MMIO registers + */ +#define MMIO_ME_CB_WW 0x00 +#define MMIO_HOST_CSR 0x04 + +struct host_csr { + u32 int_en: 1; + u32 int_sts: 1; + u32 int_gen: 1; + u32 host_ready: 1; + u32 host_reset: 1; + u32 rsv: 3; + u32 host_read_ptr: 8; + u32 host_write_ptr: 8; + u32 me_cir_depth: 8; +} __attribute__ ((packed)); + +#define MMIO_ME_CB_RW 0x08 +#define MMIO_ME_CSR 0x0C + +struct me_csr { + u32 int_en: 1; + u32 int_sts: 1; + u32 int_gen: 1; + u32 host_ready: 1; + u32 host_reset: 1; + u32 rsv: 3; + u32 me_read_ptr: 8; + u32 me_write_ptr: 8; + u32 me_cir_buff: 8; +} __attribute__ ((packed)); + +#define MMIO_ME_D0I3 0x800 + +/* Reset Request */ +#define MKHI_GLOBAL_RESET 0x0b + +#define GR_ORIGIN_BIOS_MEM_INIT 0x01 +#define GR_ORIGIN_BIOS_POST 0x02 +#define GR_ORIGIN_MEBX 0x03 + +#define GLOBAL_RST_TYPE 0x01 + +#define BIOS_HOST_ADD 0x00 +#define HECI_MKHI_ADD 0x07 + +#define MAX_HECI_MESSAGE 5 +#define HECI_TIMEOUT 15000000 /* 15sec */ +#define HECI_SEND_TIMEOUT 5000000 /* 5sec */ +#define HECI_READ_TIMEOUT 5000000 /* 5sec */ +#define HECI_DELAY 1000 /* 1ms */ + +struct mei_header { + u32 client_address: 8; + u32 host_address: 8; + u32 length: 9; + u32 reserved: 6; + u32 is_complete: 1; +} __attribute__ ((packed)); + void intel_me_status(void); +int send_global_reset(void); #endif diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c new file mode 100644 index 0000000..9819970 --- /dev/null +++ b/src/soc/intel/skylake/me.c @@ -0,0 +1,694 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/me.h> +#include <delay.h> +#include <timer.h> + +static inline void me_read_dword_ptr(void *ptr, int offset) +{ + u32 dword = pci_read_config32(PCH_DEV_ME, offset); + memcpy(ptr, &dword, sizeof(dword)); +} + +static inline void me_write_dword(int offset, u32 value) +{ + pci_write_config32(PCH_DEV_ME, offset, value); +} + +static inline void me_mmio_read_dword_ptr(void *ptr, u16 offset) +{ + u32 dword = read32((void *)(HECI1_BASE_ADDRESS + offset)); + memcpy(ptr, &dword, sizeof(dword)); +} + +static inline void me_mmio_write_dword_ptr(u16 offset, u32 value) +{ + write32((void *)(HECI1_BASE_ADDRESS + offset), value); +} + +/* HFSTS1[3:0] Current Working State Values */ +static const char *me_cws_values[] = { + [ME_HFS_CWS_RESET] = "Reset", + [ME_HFS_CWS_INIT] = "Initializing", + [ME_HFS_CWS_REC] = "Recovery", + [3] = "Unknown (3)", + [4] = "Unknown (4)", + [ME_HFS_CWS_NORMAL] = "Normal", + [ME_HFS_CWS_WAIT] = "Platform Disable Wait", + [ME_HFS_CWS_TRANS] = "OP State Transition", + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", + [9] = "Unknown (9)", + [10] = "Unknown (10)", + [11] = "Unknown (11)", + [12] = "Unknown (12)", + [13] = "Unknown (13)", + [14] = "Unknown (14)", + [15] = "Unknown (15)", +}; + +/* HFSTS1[8:6] Current Operation State Values */ +static const char *me_opstate_values[] = { + [ME_HFS_STATE_PREBOOT] = "Preboot", + [ME_HFS_STATE_M0_UMA] = "M0 with UMA", + [ME_HFS_STATE_M3] = "M3 without UMA", + [ME_HFS_STATE_M0] = "M0 without UMA", + [ME_HFS_STATE_BRINGUP] = "Bring up", + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" +}; + +/* HFSTS1[19:16] Current Operation Mode Values */ +static const char *me_opmode_values[] = { + [ME_HFS_MODE_NORMAL] = "Normal", + [ME_HFS_MODE_DEBUG] = "Debug", + [ME_HFS_MODE_DIS] = "Soft Temporary Disable", + [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" +}; + +/* HFSTS1[15:12] Error Code Values */ +static const char *me_error_values[] = { + [ME_HFS_ERROR_NONE] = "No Error", + [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", + [ME_HFS_ERROR_IMAGE] = "Image Failure", + [ME_HFS_ERROR_DEBUG] = "Debug Failure" +}; + +/* HFSTS2[31:28] ME Progress Code */ +static const char *me_progress_values[] = { + [ME_HFS2_PHASE_ROM] = "ROM Phase", + [1] = "Unknown (1)", + [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", + [ME_HFS2_PHASE_BUP] = "BUP Phase", + [4] = "Unknown (4)", + [5] = "Unknown (5)", + [ME_HFS2_PHASE_HOST_COMM] = "Host Communication", + [7] = "Unknown (7)", + [8] = "Unknown (8)" +}; + +/* HFSTS2[27:24] Power Management Event */ +static const char *me_pmevent_values[] = { + [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = + "Clean Moff->Mx wake", + [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = + "Moff->Mx wake after an error", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = + "Clean global reset", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = + "Global reset after an error", + [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = + "Clean Intel ME reset", + [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = + "Intel ME reset due to exception", + [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = + "Pseudo-global reset", + [ME_HFS2_PMEVENT_CM0_CM3] = + "CM0->CM3", + [ME_HFS2_PMEVENT_CM3_CM0] = + "CM3->CM0", + [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = + "Non-power cycle reset", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = + "Power cycle reset through M3", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = + "Power cycle reset through Moff", + [ME_HFS2_PMEVENT_CMX_CMOFF] = + "Cx/Mx->Cx/Moff", + [ME_HFS2_PMEVENT_CM0_CM0PG] = + "CM0->CM0PG", + [ME_HFS2_PMEVENT_CM3_CM3PG] = + "CM3->CM3PG", + [ME_HFS2_PMEVENT_CM0PG_CM0] = + "CM0PG->CM0" + +}; + +/* Progress Code 0 states */ +static const char *me_progress_rom_values[] = { + [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", + [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" +}; + +/* Progress Code 1 states */ +static const char *me_progress_bup_values[] = { + [ME_HFS2_STATE_BUP_INIT] = + "Initialization starts", + [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = + "Disable the host wake event", + [ME_HFS2_STATE_BUP_CG_ENABLE] = + "Enabling CG for cset", + [ME_HFS2_STATE_BUP_PM_HND_EN] = + "Enabling PM handshaking", + [ME_HFS2_STATE_BUP_FLOW_DET] = + "Flow determination start process", + [ME_HFS2_STATE_BUP_PMC_PATCHING] = + "PMC Patching process", + [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = + "Get VSCC params", + [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = + "Set VSCC params", + [ME_HFS2_STATE_BUP_VSCC_ERR] = + "Error reading/matching the VSCC table in the descriptor", + [ME_HFS2_STATE_BUP_EFSS_INIT] = + "Initialize EFFS", + [ME_HFS2_STATE_BUP_CHECK_STRAP] = + "Check to see if straps say ME DISABLED", + [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = + "Timeout waiting for PWROK", + [ME_HFS2_STATE_BUP_STRAP_DIS] = + "EFFS says ME disabled", + [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = + "Possibly handle BUP manufacturing override strap", + [ME_HFS2_STATE_BUP_M3] = + "Bringup in M3", + [ME_HFS2_STATE_BUP_M0] = + "Bringup in M0", + [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = + "Flow detection error", + [ME_HFS2_STATE_BUP_M3_CLK_ERR] = + "M3 clock switching error", + [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = + "Host error - CPU reset timeout, DID timeout, memory missing", + [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = + "M3 kernel load", + [ME_HFS2_STATE_BUP_T32_MISSING] = + "T34 missing - cannot program ICC", + [ME_HFS2_STATE_BUP_WAIT_DID] = + "Waiting for DID BIOS message", + [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = + "Waiting for DID BIOS message failure", + [ME_HFS2_STATE_BUP_DID_NO_FAIL] = + "DID reported no error", + [ME_HFS2_STATE_BUP_ENABLE_UMA] = + "Enabling UMA", + [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = + "Enabling UMA error", + [ME_HFS2_STATE_BUP_SEND_DID_ACK] = + "Sending DID Ack to BIOS", + [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = + "Sending DID Ack to BIOS error", + [ME_HFS2_STATE_BUP_M0_CLK] = + "Switching clocks in M0", + [ME_HFS2_STATE_BUP_M0_CLK_ERR] = + "Switching clocks in M0 error", + [ME_HFS2_STATE_BUP_TEMP_DIS] = + "ME in temp disable", + [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = + "M0 kernel load", +}; + +void intel_me_status(void) +{ + struct me_hfs _hfs, *hfs = &_hfs; + struct me_hfs2 _hfs2, *hfs2 = &_hfs2; + struct me_hfs3 _hfs3, *hfs3 = &_hfs3; + + me_read_dword_ptr(hfs, PCI_ME_HFSTS1); + me_read_dword_ptr(hfs2, PCI_ME_HFSTS2); + me_read_dword_ptr(hfs3, PCI_ME_HFSTS3); + + /* Check Current States */ + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfs->fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfs->ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfs->fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfs->mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfs->boot_options_present ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfs->update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D3 Support : %s\n", + hfs->d3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", + hfs->d0i3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", + hfs2->low_power_state ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Power Gated : %s\n", + hfs2->power_gating_ind ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfs2->cpu_replaced_sts ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfs2->cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %s\n", + me_cws_values[hfs->working_state]); + printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", + me_opstate_values[hfs->operation_state]); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", + me_opmode_values[hfs->operation_mode]); + printk(BIOS_DEBUG, "ME: Error Code : %s\n", + me_error_values[hfs->error_code]); + printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", + me_progress_values[hfs2->progress_code]); + printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", + me_pmevent_values[hfs2->current_pmevent]); + + printk(BIOS_DEBUG, "ME: Progress Phase State : "); + switch (hfs2->progress_code) { + case ME_HFS2_PHASE_ROM: /* ROM Phase */ + printk(BIOS_DEBUG, "%s", + me_progress_rom_values[hfs2->current_state]); + break; + + case ME_HFS2_PHASE_UKERNEL: /* uKernel Phase */ + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + break; + + case ME_HFS2_PHASE_BUP: /* Bringup Phase */ + if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) + && me_progress_bup_values[hfs2->current_state]) + printk(BIOS_DEBUG, "%s", + me_progress_bup_values[hfs2->current_state]); + else + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + break; + + case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ + if (!hfs2->current_state) + printk(BIOS_DEBUG, "Host communication established"); + else + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + break; + + default: + printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", + hfs2->progress_code, hfs2->current_state); + } + printk(BIOS_DEBUG, "\n"); + + /* Power Down Mitigation Status */ + printk(BIOS_DEBUG, "ME: Power Down Mitigation : %s\n", + hfs3->power_down_mitigation ? "YES" : "NO"); + + if (hfs3->power_down_mitigation) { + printk(BIOS_INFO, "ME: PD Mitigation State : "); + if (hfs3->encrypt_key_override == 1 && + hfs3->encrypt_key_check == 0 && + hfs3->pch_config_change == 0) + printk(BIOS_INFO, "Normal Operation"); + else if (hfs3->encrypt_key_override == 1 && + hfs3->encrypt_key_check == 1 && + hfs3->pch_config_change == 0) + printk(BIOS_INFO, "Issue Detected and Recovered"); + else + printk(BIOS_INFO, "Issue Detected but not Recovered"); + printk(BIOS_INFO, "\n"); + + printk(BIOS_DEBUG, "ME: Encryption Key Override : %s\n", + hfs3->encrypt_key_override ? "Workaround Applied" : + "Unable to override"); + printk(BIOS_DEBUG, "ME: Encryption Key Check : %s\n", + hfs3->encrypt_key_check ? "FAIL" : "PASS"); + printk(BIOS_DEBUG, "ME: PCH Configuration Info : %s\n", + hfs3->pch_config_change ? "Changed" : "No Change"); + + printk(BIOS_DEBUG, "ME: Firmware SKU : "); + switch (hfs3->fw_sku) { + case ME_HFS3_FW_SKU_CONSUMER: + printk(BIOS_DEBUG, "Consumer\n"); + break; + case ME_HFS3_FW_SKU_CORPORATE: + printk(BIOS_DEBUG, "Corporate\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown (0x%x)\n", hfs3->fw_sku); + } + } +} +static int wait_heci_ready(void) +{ + struct stopwatch sw; + int timeout = 0; + struct me_csr _csr, *csr = &_csr; + + stopwatch_init_msecs_expire(&sw, HECI_TIMEOUT); + while (1) { + do { + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + if (csr->host_ready) + return 0; + } while (!(timeout = stopwatch_expired(&sw))); + + if (timeout) { + printk(BIOS_ERR, + "ME_RDY bit is not set after 15 sec"); + return -1; + } + udelay(HECI_DELAY); + } +} + +static int wait_heci_cb_avail(int len) +{ + struct stopwatch sw; + int timeout = 0; + struct host_csr _csr, *csr = &_csr; + + me_mmio_read_dword_ptr(csr, MMIO_HOST_CSR); + /* + * if timeout has happened, return failure as + * the circular buffer is not empty + */ + stopwatch_init_msecs_expire(&sw, HECI_SEND_TIMEOUT); + /* Must have room for message and message header */ + while (len > (csr->me_cir_depth - (csr->host_write_ptr - + csr->host_read_ptr))) { + timeout = stopwatch_expired(&sw); + + if (timeout) { + printk(BIOS_ERR, + "Circular Buffer never emptied within 5 sec"); + return -1; + } + /* wait before trying again */ + udelay(HECI_DELAY); + /* read HOST_CSR for next iteration */ + me_mmio_read_dword_ptr(csr, MMIO_HOST_CSR); + } + return 0; +} + +static int send_heci_packet(struct mei_header *head, u32 *payload) +{ + /* compute the message length in dwords */ + int len = (head->length + 3) / 4; + int sts; + int index; + struct me_csr _csr, *csr = &_csr; + struct host_csr _hcsr, *hcsr = &_hcsr; + + /* + * wait until there is sufficient room in CB + */ + sts = wait_heci_cb_avail(len+1); + if (sts != 0) + return -1; + + /* Write message header */ + me_mmio_write_dword_ptr(MMIO_ME_CB_WW, *(u32 *) head); + + /* Write message body */ + for (index = 0; index < len; index++) + me_mmio_write_dword_ptr(MMIO_ME_CB_WW, payload[index]); + + /* Set Interrupt Generate bit */ + me_mmio_read_dword_ptr(hcsr, MMIO_HOST_CSR); + hcsr->int_gen = 1; + me_mmio_write_dword_ptr(MMIO_HOST_CSR, *(u32 *) hcsr); + + /* Check if ME Ready bit is set, if set to 0 then return fatal error */ + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + if (csr->host_ready) + return 0; + else + return -1; +} + +static int recv_heci_packet(struct mei_header *head, u32 *packet, + u32 *packet_size) +{ + struct me_csr _csr, *csr = &_csr; + struct host_csr _hcsr, *hcsr = &_hcsr; + int rec_msg = 0; + struct stopwatch sw; + int timeout = 0; + u32 length, index; + + /* Clear Interrupt Status bit */ + me_mmio_read_dword_ptr(hcsr, MMIO_HOST_CSR); + hcsr->int_sts = 1; + me_mmio_write_dword_ptr(MMIO_HOST_CSR, *(u32 *) hcsr); + + /* Check if circular buffer overflow */ + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + /* if yes then return fatal error */ + if ((csr->me_write_ptr - csr->me_read_ptr) > csr->me_cir_buff) + return -1; + /* + * if timeout has happened, return failure as + * the circular buffer is not empty + */ + stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); + /* go until we got message pkt */ + do { + timeout = stopwatch_expired(&sw); + + if (timeout) { + printk(BIOS_ERR, + "Circular Buffer not filled within 5 sec"); + *packet_size = 0; + return -1; + } + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + /* Read one message from HECI buffer */ + if ((csr->me_write_ptr - csr->me_read_ptr) > 0) { + me_mmio_read_dword_ptr(head, MMIO_ME_CB_RW); + /* calculate the message length in dword */ + length = ((head->length + 3) / 4); + if (head->length == 0) { + *packet_size = 0; + goto SET_IG; + } + /* Make sure, we have enough space to catch all */ + if (head->length <= *packet_size) { + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + /* get complete message into circular buffer */ + while (length > (csr->me_write_ptr - + csr->me_read_ptr)) { + udelay(HECI_DELAY); + me_mmio_read_dword_ptr(csr, + MMIO_ME_CSR); + } + /* here is the message */ + for (index = 0; index < length; index++) { + packet[index] = read32( + (void *)(HECI1_BASE_ADDRESS + + MMIO_ME_CB_RW)); + } + rec_msg = 1; + *packet_size = head->length; + } else { + /* Too small buffer */ + *packet_size = 0; + return -1; + } + } + udelay(HECI_DELAY); + } while (!rec_msg); + + /* + * Check if ME Ready bit is set, if set to 0 then return fatal error + * because ME might have reset during transaction and we might have + * read a junk data from CB + */ + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + if (!(csr->host_ready)) + return -1; +SET_IG: + /* Set Interrupt Generate bit */ + me_mmio_read_dword_ptr(hcsr, MMIO_HOST_CSR); + hcsr->int_gen = 1; + me_mmio_write_dword_ptr(MMIO_HOST_CSR, *(u32 *) hcsr); + return 0; +} + +static int +send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress) +{ + u8 retry; + int status = -1; + u32 cir_buff_depth; + struct host_csr _csr, *csr = &_csr; + struct mei_header head; + int cur = 0; + u32 slength; + + for (retry = 0; retry < MAX_HECI_MESSAGE; retry++) { + if (wait_heci_ready() != 0) + continue; + /* HECI is ready */ + me_mmio_read_dword_ptr(csr, MMIO_HOST_CSR); + cir_buff_depth = csr->me_cir_depth; + head.client_address = clientaddress; + head.host_address = hostaddress; + while (len > cur) { + /* + * Set the message complete bit if this is last packet + * in message needs to be "less than" to account for + * the header OR needs to be exact equal to CB depth + */ + if (((((len - cur) + 3) / 4) < cir_buff_depth) || + (((((len - cur) + 3) / 4) == + cir_buff_depth) && + ((((len - cur) + 3) % 4) == 0))) + head.is_complete = 1; + else + head.is_complete = 0; + /* + * calculate length for message header + * header length = smaller of CB buffer or + * remaining message + */ + slength = ((cir_buff_depth <= (((len - cur) + 3) / 4)) + ? ((cir_buff_depth - 1) * 4) + : (len - cur)); + head.length = slength; + head.reserved = 0; + /* + * send the current packet + * (cur should be treated as index for message) + */ + status = send_heci_packet(&head, (u32 *) msg); + if (status != 0) + break; + /* update the length information */ + cur += slength; + msg += cur; + } + if (status != 0) + continue; + else + return status; + } + return status; +} + +static int +recv_heci_message(u32 *message, u32 *message_size) +{ + struct mei_header head; + int cur = 0; + u8 retry; + int status = -1; + int msg_complete = 0; + u32 pkt_buff; + + for (retry = 0; retry < MAX_HECI_MESSAGE; retry++) { + if (wait_heci_ready() != 0) + continue; + /* HECI is ready */ + while ((cur < *message_size) && (msg_complete == 0)) { + pkt_buff = *message_size - cur; + status = recv_heci_packet(&head, message + (cur >> 2), + &pkt_buff); + if (status == -1) { + *message_size = 0; + break; + } + msg_complete = head.is_complete; + if (pkt_buff == 0) { + /* if not in middle of msg and msg complete bit + * is set then this is a valid zero length msg + */ + if ((cur == 0) && (msg_complete == 1)) + status = 0; + else + status = -1; + *message_size = 0; + break; + } + cur += pkt_buff; + } + if (status != 0) + continue; + else { + *message_size = cur; + break; + } + } + return status; +} + +static int send_heci_reset_message(void) +{ + int status; + struct reset_reply { + u8 group_id; + u8 command; + u8 reserved; + u8 result; + } __attribute__ ((packed)) reply; + struct reset_message { + u8 group_id; + u8 cmd; + u8 reserved; + u8 result; + u8 req_origin; + u8 reset_type; + } __attribute__ ((packed)) msg = { + 0, MKHI_GLOBAL_RESET, 0, 0, + GR_ORIGIN_BIOS_POST, GLOBAL_RST_TYPE}; + u32 reply_size; + + status = send_heci_message((u8 *) &msg, sizeof(msg), + BIOS_HOST_ADD, HECI_MKHI_ADD); + if (status != 0) + return -1; + + reply_size = sizeof(reply); + if (recv_heci_message((u32 *) &reply, &reply_size) == -1) + return -1; + /* get reply result from HECI MSG */ + if (reply.result != 0) { + printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); + return -1; + } else { + printk(BIOS_DEBUG, "%s: Exit with Success\n", __func__); + return 0; + } +} + +int send_global_reset(void) +{ + u32 heci1_bar; + u32 heci1_cmdsts; + int status = -1; + struct me_hfs _hfs, *hfs = &_hfs; + + /* Check HECI1 BAR gets programmed */ + me_read_dword_ptr(&heci1_bar, PCI_ME_BAR); + heci1_bar &= ~0xfff; + if (heci1_bar != HECI1_BASE_ADDRESS) { + /* use default HECI BAR for SoC */ + me_write_dword(PCI_ME_BAR, HECI1_BASE_ADDRESS); + } + /* Check MMIO space & Bus master enabled */ + me_read_dword_ptr(&heci1_cmdsts, PCI_ME_CMDSTS); + if ((heci1_cmdsts & (ME_CMDSTS_MSE | ME_CMDSTS_BME)) != + (ME_CMDSTS_MSE | ME_CMDSTS_BME)) { + me_write_dword(PCI_ME_CMDSTS, ME_CMDSTS_MSE | ME_CMDSTS_BME); + } + /* Check ME operating mode */ + me_read_dword_ptr(hfs, PCI_ME_HFSTS1); + if (hfs->operation_mode) + goto ret; + + /* ME should be in Normal Mode for this command */ + status = send_heci_reset_message(); +ret: + return status; +} diff --git a/src/soc/intel/skylake/me_status.c b/src/soc/intel/skylake/me_status.c deleted file mode 100644 index 79d4dfb..0000000 --- a/src/soc/intel/skylake/me_status.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <stdlib.h> -#include <string.h> -#include <soc/pci_devs.h> -#include <soc/me.h> -#include <delay.h> - -static inline void me_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = pci_read_config32(PCH_DEV_ME, offset); - memcpy(ptr, &dword, sizeof(dword)); -} - -/* HFSTS1[3:0] Current Working State Values */ -static const char *me_cws_values[] = { - [ME_HFS_CWS_RESET] = "Reset", - [ME_HFS_CWS_INIT] = "Initializing", - [ME_HFS_CWS_REC] = "Recovery", - [3] = "Unknown (3)", - [4] = "Unknown (4)", - [ME_HFS_CWS_NORMAL] = "Normal", - [ME_HFS_CWS_WAIT] = "Platform Disable Wait", - [ME_HFS_CWS_TRANS] = "OP State Transition", - [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", - [9] = "Unknown (9)", - [10] = "Unknown (10)", - [11] = "Unknown (11)", - [12] = "Unknown (12)", - [13] = "Unknown (13)", - [14] = "Unknown (14)", - [15] = "Unknown (15)", -}; - -/* HFSTS1[8:6] Current Operation State Values */ -static const char *me_opstate_values[] = { - [ME_HFS_STATE_PREBOOT] = "Preboot", - [ME_HFS_STATE_M0_UMA] = "M0 with UMA", - [ME_HFS_STATE_M3] = "M3 without UMA", - [ME_HFS_STATE_M0] = "M0 without UMA", - [ME_HFS_STATE_BRINGUP] = "Bring up", - [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" -}; - -/* HFSTS1[19:16] Current Operation Mode Values */ -static const char *me_opmode_values[] = { - [ME_HFS_MODE_NORMAL] = "Normal", - [ME_HFS_MODE_DEBUG] = "Debug", - [ME_HFS_MODE_DIS] = "Soft Temporary Disable", - [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", - [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" -}; - -/* HFSTS1[15:12] Error Code Values */ -static const char *me_error_values[] = { - [ME_HFS_ERROR_NONE] = "No Error", - [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", - [ME_HFS_ERROR_IMAGE] = "Image Failure", - [ME_HFS_ERROR_DEBUG] = "Debug Failure" -}; - -/* HFSTS2[31:28] ME Progress Code */ -static const char *me_progress_values[] = { - [ME_HFS2_PHASE_ROM] = "ROM Phase", - [1] = "Unknown (1)", - [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", - [ME_HFS2_PHASE_BUP] = "BUP Phase", - [4] = "Unknown (4)", - [5] = "Unknown (5)", - [ME_HFS2_PHASE_HOST_COMM] = "Host Communication", - [7] = "Unknown (7)", - [8] = "Unknown (8)" -}; - -/* HFSTS2[27:24] Power Management Event */ -static const char *me_pmevent_values[] = { - [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = - "Clean Moff->Mx wake", - [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = - "Moff->Mx wake after an error", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = - "Clean global reset", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = - "Global reset after an error", - [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = - "Clean Intel ME reset", - [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = - "Intel ME reset due to exception", - [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = - "Pseudo-global reset", - [ME_HFS2_PMEVENT_CM0_CM3] = - "CM0->CM3", - [ME_HFS2_PMEVENT_CM3_CM0] = - "CM3->CM0", - [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = - "Non-power cycle reset", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = - "Power cycle reset through M3", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = - "Power cycle reset through Moff", - [ME_HFS2_PMEVENT_CMX_CMOFF] = - "Cx/Mx->Cx/Moff", - [ME_HFS2_PMEVENT_CM0_CM0PG] = - "CM0->CM0PG", - [ME_HFS2_PMEVENT_CM3_CM3PG] = - "CM3->CM3PG", - [ME_HFS2_PMEVENT_CM0PG_CM0] = - "CM0PG->CM0" - -}; - -/* Progress Code 0 states */ -static const char *me_progress_rom_values[] = { - [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", - [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" -}; - -/* Progress Code 1 states */ -static const char *me_progress_bup_values[] = { - [ME_HFS2_STATE_BUP_INIT] = - "Initialization starts", - [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = - "Disable the host wake event", - [ME_HFS2_STATE_BUP_CG_ENABLE] = - "Enabling CG for cset", - [ME_HFS2_STATE_BUP_PM_HND_EN] = - "Enabling PM handshaking", - [ME_HFS2_STATE_BUP_FLOW_DET] = - "Flow determination start process", - [ME_HFS2_STATE_BUP_PMC_PATCHING] = - "PMC Patching process", - [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = - "Get VSCC params", - [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = - "Set VSCC params", - [ME_HFS2_STATE_BUP_VSCC_ERR] = - "Error reading/matching the VSCC table in the descriptor", - [ME_HFS2_STATE_BUP_EFSS_INIT] = - "Initialize EFFS", - [ME_HFS2_STATE_BUP_CHECK_STRAP] = - "Check to see if straps say ME DISABLED", - [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = - "Timeout waiting for PWROK", - [ME_HFS2_STATE_BUP_STRAP_DIS] = - "EFFS says ME disabled", - [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = - "Possibly handle BUP manufacturing override strap", - [ME_HFS2_STATE_BUP_M3] = - "Bringup in M3", - [ME_HFS2_STATE_BUP_M0] = - "Bringup in M0", - [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = - "Flow detection error", - [ME_HFS2_STATE_BUP_M3_CLK_ERR] = - "M3 clock switching error", - [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = - "Host error - CPU reset timeout, DID timeout, memory missing", - [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = - "M3 kernel load", - [ME_HFS2_STATE_BUP_T32_MISSING] = - "T34 missing - cannot program ICC", - [ME_HFS2_STATE_BUP_WAIT_DID] = - "Waiting for DID BIOS message", - [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = - "Waiting for DID BIOS message failure", - [ME_HFS2_STATE_BUP_DID_NO_FAIL] = - "DID reported no error", - [ME_HFS2_STATE_BUP_ENABLE_UMA] = - "Enabling UMA", - [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = - "Enabling UMA error", - [ME_HFS2_STATE_BUP_SEND_DID_ACK] = - "Sending DID Ack to BIOS", - [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = - "Sending DID Ack to BIOS error", - [ME_HFS2_STATE_BUP_M0_CLK] = - "Switching clocks in M0", - [ME_HFS2_STATE_BUP_M0_CLK_ERR] = - "Switching clocks in M0 error", - [ME_HFS2_STATE_BUP_TEMP_DIS] = - "ME in temp disable", - [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = - "M0 kernel load", -}; - -void intel_me_status(void) -{ - struct me_hfs _hfs, *hfs = &_hfs; - struct me_hfs2 _hfs2, *hfs2 = &_hfs2; - struct me_hfs3 _hfs3, *hfs3 = &_hfs3; - - me_read_dword_ptr(hfs, PCI_ME_HFSTS1); - me_read_dword_ptr(hfs2, PCI_ME_HFSTS2); - me_read_dword_ptr(hfs3, PCI_ME_HFSTS3); - - /* Check Current States */ - printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfs->fpt_bad ? "BAD" : "OK"); - printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfs->ft_bup_ld_flr ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfs->fw_init_complete ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfs->mfg_mode ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfs->boot_options_present ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfs->update_in_progress ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: D3 Support : %s\n", - hfs->d3_support_valid ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", - hfs->d0i3_support_valid ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", - hfs2->low_power_state ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Power Gated : %s\n", - hfs2->power_gating_ind ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", - hfs2->cpu_replaced_sts ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", - hfs2->cpu_replaced_valid ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - me_cws_values[hfs->working_state]); - printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - me_opstate_values[hfs->operation_state]); - printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - me_opmode_values[hfs->operation_mode]); - printk(BIOS_DEBUG, "ME: Error Code : %s\n", - me_error_values[hfs->error_code]); - printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - me_progress_values[hfs2->progress_code]); - printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - me_pmevent_values[hfs2->current_pmevent]); - - printk(BIOS_DEBUG, "ME: Progress Phase State : "); - switch (hfs2->progress_code) { - case ME_HFS2_PHASE_ROM: /* ROM Phase */ - printk(BIOS_DEBUG, "%s", - me_progress_rom_values[hfs2->current_state]); - break; - - case ME_HFS2_PHASE_UKERNEL: /* uKernel Phase */ - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - case ME_HFS2_PHASE_BUP: /* Bringup Phase */ - if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) - && me_progress_bup_values[hfs2->current_state]) - printk(BIOS_DEBUG, "%s", - me_progress_bup_values[hfs2->current_state]); - else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ - if (!hfs2->current_state) - printk(BIOS_DEBUG, "Host communication established"); - else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - default: - printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", - hfs2->progress_code, hfs2->current_state); - } - printk(BIOS_DEBUG, "\n"); - - /* Power Down Mitigation Status */ - printk(BIOS_DEBUG, "ME: Power Down Mitigation : %s\n", - hfs3->power_down_mitigation ? "YES" : "NO"); - - if (hfs3->power_down_mitigation) { - printk(BIOS_INFO, "ME: PD Mitigation State : "); - if (hfs3->encrypt_key_override == 1 && - hfs3->encrypt_key_check == 0 && - hfs3->pch_config_change == 0) - printk(BIOS_INFO, "Normal Operation"); - else if (hfs3->encrypt_key_override == 1 && - hfs3->encrypt_key_check == 1 && - hfs3->pch_config_change == 0) - printk(BIOS_INFO, "Issue Detected and Recovered"); - else - printk(BIOS_INFO, "Issue Detected but not Recovered"); - printk(BIOS_INFO, "\n"); - - printk(BIOS_DEBUG, "ME: Encryption Key Override : %s\n", - hfs3->encrypt_key_override ? "Workaround Applied" : - "Unable to override"); - printk(BIOS_DEBUG, "ME: Encryption Key Check : %s\n", - hfs3->encrypt_key_check ? "FAIL" : "PASS"); - printk(BIOS_DEBUG, "ME: PCH Configuration Info : %s\n", - hfs3->pch_config_change ? "Changed" : "No Change"); - - printk(BIOS_DEBUG, "ME: Firmware SKU : "); - switch (hfs3->fw_sku) { - case ME_HFS3_FW_SKU_CONSUMER: - printk(BIOS_DEBUG, "Consumer\n"); - break; - case ME_HFS3_FW_SKU_CORPORATE: - printk(BIOS_DEBUG, "Corporate\n"); - break; - default: - printk(BIOS_DEBUG, "Unknown (0x%x)\n", hfs3->fw_sku); - } - } -}

1 0

New patch to review for coreboot: drivers/intel/wifi: Add depends on ARCH_X86
by Martin Roth 06 Oct '16

06 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16906 -gerrit commit bec3c86d15c129f2109afa1f1454e425ed60e434 Author: Martin Roth <martinroth(a)google.com> Date: Thu Oct 6 10:27:59 2016 -0600 drivers/intel/wifi: Add depends on ARCH_X86 When compiling a non-x86 platform with DRIVERS_INTEL_WIFI enabled, we get the build error: src/drivers/intel/wifi/wifi.c:17:30: fatal error: arch/acpi_device.h: No such file or directory acpi_device.h only exists in the x86 architecture directory. Change-Id: Id0e29558336bf44e638cfcb97c22f31683ea4ec7 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/drivers/intel/wifi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 40a8528..330de6c 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -1,5 +1,6 @@ config DRIVERS_INTEL_WIFI bool "Support Intel PCI-e WiFi adapters" + depends on ARCH_X86 default y if PCIEXP_PLUGIN_SUPPORT help When enabled, add identifiers in ACPI and SMBIOS tables to

1 0

Patch set updated for coreboot: google/gru: set W2W_DIFFCS_DLY to 5
by Patrick Georgi 06 Oct '16

06 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16721 -gerrit commit 98cc669821e6b9b9fe50d81ebebeda417afc13b9 Author: Lin Huang <hl(a)rock-chips.com> Date: Wed Sep 21 17:05:43 2016 +0800 google/gru: set W2W_DIFFCS_DLY to 5 PHY_PER_CS_TRAINING is being when DDR frequency >= 666. For per cs training, the controller should consider the PHY delay line switch time and there should be more cycles to switch the delay line, so update the W2W_DIFFCS_DLY_ value from 0x1 to 0x5. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: I00df2d4724b0b77f3e7565809fb35bbd2ff01ea5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c135ea3e33d810ed322d947eb8d512d1ac119cfc Original-Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387506 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c | 4 ++-- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c | 4 ++-- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 4 ++-- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 6 +++--- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c index c877158..5330141 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x05050502, /* DENALI_CTL_215_DATA */ 0x02080808, /* DENALI_CTL_216_DATA */ 0x02050202, /* DENALI_CTL_217_DATA */ - 0x02010202, /* DENALI_CTL_218_DATA */ - 0x00010202, /* DENALI_CTL_219_DATA */ + 0x02050202, /* DENALI_CTL_218_DATA */ + 0x00050202, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x02010200, /* DENALI_CTL_221_DATA */ 0x00010201, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c index 591924d..4b73cb0 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x08080803, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ 0x02050203, /* DENALI_CTL_217_DATA */ - 0x02010303, /* DENALI_CTL_218_DATA */ - 0x00010203, /* DENALI_CTL_219_DATA */ + 0x02050303, /* DENALI_CTL_218_DATA */ + 0x00050203, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x03020400, /* DENALI_CTL_221_DATA */ 0x00020401, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index b738644..3056e55 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x0a0a0a03, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ 0x02050103, /* DENALI_CTL_217_DATA */ - 0x02010103, /* DENALI_CTL_218_DATA */ - 0x00010103, /* DENALI_CTL_219_DATA */ + 0x02050103, /* DENALI_CTL_218_DATA */ + 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x03020500, /* DENALI_CTL_221_DATA */ 0x00020501, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index 362489b..3947881 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -278,9 +278,9 @@ struct rk3399_sdram_params params = { 0x04040001, /* DENALI_CTL_214_DATA */ 0x0c0c0c04, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ - 0x02010103, /* DENALI_CTL_217_DATA */ - 0x02010103, /* DENALI_CTL_218_DATA */ - 0x00010103, /* DENALI_CTL_219_DATA */ + 0x02050103, /* DENALI_CTL_217_DATA */ + 0x02050103, /* DENALI_CTL_218_DATA */ + 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x06030600, /* DENALI_CTL_221_DATA */ 0x00030603, /* DENALI_CTL_222_DATA */

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coreboot-gerrit October 2016