coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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1281 discussions

Patch set updated for coreboot: soc/intel/apollolake:Implement stage cache to improve resume time
by Brandon Breitenstein 05 Oct '16

05 Oct '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16833 -gerrit commit 91786a38dbf561b22327f333c080d33761bec40c Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Sep 30 13:57:12 2016 -0700 soc/intel/apollolake:Implement stage cache to improve resume time This patch enables stage cache to save some time during resume. It saves ramstage in the stage cache and restores it on resume so that it does not have to reinitialize ramstage during the resume flow. Stage cache functionality is added to postcar stage since ramstage is called from postcar. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for Reef and tested ramstage being cached Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/lib/Makefile.inc | 1 + src/soc/intel/apollolake/Kconfig | 11 ++++++++++- src/soc/intel/apollolake/cpu.c | 8 ++++++-- src/soc/intel/apollolake/include/soc/smm.h | 4 +--- src/soc/intel/apollolake/memmap.c | 30 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/romstage.c | 17 +++++++++++++++++ 6 files changed, 65 insertions(+), 6 deletions(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 394491c..67f8364 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -159,6 +159,7 @@ ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y) ramstage-y += ext_stage_cache.c romstage-y += ext_stage_cache.c +postcar-y += ext_stage_cache.c else ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3a23dbd..2edebf6 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS select COMMON_FADT select GENERIC_GPIO_LIB @@ -34,7 +35,7 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE - select NO_STAGE_CACHE + # select NO_STAGE_CACHE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PCIEXP_ASPM @@ -254,4 +255,12 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n +config SMM_RESERVED_SIZE + hex + default 0x100000 + +config SMM_TSEG_SIZE + hex + default 0x800000 + endif diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f3cf050..e67842c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -102,19 +102,23 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, { void *smm_base; size_t smm_size; + void *handler_base; + size_t handler_size; /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ smm_region(&smm_base, &smm_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; + *perm_smbase = (uintptr_t)handler_base; + *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h index 7a9846e..740d02b 100644 --- a/src/soc/intel/apollolake/include/soc/smm.h +++ b/src/soc/intel/apollolake/include/soc/smm.h @@ -20,6 +20,7 @@ #include <stdint.h> #include <soc/gpio.h> +#include <fsp/memmap.h> /* These helpers are for performing SMM relocation. */ void southbridge_clear_smi_status(void); @@ -35,7 +36,4 @@ void southbridge_smm_enable_smi(void); /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts); -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); #endif diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index ea6f447..7436492 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -52,3 +52,33 @@ void smm_region(void **start, size_t *size) *start = (void *)smm_region_start(); *size = smm_region_size(); } + +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} + diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..4eaf0d6 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/northbridge.h> @@ -135,6 +136,22 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, + MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); }

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Patch set updated for coreboot: Update build-release script
by Martin Roth 05 Oct '16

05 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16883 -gerrit commit 6b430b0847a49eb91fe87ab278f2624cf432ef1e Author: Martin Roth <martinroth(a)google.com> Date: Tue Oct 4 16:45:17 2016 -0600 Update build-release script - Add more help text. - Remove braces from variables where the variable is isolated. - Remove --recurse-submodules from clone. This breaks on old coreboot versions. - Add some whitespace between blocks. - Fix all shellcheck warnings. - Verify tar version and fail if it doesn't support --sort. Change-Id: I4a49df99532d9a92a4a05bceff16f96a4fc3e205 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/release/build-release | 56 ++++++++++++++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/util/release/build-release b/util/release/build-release index 11e7177..20fbfb6 100755 --- a/util/release/build-release +++ b/util/release/build-release @@ -3,10 +3,10 @@ # ${GPG_KEY_ID}: gpg key id (if not don't sign) # ${USERNAME}: username (if not default to https) # ${COMMIT_ID}: commit id (if not master) -VERSION_NAME=${1} -COMMIT_ID=${2} -USERNAME=${3} -GPG_KEY_ID=${4} +VERSION_NAME=$1 +COMMIT_ID=$2 +USERNAME=$3 +GPG_KEY_ID=$4 set -e @@ -16,32 +16,50 @@ LANG=C TZ=UTC export LC_ALL LANG TZ -if [ -z "${VERSION_NAME}" ] || [ "${VERSION_NAME}" = "--help" ]; then +if [ -z "$VERSION_NAME" ] || [ "$VERSION_NAME" = "--help" ]; then echo "usage: $0 <version> [commit id] [gpg key id] [username]" - echo "tags a new coreboot version and creates a tar archive" + echo "Tags a new coreboot version and creates a tar archive" + echo + echo "version: New version name to tag the tree with" + echo "commit id: check out this commit-id after cloning the coreboot tree" + echo "gpg key id: used to tag the version, and generate a gpg signature" + echo "username: clone the tree using ssh://USERNAME - defaults to https://" exit 1 fi + +# Verify that tar supports --sort +if ! tar --sort=name -cf /dev/null /dev/null 2>/dev/null ; then + echo "Error: The installed version of tar does not support --sort" + echo " GNU tar version 1.28 or greater is required. Exiting." + exit 1 +fi + if [ -n "${USERNAME}" ]; then - git clone --recurse-submodules ssh://${USERNAME}@review.coreboot.org:29418/coreboot.git coreboot-${VERSION_NAME} + git clone "ssh://${USERNAME}@review.coreboot.org:29418/coreboot.git" "coreboot-${VERSION_NAME}" else - git clone --recurse-submodules https://review.coreboot.org/coreboot.git coreboot-${VERSION_NAME} + git clone https://review.coreboot.org/coreboot.git "coreboot-${VERSION_NAME}" fi -cd coreboot-${VERSION_NAME} -if [ -n "${COMMIT_ID}" ]; then - git reset --hard ${COMMIT_ID} + +cd "coreboot-${VERSION_NAME}" || exit 1 +if [ -n "$COMMIT_ID" ]; then + git reset --hard "$COMMIT_ID" fi + git submodule update --init --checkout -if [ -n "${GPG_KEY_ID}" ]; then - git tag -a -s -u ${GPG_KEY_ID} --force ${VERSION_NAME} -m "coreboot version ${VERSION_NAME}" +if [ -n "$GPG_KEY_ID" ]; then + git tag -a -s -u "$GPG_KEY_ID" --force "$VERSION_NAME" -m "coreboot version $VERSION_NAME" else - git tag -a --force ${VERSION_NAME} -m "coreboot version ${VERSION_NAME}" + git tag -a --force "$VERSION_NAME" -m "coreboot version $VERSION_NAME" fi -printf "${VERSION_NAME}-$(git log --pretty=%H|head -1)\n" > .coreboot-version + +printf "%s-%s\n" "$VERSION_NAME" "$(git log --pretty=%H|head -1)" > .coreboot-version tstamp=$(git log --pretty=format:%ci -1) cd .. -tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs --exclude=coreboot-${VERSION_NAME}/3rdparty/blobs -cvf - coreboot-${VERSION_NAME} |xz -9 > coreboot-${VERSION_NAME}.tar.xz -tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs -cvf - coreboot-${VERSION_NAME}/3rdparty/blobs |xz -9 > coreboot-blobs-${VERSION_NAME}.tar.xz + +tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs --exclude="coreboot-${VERSION_NAME}/3rdparty/blobs" -cvf - "coreboot-${VERSION_NAME}" |xz -9 > "coreboot-${VERSION_NAME}.tar.xz" +tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs -cvf - "coreboot-${VERSION_NAME}/3rdparty/blobs" |xz -9 > "coreboot-blobs-${VERSION_NAME}.tar.xz" + if [ -n "${GPG_KEY_ID}" ]; then - gpg2 --armor --local-user ${GPG_KEY_ID} --output coreboot-${VERSION_NAME}.tar.xz.sig --detach-sig coreboot-${VERSION_NAME}.tar.xz - gpg2 --armor --local-user ${GPG_KEY_ID} --output coreboot-blobs-${VERSION_NAME}.tar.xz.sig --detach-sig coreboot-blobs-${VERSION_NAME}.tar.xz + gpg2 --armor --local-user "$GPG_KEY_ID" --output "coreboot-${VERSION_NAME}.tar.xz.sig" --detach-sig "coreboot-${VERSION_NAME}.tar.xz" + gpg2 --armor --local-user "$GPG_KEY_ID" --output "coreboot-blobs-${VERSION_NAME}.tar.xz.sig" --detach-sig "coreboot-blobs-${VERSION_NAME}.tar.xz" fi

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New patch to review for coreboot: northbridge/amd/agesa/family14: Remove commented code
by HAOUAS Elyes 05 Oct '16

05 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16895 -gerrit commit e3129c34ab798284bec77c1853538fb2df64c26b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 19:41:12 2016 +0200 northbridge/amd/agesa/family14: Remove commented code Change-Id: I04fe6b7a8798d0f3cb54130283ce5a50eb9ac5b4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 34 ---------------------- src/northbridge/amd/agesa/family14/northbridge.c | 27 ----------------- 2 files changed, 61 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index dda6bf9..0e588ad 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -84,34 +84,11 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, #if !defined(__PRE_RAM__) static u32 get_io_addr_index(u32 nodeid, u32 linkn) { -#if 0 - u32 index; - - for (index = 0; index < 256; index++) { - if (sysconf.conf_io_addrx[index+4] == 0) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f); - sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); - return index; - } - } -#endif return 0; } static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) { -#if 0 - u32 index; - - for (index = 0; index < 64; index++) { - if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f); - sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); - return index; - } - } -#endif - return 0; } @@ -125,17 +102,6 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, pci_write_config32(__f1_dev[0], reg+4, tempreg); tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? -#if 0 - // FIXME: can we use VGA reg instead? - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", - __func__, dev_path(dev), link); - tempreg |= PCI_IO_BASE_VGA_EN; - } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { - tempreg |= PCI_IO_BASE_NO_ISA; - } -#endif pci_write_config32(__f1_dev[0], reg, tempreg); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 4f10564..21978f6 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -36,7 +36,6 @@ #include <sb_cimx.h> #endif -//#define FX_DEVS NODE_NUMS #define FX_DEVS 1 static device_t __f0_dev[FX_DEVS]; @@ -280,32 +279,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) mem_hole.node_id = 0; // record the node No with hole } } -#if 0 - /* We need to double check if there is special set on base reg and limit reg - * are not continuous instead of hole, it will find out its hole_startk. - */ - if (mem_hole.node_id == -1) { - resource_t limitk_pri = 0; - struct dram_base_mask_t d; - resource_t base_k, limit_k; - d = get_dram_base_mask(0); - if (d.base & 1) { - base_k = ((resource_t) (d.base & 0x1fffff00)) << 9; - if (base_k <= 4 * 1024 * 1024) { - if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G - mem_hole.node_id = 0; - } - } - - limit_k = - ((resource_t) ((d.mask + 0x00000100) & 0x1fffff00)) - << 9; - limitk_pri = limit_k; - } - } -#endif - return mem_hole; } #endif

1 0

New patch to review for coreboot: soc/intel/fsp_broadwell_de: Fix system hang when timestamp is enabled
by York Yang 05 Oct '16

05 Oct '16

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16894 -gerrit commit 5b1999f33bb9321223f940f3b3a64245736f8bf5 Author: York Yang <york.yang(a)intel.com> Date: Wed Oct 5 10:19:40 2016 -0700 soc/intel/fsp_broadwell_de: Fix system hang when timestamp is enabled When timestamp is enabled, system hang in romstage because the timestamp data area is not yet available. This data area will be set after return from FspInit(), so move timestamp_init() to right after FspInit(). Verified on Intel Camelback Mountain CRB and ensured that system can boot to payload with timpstamp feature enabled. Change-Id: I59c4bb83ae7e166cceca34988d5a392e5a831afa Signed-off-by: York Yang <york.yang(a)intel.com> --- src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 309a672..49bdedb 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -58,11 +58,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) console_init(); init_rtc(); - post_code(0x41); - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Call into mainboard. */ + post_code(0x41); early_mainboard_romstage_entry(); /* @@ -71,7 +68,6 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) * structure. */ post_code(0x48); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); fsp_early_init(fsp_info_header); die("Uh Oh! fsp_early_init should not return here.\n"); @@ -87,6 +83,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) void *cbmem_hob_ptr; post_code(0x4a); + timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_AFTER_INITRAM); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr);

1 0

Patch set updated for coreboot: northbridge/amd/amdk8: Remove commented code
by HAOUAS Elyes 05 Oct '16

05 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16893 -gerrit commit 94dd2196bb3a0b8e1f4c91b74a522dae68ab3db9 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 18:47:26 2016 +0200 northbridge/amd/amdk8: Remove commented code Change-Id: Ifd6aefa6c046d100a5388a24a7d23cbd77905a85 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/amdk8/acpi.c | 30 ---------- src/northbridge/amd/amdk8/coherent_ht.c | 48 ---------------- src/northbridge/amd/amdk8/f.h | 5 -- src/northbridge/amd/amdk8/get_sblk_pci1234.c | 38 ------------ src/northbridge/amd/amdk8/incoherent_ht.c | 41 ------------- src/northbridge/amd/amdk8/northbridge.c | 10 ---- src/northbridge/amd/amdk8/raminit.c | 23 +------- src/northbridge/amd/amdk8/raminit_f.c | 35 ----------- src/northbridge/amd/amdk8/raminit_f_dqs.c | 17 ------ src/northbridge/amd/amdk8/raminit_test.c | 31 ---------- src/northbridge/amd/amdk8/setup_resource_map.c | 80 -------------------------- 11 files changed, 1 insertion(+), 357 deletions(-) diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 906dc0b..2fbe7aa 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -147,49 +147,19 @@ static unsigned long acpi_fill_slit(unsigned long current) 3, 4, 2, 3, 1, 2, 0, 1, 4, 4, 3, 2, 2, 1, 1, 0 }; -// u8 outer_node[8]; - u8 *p = (u8 *)current; int nodes = sysconf.nodes; int i,j; memset(p, 0, 8+nodes*nodes); -// memset((u8 *)outer_node, 0, 8); *p = (u8) nodes; p += 8; -#if 0 - for (i = 0; i < sysconf.hc_possible_num; i++) { - if ((sysconf.pci1234[i]&1) !=1) continue; - outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node - } -#endif - for (i = 0; i < nodes; i++) { for (j = 0; j < nodes; j++) { if (i == j) { p[i*nodes+j] = 10; } else { -#if 0 - int k; - u8 latency_factor = 0; - int k_start, k_end; - if (i < j) { - k_start = i; - k_end = j; - } else { - k_start = j; - k_end = i; - } - for (k = k_start; k <= k_end; k++) { - if (outer_node[k]) { - latency_factor = 1; - break; - } - } - p[i*nodes+j] = hops_8[i*nodes+j] * 2 + latency_factor + 10; -#else p[i*nodes+j] = hops_8[i*nodes+j] * 2 + 10; -#endif } } diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index ef4b829..464375f 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -149,21 +149,6 @@ static void disable_probes(void) } -#if 0 -static void enable_apic_ext_id(u8 node) -{ -#if CONFIG_ENABLE_APIC_EXT_ID -#warning "FIXME Is the right place to enable apic ext id here?" - - u32 val; - - val = pci_read_config32(NODE_HT(node), 0x68); - val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); - pci_write_config32(NODE_HT(node), 0x68, val); -#endif -} -#endif - static void enable_routing(u8 node) { u32 val; @@ -566,13 +551,6 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif val_s-=link_connection(temp, source-2); /* -down*/ } else { #if CROSS_BAR_47_56 - #if 0 - if (source == 7) { - val_s-=link_connection(temp, 6); // for 7,2 via 5 - } else if (source == 6) { - val_s-=link_connection(temp, 7); // for 6,3 via 4 - } else - #endif if (source < gateway) { // for 5, 4 via 7 val_s-=link_connection(temp, source-2); } else @@ -743,10 +721,6 @@ static unsigned setup_smp2(void) setup_remote_node(1); /* Setup the regs on the remote node */ rename_temp_node(1); /* Rename Node 7 to Node 1 */ enable_routing(1); /* Enable routing on Node 1 */ -#if 0 - /*don't need and it is done by clear_dead_links */ - clear_temp_row(0); -#endif return nodes; } @@ -910,13 +884,6 @@ static unsigned setup_smp4(void) #endif setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2)); -#if 0 - /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */ - /* it will be done by clear_dead_links */ - clear_temp_row(0); - clear_temp_row(1); -#endif - return nodes; } @@ -1111,15 +1078,6 @@ static unsigned setup_smp6(void) setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4)); -#if 0 - /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) - * It will be done by clear_dead_links - */ - for (byte = 0; byte < 4; byte++) { - clear_temp_row(byte); - } -#endif - return nodes; } @@ -1260,12 +1218,6 @@ static unsigned setup_smp8(void) #endif print_linkn("\t-->(5,6) link=", byte); setup_row_direct(5, 6, byte); -#if 0 - setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for (byte = 0; byte < 4; byte+=2) { - setup_temp_row(byte+1,byte+3); - } -#endif setup_temp_row(5,6); verify_connection(7); diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index a679150..359a1d6 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -555,11 +555,6 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) if (!mask) break; -#if 0 - /* cpu_relax */ - __asm__ __volatile__("rep;nop": : :"memory"); -#endif - i++; i%=sysinfo->nodes; } diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index 764b6d1..1343ae4 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -27,44 +27,6 @@ #include <cpu/amd/amdk8_sysconf.h> - -#if 0 -unsigned node_link_to_bus(unsigned node, unsigned link) -{ - device_t dev; - unsigned reg; - - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - if (!dev) { - return 0; - } - for (reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; - unsigned dst_node; - unsigned dst_link; - unsigned bus_base; - config_map = pci_read_config32(dev, reg); - if ((config_map & 3) != 3) { - continue; - } - dst_node = (config_map >> 4) & 7; - dst_link = (config_map >> 8) & 3; - bus_base = (config_map >> 16) & 0xff; -#if 0 - printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", - dst_node, dst_link, bus_base, - reg, config_map); -#endif - if ((dst_node == node) && (dst_link == link)) - { - return bus_base; - } - } - return 0; -} -#endif - - /* * Why we need the pci1234[] array * diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 48a4709..b72bf29 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -56,13 +56,6 @@ static uint8_t ht_lookup_slave_capability(pci_devfn_t dev) return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format } -#if 0 -static uint8_t ht_lookup_host_capability(pci_devfn_t dev) -{ - return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format -} -#endif - static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid) { pci_devfn_t dev; @@ -470,40 +463,6 @@ end_of_chain:; } -#if 0 -#if CONFIG_RAMINIT_SYSINFO -static void ht_setup_chain(pci_devfn_t udev, unsigned upos, - struct sys_info *sysinfo) -#else -static int ht_setup_chain(pci_devfn_t udev, unsigned upos) -#endif -{ - unsigned offset_unitid = 0; -#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) - offset_unitid = 1; -#endif - - /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a CPU has multiple - * non Coherent links the appropriate bus registers for the - * links needs to be programed to point at bus 0. - */ - - /* Make certain the HT bus is not enumerated */ - ht_collapse_previous_enumeration(0, 0); - -#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) - offset_unitid = 1; -#endif - -#if CONFIG_RAMINIT_SYSINFO - ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo); -#else - return ht_setup_chainx(udev, upos, 0, offset_unitid); -#endif -} -#endif - static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val) { uint32_t dword, dword_old; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index f18919b..02d5560 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -563,12 +563,6 @@ static void amdk8_set_resources(device_t dev) static void mcf0_control_init(struct device *dev) { -#if 0 - printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. "); -#endif -#if 0 - printk(BIOS_DEBUG, "done.\n"); -#endif } static struct device_operations northbridge_operations = { @@ -902,8 +896,6 @@ static void amdk8_domain_set_resources(device_t dev) reset_memhole = 0; } - //mmio_basek = 3*1024*1024; // for debug to meet boundary - if (reset_memhole) { if (mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! // We need to reset our Mem Hole, because We want more big HOLE than we already set @@ -965,8 +957,6 @@ static void amdk8_domain_set_resources(device_t dev) printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); if ((uma_memory_base >> 10) < mmio_basek) printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i); -#else -// printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu #endif /* See if I need to split the region to accommodate pci memory space */ diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 7fbe4ec..9f333fd 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -20,7 +20,6 @@ void setup_resource_map(const unsigned int *register_values, int max) { int i; -// printk(BIOS_DEBUG, "setting up resource map...."); for (i = 0; i < max; i += 3) { pci_devfn_t dev; unsigned where; @@ -32,7 +31,6 @@ void setup_resource_map(const unsigned int *register_values, int max) reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } -// printk(BIOS_DEBUG, "done.\n"); } static int controller_present(const struct mem_controller *ctrl) @@ -519,7 +517,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl) int max; if (!controller_present(ctrl)) { -// printk(BIOS_DEBUG, "No memory controller present\n"); return; } printk(BIOS_SPEW, "setting up CPU%02x northbridge registers\n", ctrl->node_id); @@ -965,7 +962,6 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) if (is_dual_channel(ctrl)) { /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */ if ((bits == 3) && (common_size == (1 << (32 - 3)))) { -// printk(BIOS_DEBUG, "8 4GB chip selects cannot be interleaved\n"); return 0; } csbase_inc <<=1; @@ -975,7 +971,6 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode]; if (is_dual_channel(ctrl)) { if ((bits == 3) && (common_cs_mode > 8)) { -// printk(BIOS_DEBUG, "8 cs_mode > 8 chip selects cannot be interleaved\n"); return 0; } csbase_inc <<=1; @@ -1469,9 +1464,7 @@ static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_ } /* now the lookup, decode the max speed DDR400_2T etc */ dloading = dimm_loading_config[dpos][rpos] & DDR_MASK; -#if 0 - printk(BIOS_DEBUG, "XXX %x %x dload %x 2T %x\n", dpos,rpos, dloading, dimm_loading_config[dpos][rpos] & DDR_2T); -#endif + hw_error: if (dloading != 0) { /* we have valid combination check the restrictions */ @@ -1671,14 +1664,6 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT); -#if 0 - /* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 and higher speeds with certain DIMM loadings ---- cheating???*/ - if (!is_cpu_pre_e0()) { - if (min_cycle_time == 0x50) { - value |= 1<<31; - } - } -#endif value |= result.param->dch_memclk; pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value); @@ -2189,7 +2174,6 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) long dimm_mask; #if 1 if (!controller_present(ctrl)) { -// printk(BIOS_DEBUG, "No memory controller present\n"); return; } #endif @@ -2453,11 +2437,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) if (!is_cpu_pre_c0()) { /* Wait until it is safe to touch memory */ -#if 0 - /* the registers are marked read-only but code zeros them */ - dcl &= ~(DCL_MemClrStatus | DCL_DramEnable); - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); -#endif do { dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); } while (((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) || diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index a42614e..aa2349d 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -701,15 +701,6 @@ index: printk(BIOS_SPEW, "done.\n"); } -#if 0 -static int is_dual_channel(const struct mem_controller *ctrl) -{ - uint32_t dcl; - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - return dcl & DCL_Width128; -} -#endif - static int is_opteron(const struct mem_controller *ctrl) { /* Test to see if I am an Opteron. M2 and S1G1 support dual @@ -725,19 +716,6 @@ static int is_opteron(const struct mem_controller *ctrl) return !!(nbcap & NBCAP_128Bit); } -#if 0 -static int is_registered(const struct mem_controller *ctrl) -{ - /* Test to see if we are dealing with registered SDRAM. - * If we are not registered we are unbuffered. - * This function must be called after spd_handle_unbuffered_dimms. - */ - uint32_t dcl; - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - return !(dcl & DCL_UnBuffDimm); -} -#endif - static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) { /* Calculate the log base 2 size of a DIMM in bits */ @@ -776,7 +754,6 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) /* number of physical banks */ value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK); if (value < 0) goto hw_err; -/* value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT; */ value &= SPD_MOD_ATTRIB_RANK_NUM_MASK; value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4 /* @@ -1350,16 +1327,6 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, } if (is_opteron(ctrl)) { -#if 0 - if (registered != (meminfo->dimm_mask & ((1 << DIMM_SOCKETS)-1))) { - meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS)); //disable unbuffered dimm -// die("Mixed buffered and registered dimms not supported"); - } - //By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM - if (!registered) { - die("Unbuffered Dimms not supported on Opteron"); - } -#endif } @@ -1524,7 +1491,6 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i dcm |= DCM_Mode64BitMux; pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm); dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - //dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */ pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); meminfo->is_64MuxMode = 1; } else { @@ -2080,7 +2046,6 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE; if (old_clocks >= clocks) { //some one did it? -// clocks = old_clocks; return 1; } dtl &= ~(TT_MASK << TT_SHIFT); diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 0cea94a..204339c 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -1694,13 +1694,6 @@ static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k) { msr_t msr; -#if 0 - //still enable from cache_as_ram.inc - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR,msr); -#endif - //[0,512k), [512k, 640k) msr.hi = 0x1e1e1e1e; msr.lo = msr.hi; @@ -2037,8 +2030,6 @@ out: static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox) { dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy -// memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 * 8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8); -// memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9], &sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9); sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid]; } @@ -2054,15 +2045,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy wait_till_sysinfo_in_ram(); // use pci to get it if (sysinfox->mem_trained[nodeid] == 0x80) { - #if 0 - sysinfo->tom_k = sysinfox->tom_k; - sysinfo->tom2_k = sysinfox->tom2_k; - sysinfo->meminfo[nodeid].is_Width128 = sysinfox->meminfo[nodeid].is_Width128; - sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid]; - memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller)); - #else memcpy(sysinfo, sysinfox, sizeof(*sysinfo)); - #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's printk(BIOS_DEBUG, "CODE IN ROM AND RUN ON NODE: %02x\n", nodeid); train_ram(nodeid, sysinfo, sysinfox); diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index 597b689..3d0b0f4 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -56,10 +56,6 @@ static uint32_t pci_read_config32(device_t dev, unsigned where) (pci_register[addr + 1] << 8) | (pci_register[addr + 2] << 16) | (pci_register[addr + 3] << 24); - -#if 0 - printk(BIOS_DEBUG, "pcir32(%08x): %08x\n", addr, value); -#endif return value; } @@ -87,10 +83,6 @@ static void pci_write_config32(device_t dev, unsigned where, uint32_t value) pci_register[addr + 1] = (value >> 8) & 0xff; pci_register[addr + 2] = (value >> 16) & 0xff; pci_register[addr + 3] = (value >> 24) & 0xff; - -#if 0 - printk(BIOS_DEBUG, "pciw32(%08x, %08x)\n", addr, value); -#endif } #define PCI_DEV_INVALID (0xffffffffU) @@ -277,10 +269,6 @@ static int spd_read_byte(unsigned device, unsigned address) result = spd_data[(device << 8) | address]; } } -#if 0 - printk(BIOS_DEBUG, "spd_read_byte(%08x, %08x) -> %08x\n", - device, address, result); -#endif if (spd_count >= spd_fail_count) { result = -1; } @@ -355,10 +343,6 @@ static void reset_tests(void) /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */ (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) | NBCAP_MEMCTRL); - -#if 0 - pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP); -#endif } static void test1(void) @@ -367,22 +351,7 @@ static void test1(void) memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); -#if 0 - memcpy(&spd_data[2*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[3*256], spd_micron_512MB_DDR333, 256); - - memcpy(&spd_data[8*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[9*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[10*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[11*256], spd_micron_512MB_DDR333, 256); -#endif - raminit_main(); - -#if 0 - printk(BIOS_DEBUG, "spd_count: %d\n", spd_count); -#endif - } diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index e6e79c8..38f8fdd 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -22,12 +22,6 @@ void setup_resource_map_offset(const unsigned int *register_values, int max, uns reg &= register_values[i+1]; reg |= register_values[i+2] + offset_io_base; pci_write_config32(dev, where, reg); -#if 0 - reg = pci_read_config32(register_values[i]); - reg &= register_values[i+1]; - reg |= register_values[i+2] & ~register_values[i+1]; - pci_write_config32(register_values[i], reg); -#endif } #if RES_DEBUG printk(BIOS_DEBUG, "done.\n"); @@ -94,20 +88,6 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int outl(reg, where); } break; -#if 0 - case RES_MEM_IO: //mem - { - unsigned where; - unsigned long reg; - where = register_values[i+1]; - reg = read32(where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - write32(where, reg); - } - break; -#endif - } // switch @@ -122,63 +102,3 @@ static inline void setup_resource_map_x(const unsigned int *register_values, int { setup_resource_map_x_offset(register_values, max, 0, 0); } - -#if 0 -static void setup_io_resource_map(const unsigned int *register_values, int max) -{ - int i; - - for (i = 0; i < max; i += 3) { - unsigned where; - unsigned long reg; - - where = register_values[i]; -#if 0 - udelay(2000); - printk(BIOS_DEBUG, "%04x", where); -#endif - - reg = inl(where); -#if 0 - udelay(2000); - printk(BIOS_DEBUG, "=%08x", reg); -#endif - reg &= register_values[i+1]; - reg |= register_values[i+2]; - -#if 0 - udelay(2000); - printk(BIOS_DEBUG, " <- %08x", reg); -#endif - outl(reg, where); -#if 0 - udelay(2000); - reg = inl(where); - printk(BIOS_DEBUG, " -> %08x\n", reg); -#endif - } -} - -static void setup_mem_resource_map(const unsigned int *register_values, int max) -{ - int i; - - for (i = 0; i < max; i += 3) { - unsigned where; - unsigned long reg; -#if 0 - prink(BIOS_DEBUG, "%08x <- %08x\n", - register_values[i], register_values[i+2]); -#endif - where = register_values[i]; - reg = read32(where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - write32(where, reg); -#if 0 - reg = read32(where); - prink(BIOS_DEBUG, " RB %08x\n", reg); -#endif - } -} -#endif

1 0

New patch to review for coreboot: northbridge/amd/amdk8: Remove commented code
by HAOUAS Elyes 05 Oct '16

05 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16893 -gerrit commit 837635b84feff225e5963ea9bac59929afba529e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 18:47:26 2016 +0200 northbridge/amd/amdk8: Remove commented code Change-Id: Ifd6aefa6c046d100a5388a24a7d23cbd77905a85 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/amdk8/acpi.c | 30 ---------- src/northbridge/amd/amdk8/coherent_ht.c | 48 ---------------- src/northbridge/amd/amdk8/f.h | 5 -- src/northbridge/amd/amdk8/get_sblk_pci1234.c | 38 ------------ src/northbridge/amd/amdk8/incoherent_ht.c | 41 ------------- src/northbridge/amd/amdk8/northbridge.c | 10 ---- src/northbridge/amd/amdk8/raminit.c | 23 +------- src/northbridge/amd/amdk8/raminit_f.c | 37 +----------- src/northbridge/amd/amdk8/raminit_f_dqs.c | 17 ------ src/northbridge/amd/amdk8/raminit_test.c | 31 ---------- src/northbridge/amd/amdk8/setup_resource_map.c | 80 -------------------------- 11 files changed, 2 insertions(+), 358 deletions(-) diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 906dc0b..2fbe7aa 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -147,49 +147,19 @@ static unsigned long acpi_fill_slit(unsigned long current) 3, 4, 2, 3, 1, 2, 0, 1, 4, 4, 3, 2, 2, 1, 1, 0 }; -// u8 outer_node[8]; - u8 *p = (u8 *)current; int nodes = sysconf.nodes; int i,j; memset(p, 0, 8+nodes*nodes); -// memset((u8 *)outer_node, 0, 8); *p = (u8) nodes; p += 8; -#if 0 - for (i = 0; i < sysconf.hc_possible_num; i++) { - if ((sysconf.pci1234[i]&1) !=1) continue; - outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node - } -#endif - for (i = 0; i < nodes; i++) { for (j = 0; j < nodes; j++) { if (i == j) { p[i*nodes+j] = 10; } else { -#if 0 - int k; - u8 latency_factor = 0; - int k_start, k_end; - if (i < j) { - k_start = i; - k_end = j; - } else { - k_start = j; - k_end = i; - } - for (k = k_start; k <= k_end; k++) { - if (outer_node[k]) { - latency_factor = 1; - break; - } - } - p[i*nodes+j] = hops_8[i*nodes+j] * 2 + latency_factor + 10; -#else p[i*nodes+j] = hops_8[i*nodes+j] * 2 + 10; -#endif } } diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index ef4b829..464375f 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -149,21 +149,6 @@ static void disable_probes(void) } -#if 0 -static void enable_apic_ext_id(u8 node) -{ -#if CONFIG_ENABLE_APIC_EXT_ID -#warning "FIXME Is the right place to enable apic ext id here?" - - u32 val; - - val = pci_read_config32(NODE_HT(node), 0x68); - val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); - pci_write_config32(NODE_HT(node), 0x68, val); -#endif -} -#endif - static void enable_routing(u8 node) { u32 val; @@ -566,13 +551,6 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif val_s-=link_connection(temp, source-2); /* -down*/ } else { #if CROSS_BAR_47_56 - #if 0 - if (source == 7) { - val_s-=link_connection(temp, 6); // for 7,2 via 5 - } else if (source == 6) { - val_s-=link_connection(temp, 7); // for 6,3 via 4 - } else - #endif if (source < gateway) { // for 5, 4 via 7 val_s-=link_connection(temp, source-2); } else @@ -743,10 +721,6 @@ static unsigned setup_smp2(void) setup_remote_node(1); /* Setup the regs on the remote node */ rename_temp_node(1); /* Rename Node 7 to Node 1 */ enable_routing(1); /* Enable routing on Node 1 */ -#if 0 - /*don't need and it is done by clear_dead_links */ - clear_temp_row(0); -#endif return nodes; } @@ -910,13 +884,6 @@ static unsigned setup_smp4(void) #endif setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2)); -#if 0 - /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */ - /* it will be done by clear_dead_links */ - clear_temp_row(0); - clear_temp_row(1); -#endif - return nodes; } @@ -1111,15 +1078,6 @@ static unsigned setup_smp6(void) setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4)); -#if 0 - /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) - * It will be done by clear_dead_links - */ - for (byte = 0; byte < 4; byte++) { - clear_temp_row(byte); - } -#endif - return nodes; } @@ -1260,12 +1218,6 @@ static unsigned setup_smp8(void) #endif print_linkn("\t-->(5,6) link=", byte); setup_row_direct(5, 6, byte); -#if 0 - setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for (byte = 0; byte < 4; byte+=2) { - setup_temp_row(byte+1,byte+3); - } -#endif setup_temp_row(5,6); verify_connection(7); diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index a679150..359a1d6 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -555,11 +555,6 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) if (!mask) break; -#if 0 - /* cpu_relax */ - __asm__ __volatile__("rep;nop": : :"memory"); -#endif - i++; i%=sysinfo->nodes; } diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index 764b6d1..1343ae4 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -27,44 +27,6 @@ #include <cpu/amd/amdk8_sysconf.h> - -#if 0 -unsigned node_link_to_bus(unsigned node, unsigned link) -{ - device_t dev; - unsigned reg; - - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - if (!dev) { - return 0; - } - for (reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; - unsigned dst_node; - unsigned dst_link; - unsigned bus_base; - config_map = pci_read_config32(dev, reg); - if ((config_map & 3) != 3) { - continue; - } - dst_node = (config_map >> 4) & 7; - dst_link = (config_map >> 8) & 3; - bus_base = (config_map >> 16) & 0xff; -#if 0 - printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", - dst_node, dst_link, bus_base, - reg, config_map); -#endif - if ((dst_node == node) && (dst_link == link)) - { - return bus_base; - } - } - return 0; -} -#endif - - /* * Why we need the pci1234[] array * diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 48a4709..b72bf29 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -56,13 +56,6 @@ static uint8_t ht_lookup_slave_capability(pci_devfn_t dev) return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format } -#if 0 -static uint8_t ht_lookup_host_capability(pci_devfn_t dev) -{ - return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format -} -#endif - static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid) { pci_devfn_t dev; @@ -470,40 +463,6 @@ end_of_chain:; } -#if 0 -#if CONFIG_RAMINIT_SYSINFO -static void ht_setup_chain(pci_devfn_t udev, unsigned upos, - struct sys_info *sysinfo) -#else -static int ht_setup_chain(pci_devfn_t udev, unsigned upos) -#endif -{ - unsigned offset_unitid = 0; -#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) - offset_unitid = 1; -#endif - - /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a CPU has multiple - * non Coherent links the appropriate bus registers for the - * links needs to be programed to point at bus 0. - */ - - /* Make certain the HT bus is not enumerated */ - ht_collapse_previous_enumeration(0, 0); - -#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) - offset_unitid = 1; -#endif - -#if CONFIG_RAMINIT_SYSINFO - ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo); -#else - return ht_setup_chainx(udev, upos, 0, offset_unitid); -#endif -} -#endif - static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val) { uint32_t dword, dword_old; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index f18919b..02d5560 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -563,12 +563,6 @@ static void amdk8_set_resources(device_t dev) static void mcf0_control_init(struct device *dev) { -#if 0 - printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. "); -#endif -#if 0 - printk(BIOS_DEBUG, "done.\n"); -#endif } static struct device_operations northbridge_operations = { @@ -902,8 +896,6 @@ static void amdk8_domain_set_resources(device_t dev) reset_memhole = 0; } - //mmio_basek = 3*1024*1024; // for debug to meet boundary - if (reset_memhole) { if (mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! // We need to reset our Mem Hole, because We want more big HOLE than we already set @@ -965,8 +957,6 @@ static void amdk8_domain_set_resources(device_t dev) printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); if ((uma_memory_base >> 10) < mmio_basek) printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i); -#else -// printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu #endif /* See if I need to split the region to accommodate pci memory space */ diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 7fbe4ec..9f333fd 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -20,7 +20,6 @@ void setup_resource_map(const unsigned int *register_values, int max) { int i; -// printk(BIOS_DEBUG, "setting up resource map...."); for (i = 0; i < max; i += 3) { pci_devfn_t dev; unsigned where; @@ -32,7 +31,6 @@ void setup_resource_map(const unsigned int *register_values, int max) reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } -// printk(BIOS_DEBUG, "done.\n"); } static int controller_present(const struct mem_controller *ctrl) @@ -519,7 +517,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl) int max; if (!controller_present(ctrl)) { -// printk(BIOS_DEBUG, "No memory controller present\n"); return; } printk(BIOS_SPEW, "setting up CPU%02x northbridge registers\n", ctrl->node_id); @@ -965,7 +962,6 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) if (is_dual_channel(ctrl)) { /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */ if ((bits == 3) && (common_size == (1 << (32 - 3)))) { -// printk(BIOS_DEBUG, "8 4GB chip selects cannot be interleaved\n"); return 0; } csbase_inc <<=1; @@ -975,7 +971,6 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode]; if (is_dual_channel(ctrl)) { if ((bits == 3) && (common_cs_mode > 8)) { -// printk(BIOS_DEBUG, "8 cs_mode > 8 chip selects cannot be interleaved\n"); return 0; } csbase_inc <<=1; @@ -1469,9 +1464,7 @@ static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_ } /* now the lookup, decode the max speed DDR400_2T etc */ dloading = dimm_loading_config[dpos][rpos] & DDR_MASK; -#if 0 - printk(BIOS_DEBUG, "XXX %x %x dload %x 2T %x\n", dpos,rpos, dloading, dimm_loading_config[dpos][rpos] & DDR_2T); -#endif + hw_error: if (dloading != 0) { /* we have valid combination check the restrictions */ @@ -1671,14 +1664,6 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT); -#if 0 - /* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 and higher speeds with certain DIMM loadings ---- cheating???*/ - if (!is_cpu_pre_e0()) { - if (min_cycle_time == 0x50) { - value |= 1<<31; - } - } -#endif value |= result.param->dch_memclk; pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value); @@ -2189,7 +2174,6 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) long dimm_mask; #if 1 if (!controller_present(ctrl)) { -// printk(BIOS_DEBUG, "No memory controller present\n"); return; } #endif @@ -2453,11 +2437,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) if (!is_cpu_pre_c0()) { /* Wait until it is safe to touch memory */ -#if 0 - /* the registers are marked read-only but code zeros them */ - dcl &= ~(DCL_MemClrStatus | DCL_DramEnable); - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); -#endif do { dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); } while (((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) || diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index a42614e..3397fcb 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -701,15 +701,6 @@ index: printk(BIOS_SPEW, "done.\n"); } -#if 0 -static int is_dual_channel(const struct mem_controller *ctrl) -{ - uint32_t dcl; - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - return dcl & DCL_Width128; -} -#endif - static int is_opteron(const struct mem_controller *ctrl) { /* Test to see if I am an Opteron. M2 and S1G1 support dual @@ -725,19 +716,6 @@ static int is_opteron(const struct mem_controller *ctrl) return !!(nbcap & NBCAP_128Bit); } -#if 0 -static int is_registered(const struct mem_controller *ctrl) -{ - /* Test to see if we are dealing with registered SDRAM. - * If we are not registered we are unbuffered. - * This function must be called after spd_handle_unbuffered_dimms. - */ - uint32_t dcl; - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - return !(dcl & DCL_UnBuffDimm); -} -#endif - static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) { /* Calculate the log base 2 size of a DIMM in bits */ @@ -776,7 +754,6 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) /* number of physical banks */ value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK); if (value < 0) goto hw_err; -/* value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT; */ value &= SPD_MOD_ATTRIB_RANK_NUM_MASK; value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4 /* @@ -1302,7 +1279,7 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index, { printk(BIOS_DEBUG, "disabling dimm %02x\n", index); if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */ - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0); + pci_write_config32(ctrl-<>f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0); } else { pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0); @@ -1350,16 +1327,6 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, } if (is_opteron(ctrl)) { -#if 0 - if (registered != (meminfo->dimm_mask & ((1 << DIMM_SOCKETS)-1))) { - meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS)); //disable unbuffered dimm -// die("Mixed buffered and registered dimms not supported"); - } - //By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM - if (!registered) { - die("Unbuffered Dimms not supported on Opteron"); - } -#endif } @@ -1524,7 +1491,6 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i dcm |= DCM_Mode64BitMux; pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm); dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - //dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */ pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); meminfo->is_64MuxMode = 1; } else { @@ -2080,7 +2046,6 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE; if (old_clocks >= clocks) { //some one did it? -// clocks = old_clocks; return 1; } dtl &= ~(TT_MASK << TT_SHIFT); diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 0cea94a..204339c 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -1694,13 +1694,6 @@ static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k) { msr_t msr; -#if 0 - //still enable from cache_as_ram.inc - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR,msr); -#endif - //[0,512k), [512k, 640k) msr.hi = 0x1e1e1e1e; msr.lo = msr.hi; @@ -2037,8 +2030,6 @@ out: static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox) { dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy -// memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 * 8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8); -// memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9], &sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9); sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid]; } @@ -2054,15 +2045,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy wait_till_sysinfo_in_ram(); // use pci to get it if (sysinfox->mem_trained[nodeid] == 0x80) { - #if 0 - sysinfo->tom_k = sysinfox->tom_k; - sysinfo->tom2_k = sysinfox->tom2_k; - sysinfo->meminfo[nodeid].is_Width128 = sysinfox->meminfo[nodeid].is_Width128; - sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid]; - memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller)); - #else memcpy(sysinfo, sysinfox, sizeof(*sysinfo)); - #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's printk(BIOS_DEBUG, "CODE IN ROM AND RUN ON NODE: %02x\n", nodeid); train_ram(nodeid, sysinfo, sysinfox); diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index 597b689..3d0b0f4 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -56,10 +56,6 @@ static uint32_t pci_read_config32(device_t dev, unsigned where) (pci_register[addr + 1] << 8) | (pci_register[addr + 2] << 16) | (pci_register[addr + 3] << 24); - -#if 0 - printk(BIOS_DEBUG, "pcir32(%08x): %08x\n", addr, value); -#endif return value; } @@ -87,10 +83,6 @@ static void pci_write_config32(device_t dev, unsigned where, uint32_t value) pci_register[addr + 1] = (value >> 8) & 0xff; pci_register[addr + 2] = (value >> 16) & 0xff; pci_register[addr + 3] = (value >> 24) & 0xff; - -#if 0 - printk(BIOS_DEBUG, "pciw32(%08x, %08x)\n", addr, value); -#endif } #define PCI_DEV_INVALID (0xffffffffU) @@ -277,10 +269,6 @@ static int spd_read_byte(unsigned device, unsigned address) result = spd_data[(device << 8) | address]; } } -#if 0 - printk(BIOS_DEBUG, "spd_read_byte(%08x, %08x) -> %08x\n", - device, address, result); -#endif if (spd_count >= spd_fail_count) { result = -1; } @@ -355,10 +343,6 @@ static void reset_tests(void) /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */ (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) | NBCAP_MEMCTRL); - -#if 0 - pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP); -#endif } static void test1(void) @@ -367,22 +351,7 @@ static void test1(void) memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); -#if 0 - memcpy(&spd_data[2*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[3*256], spd_micron_512MB_DDR333, 256); - - memcpy(&spd_data[8*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[9*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[10*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[11*256], spd_micron_512MB_DDR333, 256); -#endif - raminit_main(); - -#if 0 - printk(BIOS_DEBUG, "spd_count: %d\n", spd_count); -#endif - } diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index e6e79c8..38f8fdd 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -22,12 +22,6 @@ void setup_resource_map_offset(const unsigned int *register_values, int max, uns reg &= register_values[i+1]; reg |= register_values[i+2] + offset_io_base; pci_write_config32(dev, where, reg); -#if 0 - reg = pci_read_config32(register_values[i]); - reg &= register_values[i+1]; - reg |= register_values[i+2] & ~register_values[i+1]; - pci_write_config32(register_values[i], reg); -#endif } #if RES_DEBUG printk(BIOS_DEBUG, "done.\n"); @@ -94,20 +88,6 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int outl(reg, where); } break; -#if 0 - case RES_MEM_IO: //mem - { - unsigned where; - unsigned long reg; - where = register_values[i+1]; - reg = read32(where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - write32(where, reg); - } - break; -#endif - } // switch @@ -122,63 +102,3 @@ static inline void setup_resource_map_x(const unsigned int *register_values, int { setup_resource_map_x_offset(register_values, max, 0, 0); } - -#if 0 -static void setup_io_resource_map(const unsigned int *register_values, int max) -{ - int i; - - for (i = 0; i < max; i += 3) { - unsigned where; - unsigned long reg; - - where = register_values[i]; -#if 0 - udelay(2000); - printk(BIOS_DEBUG, "%04x", where); -#endif - - reg = inl(where); -#if 0 - udelay(2000); - printk(BIOS_DEBUG, "=%08x", reg); -#endif - reg &= register_values[i+1]; - reg |= register_values[i+2]; - -#if 0 - udelay(2000); - printk(BIOS_DEBUG, " <- %08x", reg); -#endif - outl(reg, where); -#if 0 - udelay(2000); - reg = inl(where); - printk(BIOS_DEBUG, " -> %08x\n", reg); -#endif - } -} - -static void setup_mem_resource_map(const unsigned int *register_values, int max) -{ - int i; - - for (i = 0; i < max; i += 3) { - unsigned where; - unsigned long reg; -#if 0 - prink(BIOS_DEBUG, "%08x <- %08x\n", - register_values[i], register_values[i+2]); -#endif - where = register_values[i]; - reg = read32(where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - write32(where, reg); -#if 0 - reg = read32(where); - prink(BIOS_DEBUG, " RB %08x\n", reg); -#endif - } -} -#endif

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New patch to review for coreboot: soc/intel/fsp_broadwell_de: Remove the enforced fsp1.0 APIs call sequence
by York Yang 05 Oct '16

05 Oct '16

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16892 -gerrit commit 0245a5a7e3911e0fad0fcaae9a02ade61cb2a98f Author: York Yang <york.yang(a)intel.com> Date: Wed Oct 5 09:32:46 2016 -0700 soc/intel/fsp_broadwell_de: Remove the enforced fsp1.0 APIs call sequence The enforced FSP 1.0 APIs call was used to workaround a fsp1.0 driver issue. As the issue has been fixed in fsp1.0 driver, need to remove the enforced workaround. Otherwise will see error message 'FSP API NotifyPhase failed' in serial log. Verified on Intel Camelback Mountain CRB and confirmed that the serial log error message regarding the 'FSP API NotifyPhase failed' is gone. Change-Id: Iafa1d22e2476769fd841a3ebaa1ab4f9713c6c39 Signed-off-by: York Yang <york.yang(a)intel.com> --- src/soc/intel/fsp_broadwell_de/chip.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index 78649fc..b8db395 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -66,21 +66,9 @@ static void enable_dev(device_t dev) } } -static void fsp_notify(void *arg) -{ - FspNotify (*(uint32_t *)arg); -} - -static uint32_t gFspNotifyAfterPciEnumeration = EnumInitPhaseAfterPciEnumeration; -static uint32_t gFspNotifyReadtToBoot = EnumInitPhaseReadyToBoot; -static BOOT_STATE_CALLBACK(bscb_fspnotify1, fsp_notify, &gFspNotifyAfterPciEnumeration); -static BOOT_STATE_CALLBACK(bscb_fspnotify2, fsp_notify, &gFspNotifyReadtToBoot); - /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ static void soc_init(void *chip_info) { - boot_state_sched_on_exit(&bscb_fspnotify1, BS_DEV_RESOURCES); - boot_state_sched_on_exit(&bscb_fspnotify2, BS_PAYLOAD_LOAD); broadwell_de_init_pre_device(); }

1 0

New patch to review for coreboot: northbridge/amd/lx: Remove commented code
by HAOUAS Elyes 05 Oct '16

05 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16891 -gerrit commit ba7fc2b8ec8dd7d7467a1f1c1fbd98d9183315bb Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 18:40:51 2016 +0200 northbridge/amd/lx: Remove commented code Change-Id: I37c1674ee380936aba797e24897593fcca3b0269 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/lx/northbridge.c | 24 ------------------------ src/northbridge/amd/lx/pll_reset.c | 29 ----------------------------- 2 files changed, 53 deletions(-) diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4b6090f..f0304be 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -293,37 +293,17 @@ static void enable_shadow(device_t dev) static void northbridge_init(device_t dev) { - //msr_t msr; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); enable_shadow(dev); - /* - * Swiss cheese - */ - //msr = rdmsr(MSR_GLIU0_SHADOW); - //msr.hi |= 0x3; - //msr.lo |= 0x30000; - - //printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo); - //printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo); } static void northbridge_set_resources(struct device *dev) { uint8_t line; -#if 0 - struct resource *res; - for (res = dev->resource_list; res; res = res->next) { - - // andrei: do not change the base address, it will make the VSA virtual registers unusable - //pci_set_resource(dev, res); - // FIXME: static allocation may conflict with dynamic mappings! - } -#endif - struct bus *bus; for (bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { @@ -400,12 +380,8 @@ static void pci_domain_enable(device_t dev) cpubug(); chipsetinit(); - // print_conf(); - do_vsmbios(); // do the magic stuff here, so prepare your tambourine;) - // print_conf(); - graphics_init(); } diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 318c7a1..d98a8ea 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -65,21 +65,6 @@ static void pll_reset(void) return; } -#if 0 // Unused -static unsigned int CPUSpeed(void) -{ - unsigned int speed; - msr_t msr; - - msr = rdmsr(GLCP_SYS_RSTPLL); - speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10; - if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) { - ++speed; - } - return (speed); -} -#endif - unsigned int GeodeLinkSpeed(void) { unsigned int speed; @@ -92,17 +77,3 @@ unsigned int GeodeLinkSpeed(void) } return (speed); } - -#if 0 // Unused -static unsigned int PCISpeed(void) -{ - msr_t msr; - - msr = rdmsr(GLCP_SYS_RSTPLL); - if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) { - return (66); - } else { - return (33); - } -} -#endif

1 0

New patch to review for coreboot: northbridge/amd/pi/00730F01: Remove commented code
by HAOUAS Elyes 05 Oct '16

05 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16890 -gerrit commit 305eb39b3a72a67cf62481ba679c0a83c71792c2 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 18:37:56 2016 +0200 northbridge/amd/pi/00730F01: Remove commented code Change-Id: I930c761b9a2422590af3a0a5008b4ff2abe3fd96 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/pi/00730F01/northbridge.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index c87d68a..e8bc425 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -86,17 +86,6 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? -#if 0 - // FIXME: can we use VGA reg instead? - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", - __func__, dev_path(dev), link); - tempreg |= PCI_IO_BASE_VGA_EN; - } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { - tempreg |= PCI_IO_BASE_NO_ISA; - } -#endif for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); }

1 0

New patch to review for coreboot: northbridge/amd/amdmct/mct_ddr3: Remove commented code
by HAOUAS Elyes 05 Oct '16

05 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16889 -gerrit commit d29639a406c5d4b1968d6e8a983b9fc65b6d81a9 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 18:30:58 2016 +0200 northbridge/amd/amdmct/mct_ddr3: Remove commented code Change-Id: I2a52db28353f8575d11218af936b4a233fd05f77 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 16 ---------------- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 17 ----------------- 2 files changed, 33 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index bd26a6f..f3fba25 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -34,8 +34,6 @@ #include <reset.h> -// #define DEBUG_DIMM_SPD 1 - static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void DQSTiming_D(struct MCTStatStruc *pMCTstat, @@ -2829,17 +2827,6 @@ restartinit: * speed is the same as the speed used in the previous boot. * How to get the desired speed at this point in the code? */ -#if 0 - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - if (pDCTstat->spd_data.nvram_memclk[0] != pDCTstat->DIMMAutoSpeed) - allow_config_restore = 0; - } - } -#endif printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n"); DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore); /* Get Receiver Enable and DQS signal timing*/ @@ -3623,7 +3610,6 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, } retry_dqs_training_and_levelization: - // nv_DQSTrainCTL = mctGet_NVbits(NV_DQSTrainCTL); nv_DQSTrainCTL = !allow_config_restore; mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA); @@ -3662,8 +3648,6 @@ retry_dqs_training_and_levelization: mct_WriteLevelization_HW(pMCTstat, pDCTstatA, SecondPass); if (is_fam15h()) { - /* Receiver Enable Training Pass 2 */ - // TrainReceiverEn_D(pMCTstat, pDCTstatA, SecondPass); /* TODO: * Determine why running TrainReceiverEn_D in SecondPass diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index eac2013..8c134c3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -951,11 +951,6 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, * This does not seem to be needed, and has a tendency to lock up the * boot process while attempting to write the test pattern. */ -#if 0 - SetUpperFSbase(TestAddr0); - WriteLNTestPattern(TestAddr0 << 8, (uint8_t *)TestPattern2_D, 1); - mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0); -#endif } MaxDelay_CH[Channel] = CTLRMaxDelay; } @@ -1087,7 +1082,6 @@ static void generate_dram_receiver_enable_training_pattern_fam15(struct MCTStatS /* 2.10.5.8.6.1.2 */ dword = Get_NB32_DCT(dev, dct, 0x270); dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */ -// dword |= (0x55555); dword |= (0x44443); /* Use AGESA seed */ Set_NB32_DCT(dev, dct, 0x270, dword); @@ -1097,17 +1091,6 @@ static void generate_dram_receiver_enable_training_pattern_fam15(struct MCTStatS dword |= 192; Set_NB32_DCT(dev, dct, 0x260, dword); -#if 0 - /* TODO: This applies to Fam15h model 10h and above only */ - /* Program Bubble Count and CmdStreamLen */ - dword = Get_NB32_DCT(dev, dct, 0x25c); - dword &= ~(0x3ff << 12); /* BubbleCnt = 0 */ - dword &= ~(0x3ff << 22); /* BubbleCnt2 = 0 */ - dword &= ~(0xff); /* CmdStreamLen = 1 */ - dword |= 0x1; - Set_NB32_DCT(dev, dct, 0x25c, dword); -#endif - /* Configure Target A */ dword = Get_NB32_DCT(dev, dct, 0x254); dword &= ~(0x7 << 24); /* TgtChipSelect = Receiver */

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coreboot-gerrit October 2016