coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: rockchip/rk3399: lower kevin board sdram frequency to 800MHz
by gerrit＠coreboot.org 06 Oct '16

06 Oct '16

the following patch was just integrated into master: commit 8e09de297fce1de0693d2833d7a15f76fa2ce18a Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Sep 8 11:16:26 2016 -0700 rockchip/rk3399: lower kevin board sdram frequency to 800MHz We found some boards are not stable when sdram is run at 933Mhz. Before we can fix it, we need to lower the sdram frequency to 800MHz. In this patch we modify the DQS delay from 0x280 to 0x260 and extend the DQS window. BRANCH=None BUG=chrome-os-partner:56940 TEST=Booted Kevin. Change-Id: I68561c4aa4d9ab66acfa3515a42d696157aff759 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 877a7f6ad22a5bde9f9e458bcb65f133f2f001bd Original-Change-Id: I5eab6bbe96f0dae095c5353403292022e7a25421 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/382724 Original-Commit-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Tested-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Reviewed-on: https://review.coreboot.org/16709 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16709 for details. -gerrit

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Patch merged into coreboot/master: arm64: Use 'payload' format for ATF instead of 'stage'
by gerrit＠coreboot.org 06 Oct '16

06 Oct '16

the following patch was just integrated into master: commit 7ae73fc3a07fed94846054dda30d0be67245e9c3 Author: Simon Glass <sjg(a)chromium.org> Date: Sat Aug 27 12:18:38 2016 -0600 arm64: Use 'payload' format for ATF instead of 'stage' Switch the BL31 (ARM Trusted Firmware) format to payload so that it can have multiple independent segments. This also requires disabling the region check since SRAM is currently faulted by that check. This has been tested with Rockchip's pending change: https://chromium-review.googlesource.com/#/c/368592/3 with the patch mentioned on the bug at #13. BUG=chrome-os-partner:56314 BRANCH=none TEST=boot on gru and see that BL31 loads and runs. Im not sure if it is correct though: CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1b440 size 15a75 Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x18104800 memsize 0x117fbe0 srcaddr 0x100038 filesize 0x15a3d Loading segment from ROM address 0x000000000010001c Entry Point 0x0000000018104800 Loading Segment: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d using LZMA [ 0x18104800, 18137d90, 0x192843e0) <- 00100038 Clearing Segment: addr: 0x0000000018137d90 memsz: 0x000000000114c650 dest 0000000018104800, end 00000000192843e0, bouncebuffer ffffffffffffffff Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 125150 exit 1 Jumping to boot code at 0000000018104800(00000000f7eda000) CPU0: stack: 00000000ff8ec000 - 00000000ff8f0000, lowest used address 00000000ff8ef3d0, stack used: 3120 bytes CBFS: 'VBOOT' located CBFS at [402000:44cc00) CBFS: Locating 'fallback/bl31' CBFS: Found @ offset 10ec0 size 8d0c Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x10000 memsize 0x40000 srcaddr 0x100054 filesize 0x8192 Loading segment from ROM address 0x000000000010001c code (compression=1) New segment dstaddr 0xff8d4000 memsize 0x1f50 srcaddr 0x1081e6 filesize 0xb26 Loading segment from ROM address 0x0000000000100038 Entry Point 0x0000000000010000 Loading Segment: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192 lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192 using LZMA [ 0x00010000, 00035708, 0x00050000) <- 00100054 Clearing Segment: addr: 0x0000000000035708 memsz: 0x000000000001a8f8 dest 0000000000010000, end 0000000000050000, bouncebuffer ffffffffffffffff Loading Segment: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26 lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26 using LZMA [ 0xff8d4000, ff8d5f50, 0xff8d5f50) <- 001081e6 dest 00000000ff8d4000, end 00000000ff8d5f50, bouncebuffer ffffffffffffffff Loaded segments INFO: plat_rockchip_pmusram_prepare pmu: code d2bfe625,d2bfe625,80 INFO: plat_rockchip_pmusram_prepare pmu: code 0xff8d4000,0x50000,3364 INFO: plat_rockchip_pmusram_prepare: data 0xff8d4d28,0xff8d4d24,4648 NOTICE: BL31: v1.2(debug): NOTICE: BL31: Built : Sun Sep 4 22:36:16 UTC 2016 INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 INFO: plat_rockchip_pmu_init(1189): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x18104800 INFO: SPSR = 0x8 Change-Id: Ie2484d122a603f1c7b7082a1de3f240aa6e6d540 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8c1d75bff6e810a39776048ad9049ec0a9c5d94e Original-Change-Id: I2d60e5762f8377e43835558f76a3928156acb26c Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376849 Original-Commit-Ready: Simon Glass <sjg(a)google.com> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/16706 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16706 for details. -gerrit

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Patch merged into coreboot/master: rockchip: Correct and standardize clock divisor range assertions
by gerrit＠coreboot.org 06 Oct '16

06 Oct '16

the following patch was just integrated into master: commit b37c8c065cc857ef8d52816ae65be5c4b1e4d62a Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Sep 6 14:09:16 2016 -0700 rockchip: Correct and standardize clock divisor range assertions Some of the asserts for valid clock divisor ranges were off by one. This patch corrects them and writes them all in a consistent way. BRANCH=None BUG=None TEST=Booted Kevin. Change-Id: I81749408a40822100797f1734f3b88987d12d8d5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e09cdfde26700496aaa1fc41489f63a355e8a89d Original-Change-Id: I429edb99e2d5ff2302d9750e6569b3d21f5686fa Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381574 Original-Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-on: https://review.coreboot.org/16704 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16704 for details. -gerrit

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Patch merged into coreboot/master: spi: Add a way to show SPI transfer speed for reads
by gerrit＠coreboot.org 06 Oct '16

06 Oct '16

the following patch was just integrated into master: commit aa58a9eebfc1a60ccc614ef6a064cf0ffce1c114 Author: Simon Glass <sjg(a)chromium.org> Date: Sat Aug 27 15:03:02 2016 -0600 spi: Add a way to show SPI transfer speed for reads SPI read speed directly impacts boot time and we do quite a lot of reading. Add a way to easily find out the speed of SPI flash reads within coreboot. Write speed is less important since there are very few writes and they are small. BUG=chrome-os-partner:56556 BRANCH=none TEST=run on gru with SPI_SPEED_DEBUG set to 1. See the output messages: read SPI 627d4 7d73: 18455 us, 1740 KB/s, 13.920 Mbps Change-Id: Id3814bd2b7bd045cdfcc67eb1fabc861bf9ed3b2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 82cb93f6be47efce3b0a3843bab89d2381baef89 Original-Change-Id: Iec66f5b8e3ad62f14d836a538dc7801e4ca669e7 Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376944 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/16701 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16701 for details. -gerrit

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Patch merged into coreboot/master: google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration
by gerrit＠coreboot.org 06 Oct '16

06 Oct '16

the following patch was just integrated into master: commit dd42db63489d2a2021f40aec894b1eded62e9a04 Author: Jeffy Chen <jeffy.chen(a)rock-chips.com> Date: Fri Sep 2 18:16:33 2016 +0800 google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto. BUG=chrome-os-partner:56759 BRANCH=none TEST=Build Change-Id: I698fe450d48b64a06232aa44ecf91d688d9dc17a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d3edecdb135939c3264ab1b831e7821d3a3e0149 Original-Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531 Original-Signed-off-by: Jeffy Chen <jeffy.chen(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380443 Original-Commit-Ready: Alexandru Stan <amstan(a)chromium.org> Original-Tested-by: Alexandru Stan <amstan(a)chromium.org> Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org> Original-Reviewed-by: Jonathan Dixon <joth(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/16699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/16699 for details. -gerrit

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Patch merged into coreboot/master: rockchip/rk3399: Move big CPU cluster initialization into ramstage
by gerrit＠coreboot.org 06 Oct '16

06 Oct '16

the following patch was just integrated into master: commit 7f965891b6d95bf3c347d955502505597d45a7d7 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 29 15:07:58 2016 -0700 rockchip/rk3399: Move big CPU cluster initialization into ramstage This patch moves the big CPU cluster initialization on the RK3399 from the clock init bootblock function into ramstage. We're only really doing this to put the cluster into a sane state for the OS, we're never actually taking it out of reset ourselves... so there's no reason to do this so early. Also cleaned up the interface for rkclk_configure_cpu() a bit to make it more readable. BRANCH=None BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I568b891da0abb404760d120cef847737c1f9e3ec Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: bd7aa7ec3e6d211b17ed61419f80a818cee78919 Original-Change-Id: Ic3d01a51531683b53e17addf1942441663a8ea40 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/377541 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Reviewed-on: https://review.coreboot.org/16698 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16698 for details. -gerrit

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Patch merged into coreboot/master: i2c/ww_ring: Change LED configuration for Gale EVT3
by gerrit＠coreboot.org 06 Oct '16

06 Oct '16

the following patch was just integrated into master: commit a39a5b60b4a11bb2686166f58987158b980c7f21 Author: Suresh Rajashekara <sureshraj(a)google.com> Date: Mon Aug 15 16:18:11 2016 -0700 i2c/ww_ring: Change LED configuration for Gale EVT3 Gale EVT3 has only one LED controller (earlier we had 2). Remove the support for the second controller and also the corresponding microcode. The color values used are the same as onHub (Arkham to be specific). BUG=b:30890905 TEST=Move the device to different states manually by appropriate actions (like dev mode, rec mode etc) and observe the different colors. BRANCH=None Change-Id: I853035610ea7ea7c8d29c30d2de13c9e2e786b2b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 593905d2d69daa7482318aa5f5c5cd7cf984043e Original-Change-Id: If8f22abd605faac6f6215ef600041740ce15ea0c Original-Signed-off-by: Suresh Rajashekara <sureshraj(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/370821 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Kan Yan <kyan(a)google.com> Reviewed-on: https://review.coreboot.org/16697 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16697 for details. -gerrit

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Patch set updated for coreboot: mainboard/kontron: Use C89 comments style & remove commented code
by HAOUAS Elyes 06 Oct '16

06 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16908 -gerrit commit b650954b9fa7a0793193f20180cf658c53301615 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Oct 6 19:49:55 2016 +0200 mainboard/kontron: Use C89 comments style & remove commented code Change-Id: I53a0344686921012f4e031842b5108aa4a7b79b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/kontron/986lcd-m/irq_tables.c | 20 +++++----- src/mainboard/kontron/986lcd-m/mainboard.c | 57 ++++++++++++----------------- src/mainboard/kontron/986lcd-m/mptable.c | 10 ++--- src/mainboard/kontron/986lcd-m/romstage.c | 52 ++++++++++++-------------- src/mainboard/kontron/ktqm77/hda_verb.c | 12 +++--- src/mainboard/kontron/ktqm77/mainboard.c | 4 +- src/mainboard/kontron/ktqm77/romstage.c | 16 ++++---- 7 files changed, 80 insertions(+), 91 deletions(-) diff --git a/src/mainboard/kontron/986lcd-m/irq_tables.c b/src/mainboard/kontron/986lcd-m/irq_tables.c index 0c5f403..fc67c22 100644 --- a/src/mainboard/kontron/986lcd-m/irq_tables.c +++ b/src/mainboard/kontron/986lcd-m/irq_tables.c @@ -29,22 +29,22 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */ + {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */ + {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */ + {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */ + {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */ + {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */ + {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */ + {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */ + {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */ {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */ {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 2a0c147..d729533 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -41,15 +41,15 @@ static void hwm_bank(u8 bank) #define FAN_CRUISE_CONTROL_THERMAL 2 #define FAN_SPEED_5625 0 -//#define FAN_TEMPERATURE_30DEGC 0 + struct fan_speed { u8 fan_in; u16 fan_speed; }; -// FANIN Target Speed Register -// FANIN = 337500 / RPM +/* FANIN Target Speed Register */ +/* FANIN = 337500 / RPM */ struct fan_speed fan_speeds[] = { { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, @@ -79,34 +79,27 @@ static void hwm_setup(void) get_option(&cpufan_control, "cpufan_cruise_control"); cpufan_speed = FAN_SPEED_5625; get_option(&cpufan_speed, "cpufan_speed"); - //cpufan_temperature = FAN_TEMPERATURE_30DEGC; - //get_option(&cpufan_temperature, "cpufan_temperature"); sysfan_control = FAN_CRUISE_CONTROL_DISABLED; get_option(&sysfan_control, "sysfan_cruise_control"); sysfan_speed = FAN_SPEED_5625; get_option(&sysfan_speed, "sysfan_speed"); - //sysfan_temperature = FAN_TEMPERATURE_30DEGC; - //get_option(&sysfan_temperature, "sysfan_temperature"); - - // hwm_write(0x31, 0x20); // AVCC high limit - // hwm_write(0x34, 0x06); // VIN2 low limit hwm_bank(0); - hwm_write(0x59, 0x20); // Diode Selection - hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + hwm_write(0x59, 0x20); /* Diode Selection */ + hwm_write(0x5d, 0x0f); /* All Sensors Diode, not Thermistor */ hwm_bank(4); - hwm_write(0x54, 0xf1); // SYSTIN temperature offset - hwm_write(0x55, 0x19); // CPUTIN temperature offset - hwm_write(0x56, 0xfc); // AUXTIN temperature offset + hwm_write(0x54, 0xf1); /* SYSTIN temperature offset */ + hwm_write(0x55, 0x19); /* CPUTIN temperature offset */ + hwm_write(0x56, 0xfc); /* AUXTIN temperature offset */ - hwm_bank(0x80); // Default + hwm_bank(0x80); /* Default */ u8 fan_config = 0; - // 00 FANOUT is Manual Mode - // 01 FANOUT is Thermal Cruise Mode - // 10 FANOUT is Fan Speed Cruise Mode + /* 00 FANOUT is Manual Mode */ + /* 01 FANOUT is Thermal Cruise Mode */ + /* 10 FANOUT is Fan Speed Cruise Mode */ switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; @@ -115,20 +108,20 @@ static void hwm_setup(void) case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; } - // This register must be written first + /* This register must be written first */ hwm_write(0x04, fan_config); switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); /* CPUFANIN target speed */ break; case FAN_CRUISE_CONTROL_THERMAL: printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", temperatures[cpufan_temperature].deg_celsius, temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); /* CPUFANIN target temperature */ break; } @@ -136,29 +129,27 @@ static void hwm_setup(void) case FAN_CRUISE_CONTROL_SPEED: printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); /* SYSFANIN target speed */ break; case FAN_CRUISE_CONTROL_THERMAL: printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", temperatures[sysfan_temperature].deg_celsius, temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); /* SYSFANIN target temperature */ break; } - hwm_write(0x0e, 0x02); // Fan Output Step Down Time - hwm_write(0x0f, 0x02); // Fan Output Step Up Time + hwm_write(0x0e, 0x02); /* Fan Output Step Down Time */ + hwm_write(0x0f, 0x02); /* Fan Output Step Up Time */ - hwm_write(0x47, 0xaf); // FAN divisor register - hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + hwm_write(0x47, 0xaf); /* FAN divisor register */ + hwm_write(0x4b, 0x84); /* AUXFANIN speed divisor */ - hwm_write(0x40, 0x01); // Init, but no SMI# + hwm_write(0x40, 0x01); /* Init, but no SMI# */ } - - -// mainboard_enable is executed as first thing after -// enumerate_buses(). +/* mainboard_enable is executed as first thing after */ +/* enumerate_buses(). */ static void mainboard_enable(device_t dev) { diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index 2ee2890..7db977d 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -39,8 +39,8 @@ static void *smp_write_config_table(void *v) firewire_bus = firewire->bus->secondary; } - // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the - // highest bus number on the pci bus. + /* If a riser card is used, this riser is detected on bus 4, so its secondary bus is the */ + /* highest bus number on the pci bus. */ riser = dev_find_device(0x3388, 0x0021, 0); if (!riser) riser = dev_find_device(0x3388, 0x0022, 0); @@ -77,11 +77,11 @@ static void *smp_write_config_table(void *v) if (riser) { /* Old riser card */ - // riser slot top 5:8.0 + /* riser slot top 5:8.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14); - // riser slot middle 5:9.0 + /* riser slot middle 5:9.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15); - // riser slot bottom 5:a.0 + /* riser slot bottom 5:a.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16); /* New Riser Card */ diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index e9143a8..e3063b2 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. +/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> #include <string.h> @@ -57,21 +57,21 @@ static void ich7_enable_lpc(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) { - lpt_en = 1 << 2; // enable LPT + lpt_en = 1 << 2; /* enable LPT */ } - // Enable Serial IRQ + /* Enable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // Set COM1/COM2 decode range + /* Set COM1/COM2 decode range */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 + /* Enable COM1/COM2/KBD/SuperIO1+2 */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); - // Enable HWM at 0xa00 + /* Enable HWM at 0xa00 */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); - // COM3 decode + /* COM3 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); - // COM4 decode + /* COM4 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); - // io 0x300 decode + /* io 0x300 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } @@ -101,10 +101,10 @@ static void early_superio_config_w83627thg(void) dev = PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_func_mode(dev); - pnp_write_config(dev, 0x24, 0xc6); // PNPCSV + pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */ - pnp_write_config(dev, 0x29, 0x43); // GPIO settings - pnp_write_config(dev, 0x2a, 0x40); // GPIO settings + pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */ + pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */ dev = PNP_DEV(0x2e, W83627THG_SP1); pnp_set_logical_device(dev); @@ -118,7 +118,6 @@ static void early_superio_config_w83627thg(void) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1); dev = PNP_DEV(0x2e, W83627THG_KBC); @@ -126,25 +125,24 @@ static void early_superio_config_w83627thg(void) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - // pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1); dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs + pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ pnp_set_enable(dev, 1); dev = PNP_DEV(0x2e, W83627THG_GPIO2); pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); // Just enable it + pnp_set_enable(dev, 1); /* Just enable it */ dev = PNP_DEV(0x2e, W83627THG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output - pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 - pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ + pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ + pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ dev = PNP_DEV(0x2e, W83627THG_FDC); pnp_set_logical_device(dev); @@ -166,14 +164,14 @@ static void early_superio_config_w83627thg(void) dev = PNP_DEV(0x4e, W83627THG_SP1); pnp_enter_func_mode(dev); - pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values + pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */ pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); pnp_set_irq(dev, PNP_IDX_IRQ0, 11); pnp_set_enable(dev, 1); dev = PNP_DEV(0x4e, W83627THG_SP2); - pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values + pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */ pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); pnp_set_irq(dev, PNP_IDX_IRQ0, 10); @@ -201,8 +199,6 @@ static void rcba_config(void) u32 reg32; /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; @@ -267,7 +263,7 @@ static void rcba_config(void) RCBA32(0x3418) = reg32; /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; + } static void early_ich7_init(void) @@ -275,15 +271,15 @@ static void early_ich7_init(void) uint8_t reg8; uint32_t reg32; - // program secondary mlt XXX byte? + /* program secondary mlt XXX byte? */ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - // reset rtc power status + /* reset rtc power status */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); reg8 &= ~(1 << 2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - // usb transient disconnect + /* usb transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); @@ -317,7 +313,7 @@ static void early_ich7_init(void) RCBA32(0x3e0e) |= (1 << 7); RCBA32(0x3e4e) |= (1 << 7); - // next step only on ich7m b0 and later: + /* next step only on ich7m b0 and later: */ reg32 = RCBA32(0x2034); reg32 &= ~(0x0f << 16); reg32 |= (5 << 16); diff --git a/src/mainboard/kontron/ktqm77/hda_verb.c b/src/mainboard/kontron/ktqm77/hda_verb.c index 720b5a9..fdbc977 100644 --- a/src/mainboard/kontron/ktqm77/hda_verb.c +++ b/src/mainboard/kontron/ktqm77/hda_verb.c @@ -18,9 +18,9 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x11060397, // Codec Vendor / Device ID: Via VT1708S - 0x11060000, // Subsystem ID - 0x0000000c, // Number of jacks + 0x11060397, /* Codec Vendor / Device ID: Via VT1708S */ + 0x11060000, /* Subsystem ID */ + 0x0000000c, /* Number of jacks */ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x11060000 */ AZALIA_SUBVENDOR(0x0, 0x11060000), @@ -95,9 +95,9 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI - 0x80860101, // Subsystem ID - 0x00000004, // Number of jacks + 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of jacks */ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x0, 0x80860101), diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index d2d7acf..b82102a 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -159,8 +159,8 @@ static int int15_handler(void) -// mainboard_enable is executed as first thing after -// enumerate_buses(). +/* mainboard_enable is executed as first thing after */ +/* enumerate_buses(). */ static void mainboard_enable(device_t dev) { diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 57a7fa2..a078b7d 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -78,8 +78,8 @@ static void pnp_exit_ext_func_mode(device_t dev) void mainboard_config_superio(void) { - int lvds_3v = 0; // 0 (5V) or 1 (3V3) - int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled + int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */ + int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */ device_t dev = PNP_DEV(0x2e, 0x9); pnp_enter_ext_func_mode(dev); pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ @@ -114,17 +114,19 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server + .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, .gbe_enable = 1, .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600,

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Patch set updated for coreboot: mainboard/kontron: Use C89 comments style & remove commented code
by HAOUAS Elyes 06 Oct '16

06 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16908 -gerrit commit fddda4e42fb8fc6edc70bc8059091302afbeba34 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Oct 6 19:49:55 2016 +0200 mainboard/kontron: Use C89 comments style & remove commented code Change-Id: I53a0344686921012f4e031842b5108aa4a7b79b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/kontron/986lcd-m/irq_tables.c | 20 +++++----- src/mainboard/kontron/986lcd-m/mainboard.c | 57 ++++++++++++----------------- src/mainboard/kontron/986lcd-m/mptable.c | 10 ++--- src/mainboard/kontron/986lcd-m/romstage.c | 52 ++++++++++++-------------- src/mainboard/kontron/ktqm77/hda_verb.c | 12 +++--- src/mainboard/kontron/ktqm77/mainboard.c | 4 +- src/mainboard/kontron/ktqm77/romstage.c | 16 ++++---- 7 files changed, 80 insertions(+), 91 deletions(-) diff --git a/src/mainboard/kontron/986lcd-m/irq_tables.c b/src/mainboard/kontron/986lcd-m/irq_tables.c index 0c5f403..fc67c22 100644 --- a/src/mainboard/kontron/986lcd-m/irq_tables.c +++ b/src/mainboard/kontron/986lcd-m/irq_tables.c @@ -29,22 +29,22 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */ + {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */ + {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */ + {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */ + {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */ + {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */ + {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */ + {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */ + {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */ {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */ {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 2a0c147..d729533 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -41,15 +41,15 @@ static void hwm_bank(u8 bank) #define FAN_CRUISE_CONTROL_THERMAL 2 #define FAN_SPEED_5625 0 -//#define FAN_TEMPERATURE_30DEGC 0 + struct fan_speed { u8 fan_in; u16 fan_speed; }; -// FANIN Target Speed Register -// FANIN = 337500 / RPM +/* FANIN Target Speed Register */ +/* FANIN = 337500 / RPM */ struct fan_speed fan_speeds[] = { { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, @@ -79,34 +79,27 @@ static void hwm_setup(void) get_option(&cpufan_control, "cpufan_cruise_control"); cpufan_speed = FAN_SPEED_5625; get_option(&cpufan_speed, "cpufan_speed"); - //cpufan_temperature = FAN_TEMPERATURE_30DEGC; - //get_option(&cpufan_temperature, "cpufan_temperature"); sysfan_control = FAN_CRUISE_CONTROL_DISABLED; get_option(&sysfan_control, "sysfan_cruise_control"); sysfan_speed = FAN_SPEED_5625; get_option(&sysfan_speed, "sysfan_speed"); - //sysfan_temperature = FAN_TEMPERATURE_30DEGC; - //get_option(&sysfan_temperature, "sysfan_temperature"); - - // hwm_write(0x31, 0x20); // AVCC high limit - // hwm_write(0x34, 0x06); // VIN2 low limit hwm_bank(0); - hwm_write(0x59, 0x20); // Diode Selection - hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + hwm_write(0x59, 0x20); /* Diode Selection */ + hwm_write(0x5d, 0x0f); /* All Sensors Diode, not Thermistor */ hwm_bank(4); - hwm_write(0x54, 0xf1); // SYSTIN temperature offset - hwm_write(0x55, 0x19); // CPUTIN temperature offset - hwm_write(0x56, 0xfc); // AUXTIN temperature offset + hwm_write(0x54, 0xf1); /* SYSTIN temperature offset */ + hwm_write(0x55, 0x19); /* CPUTIN temperature offset */ + hwm_write(0x56, 0xfc); /* AUXTIN temperature offset */ - hwm_bank(0x80); // Default + hwm_bank(0x80); /* Default */ u8 fan_config = 0; - // 00 FANOUT is Manual Mode - // 01 FANOUT is Thermal Cruise Mode - // 10 FANOUT is Fan Speed Cruise Mode + /* 00 FANOUT is Manual Mode */ + /* 01 FANOUT is Thermal Cruise Mode */ + /* 10 FANOUT is Fan Speed Cruise Mode */ switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; @@ -115,20 +108,20 @@ static void hwm_setup(void) case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; } - // This register must be written first + /* This register must be written first */ hwm_write(0x04, fan_config); switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); /* CPUFANIN target speed */ break; case FAN_CRUISE_CONTROL_THERMAL: printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", temperatures[cpufan_temperature].deg_celsius, temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); /* CPUFANIN target temperature */ break; } @@ -136,29 +129,27 @@ static void hwm_setup(void) case FAN_CRUISE_CONTROL_SPEED: printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); /* SYSFANIN target speed */ break; case FAN_CRUISE_CONTROL_THERMAL: printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", temperatures[sysfan_temperature].deg_celsius, temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); /* SYSFANIN target temperature */ break; } - hwm_write(0x0e, 0x02); // Fan Output Step Down Time - hwm_write(0x0f, 0x02); // Fan Output Step Up Time + hwm_write(0x0e, 0x02); /* Fan Output Step Down Time */ + hwm_write(0x0f, 0x02); /* Fan Output Step Up Time */ - hwm_write(0x47, 0xaf); // FAN divisor register - hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + hwm_write(0x47, 0xaf); /* FAN divisor register */ + hwm_write(0x4b, 0x84); /* AUXFANIN speed divisor */ - hwm_write(0x40, 0x01); // Init, but no SMI# + hwm_write(0x40, 0x01); /* Init, but no SMI# */ } - - -// mainboard_enable is executed as first thing after -// enumerate_buses(). +/* mainboard_enable is executed as first thing after */ +/* enumerate_buses(). */ static void mainboard_enable(device_t dev) { diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index 2ee2890..7db977d 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -39,8 +39,8 @@ static void *smp_write_config_table(void *v) firewire_bus = firewire->bus->secondary; } - // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the - // highest bus number on the pci bus. + /* If a riser card is used, this riser is detected on bus 4, so its secondary bus is the */ + /* highest bus number on the pci bus. */ riser = dev_find_device(0x3388, 0x0021, 0); if (!riser) riser = dev_find_device(0x3388, 0x0022, 0); @@ -77,11 +77,11 @@ static void *smp_write_config_table(void *v) if (riser) { /* Old riser card */ - // riser slot top 5:8.0 + /* riser slot top 5:8.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14); - // riser slot middle 5:9.0 + /* riser slot middle 5:9.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15); - // riser slot bottom 5:a.0 + /* riser slot bottom 5:a.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16); /* New Riser Card */ diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index e9143a8..e3063b2 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. +/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> #include <string.h> @@ -57,21 +57,21 @@ static void ich7_enable_lpc(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) { - lpt_en = 1 << 2; // enable LPT + lpt_en = 1 << 2; /* enable LPT */ } - // Enable Serial IRQ + /* Enable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // Set COM1/COM2 decode range + /* Set COM1/COM2 decode range */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 + /* Enable COM1/COM2/KBD/SuperIO1+2 */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); - // Enable HWM at 0xa00 + /* Enable HWM at 0xa00 */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); - // COM3 decode + /* COM3 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); - // COM4 decode + /* COM4 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); - // io 0x300 decode + /* io 0x300 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } @@ -101,10 +101,10 @@ static void early_superio_config_w83627thg(void) dev = PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_func_mode(dev); - pnp_write_config(dev, 0x24, 0xc6); // PNPCSV + pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */ - pnp_write_config(dev, 0x29, 0x43); // GPIO settings - pnp_write_config(dev, 0x2a, 0x40); // GPIO settings + pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */ + pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */ dev = PNP_DEV(0x2e, W83627THG_SP1); pnp_set_logical_device(dev); @@ -118,7 +118,6 @@ static void early_superio_config_w83627thg(void) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1); dev = PNP_DEV(0x2e, W83627THG_KBC); @@ -126,25 +125,24 @@ static void early_superio_config_w83627thg(void) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - // pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1); dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs + pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ pnp_set_enable(dev, 1); dev = PNP_DEV(0x2e, W83627THG_GPIO2); pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); // Just enable it + pnp_set_enable(dev, 1); /* Just enable it */ dev = PNP_DEV(0x2e, W83627THG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output - pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 - pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ + pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ + pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ dev = PNP_DEV(0x2e, W83627THG_FDC); pnp_set_logical_device(dev); @@ -166,14 +164,14 @@ static void early_superio_config_w83627thg(void) dev = PNP_DEV(0x4e, W83627THG_SP1); pnp_enter_func_mode(dev); - pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values + pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */ pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); pnp_set_irq(dev, PNP_IDX_IRQ0, 11); pnp_set_enable(dev, 1); dev = PNP_DEV(0x4e, W83627THG_SP2); - pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values + pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */ pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); pnp_set_irq(dev, PNP_IDX_IRQ0, 10); @@ -201,8 +199,6 @@ static void rcba_config(void) u32 reg32; /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; @@ -267,7 +263,7 @@ static void rcba_config(void) RCBA32(0x3418) = reg32; /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; + } static void early_ich7_init(void) @@ -275,15 +271,15 @@ static void early_ich7_init(void) uint8_t reg8; uint32_t reg32; - // program secondary mlt XXX byte? + /* program secondary mlt XXX byte? */ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - // reset rtc power status + /* reset rtc power status */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); reg8 &= ~(1 << 2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - // usb transient disconnect + /* usb transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); @@ -317,7 +313,7 @@ static void early_ich7_init(void) RCBA32(0x3e0e) |= (1 << 7); RCBA32(0x3e4e) |= (1 << 7); - // next step only on ich7m b0 and later: + /* next step only on ich7m b0 and later: */ reg32 = RCBA32(0x2034); reg32 &= ~(0x0f << 16); reg32 |= (5 << 16); diff --git a/src/mainboard/kontron/ktqm77/hda_verb.c b/src/mainboard/kontron/ktqm77/hda_verb.c index 720b5a9..fdbc977 100644 --- a/src/mainboard/kontron/ktqm77/hda_verb.c +++ b/src/mainboard/kontron/ktqm77/hda_verb.c @@ -18,9 +18,9 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x11060397, // Codec Vendor / Device ID: Via VT1708S - 0x11060000, // Subsystem ID - 0x0000000c, // Number of jacks + 0x11060397, /* Codec Vendor / Device ID: Via VT1708S */ + 0x11060000, /* Subsystem ID */ + 0x0000000c, /* Number of jacks */ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x11060000 */ AZALIA_SUBVENDOR(0x0, 0x11060000), @@ -95,9 +95,9 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI - 0x80860101, // Subsystem ID - 0x00000004, // Number of jacks + 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of jacks */ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x0, 0x80860101), diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index d2d7acf..b82102a 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -159,8 +159,8 @@ static int int15_handler(void) -// mainboard_enable is executed as first thing after -// enumerate_buses(). +/* mainboard_enable is executed as first thing after */ +/* enumerate_buses(). */ static void mainboard_enable(device_t dev) { diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 57a7fa2..cdd2d79 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -78,8 +78,8 @@ static void pnp_exit_ext_func_mode(device_t dev) void mainboard_config_superio(void) { - int lvds_3v = 0; // 0 (5V) or 1 (3V3) - int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled + int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */ + int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */ device_t dev = PNP_DEV(0x2e, 0x9); pnp_enter_ext_func_mode(dev); pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ @@ -114,17 +114,19 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server + .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, .gbe_enable = 1, .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600,

1 0

New patch to review for coreboot: mainboard/ibase: Use C89 comments style & remove commented code
by HAOUAS Elyes 06 Oct '16

06 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16909 -gerrit commit 1352379d69123cd1fa99d5937bf1d20df4e88624 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Oct 6 19:52:38 2016 +0200 mainboard/ibase: Use C89 comments style & remove commented code Change-Id: I3e51b75bd63605d832f337c4d8797b2b3c965394 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/ibase/mb899/irq_tables.c | 20 ++++++------- src/mainboard/ibase/mb899/mainboard.c | 4 +-- src/mainboard/ibase/mb899/mptable.c | 10 +++---- src/mainboard/ibase/mb899/romstage.c | 48 ++++++++++++++----------------- src/mainboard/ibase/mb899/superio_hwm.c | 51 ++++++++++++++------------------- 5 files changed, 61 insertions(+), 72 deletions(-) diff --git a/src/mainboard/ibase/mb899/irq_tables.c b/src/mainboard/ibase/mb899/irq_tables.c index 9c8a5cc..aaa6677 100644 --- a/src/mainboard/ibase/mb899/irq_tables.c +++ b/src/mainboard/ibase/mb899/irq_tables.c @@ -29,22 +29,22 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */ + {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */ + {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */ + {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */ + {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */ + {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */ + {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */ + {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */ + {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */ {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053 + {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet Marvell 88E8053 */ {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index 376e08a..24f807b 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -24,8 +24,8 @@ -// mainboard_enable is executed as first thing after -// enumerate_buses(). +/* mainboard_enable is executed as first thing after */ +/* enumerate_buses(). */ static void mainboard_enable(device_t dev) { diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c index 89fba6b..440929d 100644 --- a/src/mainboard/ibase/mb899/mptable.c +++ b/src/mainboard/ibase/mb899/mptable.c @@ -41,8 +41,8 @@ static void *smp_write_config_table(void *v) firewire_bus); } - // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the - // highest bus number on the pci bus. + /* If a riser card is used, this riser is detected on bus 4, so its secondary bus is the */ + /* highest bus number on the pci bus. */ riser = dev_find_device(0x3388, 0x0021, 0); if (!riser) riser = dev_find_device(0x3388, 0x0022, 0); @@ -94,11 +94,11 @@ static void *smp_write_config_table(void *v) if (riser) { /* Old riser card */ - // riser slot top 5:8.0 + /* riser slot top 5:8.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14); - // riser slot middle 5:9.0 + /* riser slot middle 5:9.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15); - // riser slot bottom 5:a.0 + /* riser slot bottom 5:a.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16); /* New Riser Card */ diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 3fa339f..13b68c0 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. +/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> #include <string.h> @@ -56,15 +56,15 @@ void setup_ich7_gpios(void) static void ich7_enable_lpc(void) { - // Enable Serial IRQ + /* Enable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // Set COM1/COM2 decode range + /* Set COM1/COM2 decode range */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 + /* Enable COM1/COM2/KBD/SuperIO1+2 */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); - // Enable HWM at 0x290 + /* Enable HWM at 0x290 */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291); - // io 0x300 decode + /* io 0x300 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } @@ -79,13 +79,13 @@ static void early_superio_config_w83627ehg(void) dev = DUMMY_DEV; pnp_enter_ext_func_mode(dev); - pnp_write_config(dev, 0x24, 0xc4); // PNPCSV + pnp_write_config(dev, 0x24, 0xc4); /* PNPCSV */ - pnp_write_config(dev, 0x29, 0x01); // GPIO settings - pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 - pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings? - pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? - pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? + pnp_write_config(dev, 0x29, 0x01); /* GPIO settings */ + pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings should be fc but gets set to 02 */ + pnp_write_config(dev, 0x2b, 0xc0); /* GPIO settings? */ + pnp_write_config(dev, 0x2c, 0x03); /* GPIO settings? */ + pnp_write_config(dev, 0x2d, 0x20); /* GPIO settings? */ dev = PNP_DEV(0x4e, W83627EHG_SP1); pnp_set_logical_device(dev); @@ -99,27 +99,25 @@ static void early_superio_config_w83627ehg(void) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1); - dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard + dev = PNP_DEV(0x4e, W83627EHG_KBC); /* Keyboard */ pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - //pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1); dev = PNP_DEV(0x4e, W83627EHG_GPIO2); pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); // Just enable it + pnp_set_enable(dev, 1); /* Just enable it */ dev = PNP_DEV(0x4e, W83627EHG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output - pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 - pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ + pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ + pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ dev = PNP_DEV(0x4e, W83627EHG_FDC); pnp_set_logical_device(dev); @@ -142,8 +140,6 @@ static void early_superio_config_w83627ehg(void) static void rcba_config(void) { /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; @@ -161,7 +157,7 @@ static void rcba_config(void) RCBA8(0x31ff) = 0x03; /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; + } static void early_ich7_init(void) @@ -169,15 +165,15 @@ static void early_ich7_init(void) uint8_t reg8; uint32_t reg32; - // program secondary mlt XXX byte? + /* program secondary mlt XXX byte? */ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - // reset rtc power status + /* reset rtc power status */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); reg8 &= ~(1 << 2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - // usb transient disconnect + /* usb transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); @@ -211,7 +207,7 @@ static void early_ich7_init(void) RCBA32(0x3e0e) |= (1 << 7); RCBA32(0x3e4e) |= (1 << 7); - // next step only on ich7m b0 and later: + /* next step only on ich7m b0 and later: */ reg32 = RCBA32(0x2034); reg32 &= ~(0x0f << 16); reg32 |= (5 << 16); diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index 7fb45f9..b1dd21e 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -29,7 +29,6 @@ #define FAN_CRUISE_CONTROL_THERMAL 2 #define FAN_SPEED_5625 0 -//#define FAN_TEMPERATURE_30DEGC 0 #define HWM_BASE 0x290 @@ -49,8 +48,8 @@ struct fan_speed { u16 fan_speed; }; -// FANIN Target Speed Register -// FANIN = 337500 / RPM +/* FANIN Target Speed Register */ +/* FANIN = 337500 / RPM */ struct fan_speed fan_speeds[] = { { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, @@ -80,34 +79,28 @@ void hwm_setup(void) get_option(&cpufan_control, "cpufan_cruise_control"); cpufan_speed = FAN_SPEED_5625; get_option(&cpufan_speed, "cpufan_speed"); - //cpufan_temperature = FAN_TEMPERATURE_30DEGC; - //get_option(&cpufan_temperature, "cpufan_temperature"); + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; get_option(&sysfan_control, "sysfan_cruise_control"); sysfan_speed = FAN_SPEED_5625; get_option(&sysfan_speed, "sysfan_speed"); - //sysfan_temperature = FAN_TEMPERATURE_30DEGC; - //get_option(&sysfan_temperature, "sysfan_temperature"); - - // hwm_write(0x31, 0x20); // AVCC high limit - // hwm_write(0x34, 0x06); // VIN2 low limit hwm_bank(0); - hwm_write(0x59, 0x20); // Diode Selection - hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + hwm_write(0x59, 0x20); /* Diode Selection */ + hwm_write(0x5d, 0x0f); /* All Sensors Diode, not Thermistor */ hwm_bank(4); - hwm_write(0x54, 0xf1); // SYSTIN temperature offset - hwm_write(0x55, 0x19); // CPUTIN temperature offset - hwm_write(0x56, 0xfc); // AUXTIN temperature offset + hwm_write(0x54, 0xf1); /* SYSTIN temperature offset */ + hwm_write(0x55, 0x19); /* CPUTIN temperature offset */ + hwm_write(0x56, 0xfc); /* AUXTIN temperature offset */ - hwm_bank(0x80); // Default + hwm_bank(0x80); /* Default */ u8 fan_config = 0; - // 00 FANOUT is Manual Mode - // 01 FANOUT is Thermal Cruise Mode - // 10 FANOUT is Fan Speed Cruise Mode + /* 00 FANOUT is Manual Mode */ + /* 01 FANOUT is Thermal Cruise Mode */ + /* 10 FANOUT is Fan Speed Cruise Mode */ switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; @@ -116,20 +109,20 @@ void hwm_setup(void) case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; } - // This register must be written first + /* This register must be written first */ hwm_write(0x04, fan_config); switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); /* CPUFANIN target speed */ break; case FAN_CRUISE_CONTROL_THERMAL: printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", temperatures[cpufan_temperature].deg_celsius, temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); /* CPUFANIN target temperature */ break; } @@ -137,21 +130,21 @@ void hwm_setup(void) case FAN_CRUISE_CONTROL_SPEED: printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); /* SYSFANIN target speed */ break; case FAN_CRUISE_CONTROL_THERMAL: printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", temperatures[sysfan_temperature].deg_celsius, temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); /* SYSFANIN target temperature */ break; } - hwm_write(0x0e, 0x02); // Fan Output Step Down Time - hwm_write(0x0f, 0x02); // Fan Output Step Up Time + hwm_write(0x0e, 0x02); /* Fan Output Step Down Time */ + hwm_write(0x0f, 0x02); /* Fan Output Step Up Time */ - hwm_write(0x47, 0xaf); // FAN divisor register - hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + hwm_write(0x47, 0xaf); /* FAN divisor register */ + hwm_write(0x4b, 0x84); /* AUXFANIN speed divisor */ - hwm_write(0x40, 0x01); // Init, but no SMI# + hwm_write(0x40, 0x01); /* Init, but no SMI# */ }

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coreboot-gerrit October 2016