coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

1 participants
1281 discussions

Patch set updated for coreboot: soc/intel/apollolake: Implement stage cache to improve resume time
by Brandon Breitenstein 05 Oct '16

05 Oct '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16833 -gerrit commit faec6ed3fa2d05493815c581b0dc6c2a9d9d5345 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Sep 30 13:57:12 2016 -0700 soc/intel/apollolake: Implement stage cache to improve resume time This patch enables stage cache to save ~40ms during S3 resume. It saves ramstage in the stage cache and restores it on resume so that ramstage does not have to reinitialize during the resume flow. Stage cache functionality is added to postcar stage since ramstage is called from postcar. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for Reef and tested ramstage being cached Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 2 ++ src/lib/Makefile.inc | 1 + src/lib/ext_stage_cache.c | 1 + src/soc/intel/apollolake/Kconfig | 6 +++++- src/soc/intel/apollolake/cpu.c | 8 ++++++-- src/soc/intel/apollolake/include/soc/smm.h | 4 +--- src/soc/intel/apollolake/memmap.c | 32 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/romstage.c | 15 ++++++++++++++ 8 files changed, 63 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 3986fe6..beeec7c 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -37,6 +37,8 @@ ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 394491c..67f8364 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -159,6 +159,7 @@ ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y) ramstage-y += ext_stage_cache.c romstage-y += ext_stage_cache.c +postcar-y += ext_stage_cache.c else ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 770097f..2a99188 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -126,3 +126,4 @@ static void stage_cache_setup(int is_recovery) ROMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) RAMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) +POSTCAR_CBMEM_INIT_HOOK(stage_cache_setup) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3a23dbd..6c178c3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS select COMMON_FADT select GENERIC_GPIO_LIB @@ -34,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE - select NO_STAGE_CACHE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PCIEXP_ASPM @@ -254,4 +254,8 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n +config SMM_RESERVED_SIZE + hex + default 0x100000 + endif diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f3cf050..e67842c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -102,19 +102,23 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, { void *smm_base; size_t smm_size; + void *handler_base; + size_t handler_size; /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ smm_region(&smm_base, &smm_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; + *perm_smbase = (uintptr_t)handler_base; + *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h index 7a9846e..740d02b 100644 --- a/src/soc/intel/apollolake/include/soc/smm.h +++ b/src/soc/intel/apollolake/include/soc/smm.h @@ -20,6 +20,7 @@ #include <stdint.h> #include <soc/gpio.h> +#include <fsp/memmap.h> /* These helpers are for performing SMM relocation. */ void southbridge_clear_smi_status(void); @@ -35,7 +36,4 @@ void southbridge_smm_enable_smi(void); /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts); -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); #endif diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index ea6f447..b4f981a 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -52,3 +52,35 @@ void smm_region(void **start, size_t *size) *start = (void *)smm_region_start(); *size = smm_region_size(); } + +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + if(sub_size < CONFIG_SMM_RESERVED_SIZE) + return -1; + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..2384ceb 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/northbridge.h> @@ -105,6 +106,9 @@ asmlinkage void car_stage_entry(void) uintptr_t top_of_ram; bool s3wake; struct chipset_power_state *ps = car_get_var_ptr(&power_state); + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; timestamp_add_now(TS_START_ROMSTAGE); @@ -135,6 +139,17 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); }

1 0

Patch set updated for coreboot: soc/intel/apollolake: Implement stage cache to improve resume time
by Brandon Breitenstein 05 Oct '16

05 Oct '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16833 -gerrit commit 00041fd86c3d9478e4a43d04d6ad04bf5d8218a9 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Sep 30 13:57:12 2016 -0700 soc/intel/apollolake: Implement stage cache to improve resume time This patch enables stage cache to save ~100ms during S3 resume. It saves ramstage in the stage cache and restores it on resume so that ramstage does not have to reinitialize during the resume flow. Stage cache functionality is added to postcar stage since ramstage is called from postcar. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for Reef and tested ramstage being cached Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 2 ++ src/lib/Makefile.inc | 1 + src/lib/ext_stage_cache.c | 1 + src/soc/intel/apollolake/Kconfig | 6 +++++- src/soc/intel/apollolake/cpu.c | 8 ++++++-- src/soc/intel/apollolake/include/soc/smm.h | 4 +--- src/soc/intel/apollolake/memmap.c | 32 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/romstage.c | 15 ++++++++++++++ 8 files changed, 63 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 3986fe6..beeec7c 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -37,6 +37,8 @@ ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 394491c..67f8364 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -159,6 +159,7 @@ ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y) ramstage-y += ext_stage_cache.c romstage-y += ext_stage_cache.c +postcar-y += ext_stage_cache.c else ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 770097f..2a99188 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -126,3 +126,4 @@ static void stage_cache_setup(int is_recovery) ROMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) RAMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) +POSTCAR_CBMEM_INIT_HOOK(stage_cache_setup) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3a23dbd..6c178c3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS select COMMON_FADT select GENERIC_GPIO_LIB @@ -34,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE - select NO_STAGE_CACHE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PCIEXP_ASPM @@ -254,4 +254,8 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n +config SMM_RESERVED_SIZE + hex + default 0x100000 + endif diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f3cf050..e67842c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -102,19 +102,23 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, { void *smm_base; size_t smm_size; + void *handler_base; + size_t handler_size; /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ smm_region(&smm_base, &smm_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; + *perm_smbase = (uintptr_t)handler_base; + *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h index 7a9846e..740d02b 100644 --- a/src/soc/intel/apollolake/include/soc/smm.h +++ b/src/soc/intel/apollolake/include/soc/smm.h @@ -20,6 +20,7 @@ #include <stdint.h> #include <soc/gpio.h> +#include <fsp/memmap.h> /* These helpers are for performing SMM relocation. */ void southbridge_clear_smi_status(void); @@ -35,7 +36,4 @@ void southbridge_smm_enable_smi(void); /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts); -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); #endif diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index ea6f447..b4f981a 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -52,3 +52,35 @@ void smm_region(void **start, size_t *size) *start = (void *)smm_region_start(); *size = smm_region_size(); } + +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + if(sub_size < CONFIG_SMM_RESERVED_SIZE) + return -1; + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..2384ceb 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/northbridge.h> @@ -105,6 +106,9 @@ asmlinkage void car_stage_entry(void) uintptr_t top_of_ram; bool s3wake; struct chipset_power_state *ps = car_get_var_ptr(&power_state); + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; timestamp_add_now(TS_START_ROMSTAGE); @@ -135,6 +139,17 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); }

1 0

Patch set updated for coreboot: soc/intel/apollolake:Implement stage cache to improve resume time
by Brandon Breitenstein 05 Oct '16

05 Oct '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16833 -gerrit commit b91aa366d0e6cec832585efb148c75730379db6c Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Sep 30 13:57:12 2016 -0700 soc/intel/apollolake:Implement stage cache to improve resume time This patch enables stage cache to save some time during resume. It saves ramstage in the stage cache and restores it on resume so that it does not have to reinitialize ramstage during the resume flow. Stage cache functionality is added to postcar stage since ramstage is called from postcar. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for Reef and tested ramstage being cached Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 2 ++ src/lib/Makefile.inc | 1 + src/lib/ext_stage_cache.c | 1 + src/soc/intel/apollolake/Kconfig | 6 +++++- src/soc/intel/apollolake/cpu.c | 8 ++++++-- src/soc/intel/apollolake/include/soc/smm.h | 4 +--- src/soc/intel/apollolake/memmap.c | 32 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/romstage.c | 15 ++++++++++++++ 8 files changed, 63 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 3986fe6..beeec7c 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -37,6 +37,8 @@ ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 394491c..67f8364 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -159,6 +159,7 @@ ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y) ramstage-y += ext_stage_cache.c romstage-y += ext_stage_cache.c +postcar-y += ext_stage_cache.c else ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 770097f..2a99188 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -126,3 +126,4 @@ static void stage_cache_setup(int is_recovery) ROMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) RAMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) +POSTCAR_CBMEM_INIT_HOOK(stage_cache_setup) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3a23dbd..6c178c3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS select COMMON_FADT select GENERIC_GPIO_LIB @@ -34,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE - select NO_STAGE_CACHE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PCIEXP_ASPM @@ -254,4 +254,8 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n +config SMM_RESERVED_SIZE + hex + default 0x100000 + endif diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f3cf050..e67842c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -102,19 +102,23 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, { void *smm_base; size_t smm_size; + void *handler_base; + size_t handler_size; /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ smm_region(&smm_base, &smm_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; + *perm_smbase = (uintptr_t)handler_base; + *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h index 7a9846e..740d02b 100644 --- a/src/soc/intel/apollolake/include/soc/smm.h +++ b/src/soc/intel/apollolake/include/soc/smm.h @@ -20,6 +20,7 @@ #include <stdint.h> #include <soc/gpio.h> +#include <fsp/memmap.h> /* These helpers are for performing SMM relocation. */ void southbridge_clear_smi_status(void); @@ -35,7 +36,4 @@ void southbridge_smm_enable_smi(void); /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts); -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); #endif diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index ea6f447..b4f981a 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -52,3 +52,35 @@ void smm_region(void **start, size_t *size) *start = (void *)smm_region_start(); *size = smm_region_size(); } + +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + if(sub_size < CONFIG_SMM_RESERVED_SIZE) + return -1; + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..2384ceb 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/northbridge.h> @@ -105,6 +106,9 @@ asmlinkage void car_stage_entry(void) uintptr_t top_of_ram; bool s3wake; struct chipset_power_state *ps = car_get_var_ptr(&power_state); + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; timestamp_add_now(TS_START_ROMSTAGE); @@ -135,6 +139,17 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); }

1 0

Patch set updated for coreboot: soc/intel/apollolake:Implement stage cache to improve resume time
by Brandon Breitenstein 05 Oct '16

05 Oct '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16833 -gerrit commit 2a0f36f87c458eb5fd444b1a58f67057054c0fad Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Sep 30 13:57:12 2016 -0700 soc/intel/apollolake:Implement stage cache to improve resume time This patch enables stage cache to save some time during resume. It saves ramstage in the stage cache and restores it on resume so that it does not have to reinitialize ramstage during the resume flow. Stage cache functionality is added to postcar stage since ramstage is called from postcar. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for Reef and tested ramstage being cached Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 2 ++ src/lib/Makefile.inc | 1 + src/lib/ext_stage_cache.c | 1 + src/soc/intel/apollolake/Kconfig | 6 +++++- src/soc/intel/apollolake/cpu.c | 8 ++++++-- src/soc/intel/apollolake/include/soc/smm.h | 4 +--- src/soc/intel/apollolake/memmap.c | 32 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/romstage.c | 15 ++++++++++++++ 8 files changed, 63 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 3986fe6..beeec7c 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -37,6 +37,8 @@ ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 394491c..67f8364 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -159,6 +159,7 @@ ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y) ramstage-y += ext_stage_cache.c romstage-y += ext_stage_cache.c +postcar-y += ext_stage_cache.c else ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 770097f..2a99188 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -126,3 +126,4 @@ static void stage_cache_setup(int is_recovery) ROMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) RAMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) +POSTCAR_CBMEM_INIT_HOOK(stage_cache_setup) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3a23dbd..6c178c3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS select COMMON_FADT select GENERIC_GPIO_LIB @@ -34,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE - select NO_STAGE_CACHE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PCIEXP_ASPM @@ -254,4 +254,8 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n +config SMM_RESERVED_SIZE + hex + default 0x100000 + endif diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f3cf050..e67842c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -102,19 +102,23 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, { void *smm_base; size_t smm_size; + void *handler_base; + size_t handler_size; /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ smm_region(&smm_base, &smm_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; + *perm_smbase = (uintptr_t)handler_base; + *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h index 7a9846e..740d02b 100644 --- a/src/soc/intel/apollolake/include/soc/smm.h +++ b/src/soc/intel/apollolake/include/soc/smm.h @@ -20,6 +20,7 @@ #include <stdint.h> #include <soc/gpio.h> +#include <fsp/memmap.h> /* These helpers are for performing SMM relocation. */ void southbridge_clear_smi_status(void); @@ -35,7 +36,4 @@ void southbridge_smm_enable_smi(void); /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts); -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); #endif diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index ea6f447..41744e5 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -52,3 +52,35 @@ void smm_region(void **start, size_t *size) *start = (void *)smm_region_start(); *size = smm_region_size(); } + +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + if(sub_size < CONFIG_SMM_RESERVED_SIZE) + return -1; + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..2384ceb 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/northbridge.h> @@ -105,6 +106,9 @@ asmlinkage void car_stage_entry(void) uintptr_t top_of_ram; bool s3wake; struct chipset_power_state *ps = car_get_var_ptr(&power_state); + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; timestamp_add_now(TS_START_ROMSTAGE); @@ -135,6 +139,17 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); }

1 0

New patch to review for coreboot: southbridge/nvidia: Remove commented code
by HAOUAS Elyes 05 Oct '16

05 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16899 -gerrit commit 25ad2c25c7b33edf39aa71628299ba76511902c1 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 22:17:30 2016 +0200 southbridge/nvidia: Remove commented code Change-Id: Ice4a5cae1a289852895012bb55035707b54cefb5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/nvidia/ck804/early_setup.c | 4 --- src/southbridge/nvidia/ck804/lpc.c | 6 ---- src/southbridge/nvidia/ck804/pci.c | 7 ----- src/southbridge/nvidia/ck804/sata.c | 35 --------------------- src/southbridge/nvidia/ck804/smbus.h | 43 -------------------------- src/southbridge/nvidia/mcp55/bootblock.c | 6 +--- src/southbridge/nvidia/mcp55/early_setup_car.c | 19 ------------ src/southbridge/nvidia/mcp55/lpc.c | 14 --------- src/southbridge/nvidia/mcp55/mcp55.c | 11 ------- 9 files changed, 1 insertion(+), 144 deletions(-) diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index abcb913..1d4999c 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -300,10 +300,6 @@ static void ck804_early_setup(void) setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); #endif -#if 0 - dump_io_resources(ANACTRL_IO_BASE); - dump_io_resources(SYSCTRL_IO_BASE); -#endif } static int ck804_early_setup_x(void) diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index d15ef8e..2b0bdd5 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -136,12 +136,6 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on * 12) + (on >> 1), (on & 1) * 5); } -#if 0 - /* Enable Port 92 fast reset (default is enabled). */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif /* Set up NMI on errors. */ byte = inb(0x70); /* RTC70 */ diff --git a/src/southbridge/nvidia/ck804/pci.c b/src/southbridge/nvidia/ck804/pci.c index 8ccf80c..5f21e09 100644 --- a/src/southbridge/nvidia/ck804/pci.c +++ b/src/southbridge/nvidia/ck804/pci.c @@ -33,13 +33,6 @@ static void pci_init(struct device *dev) dword |= (1 << 30); /* Clear possible errors */ pci_write_config32(dev, 0x04, dword); -#if 0 - word = pci_read_config16(dev, 0x48); - word |= (1 << 0); /* MRL2MRM */ - word |= (1 << 2); /* MR2MRM */ - pci_write_config16(dev, 0x48, word); -#endif - #if 1 dword = pci_read_config32(dev, 0x4c); dword |= 0x00440000; /* TABORT_SER_ENABLE Park Last Enable. */ diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c index b67cf28..c5dc56e 100644 --- a/src/southbridge/nvidia/ck804/sata.c +++ b/src/southbridge/nvidia/ck804/sata.c @@ -51,13 +51,6 @@ static void sata_com_reset(struct device *dev, unsigned reset) *(base + 8) = dword; *(base + 0x48) = dword; -#if 0 - udelay(1000); - dword &= ~(0xf); - *(base + 8) = dword; - *(base + 0x48) = dword; -#endif - if (reset) return; @@ -109,17 +102,6 @@ static void sata_init(struct device *dev) dword |= (1 << 1); printk(BIOS_DEBUG, "SATA P\n"); } -#if 0 - /* Write back */ - dword |= (1 << 12); - dword |= (1 << 14); -#endif - -#if 0 - /* ADMA */ - dword |= (1 << 16); - dword |= (1 << 17); -#endif #if 1 /* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */ @@ -128,23 +110,6 @@ static void sata_init(struct device *dev) #endif pci_write_config32(dev, 0x50, dword); -#if 0 - /* SLUMBER_DURING_D3 */ - dword = pci_read_config32(dev, 0x7c); - dword &= ~(1 << 4); - pci_write_config32(dev, 0x7c, dword); - - dword = pci_read_config32(dev, 0xd0); - dword &= ~(0xff << 24); - dword |= (0x68 << 24); - pci_write_config32(dev, 0xd0, dword); - - dword = pci_read_config32(dev, 0xe0); - dword &= ~(0xff << 24); - dword |= (0x68 << 24); - pci_write_config32(dev, 0xe0, dword); -#endif - dword = pci_read_config32(dev, 0xf8); dword |= 2; pci_write_config32(dev, 0xf8, dword); diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h index 6d0c510..40b8cb7 100644 --- a/src/southbridge/nvidia/ck804/smbus.h +++ b/src/southbridge/nvidia/ck804/smbus.h @@ -34,25 +34,6 @@ static inline void smbus_delay(void) outb(0x80, 0x80); } -#if 0 -/* Not needed, upon write to PRTCL, the status will be auto-cleared. */ -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) - return 0; - outb(val, smbus_io_base + SMBHSTSTAT); - } while (--loops); - return -2; -} -#endif - static int smbus_wait_until_done(unsigned smbus_io_base) { unsigned long loops; @@ -72,12 +53,6 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { unsigned char global_status_register, byte; -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - /* Set the device I'm talking to. */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); smbus_delay(); @@ -112,12 +87,6 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, { unsigned global_status_register; -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); @@ -151,12 +120,6 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, { unsigned char global_status_register, byte; -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - /* Set the device I'm talking to. */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); smbus_delay(); @@ -191,12 +154,6 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, { unsigned global_status_register; -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index b77463a..3d46e4b 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -28,11 +28,7 @@ static void mcp55_enable_rom(void) pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ -#if 0 - /* Default MCP55 LPC single */ - addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0); -#else -// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0); + addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0); #endif diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 76947ec..7f1d03b 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -253,7 +253,6 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, #if CONFIG_MCP55_USE_AZA RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, - // RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1 << 14), (1 << 14), #endif #ifdef MCP55_MB_SETUP @@ -326,22 +325,6 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, PCI_DEV(busn[j], devn[j], 0), io_base[j]); } -#if 0 - for (j = 0; j < mcp55_num; j++) { - // PCI-E (XSPLL) SS table 0x40, x044, 0x48 - // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 - // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, - io_base[j] + ANACTRL_IO_BASE + 0x44, - io_base[j] + ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, - io_base[j] + ANACTRL_IO_BASE + 0xb4, - io_base[j] + ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, - io_base[j] + ANACTRL_IO_BASE + 0xc4, - io_base[j] + ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); - } -#endif } #ifndef HT_CHAIN_NUM_MAX @@ -405,7 +388,5 @@ out: mcp55_early_clear_port(mcp55_num, busn, devn, io_base); - // set_ht_link_mcp55(HT_CHAIN_NUM_MAX); - return 0; } diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 824abc5..afc6e64 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -91,11 +91,6 @@ static void lpc_init(device_t dev) lpc_common_init(dev, 1); -#if 0 - /* Posted memory write enable. */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1 << 0)); -#endif /* power after power fail */ #if 1 @@ -122,13 +117,6 @@ static void lpc_init(device_t dev) (on * 12) + (on >> 1), (on & 1) * 5); } -#if 0 - /* Enable Port 92 fast reset (default is enabled). */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif - /* Enable error reporting. */ /* Set up sync flood detected. */ byte = pci_read_config8(dev, 0x47); @@ -258,7 +246,6 @@ static struct device_operations lpc_ops = { .enable_resources = mcp55_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_lpc_bus, -// .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; static const unsigned short lpc_ids[] = { @@ -295,7 +282,6 @@ static struct device_operations lpc_slave_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_slave_init, -// .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c index cfe5e17..7c43fea 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ b/src/southbridge/nvidia/mcp55/mcp55.c @@ -68,9 +68,7 @@ void mcp55_enable(device_t dev) if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid >> 16) & 0xffff; -// vendorid &= 0xffff; } else { -// vendorid = dev->vendor; deviceid = dev->device; } @@ -200,15 +198,6 @@ void mcp55_enable(device_t dev) | (1 << 11) | (1 << 10) | (1 << 9)); pci_write_config32(sm_dev, 0xe8, final_reg); /* Enable all at first. */ -#if 0 - reg_old = reg = pci_read_config32(sm_dev, 0xe4); -// reg |= (1 << 0); - reg &= ~(0x3f << 4); - if (reg != reg_old) { - printk(BIOS_DEBUG, "mcp55.c pcie enabled\n"); - pci_write_config32(sm_dev, 0xe4, reg); - } -#endif } if (!dev->enabled) {

1 0

Patch set updated for coreboot: src/northbridge/via: Remove commented code
by HAOUAS Elyes 05 Oct '16

05 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16898 -gerrit commit 15fa7eff6534a12b8d618e52582424ff6b74f378 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 21:02:23 2016 +0200 src/northbridge/via: Remove commented code Change-Id: Ic589b26c6c94df12e1fe218d079018db8b38fbd9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/via/cx700/early_smbus.c | 6 - src/northbridge/via/cx700/lpc.c | 2 - src/northbridge/via/cx700/raminit.c | 8 - src/northbridge/via/vx800/detection.c | 2 - src/northbridge/via/vx800/dev_init.c | 363 +-------------------- src/northbridge/via/vx800/dram_init.h | 14 +- src/northbridge/via/vx800/dram_util.c | 1 - src/northbridge/via/vx800/drdy_bl.c | 89 ----- src/northbridge/via/vx800/driving_clk_phase_data.h | 32 -- src/northbridge/via/vx800/driving_setting.c | 2 - src/northbridge/via/vx800/early_serial.c | 3 - src/northbridge/via/vx800/early_smbus.c | 1 - src/northbridge/via/vx800/ide.c | 54 --- src/northbridge/via/vx800/lpc.c | 18 - src/northbridge/via/vx800/northbridge.c | 16 - src/northbridge/via/vx800/rank_map.c | 1 - src/northbridge/via/vx800/uma_ram_setting.c | 112 ------- src/northbridge/via/vx800/vga.c | 20 -- src/northbridge/via/vx800/vx800.h | 3 - src/northbridge/via/vx900/chrome9hd.c | 1 - src/northbridge/via/vx900/lpc.c | 2 +- src/northbridge/via/vx900/raminit_ddr3.c | 10 +- 22 files changed, 4 insertions(+), 756 deletions(-) diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c index 44aa743..b501baf 100644 --- a/src/northbridge/via/cx700/early_smbus.c +++ b/src/northbridge/via/cx700/early_smbus.c @@ -102,7 +102,6 @@ static void smbus_reset(void) /* Public functions */ static void set_ics_data(unsigned char dev, int data, char len) { - //int i; smbus_reset(); /* clear host data port */ outb(0x00, SMBHSTDAT0); @@ -114,7 +113,6 @@ static void set_ics_data(unsigned char dev, int data, char len) /* fill blocktransfer array */ if (dev == 0xd2) { - //char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b}; outb(0x0d, SMBBLKDAT); outb(0x00, SMBBLKDAT); outb(0x3f, SMBBLKDAT); @@ -130,7 +128,6 @@ static void set_ics_data(unsigned char dev, int data, char len) outb(0x8d, SMBBLKDAT); outb(0x9b, SMBBLKDAT); } else { - //char d4_data[] = {0x08,0xff,0x3f,0x00,0x00,0xff,0xff,0xff,0xff}; outb(0x08, SMBBLKDAT); outb(0xff, SMBBLKDAT); outb(0x3f, SMBBLKDAT); @@ -142,9 +139,6 @@ static void set_ics_data(unsigned char dev, int data, char len) outb(0xff, SMBBLKDAT); } - //for (i = 0; i < len; i++) - // outb(data[i],SMBBLKDAT); - outb(dev, SMBXMITADD); outb(0, SMBHSTCMD); outb(len, SMBHSTDAT0); diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index e9e4d98..c90dab7 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -110,7 +110,6 @@ static void setup_pm(device_t dev) /* GP2 Timer Counter */ pci_write_config8(dev, 0x99, 0xfb); /* GP3 Timer Counter */ - //pci_write_config8(dev, 0x9a, 0x20); /* Multi Function Select 1 */ pci_write_config8(dev, 0xe4, 0x00); @@ -169,7 +168,6 @@ static void cx700_set_lpc_registers(struct device *dev) pci_write_config8(dev, 0x6C, enables); // Map 4MB of FLASH into the address space -// pci_write_config8(dev, 0x41, 0x7f); // Set bit 6 of 0x40, because Award does it (IO recovery time) // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index aad851d..f8d709c 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -815,7 +815,6 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) /* Clock Phase Control for FeedBack Mode */ regs = pci_read_config8(MEMCTRL, 0x90); -// regs |= 0x80; pci_write_config8(MEMCTRL, 0x90, regs); regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ); @@ -1343,13 +1342,6 @@ static void sdram_enable(const struct mem_controller *ctrl) /****************************************************************/ /* Find out the lowest Bank Interleave and Set Register */ /****************************************************************/ -#if 0 - //TODO - reg8 = pci_read_config8(MEMCTRL, 0x69); - reg8 &= ~0xc0; - reg8 |= 0x80; //8 banks - pci_write_config8(MEMCTRL, 0x69, reg8); -#endif dl = 2; for (i = 0; i < 4; i++) { reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i)); diff --git a/src/northbridge/via/vx800/detection.c b/src/northbridge/via/vx800/detection.c index ce643a0..bbedd38 100644 --- a/src/northbridge/via/vx800/detection.c +++ b/src/northbridge/via/vx800/detection.c @@ -52,8 +52,6 @@ CB_STATUS DRAMDetect(DRAM_SYS_ATTR *DramAttr) if (CB_SUCCESS == Status) { /* 64bit or 128Bit */ - // if (RAMTYPE_SDRAMDDR == DramAttr->DramType) - /* Select command rate. */ DRAMCmdRate(DramAttr); } diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index 7ac5fe1..1bc779f 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -61,10 +61,7 @@ static const u8 DramRegTbl[][3] = { * R/W DRAM. */ - // {0x79, 0x00, 0x8F }, {0x85, 0x00, 0x00}, - // {0x90, 0x87, 0x78 }, - // {0x91, 0x00, 0x46 }, {0x40, 0x00, 0x00}, {0, 0, 0} @@ -94,9 +91,6 @@ void DRAMRegInitValue(DRAM_SYS_ATTR *DramAttr) Data |= 0x0; /* CHA + CHC */ pci_write_config8(MEMCTRL, 0x6c, Data); - // Data = 0xAA; - // pci_write_config8(MEMCTRL, 0xb1, Data); - // set CHB DQSB input delay, or else will meet error which // is some byte is right but another bit is error. Data = pci_read_config8(MEMCTRL, 0xff); @@ -104,9 +98,6 @@ void DRAMRegInitValue(DRAM_SYS_ATTR *DramAttr) pci_write_config8(MEMCTRL, 0xff, Data); // enable CHC RXDB[7] - // Data = pci_read_config8(MEMCTRL, 0xdb); - // Data = (Data & 0x7F) | 0x80; - // pci_write_config8(MEMCTRL, 0xdb, Data); // rx62[2:0], CHA and CHB CL Data = pci_read_config8(MEMCTRL, 0x62); @@ -473,7 +464,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr) Twr = (Data & 0xE0) >> 5; AccessAddr += CHA_DDR2_Twr_table[Twr]; - // AccessAddr = 0x1012D8; + DimmRead(AccessAddr); /* Set MRS command. */ PRINT_DEBUG_MEM("Step 18 Address"); PRINT_DEBUG_MEM_HEX32(AccessAddr); @@ -517,358 +508,6 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr) } /*=================================================================== -Function : InitDDR2_CHB() -Precondition : -Input : - DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard -Output : Void -Purpose : Initialize DDR2 of CHB by standard sequence -Reference : -===================================================================*/ -/*// DLL: Enable Reset -static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17 = 1, A9 = 1), (A11 = 1)(cpu address) -//u32 CHB_MRS_DLL_75[2] = { 0x00020020 | (1 << 20), 0x00000800 }; // with 75 ohm (A17 = 1, A5 = 1), (A11 = 1)(cpu address) -// CPU(DRAM) -// { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 } -// { DLL: reset. A11(MA8)=1 } -// -// DDR2 CL = 2 CL = 3 CL = 4 CL = 5 (Burst type = interleave)(WR fine tune in code) -static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL = 4; Use 1X-bandwidth MA table to init DRAM - -// MA11 MA10(AP) MA9 -#define CHB_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h -#define CHB_MRS_DDR2_TWR3 (0 << 13) + (1 << 20) + (0 << 12) // Value = 100000h -#define CHB_MRS_DDR2_TWR4 (0 << 13) + (1 << 20) + (1 << 12) // Value = 101000h -#define CHB_MRS_DDR2_TWR5 (1 << 13) + (0 << 20) + (0 << 12) // Value = 002000h -#define CHB_MRS_DDR2_TWR6 (1 << 13) + (0 << 20) + (1 << 12) // Value = 003000h - -// DDR2 Twr = 2 Twr = 3 Twr = 4 Twr = 5 -static const u32 CHB_DDR2_Twr_table[5] = { CHB_MRS_DDR2_TWR2, CHB_MRS_DDR2_TWR3, CHB_MRS_DDR2_TWR4, CHB_MRS_DDR2_TWR5, CHB_MRS_DDR2_TWR6 }; - -#define CHB_OCD_Exit_150ohm 0x20200 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 1,MA2 = 0 (DRAM bus address) -// A17 = 1, A12 = A11 = A10 = 0,A9 = 1 ,A5 = 0 (CPU address) -#define CHB_OCD_Default_150ohm 0x21E00 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 1,MA2 = 0 (DRAM bus address) -// A17 = 1, A12 = A11 = A10 = 1,A9 = 1 ,A5 = 0 (CPU address) -//#define CHB_OCD_Exit_75ohm 0x20020 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 0,MA2 = 1 (DRAM bus address) -// A17 = 1, A12 = A11 = A10 = 0,A9 = 0 ,A5 = 1 (CPU address) -//#define CHB_OCD_Default_75ohm 0x21C20 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 0,MA2 = 1 (DRAM bus address) -// A17 = 1, A12 = A11 = A10 = 1,A9 = 0 ,A5 = 1 (CPU address) -void InitDDR2CHB( - DRAM_SYS_ATTR *DramAttr - ) - -{ - u8 Data; - u8 Idx, CL, BL, Twr; - u32 AccessAddr; - - Data = 0x80; - pci_write_config8(MEMCTRL, 0x54, Data); - - // step3. - //disable bank paging and multi page - Data = pci_read_config8(MEMCTRL, 0x69); - Data &= ~0x03; - pci_write_config8(MEMCTRL, 0x69, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step 4. Initialize CHB begin - Data = pci_read_config8(MEMCTRL, 0xd3); - Data |= 0x40; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //Step 5. NOP command enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x08; - pci_write_config8(MEMCTRL, 0xd7, Data); - - //Step 6. issue a nop cycle,RegD3[7] 0 -> 1 - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - // Step 7. - // A minimum pause of 200u sec will be provided after the NOP. - // - <<< reduce BOOT UP time >>> - - // Loop 200us - for (Idx = 0; Idx < 0x10; Idx++) - WaitMicroSec(10); - - // Step 8. - // all banks precharge command enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x10; - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step 9. issue a precharge all cycle,RegD3[7] 0 -> 1 - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step10. EMRS enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x18; - pci_write_config8(MEMCTRL, 0xd7, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xC7; - Data |= 0x08; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step11. EMRS DLL Enable and Disable DQS - AccessAddr = CHB_MRS_DLL_150[0] >> 3; - Data =(u8) (AccessAddr & 0xff); - pci_write_config8(MEMCTRL, 0xd9, Data); - - Data = (u8)((AccessAddr & 0xff00) >> 8); - pci_write_config8(MEMCTRL, 0xda, Data); - - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xF9; - Data |= (u8)((AccessAddr & 0x30000) >> 15); - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step12. issue EMRS cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step13. MSR enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x18; - pci_write_config8(MEMCTRL, 0xd7, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xC7; - Data |= 0x00; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step 14. MSR DLL Reset - AccessAddr = CHB_MRS_DLL_150[1] >> 3; - Data =(u8) (AccessAddr & 0xff); - pci_write_config8(MEMCTRL, 0xd9, Data); - - Data = (u8)((AccessAddr & 0xff00) >> 8); - pci_write_config8(MEMCTRL, 0xda, Data); - - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xF9; - Data |= (u8)((AccessAddr & 0x30000) >> 15); - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step15. issue MRS cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //clear the address - Data = 0x00; - pci_write_config8(MEMCTRL, 0xda, Data); - - //step16. all banks precharge command enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x10; - pci_write_config8(MEMCTRL, 0xd7, Data); - - - // step17. issue precharge all cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step18. CBR cycle enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x20; - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step 19.20.21 - //repeat issue 8 CBR cycle, between each cycle stop 100us - for (Idx = 0; Idx < 8; Idx++) - { - // issue CBR cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - WaitMicroSec(200); - } - - //step22. MSR enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x18; - pci_write_config8(MEMCTRL, 0xd7, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xC7; - Data |= 0x00; - pci_write_config8(MEMCTRL, 0xd3, Data); - - - //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.) - //------------------------------------------------------------- - //Burst Length : really offset Rx6c[1] - Data = pci_read_config8(MEMCTRL, 0x6C); - BL = (Data & 0x02) >> 1; - - // CL = really offset RX62[2:0] - Data = pci_read_config8(MEMCTRL, 0x62); - CL = Data & 0x03; - - AccessAddr = (u32)(CHB_DDR2_MRS_table[CL]); - if (BL) - { - AccessAddr += 8; - } - - //Write recovery : really offset Rx63[7:5] - Data = pci_read_config8(MEMCTRL, 0x63); - Twr = (Data & 0xE0) >> 5; - - AccessAddr += CHB_DDR2_Twr_table[Twr]; - //MSR Address use addr[20:3] - AccessAddr >>= 3; - - //step 23. MSR command - Data = (u8)(AccessAddr & 0xFF); - pci_write_config8(MEMCTRL, 0xD9, Data); - - Data = (u8)((AccessAddr & 0xFF00) >> 8); - pci_write_config8(MEMCTRL, 0xda, Data); - - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xF9; - Data |= (u8)(((AccessAddr & 0x30000)>>16) << 1); - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step 24. issue MRS cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step 25. EMRS enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x18; - pci_write_config8(MEMCTRL, 0xd7, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xC7; - Data |= 0x08; - pci_write_config8(MEMCTRL, 0xd3, Data); - - - //step 26. OCD default - AccessAddr = (CHB_OCD_Default_150ohm) >> 3; - Data =(u8) (AccessAddr & 0xff); - pci_write_config8(MEMCTRL, 0xd9, Data); - - Data = (u8)((AccessAddr & 0xff00) >> 8); - pci_write_config8(MEMCTRL, 0xda, Data); - - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xF9; - Data |= (u8)((AccessAddr & 0x30000) >> 15); - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step 27. issue EMRS cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step 25. EMRS enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x18; - pci_write_config8(MEMCTRL, 0xd7, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xC7; - Data |= 0x08; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step 28. OCD Exit - AccessAddr = (CHB_OCD_Exit_150ohm) >> 3; - Data =(u8) (AccessAddr & 0xff); - pci_write_config8(MEMCTRL, 0xd9, Data); - - Data = (u8)((AccessAddr & 0xff00) >> 8); - pci_write_config8(MEMCTRL, 0xda, Data); - - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xF9; - Data |= (u8)((AccessAddr & 0x30000) >> 15); - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step 29. issue EMRS cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //clear all the address - Data = 0x00; - pci_write_config8(MEMCTRL, 0xd9, Data); - - Data = 0x00; - pci_write_config8(MEMCTRL, 0xda, Data); - - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xF9; - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step 30. normal SDRAM Mode - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x00; - pci_write_config8(MEMCTRL, 0xd7, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xC7; - Data |= 0x00; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step 31. exit the initialization mode - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xBF; - pci_write_config8(MEMCTRL, 0xd3, Data); - - - //step 32. Enable bank paging and multi page - Data = pci_read_config8(MEMCTRL, 0x69); - Data |= 0x03; - pci_write_config8(MEMCTRL, 0x69, Data); -} -*/ - -/*=================================================================== Function : InitDDR2CHC() Precondition : Input : diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h index e4e143a..3e3f6af 100644 --- a/src/northbridge/via/vx800/dram_init.h +++ b/src/northbridge/via/vx800/dram_init.h @@ -33,7 +33,6 @@ //Dram Freq #define DIMMFREQ_800 400 #define DIMMFREQ_667 333 -//#define DIMMFREQ_600 300 #define DIMMFREQ_533 266 #define DIMMFREQ_400 200 #define DIMMFREQ_333 166 @@ -66,9 +65,7 @@ #define BURSTLENGTH4 4 //Data Width -//#define DATAWIDTHX16 16 -//#define DATAWIDTHX8 8 -//#define DATAWIDTHX4 4 + #define SPD_MEMORY_TYPE 2 /*Memory type FPM,EDO,SDRAM,DDR,DDR2 */ #define SPD_SDRAM_ROW_ADDR 3 /*Number of row addresses on this assembly */ @@ -133,17 +130,8 @@ typedef struct _DRAM_CONFIG_DATA { u8 CmdRate; u8 DualEn; - //u8 IntLv0; - //u8 IntLv1; - //u8 Ba0Sel; - //u8 Ba1Sel; - //u8 Ba2Sel; u8 BaScmb; u8 DrdyTiming; - //u8 Above4G; - //u8 RdsaitMode; - //u8 Rdsait; - //u8 TopPerf; u16 UMASize; } DRAM_CONFIG_DATA; diff --git a/src/northbridge/via/vx800/dram_util.c b/src/northbridge/via/vx800/dram_util.c index bb64989..31297b9 100644 --- a/src/northbridge/via/vx800/dram_util.c +++ b/src/northbridge/via/vx800/dram_util.c @@ -182,7 +182,6 @@ void DumpRegisters(INTN DevNum, INTN FuncNum) u8 ByteVal; ByteVal = 0; - //pci_write_config8(PCI_DEV(0, DevNum, FuncNum), 0xA1, ByteVal); PRINT_DEBUG_MEM("\rDev %02x Fun %02x\r"); PRINT_DEBUG_MEM ("\r 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\r"); diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c index 0c5f63c..73d897a 100644 --- a/src/northbridge/via/vx800/drdy_bl.c +++ b/src/northbridge/via/vx800/drdy_bl.c @@ -439,101 +439,12 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr) Data |= 0x08; pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data); - //Data = pci_read_config8(PCI_DEV(0,0,2), 0x55); - //Data = Data & (~0x20); - //pci_write_config8(PCI_DEV(0,0,2), 0x55, Data); - //enable drdy timing Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51); Data = Data | 0x80; pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data); #endif -#if 0 //default - { - //disable drdy timing - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51); - Data = Data & 0x7F; - pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data); - } -#endif -#if 0 // 2:Optimize - u8 CpuFreq, DramFreq; - u8 CL, RDRPH; - - //CL :reg6x[2:0] - Data = pci_read_config8(MEMCTRL, 0x62); - CL = Data & 0x07; - - //RDRPH: reg7B[6:4] - Data = pci_read_config8(MEMCTRL, 0x7B); - RDRPH = (Data & 0x70) >> 4; - - //CpuFreq: F2Reg54[7:5] - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x54); - CpuFreq = (Data & 0xE0) >> 5; - - //DramFreq:F3Reg90[2:0] - Data = pci_read_config8(MEMCTRL, 0x90); - DramFreq = Data & 0x07; - - u8 DelayMode; - DelayMode = CL + RDRPH; // RDELAYMD = bit0 of (CAS Latency + RDRPH) - DelayMode &= 0x01; - u8 ProgData[PT894_RDRDY_TBL_Width]; - - //In 364, there is no 128 bit - if (DelayMode == 1) { // DelayMode 1 - u8 Index; - for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++) - ProgData[Index] = - PT894_64bit_DELAYMD1_RCONV0[CpuFreq][DramFreq] - [Index]; - } else { // DelayMode 0 - u8 Index; - for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++) - ProgData[Index] = - PT894_64bit_DELAYMD0_RCONV0[CpuFreq][DramFreq] - [Index]; - } - - Data = ProgData[0]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x60, Data); - - Data = ProgData[1]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x61, Data); - - Data = ProgData[2]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x62, Data); - - Data = ProgData[3]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x63, Data); - - Data = ProgData[4]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x64, Data); - - Data = ProgData[5]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x65, Data); - - Data = ProgData[6]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x66, Data); - - Data = ProgData[7]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x67, Data); - - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x54); - Data = (Data & 0xF5) | ProgData[8]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data); - - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x55); - Data = Data & (~0x22) | ProgData[9]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x62, Data); - - //enable drdy timing - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51); - Data = Data | 0x80; - pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data); -#endif } /*This routine process the ability for North Bridge side burst functionality diff --git a/src/northbridge/via/vx800/driving_clk_phase_data.h b/src/northbridge/via/vx800/driving_clk_phase_data.h index e9190fac..b77c593 100644 --- a/src/northbridge/via/vx800/driving_clk_phase_data.h +++ b/src/northbridge/via/vx800/driving_clk_phase_data.h @@ -16,51 +16,19 @@ #ifndef DRIVINGCLKPHASEDATA_H #define DRIVINGCLKPHASEDATA_H -//extern u8 DDR2_DQSA_Driving_Table[4]; -//extern u8 DDR2_DQSB_Driving_Table[2]; - -//extern u8 DDR2_DQA_Driving_Table[4]; -//extern u8 DDR2_DQB_Driving_Table[2]; - -//extern u8 DDR2_CSA_Driving_Table_x8[4]; -//extern u8 DDR2_CSB_Driving_Table_x8[2]; -//extern u8 DDR2_CSA_Driving_Table_x16[4]; -//extern u8 DDR2_CSB_Driving_Table_x16[2]; - #define MA_Table 3 -//extern u8 DDR2_MAA_Driving_Table[MA_Table][4]; -//extern u8 DDR2_MAB_Driving_Table[MA_Table][2]; - -//extern u8 DDR2_DCLKA_Driving_Table[4]; -//extern u8 DDR2_DCLKB_Driving_Table[4]; #define DUTY_CYCLE_FREQ_NUM 6 #define DUTY_CYCLE_REG_NUM 3 -//extern u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM]; -//extern u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM]; #define Clk_Phase_Table_DDR2_Width 6 -//extern u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width]; -//extern u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width]; -//extern u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width]; #define WrtData_REG_NUM 4 #define WrtData_FREQ_NUM 6 -//extern u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM]; -//extern u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM]; #define DQ_DQS_Delay_Table_Width 4 -//extern u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width]; -//extern u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width]; #define DQS_INPUT_CAPTURE_REG_NUM 3 #define DQS_INPUT_CAPTURE_FREQ_NUM 6 -//extern u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM]; -//extern u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM]; - -//extern u8 Fixed_DQSA_1_2_Rank_Table[4][2]; -//extern u8 Fixed_DQSA_3_4_Rank_Table[4][2]; -//extern u8 Fixed_DQSB_1_2_Rank_Table[4][2]; -//extern u8 Fixed_DQSB_3_4_Rank_Table[4][2]; #endif /* DRIVINGCLKPHASEDATA_H */ diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c index 95bae3c..a67c5b0 100644 --- a/src/northbridge/via/vx800/driving_setting.c +++ b/src/northbridge/via/vx800/driving_setting.c @@ -223,8 +223,6 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr) /*channel B */ if (1 == ENABLE_CHC) { //CHB has not auto compensation mode ,so must set it manual,or else CHB initialization will not successful - // Data =0x88; - //pci_write_config8(MEMCTRL, 0xd0, Data); Data = pci_read_config8(MEMCTRL, 0xd5); Data &= 0xAF; diff --git a/src/northbridge/via/vx800/early_serial.c b/src/northbridge/via/vx800/early_serial.c index 649339b..8393aa7 100644 --- a/src/northbridge/via/vx800/early_serial.c +++ b/src/northbridge/via/vx800/early_serial.c @@ -54,9 +54,6 @@ void enable_vx800_serial(void) post_code(0x06); outb(0x03, 0x22); - //pci_write_config8(PCI_DEV(0,17,0),0xb4,0x7e); - //pci_write_config8(PCI_DEV(0,17,0),0xb0,0x10); - // turn on pnp vx800_writepnpaddr(0x87); vx800_writepnpaddr(0x87); diff --git a/src/northbridge/via/vx800/early_smbus.c b/src/northbridge/via/vx800/early_smbus.c index c7ef204..fd03cfb 100644 --- a/src/northbridge/via/vx800/early_smbus.c +++ b/src/northbridge/via/vx800/early_smbus.c @@ -54,7 +54,6 @@ /* Internal functions */ static void smbus_print_error(unsigned char host_status_register, int loops) { -// printk(BIOS_ERR, "some i2c error\n"); /* Check if there actually was an error */ if (host_status_register == 0x00 || host_status_register == 0x40 || host_status_register == 0x42) diff --git a/src/northbridge/via/vx800/ide.c b/src/northbridge/via/vx800/ide.c index 3fb2c23..d2cdb51 100644 --- a/src/northbridge/via/vx800/ide.c +++ b/src/northbridge/via/vx800/ide.c @@ -172,7 +172,6 @@ static void ide_init(struct device *dev) for (i = 0; i < (16 * 12); i++) { pci_write_config8(dev, 0x40 + i, idedevicepcitable[i]); } - //pci_write_config8(dev, 0x0d, 0x20); data = pci_read_config8(dev, 0x0d); data &= 0x0f; data |= 0x40; @@ -185,59 +184,6 @@ static void ide_init(struct device *dev) /* Force interrupts to use compat mode. */ pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); -#if 0 - u8 enables; - u32 cablesel; - - pci_write_config16(dev, 0x04, 0x0007); - - enables = pci_read_config8(dev, IDE_CS) & ~0x3; - enables |= 0x02; - pci_write_config8(dev, IDE_CS, enables); - enables = pci_read_config8(dev, IDE_CS); - printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); - - /* Enable only compatibility mode. */ - enables = pci_read_config8(dev, IDE_CONF_II); - enables &= ~0xc0; - pci_write_config8(dev, IDE_CONF_II, enables); - enables = pci_read_config8(dev, IDE_CONF_II); - printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables); - - /* Enable prefetch buffers. */ - enables = pci_read_config8(dev, IDE_CONF_I); - enables |= 0xf0; - pci_write_config8(dev, IDE_CONF_I, enables); - - /* Flush FIFOs at half. */ - enables = pci_read_config8(dev, IDE_CONF_FIFO); - enables &= 0xf0; - enables |= (1 << 2) | (1 << 0); - pci_write_config8(dev, IDE_CONF_FIFO, enables); - - /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */ - enables = pci_read_config8(dev, IDE_MISC_I); - enables &= 0xe2; - enables |= (1 << 4) | (1 << 3); - pci_write_config8(dev, IDE_MISC_I, enables); - - /* Use memory read multiple, Memory-Write-and-Invalidate. */ - enables = pci_read_config8(dev, IDE_MISC_II); - enables |= (1 << 2) | (1 << 3); - pci_write_config8(dev, IDE_MISC_II, enables); - - /* Force interrupts to use compat mode. */ - pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); - pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); - - /* Cable guy... */ - cablesel = pci_read_config32(dev, IDE_UDMA); - cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4)); - cablesel |= (sb->ide0_80pin_cable << 28) | - (sb->ide0_80pin_cable << 20) | - (sb->ide1_80pin_cable << 12) | (sb->ide1_80pin_cable << 4); - pci_write_config32(dev, IDE_UDMA, cablesel); -#endif } static struct device_operations ide_ops = { diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 4279796..1ab11c0 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -83,11 +83,9 @@ static void pci_routing_fixup(struct device *dev) /* PCI slot */ printk(BIOS_INFO, "setting ide\n"); - //pci_assign_irqs(0, 0x0f, pin_to_irq(idePins)); /* Standard usb components */ printk(BIOS_INFO, "setting usb1-2\n"); -// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); /* sound hardware */ printk(BIOS_INFO, "setting hdac audio\n"); @@ -109,7 +107,6 @@ static void setup_pm(device_t dev) pci_write_config8(dev, 0x82, 0x49); /* Primary interupt channel, define wake events 0 = IRQ0 15 = IRQ15 1 = en. */ -// pci_write_config16(dev, 0x84, 0x30f2); pci_write_config16(dev, 0x84, 0x609a); // 0x609a?? /* SMI output level to low, 7.5us throttle clock */ @@ -131,8 +128,6 @@ static void setup_pm(device_t dev) /* GP2 Timer Counter */ pci_write_config8(dev, 0x99, 0xfb); - /* GP3 Timer Counter */ - //pci_write_config8(dev, 0x9a, 0x20); /* Multi Function Select 1 */ pci_write_config8(dev, 0xe4, 0x00); @@ -178,16 +173,6 @@ static void setup_pm(device_t dev) * Will work for C3 and for FID/VID change. */ outb(0x1, VX800_ACPI_IO_BASE + 0x11); -/* - outw(0x0, 0x424); - outw(0x0, 0x42a); - outw(0x1, 0x42c); - outl(0x0, 0x434); - outl(0x01, 0x438); - outb(0x0, 0x442); - outl(0xffff7fff, 0x448); - outw(0x001, 0x404); -*/ } static void S3_ps2_kb_ms_wakeup(struct device *dev) @@ -234,7 +219,6 @@ static void vx800_sb_init(struct device *dev) pci_write_config8(dev, 0x6C, enables); // Map 4MB of FLASH into the address space -// pci_write_config8(dev, 0x41, 0x7f); // Set bit 6 of 0x40, because Award does it (IO recovery time) // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI @@ -255,7 +239,6 @@ static void vx800_sb_init(struct device *dev) pci_write_config8(dev, 0x59, 0x80); /* Set 0x5b to 0x01 to match Award */ - //pci_write_config8(dev, 0x5b, 0x01); enables = pci_read_config8(dev, 0x5b); enables |= 0x01; pci_write_config8(dev, 0x5b, enables); @@ -264,7 +247,6 @@ static void vx800_sb_init(struct device *dev) pci_write_config8(dev, 0x48, 0x0c); /* Set 0x58 to 0x42 APIC and RTC. */ - //pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0. enables = pci_read_config8(dev, 0x58); enables |= 0x41; // pci_write_config8(dev, 0x58, enables); diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index 6391321..e6ec3b5 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -38,22 +38,6 @@ static void memctrl_init(device_t dev) /* set VGA in uma_ram_setting.c, not in this function. */ -#if 0 - pci_write_config8(dev, 0x85, 0x20); - pci_write_config8(dev, 0x86, 0x2d); - - /* Set up VGA timers */ - pci_write_config8(dev, 0xa2, 0x44); - - /* Enable VGA with a 32mb framebuffer */ - pci_write_config16(dev, 0xa0, 0xd000); - - pci_write_config16(dev, 0xa4, 0x0010); - - //b0: 60 aa aa 5a 0f 00 00 00 08 - pci_write_config16(dev, 0xb0, 0xaa00); - pci_write_config8(dev, 0xb8, 0x08); -#endif } static const struct device_operations memctrl_operations = { diff --git a/src/northbridge/via/vx800/rank_map.c b/src/northbridge/via/vx800/rank_map.c index 069257c..5c9b0ad 100644 --- a/src/northbridge/via/vx800/rank_map.c +++ b/src/northbridge/via/vx800/rank_map.c @@ -91,7 +91,6 @@ void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr) { DRAMClearEndingAddress(DramAttr); DRAMSizingEachRank(DramAttr); - //DRAMReInitDIMMBL (DramAttr); DRAMSetRankMAType(DramAttr); DRAMSetEndingAddress(DramAttr); DRAMPRToVRMapping(DramAttr); diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index bf59093..46c2782 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -94,23 +94,16 @@ void SetUMARam(void) //GMINT and GFX relatate //note Bit 3 VGA Enable pci_write_config8(MEMCTRL, 0xa7, 0x8c); - // ByteVal = 0x4c; //GMINT Misc.1 - //pci_write_config8(MEMCTRL, 0xb0, 0x80); - - //pci_write_config8(MEMCTRL, 0xb1, 0xaa); //AGPCINT MISC - //pci_write_config8(MEMCTRL, 0xb2, 0x82); - //ByteVal = 0x8A; //GMINT MISC.2 //disable read pass write pci_write_config8(MEMCTRL, 0xb3, 0x9A); //EPLL Register - //pci_write_config8(MEMCTRL, 0xb4, 0x04); //enable CHA and CHB merge mode pci_write_config8(MEMCTRL, 0xde, 0x06); @@ -133,17 +126,12 @@ void SetUMARam(void) ByteVal = (ByteVal & 0x8f) | (SLD0F3Val << 4); pci_write_config8(MEMCTRL, 0xa1, ByteVal); -// vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0); - //RxB2 may be for S.L. and RxB1 may be for L. L. // It is different from Spec. ByteVal = SLD1F0Val; pci_write_config8(vga_dev, 0xb2, ByteVal); //set M1 size - //ByteVal = pci_read_config8(MEMCTRL, 0xa3); - //ByteVal = 0x02; - //pci_write_config8(MEMCTRL, 0xa3, ByteVal); PRINT_DEBUG_MEM("UMA setting - 3\n"); @@ -177,7 +165,6 @@ void SetUMARam(void) //enable GFx memory space access control for S.L and mmio ByteVal = pci_read_config8(d0f0_dev, 0xD4); ByteVal |= 0x03; - //ByteVal |= 0x01; pci_write_config8(d0f0_dev, 0xD4, ByteVal); //enable Base VGA 16 Bits Decode @@ -189,15 +176,12 @@ void SetUMARam(void) //set VGA memory selection ByteVal = pci_read_config8(vga_dev, 0xb0); ByteVal &= 0xF8; - //ByteVal |= 0x01; ByteVal |= 0x03; pci_write_config8(vga_dev, 0xb0, ByteVal); //set LL size //enable memory access to SL,MMIO,LL and IO to 3B0~3BB,3C0 ~3DF - //ByteVal = 0x03; - //pci_write_config8(d0f0_dev, 0xc0, ByteVal); //Turn on Graphic chip IO port port access ByteVal = inb(0x03C3); @@ -216,9 +200,6 @@ void SetUMARam(void) ByteVal = inb(0x03CC); ByteVal |= 0x03; outb(ByteVal, 0x03C2); - // ByteVal = inb(0x03C2); - // ByteVal |= 0x01; - // outb(ByteVal,0x03C2); #if 1 //bios porting guide has no this two defination: 3d on 3d4/3d5 and 39 on 3c4/3c5 //set frequence 0x3D5.3d[7:4] @@ -329,101 +310,8 @@ void SetUMARam(void) ByteVal = (ByteVal & 0xE5) | 0x1A; outb(ByteVal, 0x03d5); -#if 0 - u8 table3c43c5[0x70] = { - 0x03, 0x01, 0x0F, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x78, 0x00, 0x00, 0x00, 0xBE, 0x20, 0x7F, - 0x60, 0x7F, 0x08, 0x31, 0xCC, 0x00, 0x01, 0x00, - 0x00, 0x18, 0x10, 0x00, 0x00, 0x00, 0x3D, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x04, 0xF3, 0xFF, 0xFC, - 0xF8, 0x0C, 0x00, 0x00, 0x40, 0x06, 0x11, 0x22, - 0x51, 0x10, 0x00, 0x01, 0x19, 0x0C, 0x00, 0xFF, - 0x38, 0x40, 0x30, 0xFF, 0x70, 0x8C, 0x85, 0x9D, - 0x80, 0x05, 0x54, 0x90, 0x03, 0x30, 0x00, 0x5F, - 0x1F, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, - 0x06, 0xDF, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x40, 0x20, 0x00, 0x20, 0x20, - 0xE0, 0x20, 0xD0, 0x3F, 0x00, 0xE0, 0x00, 0x00 - }; - u8 table3d43d5[0x88] = { - 0x7F, 0x63, 0x63, 0x83, 0x69, 0x19, 0x72, 0xE0, - 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x58, 0x9C, 0x57, 0x90, 0x00, 0x57, 0x73, 0xE3, - 0x57, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0C, 0x00, 0x11, 0x06, 0x00, 0x20, 0x01, 0x34, - 0xEE, 0x74, 0x01, 0x01, 0x08, 0x84, 0x00, 0x00, - 0x00, 0xF3, 0x40, 0x90, 0x00, 0x00, 0x00, 0x01, - 0x00, 0x12, 0x00, 0x02, 0x00, 0x00, 0x10, 0x00, - 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, - 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x10, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x9D, - 0x9D, 0x9D, 0x9D, 0x9D, 0x00, 0x9D, 0x1D, 0x00, - 0x00, 0x00, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, - 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, - }; - - u8 table3c0space[0xc0] = { - 0x11, 0x00, 0x10, 0x01, 0x26, 0x3D, 0xFF, 0x00, - 0x10, 0x3F, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x50, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - }; - - //for (i = 0;i < 0xc0;i++) - for (i = 0; i < 0x40; i++) - { - outb(table3c0space[i], 0x03c0 + i); - } - - for (i = 0; i < 0x70; i++) { - outb(i, 0x03c4); - outb(table3c43c5[i], 0x03c5); - } - for (i = 0; i < 0x88; i++) { - outb(i, 0x03d4); - outb(table3d43d5[i], 0x03d5); - } - - outb(0x92, 0x03d4); - outb(0x80, 0x03d5); - - outb(0xa3, 0x03d4); - outb(0x00, 0x03d5); - - outb(0xe8, 0x03d4); - outb(0x40, 0x03d5); -#endif - // 3d4 3d freq // IO Port / Index: 3X5.3D // Scratch Pad Register 4 -// outb(0x39,0x03c4); -// outb(1 << SLD0F3Val ,0x03c5); -// #endif - } diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 664e915..70a916f 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -134,10 +134,6 @@ static void write_protect_vgabios(void) PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0); if (dev) pci_write_config8(dev, 0x80, 0xff); - /*vx855 no th 0x61 reg */ - /*dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VLINK, 0); - //if (dev) - // pci_write_config8(dev, 0x61, 0xff); */ } #endif @@ -166,15 +162,6 @@ static void vga_init(device_t dev) reg8 = reg8 | 2; outb(reg8, 0x92); - //* - //pci_write_config8(dev, 0x04, 0x07); - //pci_write_config32(dev,0x10, 0xa0000008); - //pci_write_config32(dev,0x14, 0xdd000000); - pci_write_config32(dev, 0x10, VIACONFIG_VGA_PCI_10); - pci_write_config32(dev, 0x14, VIACONFIG_VGA_PCI_14); - pci_write_config8(dev, 0x3c, 0x0a); //same with vx855_lpc.c - //*/ - printk(BIOS_DEBUG, "Initializing VGA...\n"); pci_dev_init(dev); @@ -192,13 +179,6 @@ static void vga_init(device_t dev) reg8 |= (0x3 << 4); outb(0x3d, CRTM_INDEX); outb(reg8, CRTM_DATA); - -#if 0 - /* Set framebuffer size to CONFIG_VIDEO_MB mb */ - reg8 = (CONFIG_VIDEO_MB/4); - outb(0x39, SR_INDEX); - outb(reg8, SR_DATA); -#endif } } diff --git a/src/northbridge/via/vx800/vx800.h b/src/northbridge/via/vx800/vx800.h index c9ae130..d2eb46f 100644 --- a/src/northbridge/via/vx800/vx800.h +++ b/src/northbridge/via/vx800/vx800.h @@ -26,12 +26,9 @@ void smbus_fixup(const struct mem_controller *mem_ctrl); void enable_vx800_serial(void); #endif -//#define REV_B0 0x10 #define REV_B1 0x11 -//#define REV_B2 0x12 #define REV_B3 0x13 #define REV_B4 0x14 -//#define REV_B2 0xB4 #define REV_B0 0x00 #define REV_B2 0x01 diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 03c8e0c..c99f10e 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -306,7 +306,6 @@ static void chrome9hd_init(device_t dev) vga_misc_mask(1 << 0, 1 << 0); /* FIXME: recheck; Enable Base VGA 16 Bits Decode */ - ////pci_mod_config8(host, 0x4e, 0, 1<<4); u32 fb_address = pci_read_config32(dev, PCI_BASE_ADDRESS_2); fb_address &= ~0x0F; diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index 4f3d704..a9d24df 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -77,7 +77,7 @@ static void vx900_lpc_dma_setup(device_t dev) /* Enable Positive South Module PCI Cycle Decoding */ /* FIXME: Setting this seems to hang our system */ - //pci_mod_config8(dev, 0x58, 0, 1<<4); + /* Positive decoding for ROM + APIC + On-board IO ports */ pci_mod_config8(dev, 0x6c, 0, (1 << 2) | (1 << 3) | (1 << 7)); /* Enable DMA channels. BIOS guide recommends DMA channel 2 off */ diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index aff62f2..4878571 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -326,9 +326,8 @@ static void vx900_dram_write_init_config(void) /* Fast cycle control for CPU-to-DRAM Read Cycle 0:Disabled. * This CPU bus controller will wait for all data */ - ////pci_mod_config8(HOST_BUS, 0x51, (1 << 7), 0); + /* Memory to CPU bus Controller Conversion Mode 1: Synchronous mode */ - ////pci_mod_config8(HOST_BUS, 0x54, 0, (1 << 1)); } static void dram_find_spds_ddr3(const dimm_layout * addr, dimm_info * dimm) @@ -1335,7 +1334,6 @@ static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq, /* FIXME: Except that we have not yet told the MCU what * the geometry of the DIMM is, hence we don't trust * this test for now */ - ////continue; } /* Good. We should be able to use this DIMM */ /* That's it. We're done */ @@ -1614,14 +1612,8 @@ static void vx900_dram_write_final_config(ramctr_timing * ctrl) /* Tri-state MCSi# when rank is in self-refresh */ pci_mod_config8(MCU, 0x99, 0, 0x0f); - ////pci_write_config8(MCU, 0x69, 0xe7); /* Enable paging mode and 8 page registers */ pci_mod_config8(MCU, 0x69, 0, 0xe5); - ////pci_write_config8(MCU, 0x72, 0x0f); - - ////pci_write_config8(MCU, 0x97, 0xa4); /* self-refresh */ - ////pci_write_config8(MCU, 0x98, 0xba); /* self-refresh II */ - ////pci_write_config8(MCU, 0x9a, 0x80); /* self-refresh III */ /* Enable automatic triggering of short ZQ calibration */ pci_write_config8(MCU, 0xc8, 0x80);

1 0

New patch to review for coreboot: src/northbridge/via: Remove commented code
by HAOUAS Elyes 05 Oct '16

05 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16898 -gerrit commit d9ab95e44cf489956801328dffa243f5766382d4 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 21:02:23 2016 +0200 src/northbridge/via: Remove commented code Change-Id: Ic589b26c6c94df12e1fe218d079018db8b38fbd9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/via/cx700/raminit.c | 8 -- src/northbridge/via/vx800/drdy_bl.c | 89 ---------------------- src/northbridge/via/vx800/ide.c | 54 -------------- src/northbridge/via/vx800/lpc.c | 18 ----- src/northbridge/via/vx800/northbridge.c | 16 ---- src/northbridge/via/vx800/uma_ram_setting.c | 112 ---------------------------- src/northbridge/via/vx800/vga.c | 20 ----- 7 files changed, 317 deletions(-) diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index aad851d..f8d709c 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -815,7 +815,6 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) /* Clock Phase Control for FeedBack Mode */ regs = pci_read_config8(MEMCTRL, 0x90); -// regs |= 0x80; pci_write_config8(MEMCTRL, 0x90, regs); regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ); @@ -1343,13 +1342,6 @@ static void sdram_enable(const struct mem_controller *ctrl) /****************************************************************/ /* Find out the lowest Bank Interleave and Set Register */ /****************************************************************/ -#if 0 - //TODO - reg8 = pci_read_config8(MEMCTRL, 0x69); - reg8 &= ~0xc0; - reg8 |= 0x80; //8 banks - pci_write_config8(MEMCTRL, 0x69, reg8); -#endif dl = 2; for (i = 0; i < 4; i++) { reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i)); diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c index 0c5f63c..73d897a 100644 --- a/src/northbridge/via/vx800/drdy_bl.c +++ b/src/northbridge/via/vx800/drdy_bl.c @@ -439,101 +439,12 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr) Data |= 0x08; pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data); - //Data = pci_read_config8(PCI_DEV(0,0,2), 0x55); - //Data = Data & (~0x20); - //pci_write_config8(PCI_DEV(0,0,2), 0x55, Data); - //enable drdy timing Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51); Data = Data | 0x80; pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data); #endif -#if 0 //default - { - //disable drdy timing - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51); - Data = Data & 0x7F; - pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data); - } -#endif -#if 0 // 2:Optimize - u8 CpuFreq, DramFreq; - u8 CL, RDRPH; - - //CL :reg6x[2:0] - Data = pci_read_config8(MEMCTRL, 0x62); - CL = Data & 0x07; - - //RDRPH: reg7B[6:4] - Data = pci_read_config8(MEMCTRL, 0x7B); - RDRPH = (Data & 0x70) >> 4; - - //CpuFreq: F2Reg54[7:5] - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x54); - CpuFreq = (Data & 0xE0) >> 5; - - //DramFreq:F3Reg90[2:0] - Data = pci_read_config8(MEMCTRL, 0x90); - DramFreq = Data & 0x07; - - u8 DelayMode; - DelayMode = CL + RDRPH; // RDELAYMD = bit0 of (CAS Latency + RDRPH) - DelayMode &= 0x01; - u8 ProgData[PT894_RDRDY_TBL_Width]; - - //In 364, there is no 128 bit - if (DelayMode == 1) { // DelayMode 1 - u8 Index; - for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++) - ProgData[Index] = - PT894_64bit_DELAYMD1_RCONV0[CpuFreq][DramFreq] - [Index]; - } else { // DelayMode 0 - u8 Index; - for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++) - ProgData[Index] = - PT894_64bit_DELAYMD0_RCONV0[CpuFreq][DramFreq] - [Index]; - } - - Data = ProgData[0]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x60, Data); - - Data = ProgData[1]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x61, Data); - - Data = ProgData[2]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x62, Data); - - Data = ProgData[3]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x63, Data); - - Data = ProgData[4]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x64, Data); - - Data = ProgData[5]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x65, Data); - - Data = ProgData[6]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x66, Data); - - Data = ProgData[7]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x67, Data); - - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x54); - Data = (Data & 0xF5) | ProgData[8]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data); - - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x55); - Data = Data & (~0x22) | ProgData[9]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x62, Data); - - //enable drdy timing - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51); - Data = Data | 0x80; - pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data); -#endif } /*This routine process the ability for North Bridge side burst functionality diff --git a/src/northbridge/via/vx800/ide.c b/src/northbridge/via/vx800/ide.c index 3fb2c23..d2cdb51 100644 --- a/src/northbridge/via/vx800/ide.c +++ b/src/northbridge/via/vx800/ide.c @@ -172,7 +172,6 @@ static void ide_init(struct device *dev) for (i = 0; i < (16 * 12); i++) { pci_write_config8(dev, 0x40 + i, idedevicepcitable[i]); } - //pci_write_config8(dev, 0x0d, 0x20); data = pci_read_config8(dev, 0x0d); data &= 0x0f; data |= 0x40; @@ -185,59 +184,6 @@ static void ide_init(struct device *dev) /* Force interrupts to use compat mode. */ pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); -#if 0 - u8 enables; - u32 cablesel; - - pci_write_config16(dev, 0x04, 0x0007); - - enables = pci_read_config8(dev, IDE_CS) & ~0x3; - enables |= 0x02; - pci_write_config8(dev, IDE_CS, enables); - enables = pci_read_config8(dev, IDE_CS); - printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); - - /* Enable only compatibility mode. */ - enables = pci_read_config8(dev, IDE_CONF_II); - enables &= ~0xc0; - pci_write_config8(dev, IDE_CONF_II, enables); - enables = pci_read_config8(dev, IDE_CONF_II); - printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables); - - /* Enable prefetch buffers. */ - enables = pci_read_config8(dev, IDE_CONF_I); - enables |= 0xf0; - pci_write_config8(dev, IDE_CONF_I, enables); - - /* Flush FIFOs at half. */ - enables = pci_read_config8(dev, IDE_CONF_FIFO); - enables &= 0xf0; - enables |= (1 << 2) | (1 << 0); - pci_write_config8(dev, IDE_CONF_FIFO, enables); - - /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */ - enables = pci_read_config8(dev, IDE_MISC_I); - enables &= 0xe2; - enables |= (1 << 4) | (1 << 3); - pci_write_config8(dev, IDE_MISC_I, enables); - - /* Use memory read multiple, Memory-Write-and-Invalidate. */ - enables = pci_read_config8(dev, IDE_MISC_II); - enables |= (1 << 2) | (1 << 3); - pci_write_config8(dev, IDE_MISC_II, enables); - - /* Force interrupts to use compat mode. */ - pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); - pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); - - /* Cable guy... */ - cablesel = pci_read_config32(dev, IDE_UDMA); - cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4)); - cablesel |= (sb->ide0_80pin_cable << 28) | - (sb->ide0_80pin_cable << 20) | - (sb->ide1_80pin_cable << 12) | (sb->ide1_80pin_cable << 4); - pci_write_config32(dev, IDE_UDMA, cablesel); -#endif } static struct device_operations ide_ops = { diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 4279796..1ab11c0 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -83,11 +83,9 @@ static void pci_routing_fixup(struct device *dev) /* PCI slot */ printk(BIOS_INFO, "setting ide\n"); - //pci_assign_irqs(0, 0x0f, pin_to_irq(idePins)); /* Standard usb components */ printk(BIOS_INFO, "setting usb1-2\n"); -// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); /* sound hardware */ printk(BIOS_INFO, "setting hdac audio\n"); @@ -109,7 +107,6 @@ static void setup_pm(device_t dev) pci_write_config8(dev, 0x82, 0x49); /* Primary interupt channel, define wake events 0 = IRQ0 15 = IRQ15 1 = en. */ -// pci_write_config16(dev, 0x84, 0x30f2); pci_write_config16(dev, 0x84, 0x609a); // 0x609a?? /* SMI output level to low, 7.5us throttle clock */ @@ -131,8 +128,6 @@ static void setup_pm(device_t dev) /* GP2 Timer Counter */ pci_write_config8(dev, 0x99, 0xfb); - /* GP3 Timer Counter */ - //pci_write_config8(dev, 0x9a, 0x20); /* Multi Function Select 1 */ pci_write_config8(dev, 0xe4, 0x00); @@ -178,16 +173,6 @@ static void setup_pm(device_t dev) * Will work for C3 and for FID/VID change. */ outb(0x1, VX800_ACPI_IO_BASE + 0x11); -/* - outw(0x0, 0x424); - outw(0x0, 0x42a); - outw(0x1, 0x42c); - outl(0x0, 0x434); - outl(0x01, 0x438); - outb(0x0, 0x442); - outl(0xffff7fff, 0x448); - outw(0x001, 0x404); -*/ } static void S3_ps2_kb_ms_wakeup(struct device *dev) @@ -234,7 +219,6 @@ static void vx800_sb_init(struct device *dev) pci_write_config8(dev, 0x6C, enables); // Map 4MB of FLASH into the address space -// pci_write_config8(dev, 0x41, 0x7f); // Set bit 6 of 0x40, because Award does it (IO recovery time) // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI @@ -255,7 +239,6 @@ static void vx800_sb_init(struct device *dev) pci_write_config8(dev, 0x59, 0x80); /* Set 0x5b to 0x01 to match Award */ - //pci_write_config8(dev, 0x5b, 0x01); enables = pci_read_config8(dev, 0x5b); enables |= 0x01; pci_write_config8(dev, 0x5b, enables); @@ -264,7 +247,6 @@ static void vx800_sb_init(struct device *dev) pci_write_config8(dev, 0x48, 0x0c); /* Set 0x58 to 0x42 APIC and RTC. */ - //pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0. enables = pci_read_config8(dev, 0x58); enables |= 0x41; // pci_write_config8(dev, 0x58, enables); diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index 6391321..e6ec3b5 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -38,22 +38,6 @@ static void memctrl_init(device_t dev) /* set VGA in uma_ram_setting.c, not in this function. */ -#if 0 - pci_write_config8(dev, 0x85, 0x20); - pci_write_config8(dev, 0x86, 0x2d); - - /* Set up VGA timers */ - pci_write_config8(dev, 0xa2, 0x44); - - /* Enable VGA with a 32mb framebuffer */ - pci_write_config16(dev, 0xa0, 0xd000); - - pci_write_config16(dev, 0xa4, 0x0010); - - //b0: 60 aa aa 5a 0f 00 00 00 08 - pci_write_config16(dev, 0xb0, 0xaa00); - pci_write_config8(dev, 0xb8, 0x08); -#endif } static const struct device_operations memctrl_operations = { diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index bf59093..46c2782 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -94,23 +94,16 @@ void SetUMARam(void) //GMINT and GFX relatate //note Bit 3 VGA Enable pci_write_config8(MEMCTRL, 0xa7, 0x8c); - // ByteVal = 0x4c; //GMINT Misc.1 - //pci_write_config8(MEMCTRL, 0xb0, 0x80); - - //pci_write_config8(MEMCTRL, 0xb1, 0xaa); //AGPCINT MISC - //pci_write_config8(MEMCTRL, 0xb2, 0x82); - //ByteVal = 0x8A; //GMINT MISC.2 //disable read pass write pci_write_config8(MEMCTRL, 0xb3, 0x9A); //EPLL Register - //pci_write_config8(MEMCTRL, 0xb4, 0x04); //enable CHA and CHB merge mode pci_write_config8(MEMCTRL, 0xde, 0x06); @@ -133,17 +126,12 @@ void SetUMARam(void) ByteVal = (ByteVal & 0x8f) | (SLD0F3Val << 4); pci_write_config8(MEMCTRL, 0xa1, ByteVal); -// vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0); - //RxB2 may be for S.L. and RxB1 may be for L. L. // It is different from Spec. ByteVal = SLD1F0Val; pci_write_config8(vga_dev, 0xb2, ByteVal); //set M1 size - //ByteVal = pci_read_config8(MEMCTRL, 0xa3); - //ByteVal = 0x02; - //pci_write_config8(MEMCTRL, 0xa3, ByteVal); PRINT_DEBUG_MEM("UMA setting - 3\n"); @@ -177,7 +165,6 @@ void SetUMARam(void) //enable GFx memory space access control for S.L and mmio ByteVal = pci_read_config8(d0f0_dev, 0xD4); ByteVal |= 0x03; - //ByteVal |= 0x01; pci_write_config8(d0f0_dev, 0xD4, ByteVal); //enable Base VGA 16 Bits Decode @@ -189,15 +176,12 @@ void SetUMARam(void) //set VGA memory selection ByteVal = pci_read_config8(vga_dev, 0xb0); ByteVal &= 0xF8; - //ByteVal |= 0x01; ByteVal |= 0x03; pci_write_config8(vga_dev, 0xb0, ByteVal); //set LL size //enable memory access to SL,MMIO,LL and IO to 3B0~3BB,3C0 ~3DF - //ByteVal = 0x03; - //pci_write_config8(d0f0_dev, 0xc0, ByteVal); //Turn on Graphic chip IO port port access ByteVal = inb(0x03C3); @@ -216,9 +200,6 @@ void SetUMARam(void) ByteVal = inb(0x03CC); ByteVal |= 0x03; outb(ByteVal, 0x03C2); - // ByteVal = inb(0x03C2); - // ByteVal |= 0x01; - // outb(ByteVal,0x03C2); #if 1 //bios porting guide has no this two defination: 3d on 3d4/3d5 and 39 on 3c4/3c5 //set frequence 0x3D5.3d[7:4] @@ -329,101 +310,8 @@ void SetUMARam(void) ByteVal = (ByteVal & 0xE5) | 0x1A; outb(ByteVal, 0x03d5); -#if 0 - u8 table3c43c5[0x70] = { - 0x03, 0x01, 0x0F, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x78, 0x00, 0x00, 0x00, 0xBE, 0x20, 0x7F, - 0x60, 0x7F, 0x08, 0x31, 0xCC, 0x00, 0x01, 0x00, - 0x00, 0x18, 0x10, 0x00, 0x00, 0x00, 0x3D, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x04, 0xF3, 0xFF, 0xFC, - 0xF8, 0x0C, 0x00, 0x00, 0x40, 0x06, 0x11, 0x22, - 0x51, 0x10, 0x00, 0x01, 0x19, 0x0C, 0x00, 0xFF, - 0x38, 0x40, 0x30, 0xFF, 0x70, 0x8C, 0x85, 0x9D, - 0x80, 0x05, 0x54, 0x90, 0x03, 0x30, 0x00, 0x5F, - 0x1F, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, - 0x06, 0xDF, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x40, 0x20, 0x00, 0x20, 0x20, - 0xE0, 0x20, 0xD0, 0x3F, 0x00, 0xE0, 0x00, 0x00 - }; - u8 table3d43d5[0x88] = { - 0x7F, 0x63, 0x63, 0x83, 0x69, 0x19, 0x72, 0xE0, - 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x58, 0x9C, 0x57, 0x90, 0x00, 0x57, 0x73, 0xE3, - 0x57, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0C, 0x00, 0x11, 0x06, 0x00, 0x20, 0x01, 0x34, - 0xEE, 0x74, 0x01, 0x01, 0x08, 0x84, 0x00, 0x00, - 0x00, 0xF3, 0x40, 0x90, 0x00, 0x00, 0x00, 0x01, - 0x00, 0x12, 0x00, 0x02, 0x00, 0x00, 0x10, 0x00, - 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, - 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x10, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x9D, - 0x9D, 0x9D, 0x9D, 0x9D, 0x00, 0x9D, 0x1D, 0x00, - 0x00, 0x00, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, - 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, - }; - - u8 table3c0space[0xc0] = { - 0x11, 0x00, 0x10, 0x01, 0x26, 0x3D, 0xFF, 0x00, - 0x10, 0x3F, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x50, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - }; - - //for (i = 0;i < 0xc0;i++) - for (i = 0; i < 0x40; i++) - { - outb(table3c0space[i], 0x03c0 + i); - } - - for (i = 0; i < 0x70; i++) { - outb(i, 0x03c4); - outb(table3c43c5[i], 0x03c5); - } - for (i = 0; i < 0x88; i++) { - outb(i, 0x03d4); - outb(table3d43d5[i], 0x03d5); - } - - outb(0x92, 0x03d4); - outb(0x80, 0x03d5); - - outb(0xa3, 0x03d4); - outb(0x00, 0x03d5); - - outb(0xe8, 0x03d4); - outb(0x40, 0x03d5); -#endif - // 3d4 3d freq // IO Port / Index: 3X5.3D // Scratch Pad Register 4 -// outb(0x39,0x03c4); -// outb(1 << SLD0F3Val ,0x03c5); -// #endif - } diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 664e915..70a916f 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -134,10 +134,6 @@ static void write_protect_vgabios(void) PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0); if (dev) pci_write_config8(dev, 0x80, 0xff); - /*vx855 no th 0x61 reg */ - /*dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VLINK, 0); - //if (dev) - // pci_write_config8(dev, 0x61, 0xff); */ } #endif @@ -166,15 +162,6 @@ static void vga_init(device_t dev) reg8 = reg8 | 2; outb(reg8, 0x92); - //* - //pci_write_config8(dev, 0x04, 0x07); - //pci_write_config32(dev,0x10, 0xa0000008); - //pci_write_config32(dev,0x14, 0xdd000000); - pci_write_config32(dev, 0x10, VIACONFIG_VGA_PCI_10); - pci_write_config32(dev, 0x14, VIACONFIG_VGA_PCI_14); - pci_write_config8(dev, 0x3c, 0x0a); //same with vx855_lpc.c - //*/ - printk(BIOS_DEBUG, "Initializing VGA...\n"); pci_dev_init(dev); @@ -192,13 +179,6 @@ static void vga_init(device_t dev) reg8 |= (0x3 << 4); outb(0x3d, CRTM_INDEX); outb(reg8, CRTM_DATA); - -#if 0 - /* Set framebuffer size to CONFIG_VIDEO_MB mb */ - reg8 = (CONFIG_VIDEO_MB/4); - outb(0x39, SR_INDEX); - outb(reg8, SR_DATA); -#endif } }

1 0

Patch set updated for coreboot: soc/intel/apollolake:Implement stage cache to improve resume time
by Brandon Breitenstein 05 Oct '16

05 Oct '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16833 -gerrit commit fc7be8a5669fb34cddb4945c824fd775d3361f26 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Sep 30 13:57:12 2016 -0700 soc/intel/apollolake:Implement stage cache to improve resume time This patch enables stage cache to save some time during resume. It saves ramstage in the stage cache and restores it on resume so that it does not have to reinitialize ramstage during the resume flow. Stage cache functionality is added to postcar stage since ramstage is called from postcar. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for Reef and tested ramstage being cached Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 2 ++ src/lib/Makefile.inc | 1 + src/lib/ext_stage_cache.c | 1 + src/soc/intel/apollolake/Kconfig | 6 +++++- src/soc/intel/apollolake/cpu.c | 8 ++++++-- src/soc/intel/apollolake/include/soc/smm.h | 4 +--- src/soc/intel/apollolake/memmap.c | 30 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/romstage.c | 15 +++++++++++++++ 8 files changed, 61 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 3986fe6..beeec7c 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -37,6 +37,8 @@ ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 394491c..67f8364 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -159,6 +159,7 @@ ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y) ramstage-y += ext_stage_cache.c romstage-y += ext_stage_cache.c +postcar-y += ext_stage_cache.c else ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 770097f..2a99188 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -126,3 +126,4 @@ static void stage_cache_setup(int is_recovery) ROMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) RAMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) +POSTCAR_CBMEM_INIT_HOOK(stage_cache_setup) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3a23dbd..6c178c3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS select COMMON_FADT select GENERIC_GPIO_LIB @@ -34,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE - select NO_STAGE_CACHE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PCIEXP_ASPM @@ -254,4 +254,8 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n +config SMM_RESERVED_SIZE + hex + default 0x100000 + endif diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f3cf050..e67842c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -102,19 +102,23 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, { void *smm_base; size_t smm_size; + void *handler_base; + size_t handler_size; /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ smm_region(&smm_base, &smm_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; + *perm_smbase = (uintptr_t)handler_base; + *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h index 7a9846e..740d02b 100644 --- a/src/soc/intel/apollolake/include/soc/smm.h +++ b/src/soc/intel/apollolake/include/soc/smm.h @@ -20,6 +20,7 @@ #include <stdint.h> #include <soc/gpio.h> +#include <fsp/memmap.h> /* These helpers are for performing SMM relocation. */ void southbridge_clear_smi_status(void); @@ -35,7 +36,4 @@ void southbridge_smm_enable_smi(void); /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts); -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); #endif diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index ea6f447..7436492 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -52,3 +52,33 @@ void smm_region(void **start, size_t *size) *start = (void *)smm_region_start(); *size = smm_region_size(); } + +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} + diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..2384ceb 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/northbridge.h> @@ -105,6 +106,9 @@ asmlinkage void car_stage_entry(void) uintptr_t top_of_ram; bool s3wake; struct chipset_power_state *ps = car_get_var_ptr(&power_state); + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; timestamp_add_now(TS_START_ROMSTAGE); @@ -135,6 +139,17 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); }

1 0

New patch to review for coreboot: northbridge/amd/agesa: Remove commented code
by HAOUAS Elyes 05 Oct '16

05 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16897 -gerrit commit 9f58b562c69f94d0b0068a77c6b12f4c659362b0 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 20:40:51 2016 +0200 northbridge/amd/agesa: Remove commented code Change-Id: I08feb78763df15e6b9ccd2298a25ba2e6e3958f5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/agesa/agesawrapper.c | 5 - src/northbridge/amd/agesa/eventlog.c | 660 ------------------------------- 2 files changed, 665 deletions(-) diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c index a72e239..e31eceb 100644 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ b/src/northbridge/amd/agesa/agesawrapper.c @@ -188,11 +188,6 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); AmdCreateStruct(&AmdInterfaceParams); - -#if 0 - /* TODO: What to do with NvStorage here? */ - AmdS3LateParamsPtr->S3DataBlock.NvStorageSize = 0; -#endif AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; OemS3LateRestore(AmdS3LateParamsPtr); diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c index 0a40672..ce2d87f 100644 --- a/src/northbridge/amd/agesa/eventlog.c +++ b/src/northbridge/amd/agesa/eventlog.c @@ -45,666 +45,6 @@ static const char * decodeAGESA_STATUS(AGESA_STATUS sret) return statusStrings[sret]; } -#if 0 - -/** - * - */ -static void agesa_bound_check(EVENT_PARAMS *event) -{ - switch (event->EventInfo) { - case CPU_ERROR_HEAP_IS_FULL: - printk(BIOS_DEBUG, "Heap allocation for specified buffer handle failed as heap is full\n"); - break; - - case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED: - printk(BIOS_DEBUG, "Allocation incomplete as buffer has previously been allocated\n"); - break; - - case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT: - printk(BIOS_DEBUG, "Unable to locate buffer handle or deallocate heap as buffer handle cannot be located\n"); - break; - - case CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT: - printk(BIOS_DEBUG, "Unable to locate pointer to the heap buffer\n"); - break; - - default: - break; - } -} - -/** - * - */ -static void agesa_alert(EVENT_PARAMS *event) -{ - switch (event->EventInfo) { - case MEM_ALERT_USER_TMG_MODE_OVERRULED: - printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " - - "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case MEM_ALERT_ORG_MISMATCH_DIMM: - printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " - "DIMM organization miss-match\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case MEM_ALERT_BK_INT_DIS: - printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " - "Bank interleaving disable for internal issue\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case CPU_EVENT_BIST_ERROR: - printk(BIOS_DEBUG, "BIST error: %x reported on Socket %x Core %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_HW_SYNCFLOOD: - printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %x Link %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case HT_EVENT_HW_HTCRC: - printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %x Link %x Lanemask:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - default: - break; - } -} - -/** - * - */ -static void agesa_warning(EVENT_PARAMS *event) -{ -/* - if (event->EventInfo == CPU_EVENT_STACK_REENTRY) { - printk(BIOS_DEBUG, - "The stack has already been enabled and this is a - redundant invocation of AMD_ENABLE_STACK. There is no event logged and - no data values. The event sub-class is returned along with the status code\n"); - return; - } -*/ - - switch (event->EventInfo >> 24) { - case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case 0x08: - printk(BIOS_DEBUG, "Processor: "); - break; - - case 0x10: - printk(BIOS_DEBUG, "Hyper Transport: "); - break; - - default: - break; - } - - switch (event->EventInfo) { - case MEM_WARNING_UNSUPPORTED_QRDIMM: - printk(BIOS_DEBUG, "QR DIMMs detected but not supported\n"); - break; - - case MEM_WARNING_UNSUPPORTED_UDIMM: - printk(BIOS_DEBUG, "Unbuffered DIMMs detected but not supported\n"); - break; - - case MEM_WARNING_UNSUPPORTED_SODIMM: - printk(BIOS_DEBUG, "SO-DIMMs detected but not supported"); - break; - - case MEM_WARNING_UNSUPPORTED_X4DIMM: - printk(BIOS_DEBUG, "x4 DIMMs detected but not supported"); - break; - - case MEM_WARNING_UNSUPPORTED_RDIMM: - printk(BIOS_DEBUG, "Registered DIMMs detected but not supported"); - break; - -/* - case MEM_WARNING_UNSUPPORTED_LRDIMM: - printk(BIOS_DEBUG, "Load Reduced DIMMs detected but not supported"); - break; -*/ - - case MEM_WARNING_NO_SPDTRC_FOUND: - printk(BIOS_DEBUG, "NO_SPDTRC_FOUND"); - break; - - case MEM_WARNING_EMP_NOT_SUPPORTED: - printk(BIOS_DEBUG, "Processor is not capable for EMP");// - break; - - case MEM_WARNING_EMP_CONFLICT: - printk(BIOS_DEBUG, "EMP cannot be enabled if channel interleaving bank interleaving, or bank swizzle is enabled\n");// - break; - - case MEM_WARNING_EMP_NOT_ENABLED: - printk(BIOS_DEBUG, "Memory size is not power of two\n");// - break; - - case MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED: - printk(BIOS_DEBUG, "MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED\n"); - break; - - case MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED: - printk(BIOS_DEBUG, "MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED\n"); - break; - - case MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED: - printk(BIOS_DEBUG, "MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED\n"); - break; - - case MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED: - printk(BIOS_DEBUG, "MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED\n"); - break; - - case MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED: - printk(BIOS_DEBUG, "MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED\n"); - break; - -/* - case MEM_WARNING_INITIAL_DDR3VOLT_NONZERO: - printk(BIOS_DEBUG, "MEM_WARNING_INITIAL_DDR3VOLT_NONZERO\n"); - break; - - case MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO: - printk(BIOS_DEBUG, "MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO\n"); - break; -*/ - - case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: - printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); - if ((event->EventInfo & 0x000000FF) == 0x01) { - printk(BIOS_DEBUG, "AGESA_CACHE_SIZE_REDUCED\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x02) { - printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_1MB\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x03) { - printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n"); - } - printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case CPU_WARNING_ADJUSTED_LEVELING_MODE: - printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE " - "requested: %x, actual level:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case CPU_EVENT_PM_PSTATE_OVERCURRENT: - printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT " - "Socket: %x, Pstate:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG: - printk(BIOS_DEBUG, "CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG\n"); - break; - -/* - case CPU_EVENT_UNKNOWN_PROCESSOR_REVISION: - printk(BIOS_DEBUG, "CPU_EVENT_UNKNOWN_PROCESSOR_REVISION, socket: %lx, cpuid:%lx\n", - event->DataParam1, - event->DataParam2); - break; -*/ - - case HT_EVENT_OPT_REQUIRED_CAP_RETRY: - printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %lx Link %lx Depth %lx\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); - break; - - case HT_EVENT_OPT_REQUIRED_CAP_GEN3: - printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %x Link %x Depth %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_OPT_UNUSED_LINKS: - printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%x LinkA%x SocketB%x LinkB%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - break; - - case HT_EVENT_OPT_LINK_PAIR_EXCEED: - printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%x MasterLink%x SocketB%x AltLink%x\n", - - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - default: - break; - } -} - -/** - * - */ -static void agesa_error(EVENT_PARAMS *event) -{ - - switch (event->EventInfo >> 24) { - case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case 0x08: - printk(BIOS_DEBUG, "Processor: "); - break; - - case 0x10: - printk(BIOS_DEBUG, "Hyper Transport: "); - break; - - default: - break; - } - - switch (event->EventInfo) { - case MEM_ERROR_NO_DQS_POS_RD_WINDOW: - printk(BIOS_DEBUG, "No DQS Position window for RD DQS\n"); - break; - - case MEM_ERROR_SMALL_DQS_POS_RD_WINDOW: - printk(BIOS_DEBUG, "Small DQS Position window for RD DQS\n"); - break; - - case MEM_ERROR_NO_DQS_POS_WR_WINDOW: - printk(BIOS_DEBUG, "No DQS Position window for WR DQS\n"); - break; - - case MEM_ERROR_SMALL_DQS_POS_WR_WINDOW: - printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n"); - break; - - case MEM_ERROR_DIMM_SPARING_NOT_ENABLED: - printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n"); - break; - - case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE: - printk(BIOS_DEBUG, "Receive Enable value is too large\n"); - break; - case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW: - printk(BIOS_DEBUG, "There is no DQS receiver enable window\n"); - break; - - case MEM_ERROR_DRAM_ENABLED_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling DramEnabled bit\n"); - break; - - case MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling DctAccessDone bit\n"); - break; - - case MEM_ERROR_SEND_CTRL_WORD_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling SendCtrlWord bit\n"); - break; - - case MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling PrefDramTrainMode bit\n"); - break; - - case MEM_ERROR_ENTER_SELF_REF_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling EnterSelfRef bit\n"); - break; - - case MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling FreqChgInProg bit\n"); - break; - - case MEM_ERROR_EXIT_SELF_REF_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling ExitSelfRef bit\n"); - break; - - case MEM_ERROR_SEND_MRS_CMD_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling SendMrsCmd bit\n"); - break; - - case MEM_ERROR_SEND_ZQ_CMD_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling SendZQCmd bit\n"); - break; - - case MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling DctExtraAccessDone bit\n"); - break; - - case MEM_ERROR_MEM_CLR_BUSY_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling MemClrBusy bit\n"); - break; - - case MEM_ERROR_MEM_CLEARED_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling MemCleared bit\n"); - break; - - case MEM_ERROR_FLUSH_WR_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling FlushWr bit\n"); - break; - - case MEM_ERROR_MAX_LAT_NO_WINDOW: - printk(BIOS_DEBUG, "Fail to find pass during Max Rd Latency training\n"); - break; - - case MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL: - printk(BIOS_DEBUG, "Fail to launch training code on an AP\n"); - break; - - case MEM_ERROR_PARALLEL_TRAINING_TIME_OUT: - printk(BIOS_DEBUG, "Fail to finish parallel training\n"); - break; - - case MEM_ERROR_NO_ADDRESS_MAPPING: - printk(BIOS_DEBUG, "No address mapping found for a dimm\n"); - break; - - case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT: - printk(BIOS_DEBUG, "There is no DQS receiver enable window and the value is equal to the largest value\n"); - break; - - case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE: - printk(BIOS_DEBUG, "Receive Enable value is too large and is 1 less than limit\n"); - break; - - case MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR: - printk(BIOS_DEBUG, "SPD Checksum error for NV_SPDCHK_RESTRT\n"); - break; - - case MEM_ERROR_NO_CHIPSELECT: - printk(BIOS_DEBUG, "No chipselects found\n"); - break; - - case MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM: - printk(BIOS_DEBUG, "Unbuffered dimm is not supported at 333MHz\n"); - break; - - case MEM_ERROR_WL_PRE_OUT_OF_RANGE: - printk(BIOS_DEBUG, "Returned PRE value during write levelizzation was out of range\n"); - break; - - case CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE: - printk(BIOS_DEBUG, "No heap is allocated for BrandId structure\n"); - break; - - case CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED: - printk(BIOS_DEBUG, "Unable to load micro code patch\n"); - break; - - case CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE: - printk(BIOS_DEBUG, "No heap is allocated for the Pstate structure\n"); - break; - -/* - case CPU_ERROR_PM_NB_PSTATE_MISMATCH: - printk(BIOS_DEBUG, "NB P-state indicated by Index was disabled due to mismatch between processors\n"); - break; -*/ - - case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: - printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); - if ((event->EventInfo & 0x000000FF) == 0x04) { - printk(BIOS_DEBUG, "AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x05) { - printk(BIOS_DEBUG, "AGESA_START_ADDRESS_LESS_D0000\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x06) { - printk(BIOS_DEBUG, "AGESA_THREE_CACHE_REGIONS_ABOVE_1MB\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x07) { - printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n"); - } - printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_COH_NO_TOPOLOGY: - printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %x\n", - (unsigned int)event->DataParam1); - break; - - case HT_EVENT_NCOH_BUID_EXCEED: - printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%x Link%x Depth%x" - "Current BUID: %x, Unit Count: %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4 >> 16, - (unsigned int)event->DataParam4 & 0x0000FFFF); - break; - - case HT_EVENT_NCOH_BUS_MAX_EXCEED: - printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %x Link %x Bus %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_NCOH_CFG_MAP_EXCEED: - printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %x Link %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case HT_EVENT_NCOH_DEVICE_FAILED: - printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID" - "Socket %x Link %x Depth %x DeviceID %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - default: - break; - } -} -/** - * - */ -static void agesa_critical(EVENT_PARAMS *event) -{ - switch (event->EventInfo) { - case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3: - printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR3\n", - (unsigned int)event->DataParam1); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2: - printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR2\n", - (unsigned int)event->DataParam1); - break; - - case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG: - printk(BIOS_DEBUG, "Socket: %x, Dimm population is not supported\n", - (unsigned int)event->DataParam1); - break; - - case HT_EVENT_COH_PROCESSOR_TYPE_MIX: - printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_COH_MPCAP_MISMATCH: - printk(BIOS_DEBUG, "Socket %x Link %x MpCap %x TotalSockets %x, HT_EVENT_COH_MPCAP_MISMATCH\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - default: - break; - } -} - -/** - * - */ -static void agesa_fatal(EVENT_PARAMS *event) -{ - - switch (event->EventInfo >> 24) { - case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case 0x08: - printk(BIOS_DEBUG, "Processor: "); - break; - - case 0x10: - printk(BIOS_DEBUG, "Hyper Transport: "); - break; - - default: - break; - } - - switch (event->EventInfo) { - case MEM_ERROR_MINIMUM_MODE: - printk(BIOS_DEBUG, "Running in minimum mode\n"); - break; - - case MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM: - printk(BIOS_DEBUG, "DIMM modules are missmatched\n"); - break; - - case MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM: - printk(BIOS_DEBUG, "No DIMMs have been foun\n"); - break; - - case MEM_ERROR_MISMATCH_DIMM_CLOCKS: - printk(BIOS_DEBUG, "DIMM clocks miss-matched\n"); - break; - - case MEM_ERROR_NO_CYC_TIME: - printk(BIOS_DEBUG, "No cycle time found\n"); - break; - case MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS: - printk(BIOS_DEBUG, "Heap allocation error with dynamic storing of trained timings\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs: - printk(BIOS_DEBUG, "Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV: - printk(BIOS_DEBUG, "Heap allocation error with REMOTE_TRAINING_ENV\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_SPD: - printk(BIOS_DEBUG, "Heap allocation error for SPD data\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA: - printk(BIOS_DEBUG, "Heap allocation error for RECEIVED_DATA during parallel training\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS: - printk(BIOS_DEBUG, "Heap allocation error for S3 \"SPECIAL_CASE_REGISTER\"\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA: - printk(BIOS_DEBUG, "Heap allocation error for Training Data\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK: - printk(BIOS_DEBUG, "Heap allocation error for DIMM Identify \"MEM_NB_BLOCK\"\n"); - break; - - case MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM: - printk(BIOS_DEBUG, "No Constructor for DIMM Identify\n"); - break; - - case MEM_ERROR_VDDIO_UNSUPPORTED: - printk(BIOS_DEBUG, "VDDIO of the dimms on the board is not supported\n"); - break; - - case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT: - printk(BIOS_DEBUG, "Socket: %x, All PStates exceeded the motherboard current limit on specified socket\n", - (unsigned int)event->DataParam1); - break; - - default: - break; - } -} - -/** - * - * Interprte the agesa event log to an user readable string - */ -static void interpret_agesa_eventlog(EVENT_PARAMS *event) -{ - switch (event->EventClass) { - case AGESA_BOUNDS_CHK: - agesa_bound_check(event); - break; - - case AGESA_ALERT: - agesa_alert(event); - break; - - case AGESA_WARNING: - agesa_warning(event); - break; - - case AGESA_ERROR: - agesa_error(event); - break; - - case AGESA_CRITICAL: - agesa_critical(event); - break; - - case AGESA_FATAL: - agesa_fatal(event); - break; - - default: - break; - } -} -#endif - static void amd_readeventlog(AMD_CONFIG_PARAMS *StdHeader) { EVENT_PARAMS AmdEventParams;

1 0

New patch to review for coreboot: northbridge/amd/agesa/family15*: Remove commented code
by HAOUAS Elyes 05 Oct '16

05 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16896 -gerrit commit 97a6a9086535179238f91aef73d8ad9e60f1f8ca Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 20:22:29 2016 +0200 northbridge/amd/agesa/family15*: Remove commented code Change-Id: If372655700c18340d51368a39392560f664f4a45 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 34 ---------------------- src/northbridge/amd/agesa/family12/northbridge.c | 28 ------------------ src/northbridge/amd/agesa/family15/northbridge.c | 16 ---------- src/northbridge/amd/agesa/family15tn/northbridge.c | 13 --------- 4 files changed, 91 deletions(-) diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 64d904f..46af104 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -84,34 +84,11 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, #if !defined(__PRE_RAM__) static u32 get_io_addr_index(u32 nodeid, u32 linkn) { -#if 0 - u32 index; - - for (index = 0; index < 256; index++) { - if (sysconf.conf_io_addrx[index+4] == 0) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f); - sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); - return index; - } - } -#endif return 0; } static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) { -#if 0 - u32 index; - - for (index = 0; index < 64; index++) { - if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f); - sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); - return index; - } - } -#endif - return 0; } @@ -125,17 +102,6 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, pci_write_config32(__f1_dev[0], reg+4, tempreg); tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? -#if 0 - // FIXME: can we use VGA reg instead? - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", - __func__, dev_path(dev), link); - tempreg |= PCI_IO_BASE_VGA_EN; - } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { - tempreg |= PCI_IO_BASE_NO_ISA; - } -#endif pci_write_config32(__f1_dev[0], reg, tempreg); } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index cfc3438..9b2634c 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -34,7 +34,6 @@ #include "sb_cimx.h" #include <northbridge/amd/agesa/agesawrapper.h> -//#define FX_DEVS NODE_NUMS #define FX_DEVS 1 static device_t __f0_dev[FX_DEVS]; @@ -284,31 +283,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) mem_hole.node_id = 0; // record the node No with hole } } - -#if 0 - /* We need to double check if there is special set on base reg and limit reg - * are not continuous instead of hole, it will find out its hole_startk. - */ - if (mem_hole.node_id==-1) { - resource_t limitk_pri = 0; - struct dram_base_mask_t d; - resource_t base_k, limit_k; - d = get_dram_base_mask(0); - if (d.base & 1) { - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; - if (base_k <= 4 *1024 * 1024) { - if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G - mem_hole.node_id = 0; - } - } - - limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; - limitk_pri = limit_k; - } - } -#endif - return mem_hole; } #endif @@ -772,7 +746,6 @@ static unsigned long agesa_write_acpi_tables(device_t device, if (srat != NULL) { memcpy((void *)current, srat, srat->header.length); srat = (acpi_srat_t *) current; - //acpi_create_srat(srat); current += srat->header.length; acpi_add_table(rsdp, srat); } @@ -784,7 +757,6 @@ static unsigned long agesa_write_acpi_tables(device_t device, if (slit != NULL) { memcpy((void *)current, slit, slit->header.length); slit = (acpi_slit_t *) current; - //acpi_create_slit(slit); current += slit->header.length; acpi_add_table(rsdp, slit); } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index f4ca7ed..daf1de7 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -83,17 +83,6 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? -#if 0 - // FIXME: can we use VGA reg instead? - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", - __func__, dev_path(dev), link); - tempreg |= PCI_IO_BASE_VGA_EN; - } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { - tempreg |= PCI_IO_BASE_NO_ISA; - } -#endif for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -465,7 +454,6 @@ static void scan_chains(device_t dev) if (nodeid == 0) { ASSERT(dev->bus->secondary == 0); for (link = dev->link_list; link; link = link->next) { - //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ io_hub = link->children; if (!io_hub || !io_hub->enabled) { @@ -544,7 +532,6 @@ static unsigned long agesa_write_acpi_tables(device_t device, if (srat != NULL) { memcpy((void *)current, srat, srat->header.length); srat = (acpi_srat_t *) current; - //acpi_create_srat(srat); current += srat->header.length; acpi_add_table(rsdp, srat); } @@ -556,7 +543,6 @@ static unsigned long agesa_write_acpi_tables(device_t device, if (slit != NULL) { memcpy((void *)current, slit, slit->header.length); slit = (acpi_slit_t *) current; - //acpi_create_slit(slit); current += slit->header.length; acpi_add_table(rsdp, slit); } @@ -820,8 +806,6 @@ static void domain_set_resources(device_t dev) } - //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - /* split the region to accommodate pci memory space */ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 5ffee60..4279ba2 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -82,17 +82,6 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? -#if 0 - // FIXME: can we use VGA reg instead? - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", - __func__, dev_path(dev), link); - tempreg |= PCI_IO_BASE_VGA_EN; - } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { - tempreg |= PCI_IO_BASE_NO_ISA; - } -#endif for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -813,8 +802,6 @@ static void domain_set_resources(device_t dev) } - //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - /* split the region to accommodate pci memory space */ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) {

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2016