coreboot-gerrit October 2016

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Patch set updated for coreboot: soc/intel/apollolake: Set package power limits for RAPL registers
by Sumeet R Pawnikar 06 Oct '16

06 Oct '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16884 -gerrit commit 9793ad37963a23fb013bca4841a2c6b5b5bb7914 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Sep 27 23:18:35 2016 +0530 soc/intel/apollolake: Set package power limits for RAPL registers This patch sets the package power limit values in RAPL MSR and MMIO registers after boot and suspend-resume cycle. BUG=chrome-os-partner:56922 TEST=Built, booted and tested these package power limits before and after boot and suspend-resume cycle. Change-Id: I34208048a6d4a127e9b1267d2df043cb2c46cf77 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/soc/intel/apollolake/chip.c | 130 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 9 ++ 2 files changed, 139 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index eeac6ce..1928433 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -38,6 +38,39 @@ #include "chip.h" +#define MAX_NUM_ENTRY (sizeof lookup_table / sizeof lookup_table[0]) + +static const struct { + uint8_t time; + uint8_t msr_val; +} lookup_table[] = { + {0, 0}, + {1, 0x0a}, + {2, 0x0b}, + {3, 0x4b}, + {4, 0x0c}, + {5, 0x2c}, + {6, 0x4c}, + {7, 0x6c}, + {8, 0x0d}, + {10, 0x2d}, + {12, 0x4d}, + {14, 0x6d}, + {16, 0x0e}, + {20, 0x2e}, + {24, 0x4e}, + {28, 0x6e}, + {32, 0x0f}, + {40, 0x2f}, + {48, 0x4f}, + {56, 0x6f}, + {64, 0x10}, + {80, 0x30}, + {96, 0x50}, + {112, 0x70}, + {128, 0x11} +}; + static void *vbt; static struct region_device vbt_rdev; @@ -193,6 +226,100 @@ static void pcie_override_devicetree_after_silicon_init(void) pcie_update_device_tree(PCIEB0_DEVFN, 2); } +static uint8_t find_lookup_time(u8 in_msr) +{ + uint8_t index = 0; + + while (in_msr != lookup_table[index].msr_val && index < MAX_NUM_ENTRY) + index++; + + /* + * If some value is not part of this lookup table, + * assinging the default time value for PL1. + */ + if (index >= MAX_NUM_ENTRY) + return MB_POWER_LIMIT1_TIME_DEFAULT; + + return lookup_table[index].time; +} + +static uint8_t find_lookup_msr(u8 in_time) +{ + uint8_t index = 0; + + while (in_time != lookup_table[index].time && index < MAX_NUM_ENTRY) + index++; + + /* + * If some value is not part of this lookup table, + * assinging the default time value for PL1. + */ + if (index >= MAX_NUM_ENTRY) + return find_lookup_msr(MB_POWER_LIMIT1_TIME_DEFAULT); + + return lookup_table[index].msr_val; +} + +/* Configure package power limits */ +static void set_power_limits(u8 power_limit_1_time) +{ + uint32_t *rapl_mmio_reg; + msr_t rapl_msr_reg, limit; + unsigned power_unit; + unsigned tdp, min_power, max_power, max_time; + uint8_t power_limit_1_val; + + rapl_mmio_reg = (void*)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL); + + if (power_limit_1_time > MAX_NUM_ENTRY) + power_limit_1_time = MB_POWER_LIMIT1_TIME_DEFAULT; + + /* Get units */ + rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 1 << (rapl_msr_reg.lo & 0xf); + + /* Get power defaults for this SKU */ + rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU); + tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; + min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; + max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; + max_time = (rapl_msr_reg.hi >> 16) & 0x7f; + + printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); + + if (find_lookup_time(max_time) > power_limit_1_time) + power_limit_1_time = find_lookup_time(max_time); + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + power_limit_1_val = find_lookup_msr(power_limit_1_time); + + /* Set long term power limit to TDP */ + limit.lo = tdp & PKG_POWER_LIMIT_MASK; + + /* Set PL1 Pkg Power clamp bit */ + limit.lo |= PKG_POWER_LIMIT_CLAMP; + + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit PL2 to 15W */ + limit.hi = 0xf00 & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + + /* Program package power limits in RAPL MSR */ + wrmsr(MSR_PKG_POWER_LIMIT, limit); + + /* Setting RAPL MMIO register for Power limits */ + write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN)); + write32(rapl_mmio_reg + 1, limit.hi); +} + static void rapl_update(void) { uint32_t *rapl_reg; @@ -241,6 +368,9 @@ static void soc_init(void *data) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + /* Set RAPL MSR for Package power limits*/ + set_power_limits(MB_POWER_LIMIT1_TIME_DEFAULT); + /* Update RAPL package power limit */ rapl_update(); } diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 22412af..0195249 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -39,6 +39,15 @@ void apollolake_init_cpus(struct device *dev); #define PREFETCH_L2_DISABLE (1 << 2) #define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_SKU 0x614 +#define MSR_PKG_POWER_LIMIT 0x610 +#define PKG_POWER_LIMIT_MASK (0x7fff) +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK (0x7f) +/* For Mobile, default PL1 time window value is 28 seconds */ +#define MB_POWER_LIMIT1_TIME_DEFAULT 28 #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) #define MSR_IA32_PQR_ASSOC 0xc8f

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New patch to review for coreboot: soc/intel/skylake: Handle platform global reset
by Rizwan Qureshi 06 Oct '16

06 Oct '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16903 -gerrit commit 90a30e528076e873fba1823028d9b5f24fa20dc6 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Fri Aug 19 13:17:36 2016 +0530 soc/intel/skylake: Handle platform global reset In FSP1.1 all the platform resets including global was handled on its own without any intervention from coreboot. In FSP2.0, any reset required will be notified to coreboot and it is expected that coreboot will perform platform reset. Hence, implement platform global reset hooks in coreboot. If Intel ME is in non ERROR state then MEI message will able to perform global reset else force global reset by writing 0x6 or 0xE to 0xCF9 port with PCH ETR3 register bit [20] set. BUG=none BRANCH=none TEST=Verified platform global reset is working with MEI message or writing to PCH ETR3. Change-Id: I57e55caa6d20b15644bac686be8734d9652f21e5 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/reset.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index 638a151..0994762 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -16,13 +16,46 @@ #include <console/console.h> #include <fsp/util.h> #include <reset.h> +#include <soc/me.h> +#include <soc/pm.h> +#include <timer.h> + +static void do_force_global_reset(void) +{ + u32 reg32; + /*PMC Controller Device 0x1F, Func 02*/ + uint8_t *pmc_regs; + + /* + * BIOS should ensure it does a global reset + * to reset both host and Intel ME by setting + * PCH PMC [B0:D31:F2 register offset 0x1048 bit 20] + */ + pmc_regs = pmc_mmio_regs(); + reg32 = read32(pmc_regs + ETR3); + reg32 |= ETR3_CF9GR; + write32(pmc_regs + ETR3, reg32); + + /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port + * to global reset platform */ + hard_reset(); +} + +void global_reset(void) +{ + if (send_global_reset() != 0) { + /* If ME unable to reset platform then + * force global reset using PMC CF9GR register*/ + do_force_global_reset(); + } +} void chipset_handle_reset(uint32_t status) { switch(status) { case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - hard_reset(); + global_reset(); break; default: printk(BIOS_ERR, "unhandled reset type %x\n", status);

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New patch to review for coreboot: soc/intel/skylake: Implement Global Reset MEI message
by Rizwan Qureshi 06 Oct '16

06 Oct '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16902 -gerrit commit 0ffb93963ef2becf87f2805e7ddac99618b21787 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Fri Aug 19 12:33:42 2016 +0530 soc/intel/skylake: Implement Global Reset MEI message As per ME BWG, there are two mechanism to generate a Global Reset (resets both host and Intel ME), one is through CF9h IO write of 6h or Eh with "CF9h Global Reset" (CF9GR) bit set, PMC PCI offset ACh[20]. Another is to issue the Global Reset MEI message. Because any attempts to cause global reset without synchronizing the two sides might cause unwanted side effects, such as unwritten flash data that will get destroyed if the host were to cause a global reset without informing Intel ME firmware. The recommended method is to send a Global Reset MEI message when the following condition were met: The PCH chipset BIOS just needs to complete the Intel ME Interface #1 initialization and check the Intel ME HFSTS state if Intel ME is not in ERROR state and is accepting MEI commands then NIOS should be able to use Global Reset MEI message to trigger global reset. Furthermore, if Intel ME is in ERROR state, BIOS can use I/O 0xCF9 write of 0x06 or 0x0E command with PCH ETR3 register bit [20] to perform the global reset. BUG=none BRANCH=none TEST=Verified Global Reset MEI message can able to perform platform global issue in ME good state. Change-Id: If326a137eeadaa695668b76b84c510e12c546024 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 3 +- src/soc/intel/skylake/include/soc/iomap.h | 2 + src/soc/intel/skylake/include/soc/me.h | 66 +++ src/soc/intel/skylake/me.c | 695 ++++++++++++++++++++++++++++++ src/soc/intel/skylake/me_status.c | 324 -------------- 5 files changed, 765 insertions(+), 325 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ccd38ab..bf429ef 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -36,6 +36,7 @@ romstage-y += flash_controller.c romstage-y += gpio.c romstage-y += memmap.c romstage-y += monotonic_timer.c +romstage-y += me.c romstage-y += pch.c romstage-y += pcr.c romstage-y += pei_data.c @@ -59,7 +60,7 @@ ramstage-y += i2c.c ramstage-y += igd.c ramstage-y += irq.c ramstage-y += lpc.c -ramstage-y += me_status.c +ramstage-y += me.c ramstage-y += memmap.c ramstage-y += monotonic_timer.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index feba302..e736d3b 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -56,6 +56,8 @@ #define GPIO_BASE_SIZE 0x10000 +#define HECI1_BASE_ADDRESS 0xfed1a000 + /* * I/O port address space */ diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 423e9d1..b726711 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -21,6 +21,10 @@ /* * Management Engine PCI registers */ +#define PCI_ME_CMDSTS 0x04 +#define ME_CMDSTS_MSE 2 +#define ME_CMDSTS_BME 4 +#define PCI_ME_BAR 0x10 #define PCI_ME_HFSTS1 0x40 #define ME_HFS_CWS_RESET 0 #define ME_HFS_CWS_INIT 1 @@ -177,6 +181,68 @@ struct me_hfs3 { u32 power_down_mitigation: 1; } __attribute__ ((packed)); +/* + * Management Engine MMIO registers + */ +#define MMIO_ME_CB_WW 0x00 +#define MMIO_HOST_CSR 0x04 + +struct host_csr { + u32 int_en: 1; + u32 int_sts: 1; + u32 int_gen: 1; + u32 host_ready: 1; + u32 host_reset: 1; + u32 rsv: 3; + u32 host_read_ptr: 8; + u32 host_write_ptr: 8; + u32 me_cir_depth: 8; +} __attribute__ ((packed)); + +#define MMIO_ME_CB_RW 0x08 +#define MMIO_ME_CSR 0x0C + +struct me_csr { + u32 int_en: 1; + u32 int_sts: 1; + u32 int_gen: 1; + u32 host_ready: 1; + u32 host_reset: 1; + u32 rsv: 3; + u32 me_read_ptr: 8; + u32 me_write_ptr: 8; + u32 me_cir_buff: 8; +} __attribute__ ((packed)); + +#define MMIO_ME_D0I3 0x800 + +/* Reset Request */ +#define MKHI_GLOBAL_RESET 0x0b + +#define GR_ORIGIN_BIOS_MEM_INIT 0x01 +#define GR_ORIGIN_BIOS_POST 0x02 +#define GR_ORIGIN_MEBX 0x03 + +#define GLOBAL_RST_TYPE 0x01 + +#define BIOS_HOST_ADD 0x00 +#define HECI_MKHI_ADD 0x07 + +#define MAX_HECI_MESSAGE 5 +#define HECI_TIMEOUT 15000000 /* 15sec */ +#define HECI_SEND_TIMEOUT 5000000 /* 5sec */ +#define HECI_READ_TIMEOUT 5000000 /* 5sec */ +#define HECI_DELAY 1000 /* 1ms */ + +struct mei_header { + u32 client_address: 8; + u32 host_address: 8; + u32 length: 9; + u32 reserved: 6; + u32 is_complete: 1; +} __attribute__ ((packed)); + void intel_me_status(void); +int send_global_reset(void); #endif diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c new file mode 100644 index 0000000..7f62eef --- /dev/null +++ b/src/soc/intel/skylake/me.c @@ -0,0 +1,695 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/me.h> +#include <delay.h> +#include <timer.h> + +static inline void me_read_dword_ptr(void *ptr, int offset) +{ + u32 dword = pci_read_config32(PCH_DEV_ME, offset); + memcpy(ptr, &dword, sizeof(dword)); +} + +static inline void me_write_dword(int offset, u32 value) +{ + pci_write_config32(PCH_DEV_ME, offset, value); +} + +static inline void me_mmio_read_dword_ptr(void *ptr, u16 offset) +{ + u32 dword = read32((void *)(HECI1_BASE_ADDRESS + offset)); + memcpy(ptr, &dword, sizeof(dword)); +} + +static inline void me_mmio_write_dword_ptr(u16 offset, u32 value) +{ + write32((void *)(HECI1_BASE_ADDRESS + offset), value); +} + +/* HFSTS1[3:0] Current Working State Values */ +static const char *me_cws_values[] = { + [ME_HFS_CWS_RESET] = "Reset", + [ME_HFS_CWS_INIT] = "Initializing", + [ME_HFS_CWS_REC] = "Recovery", + [3] = "Unknown (3)", + [4] = "Unknown (4)", + [ME_HFS_CWS_NORMAL] = "Normal", + [ME_HFS_CWS_WAIT] = "Platform Disable Wait", + [ME_HFS_CWS_TRANS] = "OP State Transition", + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", + [9] = "Unknown (9)", + [10] = "Unknown (10)", + [11] = "Unknown (11)", + [12] = "Unknown (12)", + [13] = "Unknown (13)", + [14] = "Unknown (14)", + [15] = "Unknown (15)", +}; + +/* HFSTS1[8:6] Current Operation State Values */ +static const char *me_opstate_values[] = { + [ME_HFS_STATE_PREBOOT] = "Preboot", + [ME_HFS_STATE_M0_UMA] = "M0 with UMA", + [ME_HFS_STATE_M3] = "M3 without UMA", + [ME_HFS_STATE_M0] = "M0 without UMA", + [ME_HFS_STATE_BRINGUP] = "Bring up", + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" +}; + +/* HFSTS1[19:16] Current Operation Mode Values */ +static const char *me_opmode_values[] = { + [ME_HFS_MODE_NORMAL] = "Normal", + [ME_HFS_MODE_DEBUG] = "Debug", + [ME_HFS_MODE_DIS] = "Soft Temporary Disable", + [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" +}; + +/* HFSTS1[15:12] Error Code Values */ +static const char *me_error_values[] = { + [ME_HFS_ERROR_NONE] = "No Error", + [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", + [ME_HFS_ERROR_IMAGE] = "Image Failure", + [ME_HFS_ERROR_DEBUG] = "Debug Failure" +}; + +/* HFSTS2[31:28] ME Progress Code */ +static const char *me_progress_values[] = { + [ME_HFS2_PHASE_ROM] = "ROM Phase", + [1] = "Unknown (1)", + [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", + [ME_HFS2_PHASE_BUP] = "BUP Phase", + [4] = "Unknown (4)", + [5] = "Unknown (5)", + [ME_HFS2_PHASE_HOST_COMM] = "Host Communication", + [7] = "Unknown (7)", + [8] = "Unknown (8)" +}; + +/* HFSTS2[27:24] Power Management Event */ +static const char *me_pmevent_values[] = { + [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = + "Clean Moff->Mx wake", + [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = + "Moff->Mx wake after an error", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = + "Clean global reset", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = + "Global reset after an error", + [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = + "Clean Intel ME reset", + [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = + "Intel ME reset due to exception", + [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = + "Pseudo-global reset", + [ME_HFS2_PMEVENT_CM0_CM3] = + "CM0->CM3", + [ME_HFS2_PMEVENT_CM3_CM0] = + "CM3->CM0", + [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = + "Non-power cycle reset", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = + "Power cycle reset through M3", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = + "Power cycle reset through Moff", + [ME_HFS2_PMEVENT_CMX_CMOFF] = + "Cx/Mx->Cx/Moff", + [ME_HFS2_PMEVENT_CM0_CM0PG] = + "CM0->CM0PG", + [ME_HFS2_PMEVENT_CM3_CM3PG] = + "CM3->CM3PG", + [ME_HFS2_PMEVENT_CM0PG_CM0] = + "CM0PG->CM0" + +}; + +/* Progress Code 0 states */ +static const char *me_progress_rom_values[] = { + [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", + [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" +}; + +/* Progress Code 1 states */ +static const char *me_progress_bup_values[] = { + [ME_HFS2_STATE_BUP_INIT] = + "Initialization starts", + [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = + "Disable the host wake event", + [ME_HFS2_STATE_BUP_CG_ENABLE] = + "Enabling CG for cset", + [ME_HFS2_STATE_BUP_PM_HND_EN] = + "Enabling PM handshaking", + [ME_HFS2_STATE_BUP_FLOW_DET] = + "Flow determination start process", + [ME_HFS2_STATE_BUP_PMC_PATCHING] = + "PMC Patching process", + [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = + "Get VSCC params", + [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = + "Set VSCC params", + [ME_HFS2_STATE_BUP_VSCC_ERR] = + "Error reading/matching the VSCC table in the descriptor", + [ME_HFS2_STATE_BUP_EFSS_INIT] = + "Initialize EFFS", + [ME_HFS2_STATE_BUP_CHECK_STRAP] = + "Check to see if straps say ME DISABLED", + [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = + "Timeout waiting for PWROK", + [ME_HFS2_STATE_BUP_STRAP_DIS] = + "EFFS says ME disabled", + [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = + "Possibly handle BUP manufacturing override strap", + [ME_HFS2_STATE_BUP_M3] = + "Bringup in M3", + [ME_HFS2_STATE_BUP_M0] = + "Bringup in M0", + [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = + "Flow detection error", + [ME_HFS2_STATE_BUP_M3_CLK_ERR] = + "M3 clock switching error", + [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = + "Host error - CPU reset timeout, DID timeout, memory missing", + [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = + "M3 kernel load", + [ME_HFS2_STATE_BUP_T32_MISSING] = + "T34 missing - cannot program ICC", + [ME_HFS2_STATE_BUP_WAIT_DID] = + "Waiting for DID BIOS message", + [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = + "Waiting for DID BIOS message failure", + [ME_HFS2_STATE_BUP_DID_NO_FAIL] = + "DID reported no error", + [ME_HFS2_STATE_BUP_ENABLE_UMA] = + "Enabling UMA", + [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = + "Enabling UMA error", + [ME_HFS2_STATE_BUP_SEND_DID_ACK] = + "Sending DID Ack to BIOS", + [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = + "Sending DID Ack to BIOS error", + [ME_HFS2_STATE_BUP_M0_CLK] = + "Switching clocks in M0", + [ME_HFS2_STATE_BUP_M0_CLK_ERR] = + "Switching clocks in M0 error", + [ME_HFS2_STATE_BUP_TEMP_DIS] = + "ME in temp disable", + [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = + "M0 kernel load", +}; + +void intel_me_status(void) +{ + struct me_hfs _hfs, *hfs = &_hfs; + struct me_hfs2 _hfs2, *hfs2 = &_hfs2; + struct me_hfs3 _hfs3, *hfs3 = &_hfs3; + + me_read_dword_ptr(hfs, PCI_ME_HFSTS1); + me_read_dword_ptr(hfs2, PCI_ME_HFSTS2); + me_read_dword_ptr(hfs3, PCI_ME_HFSTS3); + + /* Check Current States */ + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfs->fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfs->ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfs->fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfs->mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfs->boot_options_present ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfs->update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D3 Support : %s\n", + hfs->d3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", + hfs->d0i3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", + hfs2->low_power_state ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Power Gated : %s\n", + hfs2->power_gating_ind ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfs2->cpu_replaced_sts ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfs2->cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %s\n", + me_cws_values[hfs->working_state]); + printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", + me_opstate_values[hfs->operation_state]); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", + me_opmode_values[hfs->operation_mode]); + printk(BIOS_DEBUG, "ME: Error Code : %s\n", + me_error_values[hfs->error_code]); + printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", + me_progress_values[hfs2->progress_code]); + printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", + me_pmevent_values[hfs2->current_pmevent]); + + printk(BIOS_DEBUG, "ME: Progress Phase State : "); + switch (hfs2->progress_code) { + case ME_HFS2_PHASE_ROM: /* ROM Phase */ + printk(BIOS_DEBUG, "%s", + me_progress_rom_values[hfs2->current_state]); + break; + + case ME_HFS2_PHASE_UKERNEL: /* uKernel Phase */ + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + break; + + case ME_HFS2_PHASE_BUP: /* Bringup Phase */ + if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) + && me_progress_bup_values[hfs2->current_state]) + printk(BIOS_DEBUG, "%s", + me_progress_bup_values[hfs2->current_state]); + else + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + break; + + case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ + if (!hfs2->current_state) + printk(BIOS_DEBUG, "Host communication established"); + else + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + break; + + default: + printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", + hfs2->progress_code, hfs2->current_state); + } + printk(BIOS_DEBUG, "\n"); + + /* Power Down Mitigation Status */ + printk(BIOS_DEBUG, "ME: Power Down Mitigation : %s\n", + hfs3->power_down_mitigation ? "YES" : "NO"); + + if (hfs3->power_down_mitigation) { + printk(BIOS_INFO, "ME: PD Mitigation State : "); + if (hfs3->encrypt_key_override == 1 && + hfs3->encrypt_key_check == 0 && + hfs3->pch_config_change == 0) + printk(BIOS_INFO, "Normal Operation"); + else if (hfs3->encrypt_key_override == 1 && + hfs3->encrypt_key_check == 1 && + hfs3->pch_config_change == 0) + printk(BIOS_INFO, "Issue Detected and Recovered"); + else + printk(BIOS_INFO, "Issue Detected but not Recovered"); + printk(BIOS_INFO, "\n"); + + printk(BIOS_DEBUG, "ME: Encryption Key Override : %s\n", + hfs3->encrypt_key_override ? "Workaround Applied" : + "Unable to override"); + printk(BIOS_DEBUG, "ME: Encryption Key Check : %s\n", + hfs3->encrypt_key_check ? "FAIL" : "PASS"); + printk(BIOS_DEBUG, "ME: PCH Configuration Info : %s\n", + hfs3->pch_config_change ? "Changed" : "No Change"); + + printk(BIOS_DEBUG, "ME: Firmware SKU : "); + switch (hfs3->fw_sku) { + case ME_HFS3_FW_SKU_CONSUMER: + printk(BIOS_DEBUG, "Consumer\n"); + break; + case ME_HFS3_FW_SKU_CORPORATE: + printk(BIOS_DEBUG, "Corporate\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown (0x%x)\n", hfs3->fw_sku); + } + } +} +static int wait_heci_ready(void) +{ + struct stopwatch sw; + int timeout = 0; + struct me_csr _csr, *csr = &_csr; + + stopwatch_init_msecs_expire(&sw, HECI_TIMEOUT); + while (1) { + do { + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + if (csr->host_ready) + return 0; + } while (!(timeout = stopwatch_expired(&sw))); + + if (timeout) { + printk(BIOS_ERR, + "ME_RDY bit is not set after 15 sec"); + return -1; + } + udelay(HECI_DELAY); + } +} + +static int wait_heci_cb_avail(int len) +{ + struct stopwatch sw; + int timeout = 0; + struct host_csr _csr, *csr = &_csr; + + me_mmio_read_dword_ptr(csr, MMIO_HOST_CSR); + /* + * if timeout has happend, return failure as + * the circular buffer is not empty + */ + stopwatch_init_msecs_expire(&sw, HECI_SEND_TIMEOUT); + /* Must have room for message and message header */ + while (len > (csr->me_cir_depth - (csr->host_write_ptr - + csr->host_read_ptr))) { + timeout = stopwatch_expired(&sw); + + if (timeout) { + printk(BIOS_ERR, + "Circular Buffer never emptied within 5 sec"); + return -1; + } + /* wait before trying again */ + udelay(HECI_DELAY); + /* read HOST_CSR for next iteration */ + me_mmio_read_dword_ptr(csr, MMIO_HOST_CSR); + } + return 0; +} + +static int send_heci_packet(struct mei_header *head, u32 * payload) +{ + /* compute the message lenth in dwords */ + int len = (head->length + 3) / 4; + int sts; + int index; + struct me_csr _csr, *csr = &_csr; + struct host_csr _hcsr, *hcsr = &_hcsr; + + /* + * wait until there is sufficient room in CB + */ + sts = wait_heci_cb_avail(len+1); + if (sts != 0) + return -1; + + /* Write message header */ + me_mmio_write_dword_ptr(MMIO_ME_CB_WW, *(u32 *) head); + + /* Write message body */ + for (index = 0; index < len; index++) + me_mmio_write_dword_ptr(MMIO_ME_CB_WW, payload[index]); + + /* Set Interrupt Generate bit */ + me_mmio_read_dword_ptr(hcsr, MMIO_HOST_CSR); + hcsr->int_gen = 1; + me_mmio_write_dword_ptr(MMIO_HOST_CSR, *(u32 *) hcsr); + + /* Check if ME Ready bit is set, if set to 0 then return fatal error */ + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + if (csr->host_ready) + return 0; + else + return -1; +} + +static int recv_heci_packet(struct mei_header *head, u32 * packet, + u32 * packet_size) +{ + struct me_csr _csr, *csr = &_csr; + struct host_csr _hcsr, *hcsr = &_hcsr; + int rec_msg = 0; + struct stopwatch sw; + int timeout = 0; + u32 length, index; + + /* Clear Interrupt Status bit */ + me_mmio_read_dword_ptr(hcsr, MMIO_HOST_CSR); + hcsr->int_sts = 1; + me_mmio_write_dword_ptr(MMIO_HOST_CSR, *(u32 *) hcsr); + + /* Check if circular buffer overflow */ + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + /* if yes then return fatal error */ + if ((csr->me_write_ptr - csr->me_read_ptr) > csr->me_cir_buff) + return -1; + /* + * if timeout has happend, return failure as + * the circular buffer is not empty + */ + stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); + /* go until we got message pkt */ + do { + timeout = stopwatch_expired(&sw); + + if (timeout) { + printk(BIOS_ERR, + "Circular Buffer not filled within 5 sec"); + *packet_size = 0; + return -1; + } + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + /* Read one message from HECI buffer */ + if ((csr->me_write_ptr - csr->me_read_ptr) > 0) { + me_mmio_read_dword_ptr(head, MMIO_ME_CB_RW); + /* calculate the message length in dword */ + length = ((head->length + 3) / 4); + if (head->length == 0) { + *packet_size = 0; + goto SET_IG; + } + /* Make sure, we have enough space to catch all */ + if (head->length <= *packet_size) { + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + /* get complete message into circular buffer */ + while (length > (csr->me_write_ptr - + csr->me_read_ptr)) { + udelay(HECI_DELAY); + me_mmio_read_dword_ptr(csr, + MMIO_ME_CSR); + } + /* here is the message */ + for (index = 0; index < length; index++) { + packet[index] = read32( + (void *)(HECI1_BASE_ADDRESS + + MMIO_ME_CB_RW)); + } + rec_msg = 1; + *packet_size = head->length; + } else { + /* Too small buffer */ + *packet_size = 0; + return -1; + } + } + udelay(HECI_DELAY); + } while (!rec_msg); + + /* + * Check if ME Ready bit is set, if set to 0 then return fatal error + * because ME might have reset during transaction and we might have + * read a junk data from CB + */ + me_mmio_read_dword_ptr(csr, MMIO_ME_CSR); + if (!(csr->host_ready)) + return -1; +SET_IG: + /* Set Interrupt Generate bit */ + me_mmio_read_dword_ptr(hcsr, MMIO_HOST_CSR); + hcsr->int_gen = 1; + me_mmio_write_dword_ptr(MMIO_HOST_CSR, *(u32 *) hcsr); + return 0; +} + +static int +send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress) +{ + u8 retry; + int status = -1; + u32 cir_buff_depth; + struct host_csr _csr, *csr = &_csr; + struct mei_header head; + int cur = 0; + u32 slength; + + for (retry = 0; retry < MAX_HECI_MESSAGE; retry++) { + if (wait_heci_ready() != 0) + continue; + /* HECI is ready */ + me_mmio_read_dword_ptr(csr, MMIO_HOST_CSR); + cir_buff_depth = csr->me_cir_depth; + head.client_address = clientaddress; + head.host_address = hostaddress; + while (len > cur) { + /* + * Set the message complete bit if this is last packet + * in message needs to be "less than" to account for + * the header OR needs to be exact equal to CB depth + */ + if (((((len - cur) + 3) / 4) < cir_buff_depth) || + (((((len - cur) + 3) / 4) == + cir_buff_depth) && + ((((len - cur) + 3) % 4) == 0))) + head.is_complete = 1; + else + head.is_complete = 0; + /* + * calculate length for message header + * header length = smaller of CB buffer or + * remaining message + */ + slength = ((cir_buff_depth <= (((len - cur) + 3) / 4)) + ? ((cir_buff_depth - 1) * 4) + : (len - cur)); + head.length = slength; + head.reserved = 0; + /* + * send the current packet + * (cur should be treated as index for message) + */ + status = send_heci_packet(&head, (u32 *) msg); + if (status != 0) + break; + /* update the length information */ + cur += slength; + msg += cur; + } + if (status != 0) + continue; + else + return status; + } + return status; +} + +static int +recv_heci_message(u32 * message, u32 * message_size) +{ + struct mei_header head; + int cur = 0; + u8 retry; + int status = -1; + int msg_complete = 0; + u32 pkt_buff; + + for (retry = 0; retry < MAX_HECI_MESSAGE; retry++) { + if (wait_heci_ready() != 0) + continue; + /* HECI is ready */ + while ((cur < *message_size) && (msg_complete == 0)) + { + pkt_buff = *message_size - cur; + status = recv_heci_packet(&head, message + (cur >> 2), + &pkt_buff); + if (status == -1) { + *message_size = 0; + break; + } + msg_complete = head.is_complete; + if (pkt_buff == 0) { + /* if not in middle of msg and msg complete bit + * is set then this is a valid zero length msg + */ + if ((cur == 0) && (msg_complete == 1)) + status = 0; + else + status = -1; + *message_size = 0; + break; + } + cur += pkt_buff; + } + if (status != 0) + continue; + else { + *message_size = cur; + break; + } + } + return status; +} + +static int send_heci_reset_message(void) +{ + int status; + struct reset_reply { + u8 group_id; + u8 command; + u8 reserved; + u8 result; + } __attribute__ ((packed)) reply; + struct reset_message { + u8 group_id; + u8 cmd; + u8 reserved; + u8 result; + u8 req_origin; + u8 reset_type; + } __attribute__ ((packed)) msg = { + 0, MKHI_GLOBAL_RESET, 0, 0, + GR_ORIGIN_BIOS_POST, GLOBAL_RST_TYPE}; + u32 reply_size; + + status= send_heci_message((u8 *) & msg, sizeof(msg), + BIOS_HOST_ADD, HECI_MKHI_ADD); + if (status != 0) + return -1; + + reply_size = sizeof(reply); + if (recv_heci_message((u32 *) & reply, &reply_size) == -1) + return -1; + /*get reply result from HECI MSG */ + if (reply.result != 0) { + printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); + return -1; + } else { + printk(BIOS_DEBUG, "%s: Exit with Success\n", __func__); + return 0; + } +} + +int send_global_reset(void) +{ + u32 heci1_bar; + u32 heci1_cmdsts; + int status = -1; + struct me_hfs _hfs, *hfs = &_hfs; + + /* Check HECI1 BAR gets programmed */ + me_read_dword_ptr(&heci1_bar, PCI_ME_BAR); + heci1_bar &= ~0xfff; + if (heci1_bar != HECI1_BASE_ADDRESS) { + /* use default HECI BAR for SoC */ + me_write_dword(PCI_ME_BAR, HECI1_BASE_ADDRESS); + } + /* Check MMIO space & Bus master enabled */ + me_read_dword_ptr(&heci1_cmdsts, PCI_ME_CMDSTS); + if ((heci1_cmdsts & (ME_CMDSTS_MSE | ME_CMDSTS_BME)) != + (ME_CMDSTS_MSE | ME_CMDSTS_BME)) { + me_write_dword(PCI_ME_CMDSTS, ME_CMDSTS_MSE | ME_CMDSTS_BME); + } + /* Check ME operating mode */ + me_read_dword_ptr(hfs, PCI_ME_HFSTS1); + if (hfs->operation_mode) { + goto ret; + } + /* ME should be in Normal Mode for this command */ + status = send_heci_reset_message(); +ret: + return status; +} diff --git a/src/soc/intel/skylake/me_status.c b/src/soc/intel/skylake/me_status.c deleted file mode 100644 index 79d4dfb..0000000 --- a/src/soc/intel/skylake/me_status.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <stdlib.h> -#include <string.h> -#include <soc/pci_devs.h> -#include <soc/me.h> -#include <delay.h> - -static inline void me_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = pci_read_config32(PCH_DEV_ME, offset); - memcpy(ptr, &dword, sizeof(dword)); -} - -/* HFSTS1[3:0] Current Working State Values */ -static const char *me_cws_values[] = { - [ME_HFS_CWS_RESET] = "Reset", - [ME_HFS_CWS_INIT] = "Initializing", - [ME_HFS_CWS_REC] = "Recovery", - [3] = "Unknown (3)", - [4] = "Unknown (4)", - [ME_HFS_CWS_NORMAL] = "Normal", - [ME_HFS_CWS_WAIT] = "Platform Disable Wait", - [ME_HFS_CWS_TRANS] = "OP State Transition", - [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", - [9] = "Unknown (9)", - [10] = "Unknown (10)", - [11] = "Unknown (11)", - [12] = "Unknown (12)", - [13] = "Unknown (13)", - [14] = "Unknown (14)", - [15] = "Unknown (15)", -}; - -/* HFSTS1[8:6] Current Operation State Values */ -static const char *me_opstate_values[] = { - [ME_HFS_STATE_PREBOOT] = "Preboot", - [ME_HFS_STATE_M0_UMA] = "M0 with UMA", - [ME_HFS_STATE_M3] = "M3 without UMA", - [ME_HFS_STATE_M0] = "M0 without UMA", - [ME_HFS_STATE_BRINGUP] = "Bring up", - [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" -}; - -/* HFSTS1[19:16] Current Operation Mode Values */ -static const char *me_opmode_values[] = { - [ME_HFS_MODE_NORMAL] = "Normal", - [ME_HFS_MODE_DEBUG] = "Debug", - [ME_HFS_MODE_DIS] = "Soft Temporary Disable", - [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", - [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" -}; - -/* HFSTS1[15:12] Error Code Values */ -static const char *me_error_values[] = { - [ME_HFS_ERROR_NONE] = "No Error", - [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", - [ME_HFS_ERROR_IMAGE] = "Image Failure", - [ME_HFS_ERROR_DEBUG] = "Debug Failure" -}; - -/* HFSTS2[31:28] ME Progress Code */ -static const char *me_progress_values[] = { - [ME_HFS2_PHASE_ROM] = "ROM Phase", - [1] = "Unknown (1)", - [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", - [ME_HFS2_PHASE_BUP] = "BUP Phase", - [4] = "Unknown (4)", - [5] = "Unknown (5)", - [ME_HFS2_PHASE_HOST_COMM] = "Host Communication", - [7] = "Unknown (7)", - [8] = "Unknown (8)" -}; - -/* HFSTS2[27:24] Power Management Event */ -static const char *me_pmevent_values[] = { - [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = - "Clean Moff->Mx wake", - [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = - "Moff->Mx wake after an error", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = - "Clean global reset", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = - "Global reset after an error", - [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = - "Clean Intel ME reset", - [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = - "Intel ME reset due to exception", - [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = - "Pseudo-global reset", - [ME_HFS2_PMEVENT_CM0_CM3] = - "CM0->CM3", - [ME_HFS2_PMEVENT_CM3_CM0] = - "CM3->CM0", - [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = - "Non-power cycle reset", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = - "Power cycle reset through M3", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = - "Power cycle reset through Moff", - [ME_HFS2_PMEVENT_CMX_CMOFF] = - "Cx/Mx->Cx/Moff", - [ME_HFS2_PMEVENT_CM0_CM0PG] = - "CM0->CM0PG", - [ME_HFS2_PMEVENT_CM3_CM3PG] = - "CM3->CM3PG", - [ME_HFS2_PMEVENT_CM0PG_CM0] = - "CM0PG->CM0" - -}; - -/* Progress Code 0 states */ -static const char *me_progress_rom_values[] = { - [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", - [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" -}; - -/* Progress Code 1 states */ -static const char *me_progress_bup_values[] = { - [ME_HFS2_STATE_BUP_INIT] = - "Initialization starts", - [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = - "Disable the host wake event", - [ME_HFS2_STATE_BUP_CG_ENABLE] = - "Enabling CG for cset", - [ME_HFS2_STATE_BUP_PM_HND_EN] = - "Enabling PM handshaking", - [ME_HFS2_STATE_BUP_FLOW_DET] = - "Flow determination start process", - [ME_HFS2_STATE_BUP_PMC_PATCHING] = - "PMC Patching process", - [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = - "Get VSCC params", - [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = - "Set VSCC params", - [ME_HFS2_STATE_BUP_VSCC_ERR] = - "Error reading/matching the VSCC table in the descriptor", - [ME_HFS2_STATE_BUP_EFSS_INIT] = - "Initialize EFFS", - [ME_HFS2_STATE_BUP_CHECK_STRAP] = - "Check to see if straps say ME DISABLED", - [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = - "Timeout waiting for PWROK", - [ME_HFS2_STATE_BUP_STRAP_DIS] = - "EFFS says ME disabled", - [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = - "Possibly handle BUP manufacturing override strap", - [ME_HFS2_STATE_BUP_M3] = - "Bringup in M3", - [ME_HFS2_STATE_BUP_M0] = - "Bringup in M0", - [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = - "Flow detection error", - [ME_HFS2_STATE_BUP_M3_CLK_ERR] = - "M3 clock switching error", - [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = - "Host error - CPU reset timeout, DID timeout, memory missing", - [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = - "M3 kernel load", - [ME_HFS2_STATE_BUP_T32_MISSING] = - "T34 missing - cannot program ICC", - [ME_HFS2_STATE_BUP_WAIT_DID] = - "Waiting for DID BIOS message", - [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = - "Waiting for DID BIOS message failure", - [ME_HFS2_STATE_BUP_DID_NO_FAIL] = - "DID reported no error", - [ME_HFS2_STATE_BUP_ENABLE_UMA] = - "Enabling UMA", - [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = - "Enabling UMA error", - [ME_HFS2_STATE_BUP_SEND_DID_ACK] = - "Sending DID Ack to BIOS", - [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = - "Sending DID Ack to BIOS error", - [ME_HFS2_STATE_BUP_M0_CLK] = - "Switching clocks in M0", - [ME_HFS2_STATE_BUP_M0_CLK_ERR] = - "Switching clocks in M0 error", - [ME_HFS2_STATE_BUP_TEMP_DIS] = - "ME in temp disable", - [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = - "M0 kernel load", -}; - -void intel_me_status(void) -{ - struct me_hfs _hfs, *hfs = &_hfs; - struct me_hfs2 _hfs2, *hfs2 = &_hfs2; - struct me_hfs3 _hfs3, *hfs3 = &_hfs3; - - me_read_dword_ptr(hfs, PCI_ME_HFSTS1); - me_read_dword_ptr(hfs2, PCI_ME_HFSTS2); - me_read_dword_ptr(hfs3, PCI_ME_HFSTS3); - - /* Check Current States */ - printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfs->fpt_bad ? "BAD" : "OK"); - printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfs->ft_bup_ld_flr ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfs->fw_init_complete ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfs->mfg_mode ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfs->boot_options_present ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfs->update_in_progress ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: D3 Support : %s\n", - hfs->d3_support_valid ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", - hfs->d0i3_support_valid ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", - hfs2->low_power_state ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Power Gated : %s\n", - hfs2->power_gating_ind ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", - hfs2->cpu_replaced_sts ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", - hfs2->cpu_replaced_valid ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - me_cws_values[hfs->working_state]); - printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - me_opstate_values[hfs->operation_state]); - printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - me_opmode_values[hfs->operation_mode]); - printk(BIOS_DEBUG, "ME: Error Code : %s\n", - me_error_values[hfs->error_code]); - printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - me_progress_values[hfs2->progress_code]); - printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - me_pmevent_values[hfs2->current_pmevent]); - - printk(BIOS_DEBUG, "ME: Progress Phase State : "); - switch (hfs2->progress_code) { - case ME_HFS2_PHASE_ROM: /* ROM Phase */ - printk(BIOS_DEBUG, "%s", - me_progress_rom_values[hfs2->current_state]); - break; - - case ME_HFS2_PHASE_UKERNEL: /* uKernel Phase */ - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - case ME_HFS2_PHASE_BUP: /* Bringup Phase */ - if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) - && me_progress_bup_values[hfs2->current_state]) - printk(BIOS_DEBUG, "%s", - me_progress_bup_values[hfs2->current_state]); - else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ - if (!hfs2->current_state) - printk(BIOS_DEBUG, "Host communication established"); - else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); - break; - - default: - printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", - hfs2->progress_code, hfs2->current_state); - } - printk(BIOS_DEBUG, "\n"); - - /* Power Down Mitigation Status */ - printk(BIOS_DEBUG, "ME: Power Down Mitigation : %s\n", - hfs3->power_down_mitigation ? "YES" : "NO"); - - if (hfs3->power_down_mitigation) { - printk(BIOS_INFO, "ME: PD Mitigation State : "); - if (hfs3->encrypt_key_override == 1 && - hfs3->encrypt_key_check == 0 && - hfs3->pch_config_change == 0) - printk(BIOS_INFO, "Normal Operation"); - else if (hfs3->encrypt_key_override == 1 && - hfs3->encrypt_key_check == 1 && - hfs3->pch_config_change == 0) - printk(BIOS_INFO, "Issue Detected and Recovered"); - else - printk(BIOS_INFO, "Issue Detected but not Recovered"); - printk(BIOS_INFO, "\n"); - - printk(BIOS_DEBUG, "ME: Encryption Key Override : %s\n", - hfs3->encrypt_key_override ? "Workaround Applied" : - "Unable to override"); - printk(BIOS_DEBUG, "ME: Encryption Key Check : %s\n", - hfs3->encrypt_key_check ? "FAIL" : "PASS"); - printk(BIOS_DEBUG, "ME: PCH Configuration Info : %s\n", - hfs3->pch_config_change ? "Changed" : "No Change"); - - printk(BIOS_DEBUG, "ME: Firmware SKU : "); - switch (hfs3->fw_sku) { - case ME_HFS3_FW_SKU_CONSUMER: - printk(BIOS_DEBUG, "Consumer\n"); - break; - case ME_HFS3_FW_SKU_CORPORATE: - printk(BIOS_DEBUG, "Corporate\n"); - break; - default: - printk(BIOS_DEBUG, "Unknown (0x%x)\n", hfs3->fw_sku); - } - } -}

1 0

Patch set updated for coreboot: cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E
by Arthur Heymans 06 Oct '16

06 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16901 -gerrit commit c368ca6e7d4a1f01307ba5b040ebb9a36478c7bd Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 6 12:14:14 2016 +0200 cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E The datasheets "Intel® Core™ Duo Processor and Intel® Core™ Solo Processor on 65 nm Process" mentions cpu C-states substates which can either be atteined by adding a substate hint to the MWAIT/P_LVLx request or automatically by setting some msr bits correctly. This just sets the same msr bits as model_6fx to enable dynamic L2 cache, C2E and C4E acpi cpu states. The results is that when limiting a thinkpad x60 with a yonah T2400 cpu to the acpi cpu C2 state, the idle power usage drops from 18W to 14W. When the lowest C-state is set to C4 the idle power usage seems to remain similar. Change-Id: I6c422656ace04659f32082a5944617eda6c79ec3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/cpu/intel/model_6ex/model_6ex_init.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 91633ec..d42ff69 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -69,7 +69,7 @@ static void configure_c_states(void) msr.lo |= (1 << 15); // config lock until next reset. msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - // TODO Do we want Deep C4 and Dynamic L2 shrinking? + msr.lo |= (1 << 3); //dynamic L2 /* Number of supported C-States */ msr.lo &= ~7; @@ -103,7 +103,13 @@ static void configure_misc(void) // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - // TODO Do we want Deep C4 and Dynamic L2 shrinking? + /* Enable C2E */ + msr.lo |= (1 << 26); + + /* Enable C4E */ + msr.hi |= (1 << (32 - 32)); // C4E + msr.hi |= (1 << (33 - 32)); // Hard C4E + wrmsr(IA32_MISC_ENABLE, msr); msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */

1 0

New patch to review for coreboot: cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E
by Arthur Heymans 06 Oct '16

06 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16901 -gerrit commit 61a007ec0defdf9e954e1ddb67b97bf4945526b9 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 6 12:14:14 2016 +0200 cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E The datasheets "Intel® Core™ Duo Processor and Intel® Core™ Solo Processor on 65 nm Process" mentions cpu C-states substates which can either be atteined by adding a substate hint to the MWAIT/P_LVLx request or automatically by setting some msr bits correctly. This just sets the same msr bits as model_6fx to enable dynamic L2 cache, C2E and C4E acpi cpu states. The results is that when limiting a thinkpad x60 with a yonah T2400 cpu to the acpi cpu C2 state, the idle power usage drops from 18W to 14W. When the lowest C-state is set to C4 the idle power usage seems to remain similar. Change-Id: I6c422656ace04659f32082a5944617eda6c79ec3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/cpu/intel/model_6ex/model_6ex_init.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 91633ec..d42ff69 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -69,7 +69,7 @@ static void configure_c_states(void) msr.lo |= (1 << 15); // config lock until next reset. msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - // TODO Do we want Deep C4 and Dynamic L2 shrinking? + msr.lo |= (1 << 3); //dynamic L2 /* Number of supported C-States */ msr.lo &= ~7; @@ -103,7 +103,13 @@ static void configure_misc(void) // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - // TODO Do we want Deep C4 and Dynamic L2 shrinking? + /* Enable C2E */ + msr.lo |= (1 << 26); + + /* Enable C4E */ + msr.hi |= (1 << (32 - 32)); // C4E + msr.hi |= (1 << (33 - 32)); // Hard C4E + wrmsr(IA32_MISC_ENABLE, msr); msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */

1 0

Patch set updated for coreboot: southbridge/nvidia: Remove commented code
by HAOUAS Elyes 06 Oct '16

06 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16899 -gerrit commit 790a9895895e7bb76e4991e0128bbc3074192824 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 5 22:17:30 2016 +0200 southbridge/nvidia: Remove commented code Change-Id: Ice4a5cae1a289852895012bb55035707b54cefb5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/nvidia/ck804/early_setup.c | 4 --- src/southbridge/nvidia/ck804/lpc.c | 6 ---- src/southbridge/nvidia/ck804/pci.c | 7 ----- src/southbridge/nvidia/ck804/sata.c | 35 --------------------- src/southbridge/nvidia/ck804/smbus.h | 43 -------------------------- src/southbridge/nvidia/mcp55/bootblock.c | 7 +---- src/southbridge/nvidia/mcp55/early_setup_car.c | 19 ------------ src/southbridge/nvidia/mcp55/lpc.c | 14 --------- src/southbridge/nvidia/mcp55/mcp55.c | 11 ------- 9 files changed, 1 insertion(+), 145 deletions(-) diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index abcb913..1d4999c 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -300,10 +300,6 @@ static void ck804_early_setup(void) setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); #endif -#if 0 - dump_io_resources(ANACTRL_IO_BASE); - dump_io_resources(SYSCTRL_IO_BASE); -#endif } static int ck804_early_setup_x(void) diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index d15ef8e..2b0bdd5 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -136,12 +136,6 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on * 12) + (on >> 1), (on & 1) * 5); } -#if 0 - /* Enable Port 92 fast reset (default is enabled). */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif /* Set up NMI on errors. */ byte = inb(0x70); /* RTC70 */ diff --git a/src/southbridge/nvidia/ck804/pci.c b/src/southbridge/nvidia/ck804/pci.c index 8ccf80c..5f21e09 100644 --- a/src/southbridge/nvidia/ck804/pci.c +++ b/src/southbridge/nvidia/ck804/pci.c @@ -33,13 +33,6 @@ static void pci_init(struct device *dev) dword |= (1 << 30); /* Clear possible errors */ pci_write_config32(dev, 0x04, dword); -#if 0 - word = pci_read_config16(dev, 0x48); - word |= (1 << 0); /* MRL2MRM */ - word |= (1 << 2); /* MR2MRM */ - pci_write_config16(dev, 0x48, word); -#endif - #if 1 dword = pci_read_config32(dev, 0x4c); dword |= 0x00440000; /* TABORT_SER_ENABLE Park Last Enable. */ diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c index b67cf28..c5dc56e 100644 --- a/src/southbridge/nvidia/ck804/sata.c +++ b/src/southbridge/nvidia/ck804/sata.c @@ -51,13 +51,6 @@ static void sata_com_reset(struct device *dev, unsigned reset) *(base + 8) = dword; *(base + 0x48) = dword; -#if 0 - udelay(1000); - dword &= ~(0xf); - *(base + 8) = dword; - *(base + 0x48) = dword; -#endif - if (reset) return; @@ -109,17 +102,6 @@ static void sata_init(struct device *dev) dword |= (1 << 1); printk(BIOS_DEBUG, "SATA P\n"); } -#if 0 - /* Write back */ - dword |= (1 << 12); - dword |= (1 << 14); -#endif - -#if 0 - /* ADMA */ - dword |= (1 << 16); - dword |= (1 << 17); -#endif #if 1 /* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */ @@ -128,23 +110,6 @@ static void sata_init(struct device *dev) #endif pci_write_config32(dev, 0x50, dword); -#if 0 - /* SLUMBER_DURING_D3 */ - dword = pci_read_config32(dev, 0x7c); - dword &= ~(1 << 4); - pci_write_config32(dev, 0x7c, dword); - - dword = pci_read_config32(dev, 0xd0); - dword &= ~(0xff << 24); - dword |= (0x68 << 24); - pci_write_config32(dev, 0xd0, dword); - - dword = pci_read_config32(dev, 0xe0); - dword &= ~(0xff << 24); - dword |= (0x68 << 24); - pci_write_config32(dev, 0xe0, dword); -#endif - dword = pci_read_config32(dev, 0xf8); dword |= 2; pci_write_config32(dev, 0xf8, dword); diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h index 6d0c510..40b8cb7 100644 --- a/src/southbridge/nvidia/ck804/smbus.h +++ b/src/southbridge/nvidia/ck804/smbus.h @@ -34,25 +34,6 @@ static inline void smbus_delay(void) outb(0x80, 0x80); } -#if 0 -/* Not needed, upon write to PRTCL, the status will be auto-cleared. */ -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) - return 0; - outb(val, smbus_io_base + SMBHSTSTAT); - } while (--loops); - return -2; -} -#endif - static int smbus_wait_until_done(unsigned smbus_io_base) { unsigned long loops; @@ -72,12 +53,6 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { unsigned char global_status_register, byte; -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - /* Set the device I'm talking to. */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); smbus_delay(); @@ -112,12 +87,6 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, { unsigned global_status_register; -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); @@ -151,12 +120,6 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, { unsigned char global_status_register, byte; -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - /* Set the device I'm talking to. */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); smbus_delay(); @@ -191,12 +154,6 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, { unsigned global_status_register; -#if 0 - /* Not needed, upon write to PRTCL, the status will be auto-cleared. */ - if (smbus_wait_until_ready(smbus_io_base) < 0) - return -2; -#endif - outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index b77463a..6d24f56 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -28,13 +28,8 @@ static void mcp55_enable_rom(void) pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ -#if 0 - /* Default MCP55 LPC single */ - addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0); -#else -// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0); + addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0); -#endif /* Set the 15MB enable bits. */ byte = pci_read_config8(addr, 0x88); diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 76947ec..7f1d03b 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -253,7 +253,6 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, #if CONFIG_MCP55_USE_AZA RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, - // RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1 << 14), (1 << 14), #endif #ifdef MCP55_MB_SETUP @@ -326,22 +325,6 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, PCI_DEV(busn[j], devn[j], 0), io_base[j]); } -#if 0 - for (j = 0; j < mcp55_num; j++) { - // PCI-E (XSPLL) SS table 0x40, x044, 0x48 - // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 - // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, - io_base[j] + ANACTRL_IO_BASE + 0x44, - io_base[j] + ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, - io_base[j] + ANACTRL_IO_BASE + 0xb4, - io_base[j] + ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, - io_base[j] + ANACTRL_IO_BASE + 0xc4, - io_base[j] + ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); - } -#endif } #ifndef HT_CHAIN_NUM_MAX @@ -405,7 +388,5 @@ out: mcp55_early_clear_port(mcp55_num, busn, devn, io_base); - // set_ht_link_mcp55(HT_CHAIN_NUM_MAX); - return 0; } diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 824abc5..afc6e64 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -91,11 +91,6 @@ static void lpc_init(device_t dev) lpc_common_init(dev, 1); -#if 0 - /* Posted memory write enable. */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1 << 0)); -#endif /* power after power fail */ #if 1 @@ -122,13 +117,6 @@ static void lpc_init(device_t dev) (on * 12) + (on >> 1), (on & 1) * 5); } -#if 0 - /* Enable Port 92 fast reset (default is enabled). */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif - /* Enable error reporting. */ /* Set up sync flood detected. */ byte = pci_read_config8(dev, 0x47); @@ -258,7 +246,6 @@ static struct device_operations lpc_ops = { .enable_resources = mcp55_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_lpc_bus, -// .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; static const unsigned short lpc_ids[] = { @@ -295,7 +282,6 @@ static struct device_operations lpc_slave_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_slave_init, -// .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c index cfe5e17..7c43fea 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ b/src/southbridge/nvidia/mcp55/mcp55.c @@ -68,9 +68,7 @@ void mcp55_enable(device_t dev) if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid >> 16) & 0xffff; -// vendorid &= 0xffff; } else { -// vendorid = dev->vendor; deviceid = dev->device; } @@ -200,15 +198,6 @@ void mcp55_enable(device_t dev) | (1 << 11) | (1 << 10) | (1 << 9)); pci_write_config32(sm_dev, 0xe8, final_reg); /* Enable all at first. */ -#if 0 - reg_old = reg = pci_read_config32(sm_dev, 0xe4); -// reg |= (1 << 0); - reg &= ~(0x3f << 4); - if (reg != reg_old) { - printk(BIOS_DEBUG, "mcp55.c pcie enabled\n"); - pci_write_config32(sm_dev, 0xe4, reg); - } -#endif } if (!dev->enabled) {

1 0

Patch set updated for coreboot: soc/intel/apollolake: Implement stage cache to improve resume time
by Brandon Breitenstein 06 Oct '16

06 Oct '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16833 -gerrit commit c815476dc70edb82779dd3e243242c918231b2c2 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Sep 30 13:57:12 2016 -0700 soc/intel/apollolake: Implement stage cache to improve resume time This patch enables stage cache to save ~40ms during S3 resume. It saves ramstage in the stage cache and restores it on resume so that ramstage does not have to reinitialize during the resume flow. Stage cache functionality is added to postcar stage since ramstage is called from postcar. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for Reef and tested ramstage being cached Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 2 ++ src/lib/Makefile.inc | 1 + src/lib/ext_stage_cache.c | 1 + src/soc/intel/apollolake/Kconfig | 6 +++++- src/soc/intel/apollolake/cpu.c | 8 ++++++-- src/soc/intel/apollolake/include/soc/smm.h | 4 +--- src/soc/intel/apollolake/memmap.c | 32 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/romstage.c | 15 ++++++++++++++ 8 files changed, 63 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 3986fe6..beeec7c 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -37,6 +37,8 @@ ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 394491c..67f8364 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -159,6 +159,7 @@ ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y) ramstage-y += ext_stage_cache.c romstage-y += ext_stage_cache.c +postcar-y += ext_stage_cache.c else ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 770097f..2a99188 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -126,3 +126,4 @@ static void stage_cache_setup(int is_recovery) ROMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) RAMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup) +POSTCAR_CBMEM_INIT_HOOK(stage_cache_setup) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3a23dbd..6c178c3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS select COMMON_FADT select GENERIC_GPIO_LIB @@ -34,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE - select NO_STAGE_CACHE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PCIEXP_ASPM @@ -254,4 +254,8 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n +config SMM_RESERVED_SIZE + hex + default 0x100000 + endif diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f3cf050..e67842c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -102,19 +102,23 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, { void *smm_base; size_t smm_size; + void *handler_base; + size_t handler_size; /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ smm_region(&smm_base, &smm_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; + *perm_smbase = (uintptr_t)handler_base; + *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h index 7a9846e..740d02b 100644 --- a/src/soc/intel/apollolake/include/soc/smm.h +++ b/src/soc/intel/apollolake/include/soc/smm.h @@ -20,6 +20,7 @@ #include <stdint.h> #include <soc/gpio.h> +#include <fsp/memmap.h> /* These helpers are for performing SMM relocation. */ void southbridge_clear_smi_status(void); @@ -35,7 +36,4 @@ void southbridge_smm_enable_smi(void); /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts); -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); #endif diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index ea6f447..cccbffd 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -24,6 +24,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <assert.h> #include <cbmem.h> #include <device/pci.h> #include <soc/northbridge.h> @@ -52,3 +53,34 @@ void smm_region(void **start, size_t *size) *start = (void *)smm_region_start(); *size = smm_region_size(); } + +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + assert(sub_size > CONFIG_SMM_RESERVED_SIZE); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..2384ceb 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/northbridge.h> @@ -105,6 +106,9 @@ asmlinkage void car_stage_entry(void) uintptr_t top_of_ram; bool s3wake; struct chipset_power_state *ps = car_get_var_ptr(&power_state); + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; timestamp_add_now(TS_START_ROMSTAGE); @@ -135,6 +139,17 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); }

1 0

Patch set updated for coreboot: soc/apollolake: Add soc core init
by Ravishankar Sarawadi 06 Oct '16

06 Oct '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16587 -gerrit commit c76a97f45475d01306f25e25b8566cd0c244ccbe Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Fri Sep 9 14:08:50 2016 -0700 soc/apollolake: Add soc core init Skip FSP initiated core/MP init. Add soc core init to setup following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST=Use iotools rdmsr and 'powertop' to check Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I97c3d82f654be30a0d2d88cb68c8212af3d6f767 --- src/soc/intel/apollolake/chip.c | 1 + src/soc/intel/apollolake/cpu.c | 21 ++++++++++++++++++++- src/soc/intel/apollolake/include/soc/cpu.h | 13 +++++++++++++ 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index eeac6ce..adc578d 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -416,6 +416,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; + silconfig->SkipMpInit = 1; /* Disable monitor mwait since it is broken due to a hardware bug without a fix */ silconfig->MonitorMwaitEnable = 0; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f3cf050..2182ef3 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -25,11 +25,30 @@ #include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> +#include <reg_script.h> #include <soc/cpu.h> #include <soc/smm.h> +static const struct reg_script core_msr_script[] = { + /* Enable C-state and IO/MWAIT redirect */ + REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL, + (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK + | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)), + /* Power Management I/O base address for I/O trapping to C-states */ + REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, 0x50414), + /* Disable C1E */ + REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + REG_SCRIPT_END +}; + +static void soc_core_init(device_t cpu) +{ + /* Set core MSRs */ + reg_script_run(core_msr_script); +} + static struct device_operations cpu_dev_ops = { - .init = DEVICE_NOOP, + .init = soc_core_init, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 22412af..3d682a0 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -40,6 +40,19 @@ void apollolake_init_cpus(struct device *dev); #define MSR_PKG_POWER_SKU_UNIT 0x606 +/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ +#define PKG_C_STATE_LIMIT_C2_MASK 0x2 +/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ +#define CORE_C_STATE_LIMIT_C10_MASK 0x70 +/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ +#define IO_MWAIT_REDIRECT_MASK 0x400 +/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ +#define CST_CFG_LOCK_MASK 0x8000 + +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_POWER_CTL 0x1fc + #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) #define MSR_IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */

1 0

New patch to review for coreboot: util/release/build-release: Update tar command
by Martin Roth 06 Oct '16

06 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16900 -gerrit commit e8efb386f79ef12e620c8570b7c7093f26cd4970 Author: Martin Roth <martinroth(a)google.com> Date: Wed Oct 5 16:35:29 2016 -0600 util/release/build-release: Update tar command Between GNU Tar 1.28 & 1.29, the files excluded by --exclude-vcs was updated. This breaks the reproducibility. Instead, just manually exclude the files to match what was excluded in v 1.28 and earlier. Change-Id: Ie0717891506f4a6d750ff264f9cc2494a296265b Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/release/build-release | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/release/build-release b/util/release/build-release index 20fbfb6..895285e 100755 --- a/util/release/build-release +++ b/util/release/build-release @@ -56,8 +56,8 @@ printf "%s-%s\n" "$VERSION_NAME" "$(git log --pretty=%H|head -1)" > .coreboot-v tstamp=$(git log --pretty=format:%ci -1) cd .. -tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs --exclude="coreboot-${VERSION_NAME}/3rdparty/blobs" -cvf - "coreboot-${VERSION_NAME}" |xz -9 > "coreboot-${VERSION_NAME}.tar.xz" -tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs -cvf - "coreboot-${VERSION_NAME}/3rdparty/blobs" |xz -9 > "coreboot-blobs-${VERSION_NAME}.tar.xz" +tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude=*/.git --exclude=*/.gitignore --exclude="coreboot-${VERSION_NAME}/3rdparty/blobs" -cvf - "coreboot-${VERSION_NAME}" |xz -9 > "coreboot-${VERSION_NAME}.tar.xz" +tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude=*/.git --exclude=*/.gitignore -cvf - "coreboot-${VERSION_NAME}/3rdparty/blobs" |xz -9 > "coreboot-blobs-${VERSION_NAME}.tar.xz" if [ -n "${GPG_KEY_ID}" ]; then gpg2 --armor --local-user "$GPG_KEY_ID" --output "coreboot-${VERSION_NAME}.tar.xz.sig" --detach-sig "coreboot-${VERSION_NAME}.tar.xz"

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Patch set updated for coreboot: soc/apollolake: Add soc core init
by Ravishankar Sarawadi 06 Oct '16

06 Oct '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16587 -gerrit commit 1fcacb7147a7cbe822808af3fd76e31578a70ce7 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Fri Sep 9 14:08:50 2016 -0700 soc/apollolake: Add soc core init Skip FSP initiated core/MP init. Add soc core init to setup following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST=Use iotools rdmsr and 'powertop' to check Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I97c3d82f654be30a0d2d88cb68c8212af3d6f767 --- src/soc/intel/apollolake/chip.c | 1 + src/soc/intel/apollolake/cpu.c | 21 ++++++++++++++++++++- src/soc/intel/apollolake/include/soc/cpu.h | 13 +++++++++++++ 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index eeac6ce..adc578d 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -416,6 +416,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; + silconfig->SkipMpInit = 1; /* Disable monitor mwait since it is broken due to a hardware bug without a fix */ silconfig->MonitorMwaitEnable = 0; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f3cf050..a1a7c17 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -25,11 +25,30 @@ #include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> +#include <reg_script.h> #include <soc/cpu.h> #include <soc/smm.h> +static const struct reg_script core_msr_script[] = { + /* Enable C-state and IO/MWAIT redirect */ + REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, + (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK + | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK), 0), + /* Power Management I/O base address for I/O trapping to C-states */ + REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, 0x50414), + /* Disable C1E */ + REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + REG_SCRIPT_END +}; + +static void soc_core_init(device_t cpu) +{ + /* Set core MSRs */ + reg_script_run(core_msr_script); +} + static struct device_operations cpu_dev_ops = { - .init = DEVICE_NOOP, + .init = soc_core_init, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 22412af..3d682a0 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -40,6 +40,19 @@ void apollolake_init_cpus(struct device *dev); #define MSR_PKG_POWER_SKU_UNIT 0x606 +/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ +#define PKG_C_STATE_LIMIT_C2_MASK 0x2 +/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ +#define CORE_C_STATE_LIMIT_C10_MASK 0x70 +/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ +#define IO_MWAIT_REDIRECT_MASK 0x400 +/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ +#define CST_CFG_LOCK_MASK 0x8000 + +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_POWER_CTL 0x1fc + #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) #define MSR_IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */

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coreboot-gerrit October 2016