coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/apollolake/cache_as_ram: Fix initial stack pointer calculation
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13314 -gerrit commit 0c00e57d0a9b37214cec1c52a25b82b32cdec427 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Oct 22 09:28:13 2015 -0700 soc/apollolake/cache_as_ram: Fix initial stack pointer calculation We want the initial stack pointer to point within the region allocated for stack, and not above it. This means we need to place it four bytes below the end address, so the first push does not write above the allocated stack region. Change-Id: I288b3c0f04b9e3be742012124ecac7825874cb7f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 6ecfa86..e496087 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -124,7 +124,7 @@ car_init_done: /* Setup bootblock stack */ mov esp, CONFIG_DCACHE_RAM_BASE - add esp, CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE + add esp, CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE - 4 /* Make sure CAR region is executable */ mov ecx, 0x120

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Patch set updated for coreboot: soc/apollolake/gpio: Use monotonically increasing pad numbers
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13315 -gerrit commit 2b633af25b62e1a1eb8e14d2e24edbda576ce251 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Oct 22 17:21:08 2015 -0700 soc/apollolake/gpio: Use monotonically increasing pad numbers After talking to Aaron, we decided we want to address the pads with a monotonically increasing numbers, so that the GPIO defines correspond to the GPIO numbers in ASL. Change-Id: I696d66634a737e515da5fae26eccaa6e1e3dcfda Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- .../apollolake/bootblock/early_chipset_config.S | 14 +- src/soc/intel/apollolake/include/soc/gpio_defs.h | 274 ++++++++++++++++++++- 2 files changed, 268 insertions(+), 20 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/early_chipset_config.S b/src/soc/intel/apollolake/bootblock/early_chipset_config.S index 4d67359..a673a28 100644 --- a/src/soc/intel/apollolake/bootblock/early_chipset_config.S +++ b/src/soc/intel/apollolake/bootblock/early_chipset_config.S @@ -63,25 +63,25 @@ init_lpc_pad: jmp cache_as_ram lpc_pad_params: - .long PAD_MMIO_ADDR(LPC_AD0) + .long PAD_MMIO_ADDR(PAD_SW(LPC_AD0)) .long PAD_CFG0_DEFAULT_NATIVE .long PAD_CFG1_DEFAULT_NATIVE - .long PAD_MMIO_ADDR(LPC_AD1) + .long PAD_MMIO_ADDR(PAD_SW(LPC_AD1)) .long PAD_CFG0_DEFAULT_NATIVE .long PAD_CFG1_DEFAULT_NATIVE - .long PAD_MMIO_ADDR(LPC_AD2) + .long PAD_MMIO_ADDR(PAD_SW(LPC_AD2)) .long PAD_CFG0_DEFAULT_NATIVE .long PAD_CFG1_DEFAULT_NATIVE - .long PAD_MMIO_ADDR(LPC_AD3) + .long PAD_MMIO_ADDR(PAD_SW(LPC_AD3)) .long PAD_CFG0_DEFAULT_NATIVE .long PAD_CFG1_DEFAULT_NATIVE - .long PAD_MMIO_ADDR(LPC_FRAMEB) + .long PAD_MMIO_ADDR(PAD_SW(LPC_FRAMEB)) .long PAD_CFG0_DEFAULT_NATIVE .long PAD_CFG1_DEFAULT_NATIVE - .long PAD_MMIO_ADDR(LPC_CLKOUT0) + .long PAD_MMIO_ADDR(PAD_SW(LPC_CLKOUT0)) .long PAD_CFG0_DEFAULT_NATIVE .long PAD_CFG1_DEFAULT_PULLUP - .long PAD_MMIO_ADDR(LPC_CLKOUT1) + .long PAD_MMIO_ADDR(PAD_SW(LPC_CLKOUT1)) .long PAD_CFG0_DEFAULT_NATIVE .long PAD_CFG1_DEFAULT_PULLUP num_lpc_pads = ( . - lpc_pad_params) / 0xc diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index c581662..f2bf00b 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -60,19 +60,267 @@ #define GPIO_NORTH 0xc5 #define GPIO_WEST 0xc7 -/* Special function pads in southwest community */ -#define SMB_ALERTB 31 -#define SMB_CLK 32 -#define SMB_DATA 33 -#define LPC_ILB_SERIRQ 34 -#define LPC_CLKOUT0 35 -#define LPC_CLKOUT1 36 -#define LPC_AD0 37 -#define LPC_AD1 38 -#define LPC_AD2 39 -#define LPC_AD3 40 -#define LPC_CLKRUNB 41 -#define LPC_FRAMEB 42 +/* North community pads */ +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_8 8 +#define GPIO_9 9 +#define GPIO_10 10 +#define GPIO_11 11 +#define GPIO_12 12 +#define GPIO_13 13 +#define GPIO_14 14 +#define GPIO_15 15 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_18 18 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_25 25 +#define GPIO_26 26 +#define GPIO_27 27 +#define GPIO_28 28 +#define GPIO_29 29 +#define GPIO_30 30 +#define GPIO_31 31 +#define GPIO_32 32 +#define GPIO_33 33 +#define GPIO_34 34 +#define GPIO_35 35 +#define GPIO_36 36 +#define GPIO_37 37 +#define GPIO_38 38 +#define GPIO_39 39 +#define GPIO_40 40 +#define GPIO_41 41 +#define GPIO_42 42 +#define GPIO_43 43 +#define GPIO_44 44 +#define GPIO_45 45 +#define GPIO_46 46 +#define GPIO_47 47 +#define GPIO_48 48 +#define GPIO_49 49 +#define GPIO_62 50 +#define GPIO_63 51 +#define GPIO_64 52 +#define GPIO_65 53 +#define GPIO_66 54 +#define GPIO_67 55 +#define GPIO_68 56 +#define GPIO_69 57 +#define GPIO_70 58 +#define GPIO_71 59 +#define GPIO_72 60 +#define GPIO_73 61 +#define TCK 62 +#define TRST_B 63 +#define TMS 64 +#define TDI 65 +#define CX_PMODE 66 +#define CX_PREQ_B 67 +#define JTAGX 68 +#define CX_PRDY_B 69 +#define TDO 70 +#define CNV_BRI_DT 71 +#define CNV_BRI_RSP 72 +#define CNV_RGI_DT 73 +#define CNV_RGI_RSP 74 +#define SVID0_ALERT_B 75 +#define SVID0_DATA 76 +#define SVID0_CLK 77 + +/* North community pads */ +#define NW_OFFSET 78 +#define GPIO_187 NW_OFFSET + 0 +#define GPIO_188 NW_OFFSET + 1 +#define GPIO_189 NW_OFFSET + 2 +#define GPIO_190 NW_OFFSET + 3 +#define GPIO_191 NW_OFFSET + 4 +#define GPIO_192 NW_OFFSET + 5 +#define GPIO_193 NW_OFFSET + 6 +#define GPIO_194 NW_OFFSET + 7 +#define GPIO_195 NW_OFFSET + 8 +#define GPIO_196 NW_OFFSET + 9 +#define GPIO_197 NW_OFFSET + 10 +#define GPIO_198 NW_OFFSET + 11 +#define GPIO_199 NW_OFFSET + 12 +#define GPIO_200 NW_OFFSET + 13 +#define GPIO_201 NW_OFFSET + 14 +#define GPIO_202 NW_OFFSET + 15 +#define GPIO_203 NW_OFFSET + 16 +#define GPIO_204 NW_OFFSET + 17 +#define PMC_SPI_FS0 NW_OFFSET + 18 +#define PMC_SPI_FS1 NW_OFFSET + 19 +#define PMC_SPI_FS2 NW_OFFSET + 20 +#define PMC_SPI_RXD NW_OFFSET + 21 +#define PMC_SPI_TXD NW_OFFSET + 22 +#define PMC_SPI_CLK NW_OFFSET + 23 +#define PMIC_PWRGOOD NW_OFFSET + 24 +#define PMIC_RESET_B NW_OFFSET + 25 +#define GPIO_213 NW_OFFSET + 26 +#define GPIO_214 NW_OFFSET + 27 +#define GPIO_215 NW_OFFSET + 28 +#define PMIC_THERMTRIP_B NW_OFFSET + 29 +#define PMIC_STDBY NW_OFFSET + 30 +#define PROCHOT_B NW_OFFSET + 31 +#define PMIC_I2C_SCL NW_OFFSET + 32 +#define PMIC_I2C_SDA NW_OFFSET + 33 +#define GPIO_74 NW_OFFSET + 34 +#define GPIO_75 NW_OFFSET + 35 +#define GPIO_76 NW_OFFSET + 36 +#define GPIO_77 NW_OFFSET + 37 +#define GPIO_78 NW_OFFSET + 38 +#define GPIO_79 NW_OFFSET + 39 +#define GPIO_80 NW_OFFSET + 40 +#define GPIO_81 NW_OFFSET + 41 +#define GPIO_82 NW_OFFSET + 42 +#define GPIO_83 NW_OFFSET + 43 +#define GPIO_84 NW_OFFSET + 44 +#define GPIO_85 NW_OFFSET + 45 +#define GPIO_86 NW_OFFSET + 46 +#define GPIO_87 NW_OFFSET + 47 +#define GPIO_88 NW_OFFSET + 48 +#define GPIO_89 NW_OFFSET + 49 +#define GPIO_90 NW_OFFSET + 50 +#define GPIO_91 NW_OFFSET + 51 +#define GPIO_92 NW_OFFSET + 52 +#define GPIO_97 NW_OFFSET + 53 +#define GPIO_98 NW_OFFSET + 54 +#define GPIO_99 NW_OFFSET + 55 +#define GPIO_100 NW_OFFSET + 56 +#define GPIO_101 NW_OFFSET + 57 +#define GPIO_102 NW_OFFSET + 58 +#define GPIO_103 NW_OFFSET + 59 +#define FST_SPI_CLK_FB NW_OFFSET + 60 +#define GPIO_104 NW_OFFSET + 61 +#define GPIO_105 NW_OFFSET + 62 +#define GPIO_106 NW_OFFSET + 63 +#define GPIO_109 NW_OFFSET + 64 +#define GPIO_110 NW_OFFSET + 65 +#define GPIO_111 NW_OFFSET + 66 +#define GPIO_112 NW_OFFSET + 67 +#define GPIO_113 NW_OFFSET + 68 +#define GPIO_116 NW_OFFSET + 69 +#define GPIO_117 NW_OFFSET + 70 +#define GPIO_118 NW_OFFSET + 71 +#define GPIO_119 NW_OFFSET + 72 +#define GPIO_120 NW_OFFSET + 73 +#define GPIO_121 NW_OFFSET + 74 +#define GPIO_122 NW_OFFSET + 75 +#define GPIO_123 NW_OFFSET + 76 + +/* West community pads */ +#define W_OFFSET (NW_OFFSET + 77) +#define GPIO_124 W_OFFSET + 0 +#define GPIO_125 W_OFFSET + 1 +#define GPIO_126 W_OFFSET + 2 +#define GPIO_127 W_OFFSET + 3 +#define GPIO_128 W_OFFSET + 4 +#define GPIO_129 W_OFFSET + 5 +#define GPIO_130 W_OFFSET + 6 +#define GPIO_131 W_OFFSET + 7 +#define GPIO_132 W_OFFSET + 8 +#define GPIO_133 W_OFFSET + 9 +#define GPIO_134 W_OFFSET + 10 +#define GPIO_135 W_OFFSET + 11 +#define GPIO_136 W_OFFSET + 12 +#define GPIO_137 W_OFFSET + 13 +#define GPIO_138 W_OFFSET + 14 +#define GPIO_139 W_OFFSET + 15 +#define GPIO_146 W_OFFSET + 16 +#define GPIO_147 W_OFFSET + 17 +#define GPIO_148 W_OFFSET + 18 +#define GPIO_149 W_OFFSET + 19 +#define GPIO_150 W_OFFSET + 20 +#define GPIO_151 W_OFFSET + 21 +#define GPIO_152 W_OFFSET + 22 +#define GPIO_153 W_OFFSET + 23 +#define GPIO_154 W_OFFSET + 24 +#define GPIO_155 W_OFFSET + 25 +#define GPIO_209 W_OFFSET + 26 +#define GPIO_210 W_OFFSET + 27 +#define GPIO_211 W_OFFSET + 28 +#define GPIO_212 W_OFFSET + 29 +#define OSC_CLK_OUT_0 W_OFFSET + 30 +#define OSC_CLK_OUT_1 W_OFFSET + 31 +#define OSC_CLK_OUT_2 W_OFFSET + 32 +#define OSC_CLK_OUT_3 W_OFFSET + 33 +#define OSC_CLK_OUT_4 W_OFFSET + 34 +#define PMU_AC_PRESENT W_OFFSET + 35 +#define PMU_BATLOW_B W_OFFSET + 36 +#define PMU_PLTRST_B W_OFFSET + 37 +#define PMU_PWRBTN_B W_OFFSET + 38 +#define PMU_RESETBUTTON_B W_OFFSET + 39 +#define PMU_SLP_S0_B W_OFFSET + 40 +#define PMU_SLP_S3_B W_OFFSET + 41 +#define PMU_SLP_S4_B W_OFFSET + 42 +#define PMU_SUSCLK W_OFFSET + 43 +#define PMU_WAKE_B W_OFFSET + 44 +#define SUS_STAT_B W_OFFSET + 45 +#define SUSPWRDNACK W_OFFSET + 46 + +/* Southwest community pads */ +#define SW_OFFSET (W_OFFSET + 47) +#define GPIO_205 SW_OFFSET + 0 +#define GPIO_206 SW_OFFSET + 1 +#define GPIO_207 SW_OFFSET + 2 +#define GPIO_208 SW_OFFSET + 3 +#define GPIO_156 SW_OFFSET + 4 +#define GPIO_157 SW_OFFSET + 5 +#define GPIO_158 SW_OFFSET + 6 +#define GPIO_159 SW_OFFSET + 7 +#define GPIO_160 SW_OFFSET + 8 +#define GPIO_161 SW_OFFSET + 9 +#define GPIO_162 SW_OFFSET + 10 +#define GPIO_163 SW_OFFSET + 11 +#define GPIO_164 SW_OFFSET + 12 +#define GPIO_165 SW_OFFSET + 13 +#define GPIO_166 SW_OFFSET + 14 +#define GPIO_167 SW_OFFSET + 15 +#define GPIO_168 SW_OFFSET + 16 +#define GPIO_169 SW_OFFSET + 17 +#define GPIO_170 SW_OFFSET + 18 +#define GPIO_171 SW_OFFSET + 19 +#define GPIO_172 SW_OFFSET + 20 +#define GPIO_179 SW_OFFSET + 21 +#define GPIO_173 SW_OFFSET + 22 +#define GPIO_174 SW_OFFSET + 23 +#define GPIO_175 SW_OFFSET + 24 +#define GPIO_176 SW_OFFSET + 25 +#define GPIO_177 SW_OFFSET + 26 +#define GPIO_178 SW_OFFSET + 27 +#define GPIO_186 SW_OFFSET + 28 +#define GPIO_182 SW_OFFSET + 29 +#define GPIO_183 SW_OFFSET + 30 +#define SMB_ALERTB SW_OFFSET + 31 +#define SMB_CLK SW_OFFSET + 32 +#define SMB_DATA SW_OFFSET + 33 +#define LPC_ILB_SERIRQ SW_OFFSET + 34 +#define LPC_CLKOUT0 SW_OFFSET + 35 +#define LPC_CLKOUT1 SW_OFFSET + 36 +#define LPC_AD0 SW_OFFSET + 37 +#define LPC_AD1 SW_OFFSET + 38 +#define LPC_AD2 SW_OFFSET + 39 +#define LPC_AD3 SW_OFFSET + 40 +#define LPC_CLKRUNB SW_OFFSET + 41 +#define LPC_FRAMEB SW_OFFSET + 42 + +/* Macros for translating a global pad offset to a local offset */ +#define PAD_N(pad) (pad) +#define PAD_NW(pad) (pad - NW_OFFSET) +#define PAD_W(pad) (pad - W_OFFSET) +#define PAD_SW(pad) (pad - SW_OFFSET) /* Default configurations */ #define PAD_CFG0_DEFAULT_FUNC(x) (0x44000000 | PAD_CFG0_MODE_FUNC(x))

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Patch set updated for coreboot: soc/apollolake: Add support for memory-mapped boot media
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13309 -gerrit commit dda0f21bf1e0687dc16a07e2d99c5e78852fa6dc Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Oct 14 11:16:30 2015 -0700 soc/apollolake: Add support for memory-mapped boot media On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Change-Id: Ib57e01310c1a2b91e027abcbd6ac2c5cad9fddf3 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/arch/x86/Makefile.inc | 3 ++ src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/mmap_boot.c | 63 +++++++++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 86290ab..bd9e348 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -144,6 +144,9 @@ ifeq ($(CONFIG_SSE),y) bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__ endif +bootblock-y += memset.c +bootblock-y += memcpy.c + # This is a hack in case there are no per chipset linker files. $(objgenerated)/empty: build-dirs touch $@ diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 9d3897f..0af3f36 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -13,6 +13,7 @@ bootblock-y += gpio.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/early_chipset_config.S bootblock-y += uart_early.c +bootblock-y += mmap_boot.c romstage-y += cpu.c romstage-y += gpio.c diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c new file mode 100644 index 0000000..7e9080b --- /dev/null +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <boot_device.h> +#include <console/console.h> +#include <cbfs.h> +#include <endian.h> +#include <stdlib.h> +#include <commonlib/region.h> +#include <fmap.h> + +/* + * If Apollo Lake is configured to boot from SPI flash "BIOS" region + * (as defined in descriptor) is mapped below 4GiB. Form a pointer for + * the base. + */ +#define ROM_BASE ((void *)(uintptr_t)(0x100000000ULL - CONFIG_IFD_BIOS_SIZE)) + +static const struct mem_region_device boot_dev = { + .base = (void *) ROM_BASE, + /* typically not whole flash is memory mapped */ + .rdev = REGION_DEV_INIT(&mem_rdev_ops, CONFIG_IFD_BIOS_START, + CONFIG_IFD_BIOS_SIZE) +}; + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} + +static int iafw_boot_region_properties(struct cbfs_props *props) +{ + struct region regn; + + /* use fmap to locate CBFS area */ + if (fmap_locate_area("COREBOOT", &regn)) + return 1; + + props->offset = regn.offset; + props->size = regn.size; + + printk(BIOS_DEBUG, "CBFS @ %zx size %zx\n", props->offset, props->size); + + return 0; +} + +/* + * Named cbfs_master_header_locator so that it overrides the default, but + * incompatible locator in cbfs.c + */ +const struct cbfs_locator cbfs_master_header_locator = { + .name = "IAFW Locator", + .locate = iafw_boot_region_properties, +};

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Patch set updated for coreboot: intel/apollolake_rvp: Add default offsets for boot media
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13310 -gerrit commit 33702a50933c38306ec1bc5b362b7cac16489a6d Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Oct 14 14:49:32 2015 -0700 intel/apollolake_rvp: Add default offsets for boot media This adds offsets necessary for accessing memory mapped flash. They should be parsed from FMAP automatically in the future. Change-Id: I4a38129b95d3eb518bcd343abd8b16f89932555f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 152e092..492ccdc 100755 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -17,4 +17,17 @@ config MAINBOARD_VENDOR string default "Intel" +config IFD_BIOS_SIZE + hex + default 0x700000 + +config IFD_BIOS_START + hex + default 0x1000 + +config FLASHMAP_OFFSET + hex + default 0x3a3040 if BOARD_INTEL_APOLLOLAKE_RVP1 + default 0x3f10c0 if BOARD_INTEL_APOLLOLAKE_RVP2 + endif # BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2

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Patch set updated for coreboot: soc/apollolake: Disable watchdog timer after console initialization
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13311 -gerrit commit 1eff21041805fc146aa59fff95c850906d250027 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Oct 9 17:34:46 2015 -0700 soc/apollolake: Disable watchdog timer after console initialization Change-Id: I0680d3866cece70e3ea03b5c1b22769149fc2278 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/bootblock/bootblock_car.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/soc/intel/apollolake/bootblock/bootblock_car.c b/src/soc/intel/apollolake/bootblock/bootblock_car.c index 3a0110e..e9cbb09 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock_car.c +++ b/src/soc/intel/apollolake/bootblock/bootblock_car.c @@ -12,9 +12,26 @@ #include <arch/io.h> #include <console/console.h> +#include <device/pci.h> #include <soc/bootblock.h> #include <soc/uart.h> +static void disable_watchdog(void) +{ + uint32_t reg; + device_t dev = PCI_DEV(0, 0xd, 1); + + /* Open up an IO window */ + pci_write_config16(dev, PCI_BASE_ADDRESS_4, 0x400); + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_IO); + + /* We don't have documentation for this bit, but it prevents reboots */ + reg = inl(0x400 + 0x68); + reg |= 1 << 11; + outl(reg, 0x400 + 0x68); +} + void bootblock_car_main(void) { /* Quick post code to show we made it to C code */ @@ -25,6 +42,9 @@ void bootblock_car_main(void) console_init(); } + /* Wait until after we have console to disable this */ + disable_watchdog(); + /* Don't return, so we see the above post code */ while (1) ;

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Patch set updated for coreboot: soc/apollolake: Override default mmap_boot.c for all stages
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13320 -gerrit commit d4b781264bcc3aea79f30a5f8d9d5095830f5e5e Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 27 10:31:26 2015 -0700 soc/apollolake: Override default mmap_boot.c for all stages The Apollolake-specific mmap_boot.c implementation was only compiled for the bootblock. This worked because the generic one was never included in the bootblock, so we didn't get duplicate symbol. However, the default mmap_boot won't work on this SOC, so we need to override it for all stages where it is used. Change-Id: If633349e0700437d8adfe6af9da045e80c9f02c5 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 4 ++++ src/soc/intel/apollolake/Makefile.inc | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index e5b0649..4b181ea 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -36,6 +36,10 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_CONSTANT_RATE +config X86_TOP4G_BOOTMEDIA_MAP + bool + default n + config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address" default 0xe0000000 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 0af3f36..4b0b31d 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -12,15 +12,17 @@ bootblock-y += cpu.c bootblock-y += gpio.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/early_chipset_config.S -bootblock-y += uart_early.c bootblock-y += mmap_boot.c +bootblock-y += uart_early.c romstage-y += cpu.c romstage-y += gpio.c +romstage-y += mmap_boot.c romstage-y += uart_early.c ramstage-y += cpu.c ramstage-y += gpio.c +ramstage-y += mmap_boot.c ramstage-y += uart.c romstage-y += placeholders.c

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New patch to review for coreboot: payloads/coreinfo: Add defaultbuild target
by Martin Roth 25 Jan '16

25 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13426 -gerrit commit 0d78a56555361e158fec0e8237eb05a3a88a0e2e Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 25 14:01:55 2016 -0700 payloads/coreinfo: Add defaultbuild target Add a single target to do the full coreinfo build using default Kconfig values for both coreinfo and libpayload. Change-Id: Id622fb2df480e826f6d868dbe01385d76587be26 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/coreinfo/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 6f7ce51..a3a02c2 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -106,6 +106,10 @@ else real-all: config endif +defaultbuild: + $(MAKE) olddefconfig + $(MAKE) all + ifneq ($(strip $(HAVE_LIBPAYLOAD)),) libpayload: printf "Found Libpayload $(LIBPAYLOAD_DIR).\n"

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Patch set updated for coreboot: soc/apollolake: Add UART and debug console support
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13308 -gerrit commit ed5a73c3665e7c2c9e50119de0b8d2cfbc24ce8a Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Oct 7 12:59:31 2015 -0700 soc/apollolake: Add UART and debug console support The UART uses a standard 8250 32-bit register map, and some config registers in the same memory window. Set it up for console. Change-Id: I866ff67d121826594b634cd00b6ef693b1d64512 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 7 ++ src/soc/intel/apollolake/Makefile.inc | 3 + src/soc/intel/apollolake/bootblock/bootblock_car.c | 8 +++ src/soc/intel/apollolake/include/soc/uart.h | 28 ++++++++ src/soc/intel/apollolake/uart.c | 28 ++++++++ src/soc/intel/apollolake/uart_early.c | 78 ++++++++++++++++++++++ 6 files changed, 152 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 825a40f..e5b0649 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -20,6 +20,8 @@ config CPU_SPECIFIC_OPTIONS # Misc options select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO # 8250 IO conflicts with 8250 MEM_32 select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT @@ -42,6 +44,11 @@ config IOSF_BASE_ADDRESS hex "MMIO Base Address of sideband bus" default 0xd0000000 +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL + hex "MMIO base address for UART" + default 0xde000000 + config DCACHE_RAM_BASE hex "Base address of cache-as-RAM" default 0xfef00000 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 9d33fe5..9d3897f 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -12,12 +12,15 @@ bootblock-y += cpu.c bootblock-y += gpio.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/early_chipset_config.S +bootblock-y += uart_early.c romstage-y += cpu.c romstage-y += gpio.c +romstage-y += uart_early.c ramstage-y += cpu.c ramstage-y += gpio.c +ramstage-y += uart.c romstage-y += placeholders.c smm-y += placeholders.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock_car.c b/src/soc/intel/apollolake/bootblock/bootblock_car.c index 4be0815..3a0110e 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock_car.c +++ b/src/soc/intel/apollolake/bootblock/bootblock_car.c @@ -11,12 +11,20 @@ */ #include <arch/io.h> +#include <console/console.h> #include <soc/bootblock.h> +#include <soc/uart.h> void bootblock_car_main(void) { /* Quick post code to show we made it to C code */ outb(0x30, 0x80); + + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + lpss_console_uart_init(); + console_init(); + } + /* Don't return, so we see the above post code */ while (1) ; diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h new file mode 100644 index 0000000..fd535fb --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/uart.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_UART_H_ +#define _SOC_APOLLOLAKE_UART_H_ + +/* Clock is 100MHz * (M / N).*/ +#define UART_CLK 0x200 +# define UART_CLK_UPDATE (1 << 31) +# define UART_CLK_DIV_N(n) (((n) & 0x7fff) << 16) +# define UART_CLK_DIV_M(m) (((m) & 0x7fff) << 1) +# define UART_CLK_EN (1 << 0) +#define UART_RESET 0x204 +# define UART_RESET_DMA_EN (1 << 2) +# define UART_RESET_UART_EN (3 << 0) + +void lpss_console_uart_init(void); + +#endif /* _SOC_APOLLOLAKE_UART_H_ */ diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c new file mode 100644 index 0000000..00bc45f --- /dev/null +++ b/src/soc/intel/apollolake/uart.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/uart.h> + +/* + * TODO: We need a mechanism to return the new BAR once the resource allocator + * gives us a new location. + */ +uintptr_t uart_platform_base(int idx) +{ + return (CONFIG_CONSOLE_UART_BASE_ADDRESS); +} + +unsigned int uart_platform_refclk(void) +{ + /* That's within 0.5% of the actual value we've set earlier */ + return 115200 * 16; +} diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c new file mode 100644 index 0000000..bc02776 --- /dev/null +++ b/src/soc/intel/apollolake/uart_early.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/uart.h> +#include <device/pci.h> +#include <soc/gpio.h> +#include <soc/uart.h> + +static const struct pad_config uart_tx_pad_configs[] = { + { + .community = GPIO_NORTH, + .pad = 39, + .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE}, + }, { + .community = GPIO_NORTH, + .pad = 42, + .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE}, + }, { + .community = GPIO_NORTH, + .pad = 47, + .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE}, + }, +}; + +static void lpss_uart_write(uint16_t reg, uint32_t val) +{ + uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS | reg; + write32((void *)base, val); +} + +void lpss_console_uart_init(void) +{ + uint32_t clk_sel; + device_t uart = PCI_DEV(0, 0x18, CONFIG_UART_FOR_CONSOLE & 3); + + if(CONFIG_UART_FOR_CONSOLE > 2) + return; + + gpio_configure_pad(&uart_tx_pad_configs[CONFIG_UART_FOR_CONSOLE]); + + /* Enable BAR0 for the UART -- this is where the 8250 registers hide */ + pci_write_config32(uart, PCI_BASE_ADDRESS_0, + CONFIG_CONSOLE_UART_BASE_ADDRESS); + + /* Enable memory access and bus master */ + pci_write_config32(uart, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Take UART out of reset */ + lpss_uart_write(UART_RESET, UART_RESET_DMA_EN | UART_RESET_UART_EN); + + /* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */ + clk_sel = UART_CLK_DIV_N(0x7fff) | UART_CLK_DIV_M(0x025a); + /* Set M and N divisor inputs and enable clock */ + lpss_uart_write(UART_CLK, clk_sel | UART_CLK_UPDATE); + lpss_uart_write(UART_CLK, clk_sel | UART_CLK_EN); + +} + +uintptr_t uart_platform_base(int idx) +{ + return (CONFIG_CONSOLE_UART_BASE_ADDRESS); +} + +unsigned int uart_platform_refclk(void) +{ + /* That's within 0.5% of the actual value we've set earlier */ + return 115200 * 16; +}

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Patch set updated for coreboot: soc/apollolake: Add UART and debug console support
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13308 -gerrit commit 7c7f66072299718c7335bbc8e9f000eacc1e8bbe Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Oct 7 12:59:31 2015 -0700 soc/apollolake: Add UART and debug console support The UART uses a standard 8250 32-bit register map, and some config registers in the same memory window. Set it up for console. Change-Id: I866ff67d121826594b634cd00b6ef693b1d64512 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 7 ++ src/soc/intel/apollolake/Makefile.inc | 3 + src/soc/intel/apollolake/bootblock/bootblock_car.c | 8 +++ src/soc/intel/apollolake/include/soc/uart.h | 28 ++++++++ src/soc/intel/apollolake/uart.c | 22 ++++++ src/soc/intel/apollolake/uart_early.c | 78 ++++++++++++++++++++++ 6 files changed, 146 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 825a40f..e5b0649 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -20,6 +20,8 @@ config CPU_SPECIFIC_OPTIONS # Misc options select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO # 8250 IO conflicts with 8250 MEM_32 select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT @@ -42,6 +44,11 @@ config IOSF_BASE_ADDRESS hex "MMIO Base Address of sideband bus" default 0xd0000000 +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL + hex "MMIO base address for UART" + default 0xde000000 + config DCACHE_RAM_BASE hex "Base address of cache-as-RAM" default 0xfef00000 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 9d33fe5..9d3897f 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -12,12 +12,15 @@ bootblock-y += cpu.c bootblock-y += gpio.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/early_chipset_config.S +bootblock-y += uart_early.c romstage-y += cpu.c romstage-y += gpio.c +romstage-y += uart_early.c ramstage-y += cpu.c ramstage-y += gpio.c +ramstage-y += uart.c romstage-y += placeholders.c smm-y += placeholders.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock_car.c b/src/soc/intel/apollolake/bootblock/bootblock_car.c index 4be0815..3a0110e 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock_car.c +++ b/src/soc/intel/apollolake/bootblock/bootblock_car.c @@ -11,12 +11,20 @@ */ #include <arch/io.h> +#include <console/console.h> #include <soc/bootblock.h> +#include <soc/uart.h> void bootblock_car_main(void) { /* Quick post code to show we made it to C code */ outb(0x30, 0x80); + + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + lpss_console_uart_init(); + console_init(); + } + /* Don't return, so we see the above post code */ while (1) ; diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h new file mode 100644 index 0000000..fd535fb --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/uart.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_UART_H_ +#define _SOC_APOLLOLAKE_UART_H_ + +/* Clock is 100MHz * (M / N).*/ +#define UART_CLK 0x200 +# define UART_CLK_UPDATE (1 << 31) +# define UART_CLK_DIV_N(n) (((n) & 0x7fff) << 16) +# define UART_CLK_DIV_M(m) (((m) & 0x7fff) << 1) +# define UART_CLK_EN (1 << 0) +#define UART_RESET 0x204 +# define UART_RESET_DMA_EN (1 << 2) +# define UART_RESET_UART_EN (3 << 0) + +void lpss_console_uart_init(void); + +#endif /* _SOC_APOLLOLAKE_UART_H_ */ diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c new file mode 100644 index 0000000..9663130 --- /dev/null +++ b/src/soc/intel/apollolake/uart.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/uart.h> + +/* + * TODO: We need a mechanism to return the new BAR once the resource allocator + * gives us a new location. + */ +uintptr_t uart_platform_base(int idx) +{ + return (CONFIG_CONSOLE_UART_BASE_ADDRESS); +} diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c new file mode 100644 index 0000000..bc02776 --- /dev/null +++ b/src/soc/intel/apollolake/uart_early.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/uart.h> +#include <device/pci.h> +#include <soc/gpio.h> +#include <soc/uart.h> + +static const struct pad_config uart_tx_pad_configs[] = { + { + .community = GPIO_NORTH, + .pad = 39, + .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE}, + }, { + .community = GPIO_NORTH, + .pad = 42, + .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE}, + }, { + .community = GPIO_NORTH, + .pad = 47, + .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE}, + }, +}; + +static void lpss_uart_write(uint16_t reg, uint32_t val) +{ + uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS | reg; + write32((void *)base, val); +} + +void lpss_console_uart_init(void) +{ + uint32_t clk_sel; + device_t uart = PCI_DEV(0, 0x18, CONFIG_UART_FOR_CONSOLE & 3); + + if(CONFIG_UART_FOR_CONSOLE > 2) + return; + + gpio_configure_pad(&uart_tx_pad_configs[CONFIG_UART_FOR_CONSOLE]); + + /* Enable BAR0 for the UART -- this is where the 8250 registers hide */ + pci_write_config32(uart, PCI_BASE_ADDRESS_0, + CONFIG_CONSOLE_UART_BASE_ADDRESS); + + /* Enable memory access and bus master */ + pci_write_config32(uart, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Take UART out of reset */ + lpss_uart_write(UART_RESET, UART_RESET_DMA_EN | UART_RESET_UART_EN); + + /* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */ + clk_sel = UART_CLK_DIV_N(0x7fff) | UART_CLK_DIV_M(0x025a); + /* Set M and N divisor inputs and enable clock */ + lpss_uart_write(UART_CLK, clk_sel | UART_CLK_UPDATE); + lpss_uart_write(UART_CLK, clk_sel | UART_CLK_EN); + +} + +uintptr_t uart_platform_base(int idx) +{ + return (CONFIG_CONSOLE_UART_BASE_ADDRESS); +} + +unsigned int uart_platform_refclk(void) +{ + /* That's within 0.5% of the actual value we've set earlier */ + return 115200 * 16; +}

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Patch set updated for coreboot: OBSOLETED BY https://review.coreboot.org/13069
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12870 -gerrit commit c4173406518eaf68bf8544d7863672b795fad754 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 16:35:39 2015 -0700 OBSOLETED BY https://review.coreboot.org/13069 src/arch/x86: Link the compiler runtime library in the bootblock At least on GCC __udivdi3 and __umoddi3 are needed by the console code. They are provided by the compiler runtime library. Change-Id: I78bbea425c33d7eebaf829d58d763b7a1c6e997c Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/arch/x86/Makefile.inc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 86290ab..75767cb 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -163,8 +163,12 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOU # $(obj)/arch/x86/bootblock.bootblock.ld is part of $(bootblock-objs) $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ - $(filter-out %.ld,$(bootblock-objs)) \ + $(LD_bootblock) $(LDFLAGS_bootblock) -static \ + -o $@ $(COMPILER_RT_FLAGS_bootblock) -L$(obj) \ + -whole-archive --start-group \ + $(filter %.o,$(bootblock-objs)) \ + --no-whole-archive $(COMPILER_RT_bootblock) \ + --end-group \ -T $(obj)/arch/x86/bootblock.bootblock.ld endif # C_ENVIRONMENT_BOOTBLOCK

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