coreboot-gerrit January 2016

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Patch set updated for coreboot: soc/apollolake: Add minimal GPIO configuration infrastruucture
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13306 -gerrit commit 517d302e5556ddda74f4d94e3a838610a0931932 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Oct 8 17:31:25 2015 -0700 soc/apollolake: Add minimal GPIO configuration infrastruucture This adds the minimal functionality needed to configure SOC pads. The only purpose right now is to allow configuration of UART pads, but will be expanded later into a proper GPIO driver. Change-Id: If01f41f94f8c506a865908d18f8b3d343c542b1b Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 3 + src/soc/intel/apollolake/gpio.c | 21 ++++++ src/soc/intel/apollolake/include/soc/gpio.h | 32 +++++++++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 85 ++++++++++++++++++++++++ 4 files changed, 141 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index d2d117a..9d33fe5 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -9,12 +9,15 @@ subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock_car.c bootblock-y += cpu.c +bootblock-y += gpio.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/early_chipset_config.S romstage-y += cpu.c +romstage-y += gpio.c ramstage-y += cpu.c +ramstage-y += gpio.c romstage-y += placeholders.c smm-y += placeholders.c diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c new file mode 100644 index 0000000..2796e42 --- /dev/null +++ b/src/soc/intel/apollolake/gpio.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <soc/gpio.h> +#include <soc/iosf.h> + +void gpio_configure_pad(const struct pad_config *cfg) +{ + uint16_t config_offset = PAD_CFG_OFFSET(cfg->pad); + iosf_write(cfg->community, config_offset, cfg->config[0]); + iosf_write(cfg->community, config_offset + 4, cfg->config[1]); +} diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h new file mode 100644 index 0000000..5744f72 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_GPIO_H_ +#define _SOC_APOLLOLAKE_GPIO_H_ + +#include <types.h> +#include <soc/gpio_defs.h> + +struct pad_config { + uint8_t community; + uint8_t pad; + uint32_t config[2]; +}; + +/* + * Configuration for raw pads. Some pads are designated as only special function + * pins, and don't have an associated GPIO number, so we need to expose the raw + * pad configuration functionality. + */ +void gpio_configure_pad(const struct pad_config *cfg); + +#endif /* _SOC_APOLLOLAKE_GPIO_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h new file mode 100644 index 0000000..c581662 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -0,0 +1,85 @@ +/* + * Definitions for the GPIO subsystem on Apollolake + * + * Placed in a separate file since some of these definitions can be used from + * assembly code + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_GPIO_DEFS_H_ +#define _SOC_APOLLOLAKE_GPIO_DEFS_H_ + +#define PAD_CFG0_TX_DISABLE (1 << 8) +#define PAD_CFG0_RX_DISABLE (1 << 9) +#define PAD_CFG0_MODE_MASK (7 << 10) +#define PAD_CFG0_MODE_GPIO (0 << 10) +#define PAD_CFG0_MODE_FUNC(x) ((x) << 10) +#define PAD_CFG0_ROUTE_NMI (1 << 17) +#define PAD_CFG0_ROUTE_SMI (1 << 18) +#define PAD_CFG0_ROUTE_SCI (1 << 19) +#define PAD_CFG0_ROUTE_IOAPIC (1 << 20) +#define PAD_CFG0_RX_INVERT (1 << 23) +#define PAD_CFG0_TRIG_MASK (3 << 25) +#define PAD_CFG0_TRIG_LEVEL (0 << 25) +#define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/ +#define PAD_CFG0_TRIG_OFF (2 << 25) +#define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25) +#define PAD_CFG0_RESET_MASK (3 << 30) +#define PAD_CFG0_RESET_STICKY (0 << 30) +#define PAD_CFG0_RESET_DEEP (1 << 30) +#define PAD_CFG0_RESET_GPIOR (2 << 30) +#define PAD_CFG0_RESET_INACTIVE (3 << 30) + +#define PAD_CFG1_PULL_MASK (0xf << 12) +#define PAD_CFG1_PULL_NONE (0x0 << 12) +#define PAD_CFG1_PULL_DN_5K (0x2 << 12) +#define PAD_CFG1_PULL_DN_20K (0x4 << 12) +#define PAD_CFG1_PULL_UP_1K (0x9 << 12) +#define PAD_CFG1_PULL_UP_5K (0xa << 12) +#define PAD_CFG1_PULL_UP_2K (0xb << 12) +#define PAD_CFG1_PULL_UP_20K (0xc << 12) +#define PAD_CFG1_PULL_UP_667 (0xd << 12) +#define PAD_CFG1_PULL_NATIVE (0xf << 12) + +#define PAD_CFG_BASE 0x500 +#define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8)) + +/* IOSF port numbers for GPIO comminuties*/ +#define GPIO_SOUTHWEST 0xc0 +#define GPIO_SOUTH 0xc2 +#define GPIO_NORTHWEST 0xc4 +#define GPIO_NORTH 0xc5 +#define GPIO_WEST 0xc7 + +/* Special function pads in southwest community */ +#define SMB_ALERTB 31 +#define SMB_CLK 32 +#define SMB_DATA 33 +#define LPC_ILB_SERIRQ 34 +#define LPC_CLKOUT0 35 +#define LPC_CLKOUT1 36 +#define LPC_AD0 37 +#define LPC_AD1 38 +#define LPC_AD2 39 +#define LPC_AD3 40 +#define LPC_CLKRUNB 41 +#define LPC_FRAMEB 42 + +/* Default configurations */ +#define PAD_CFG0_DEFAULT_FUNC(x) (0x44000000 | PAD_CFG0_MODE_FUNC(x)) +#define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1) + +#define PAD_CFG1_DEFAULT_NOPULL PAD_CFG1_PULL_NONE +#define PAD_CFG1_DEFAULT_PULLUP PAD_CFG1_PULL_UP_20K +#define PAD_CFG1_DEFAULT_NATIVE PAD_CFG1_PULL_NATIVE + +#endif /* _SOC_APOLLOLAKE_GPIO_DEFS_H_ */

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Patch set updated for coreboot: soc/apollolake: Rewrite early LPC config using gpio_defs.h macros
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13307 -gerrit commit e68698b3a56d6dba4d13a4c59ac36799e8acfaf0 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Oct 9 15:28:28 2015 -0700 soc/apollolake: Rewrite early LPC config using gpio_defs.h macros Change-Id: I6bde81d4328be0cee60d0db60d747abf8c90c664 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- .../apollolake/bootblock/early_chipset_config.S | 53 ++++++++++------------ 1 file changed, 23 insertions(+), 30 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/early_chipset_config.S b/src/soc/intel/apollolake/bootblock/early_chipset_config.S index 113188c..4d67359 100644 --- a/src/soc/intel/apollolake/bootblock/early_chipset_config.S +++ b/src/soc/intel/apollolake/bootblock/early_chipset_config.S @@ -10,6 +10,13 @@ * (at your option) any later version. */ +#include <soc/gpio_defs.h> + +/* Definitions used only here, for getting the MMIO base of LPC pad registers */ +#define XLATE_LPC(pad) ((GPIO_SOUTHWEST << 16 ) | PAD_CFG_OFFSET(pad)) +#define PAD_MMIO_ADDR(pad) (CONFIG_IOSF_BASE_ADDRESS + XLATE_LPC(pad)) + + .intel_syntax noprefix .extern cache_as_ram @@ -55,40 +62,26 @@ init_lpc_pad: jmp cache_as_ram -/* FIXME: Find a better way to define these */ - -#define LPC_CLKOUT0 0x118 -#define LPC_CLKOUT1 0x120 -#define LPC_AD0 0x128 -#define LPC_AD1 0x130 -#define LPC_AD2 0x138 -#define LPC_AD3 0x140 -#define LPC_CLKRUN 0x148 -#define LPC_FRAME 0x150 - -#define XLATE_LPC(off) ((0xc0 << 16 ) | (0x500 + (off))) -#define PAD_MMIO_ADDR(poff) CONFIG_IOSF_BASE_ADDRESS + XLATE_LPC(poff) - lpc_pad_params: - .long PAD_MMIO_ADDR(LPC_CLKOUT0) - .long 0x44000400 - .long 0x0003C000 .long PAD_MMIO_ADDR(LPC_AD0) - .long 0x44000402 - .long 0x0003F000 + .long PAD_CFG0_DEFAULT_NATIVE + .long PAD_CFG1_DEFAULT_NATIVE .long PAD_MMIO_ADDR(LPC_AD1) - .long 0x44000402 - .long 0x0003F000 + .long PAD_CFG0_DEFAULT_NATIVE + .long PAD_CFG1_DEFAULT_NATIVE .long PAD_MMIO_ADDR(LPC_AD2) - .long 0x44000402 - .long 0x0003F000 + .long PAD_CFG0_DEFAULT_NATIVE + .long PAD_CFG1_DEFAULT_NATIVE .long PAD_MMIO_ADDR(LPC_AD3) - .long 0x44000402 - .long 0x0003F000 - .long PAD_MMIO_ADDR(LPC_FRAME) - .long 0x44000400 - .long 0x0003F000 + .long PAD_CFG0_DEFAULT_NATIVE + .long PAD_CFG1_DEFAULT_NATIVE + .long PAD_MMIO_ADDR(LPC_FRAMEB) + .long PAD_CFG0_DEFAULT_NATIVE + .long PAD_CFG1_DEFAULT_NATIVE + .long PAD_MMIO_ADDR(LPC_CLKOUT0) + .long PAD_CFG0_DEFAULT_NATIVE + .long PAD_CFG1_DEFAULT_PULLUP .long PAD_MMIO_ADDR(LPC_CLKOUT1) - .long 0x44000400 - .long 0x0003C000 + .long PAD_CFG0_DEFAULT_NATIVE + .long PAD_CFG1_DEFAULT_PULLUP num_lpc_pads = ( . - lpc_pad_params) / 0xc

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Patch set updated for coreboot: intel/strago: EC_IN_RW gpio input configuration.
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13124 -gerrit commit 0996dcb71b28809d971b9351e3954c3b74ac67f3 Author: Divagar Mohandass <divagar.mohandass(a)intel.com> Date: Mon Oct 5 16:21:14 2015 +0530 intel/strago: EC_IN_RW gpio input configuration. Configure EC_IN_RW signal as gpio input. TEST=Boot to Chrome OS in normal mode and enter recovery mode use ctrl-d to switch to Dev mode. Change-Id: I835a1c70d89ef2ab75c35233f889124b60bb64a3 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/304040 Original-Tested-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Reviewed-by: Gomathi Kumar <gomathi.kumar(a)intel.com> Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Shobhit Srivastava <shobhit.srivastava(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 8b6a0e7..95dea4f 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -130,7 +130,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_OUT_HIGH, /* 75 SATA_GP0 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 76 GPI SATA_GP1 */ - Native_M1, /* 77 SATA_LEDN */ + GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */ GPIO_NC, /* 80 SATA_GP3 */ Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */

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Patch set updated for coreboot: soc/intel: Add skeleton infrastructure for Apollolake SOC
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13297 -gerrit commit d07a455216fac5206f94dd5d75ed4f4731547027 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 10:33:49 2015 -0700 soc/intel: Add skeleton infrastructure for Apollolake SOC This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 39 +++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 18 +++++++++++++++ src/soc/intel/apollolake/placeholders.c | 11 ++++++++++ 3 files changed, 68 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig new file mode 100644 index 0000000..ca38494 --- /dev/null +++ b/src/soc/intel/apollolake/Kconfig @@ -0,0 +1,39 @@ +config SOC_INTEL_APOLLOLAKE + bool + help + Intel Apollolake support + +if SOC_INTEL_APOLLOLAKE + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + # CPU specific options + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select IOAPIC + select SMP + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + # Misc options + select COLLECT_TIMESTAMPS + select HAVE_INTEL_FIRMWARE + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + select PARALLEL_MP + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK + select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE + select REG_SCRIPT + select RELOCATABLE_RAMSTAGE # Build fails if this is not selected + select SOC_INTEL_COMMON + select UDELAY_TSC + +config CPU_ADDR_BITS + int + default 36 + +endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc new file mode 100644 index 0000000..b0aeb31 --- /dev/null +++ b/src/soc/intel/apollolake/Makefile.inc @@ -0,0 +1,18 @@ +ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) + +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc + +romstage-y += placeholders.c +smm-y += placeholders.c +ramstage-y += placeholders.c + +# cpu_microcode_bins += ??? + +# CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include + +endif diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c new file mode 100644 index 0000000..cf0fe36 --- /dev/null +++ b/src/soc/intel/apollolake/placeholders.c @@ -0,0 +1,11 @@ +#include <cbmem.h> +#include <cpu/x86/smm.h> + +void *cbmem_top(void) +{ + return NULL; +} + +void southbridge_smi_set_eos(void) +{ +}

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Patch set updated for coreboot: mainboard/intel: Add skeleton for Apollolake RVP board
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13298 -gerrit commit e49f36dcfc9cd821dcc1bb0faeafdb3c26547a9a Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 10:36:20 2015 -0700 mainboard/intel: Add skeleton for Apollolake RVP board Change-Id: I3e47c157c49ad55ff1ba824672ac2630a64a6037 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 20 ++++++++++++++++++++ src/mainboard/intel/apollolake_rvp/Kconfig.name | 2 ++ src/mainboard/intel/apollolake_rvp/Makefile.inc | 1 + src/mainboard/intel/apollolake_rvp/devicetree.cb | 8 ++++++++ src/mainboard/intel/apollolake_rvp/romstage.c | 1 + 5 files changed, 32 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig new file mode 100755 index 0000000..2c3e898 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -0,0 +1,20 @@ +if BOARD_INTEL_APOLLOLAKE_RVP2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_8192 + +config MAINBOARD_DIR + string + default intel/apollolake_rvp + +config MAINBOARD_PART_NUMBER + string + default "Apollolake RVP2" + +config MAINBOARD_VENDOR + string + default "Intel" + +endif # BOARD_INTEL_APOLLOLAKE_RVP2 diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig.name b/src/mainboard/intel/apollolake_rvp/Kconfig.name new file mode 100644 index 0000000..56d5b4b --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_APOLLOLAKE_RVP2 + bool "Apollolake LPDDR3 RVP2" diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc new file mode 100755 index 0000000..a48936e --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc @@ -0,0 +1 @@ +# Nothing yet here diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb new file mode 100755 index 0000000..741d88e --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -0,0 +1,8 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + end +end diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c new file mode 100644 index 0000000..c5d3ce1 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -0,0 +1 @@ +/* Nothing here yet, but this file is needed by the buildsystem */

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Patch set updated for coreboot: soc/braswell: Add interface to program USB2_COMPBG register
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12739 -gerrit commit 69375478e7806e2f7218399c8e917649fd6d6a3e Author: shkim <sh_.kim(a)samsung.com> Date: Tue Sep 22 17:53:58 2015 +0900 soc/braswell: Add interface to program USB2_COMPBG register Add interface to program USB2_COMPBG register to set HS_DISC_BG and HS_SQ reference voltage for each project. TEST=Get build success and do EFT test Original-Reviewed-on: https://chromium-review.googlesource.com/300846 Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> Original-Tested-by: shkim <sh_.kim(a)samsung.com> Change-Id: If2201829e1a16b4f9916547f08c24e9291358325 Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Signed-off-by: shkim <sh_.kim(a)samsung.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/braswell/chip.h | 20 ++++++++++ src/soc/intel/braswell/include/soc/iosf.h | 5 +++ src/soc/intel/braswell/iosf.c | 15 +++++++- src/soc/intel/braswell/xhci.c | 62 +++++++++++++++++++++++++++++++ 4 files changed, 101 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 6eb1451..fbac84d 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -38,6 +38,18 @@ enum lpe_clk_src { LPE_CLK_SRC_PLL, }; +enum usb_comp_bg_value { + USB_COMP_BG_575_MV = 7, + USB_COMP_BG_650_MV = 6, + USB_COMP_BG_550_MV = 5, + USB_COMP_BG_537_MV = 4, + USB_COMP_BG_625_MV = 3, + USB_COMP_BG_700_MV = 2, + USB_COMP_BG_600_MV = 1, + USB_COMP_BG_675_MV = 0, +}; + + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; @@ -61,6 +73,14 @@ struct soc_intel_braswell_config { /* Allow PCIe devices to wake system from suspend. */ int pcie_wake_enable; + /* Program USB2_COMPBG register. + * [10:7] - select vref to AFE port + * x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV, + * x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV + */ + enum usb_comp_bg_value usb_comp_bg; + + /* * The following fields come from fsp_vpd.h .aka. VpdHeader.h. * These are configuration values that are passed to FSP during diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index add602f..e6758a6 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -69,6 +69,8 @@ uint32_t iosf_port58_read(int reg); void iosf_port58_write(int reg, uint32_t val); uint32_t iosf_scc_read(int reg); void iosf_scc_write(int reg, uint32_t val); +uint32_t iosf_usbphy_read(int reg); +void iosf_usbphy_write(int reg, uint32_t val); #if ENV_RAMSTAGE uint64_t reg_script_read_iosf(struct reg_script_context *ctx); @@ -91,6 +93,7 @@ void reg_script_write_iosf(struct reg_script_context *ctx); #define IOSF_PORT_0x5a 0x5a #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ #define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ +#define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_0xa2 0xa2 #define IOSF_PORT_SSUS 0xa8 /* SUS */ @@ -109,6 +112,8 @@ void reg_script_write_iosf(struct reg_script_context *ctx); #define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) #define IOSF_OP_READ_SCC 0x06 #define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) +#define IOSF_OP_READ_USBPHY 0x06 +#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) /* * BUNIT Registers. diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 1e7b924..98d1610 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -122,6 +122,15 @@ void iosf_scc_write(int reg, uint32_t val) return iosf_write_port(IOSF_WRITE(SCC), reg, val); } +uint32_t iosf_usbphy_read(int reg) +{ + return iosf_read_port(IOSF_READ(USBPHY), reg); +} + +void iosf_usbphy_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); +} #if ENV_RAMSTAGE uint64_t reg_script_read_iosf(struct reg_script_context *ctx) @@ -140,6 +149,8 @@ uint64_t reg_script_read_iosf(struct reg_script_context *ctx) return iosf_port58_read(step->reg); case IOSF_PORT_SCC: return iosf_scc_read(step->reg); + case IOSF_PORT_USBPHY: + return iosf_usbphy_read(step->reg); default: printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n", step->id); @@ -169,7 +180,9 @@ void reg_script_write_iosf(struct reg_script_context *ctx) case IOSF_PORT_SCC: iosf_scc_write(step->reg, step->value); break; - + case IOSF_PORT_USBPHY: + iosf_usbphy_write(step->reg, step->value); + break; default: printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n", step->id); diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c new file mode 100644 index 0000000..e3e3462 --- /dev/null +++ b/src/soc/intel/braswell/xhci.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <reg_script.h> + +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/ramstage.h> +#include <soc/xhci.h> + +#include "chip.h" + +static void xhci_init(device_t dev) +{ + struct soc_intel_braswell_config *config = dev->chip_info; + + if (config && config->usb_comp_bg) { + struct reg_script ops[] = { + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, + config->usb_comp_bg), + REG_SCRIPT_END + }; + printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n", config->usb_comp_bg); + reg_script_run(ops); + } +} + +static struct device_operations xhci_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = xhci_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver soc_xhci __pci_driver = { + .ops = &xhci_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = XHCI_DEVID +};

1 0

Patch set updated for coreboot: soc/braswell: Fix DSP clock
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12732 -gerrit commit d896470f50b6f7dc50a0772d59e02585c8aa8eab Author: fdurairx <felixx.durairaj(a)intel.com> Date: Fri Aug 21 15:36:53 2015 -0700 soc/braswell: Fix DSP clock The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj(a)intel.com> --- src/mainboard/google/cyan/devicetree.cb | 3 +-- src/mainboard/intel/strago/devicetree.cb | 3 +-- src/soc/intel/braswell/chip.h | 8 ++++++-- src/soc/intel/braswell/include/soc/pm.h | 4 ++-- src/soc/intel/braswell/lpe.c | 24 +++++++++++------------- 5 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index c36ae3d..8932cf4 100755 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -72,8 +72,7 @@ chip soc/intel/braswell register "ISPPciDevConfig" = "3" # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock # Enable devices in ACPI mode register "lpss_acpi_mode" = "1" diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 788153a..3b93f44 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -72,8 +72,7 @@ chip soc/intel/braswell register "ISPPciDevConfig" = "3" # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock # Enable devices in ACPI mode register "lpss_acpi_mode" = "1" diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 0f3c1d0..6eb1451 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -33,6 +33,11 @@ #define MEM_DDR3 0 #define MEM_LPDDR3 1 +enum lpe_clk_src { + LPE_CLK_SRC_XTAL, + LPE_CLK_SRC_PLL, +}; + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; @@ -41,8 +46,7 @@ struct soc_intel_braswell_config { int disable_slp_x_stretch_sus_fail; /* LPE Audio Clock configuration. */ - int lpe_codec_clk_freq; /* 19 or 25 are valid. */ - int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ + enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */ /* Native SD Card controller - override controller capabilities. */ uint32_t sdcard_cap_low; diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 9708b39..a4b2e2d 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -116,8 +116,8 @@ #define PLT_CLK_CTL_3 0x6c #define PLT_CLK_CTL_4 0x70 #define PLT_CLK_CTL_5 0x74 -# define CLK_FREQ_25MHZ (0x0 << 2) -# define CLK_FREQ_19P2MHZ (0x1 << 2) +# define CLK_SRC_XTAL (0x0 << 2) +# define CLK_SRC_PLL (0x1 << 2) # define CLK_CTL_D3_LPE (0x0 << 0) # define CLK_CTL_ON (0x1 << 0) # define CLK_CTL_OFF (0x2 << 0) diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index a1a7c64..4662b43 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -96,32 +96,30 @@ static void setup_codec_clock(device_t dev) const char *freq_str; config = dev->chip_info; - switch (config->lpe_codec_clk_freq) { - case 19: - freq_str = "19.2"; - reg = CLK_FREQ_19P2MHZ; + switch (config->lpe_codec_clk_src) { + case LPE_CLK_SRC_XTAL: + /* XTAL driven bit2=0 */ + freq_str = "19.2MHz External Crystal"; + reg = CLK_SRC_XTAL; break; - case 25: - freq_str = "25"; - reg = CLK_FREQ_25MHZ; + case LPE_CLK_SRC_PLL: + /* PLL driven bit2=1 */ + freq_str = "19.2MHz PLL"; + reg = CLK_SRC_PLL; break; default: - printk(BIOS_DEBUG, "LPE codec clock not required.\n"); + reg = CLK_SRC_XTAL; + printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n"); return; } /* Default to always running. */ reg |= CLK_CTL_ON; - if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) { - printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n"); - return; - } printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0); - clk_reg += config->lpe_codec_clk_num; write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); }

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New patch to review for coreboot: soc/braswell: Fix for auto wake from S5
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13425 -gerrit commit c61522fa0ad7163cb6c21c032a31720b11b441aa Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jul 27 19:46:34 2015 -0700 soc/braswell: Fix for auto wake from S5 Disabling S5 wake from touch panel and trackpad TEST=Build and boot the platform. TEST=Poweroff platform -> enter PG3 -> remove AC -> close Lid Plug AC in -> EC boots up and AP will shutdown the platform and open Lid -> platform boots to OS. Change-Id: I7b661a9f1327b97d904bac40e78612648f353e39 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/288970 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Tested-by: Divagar Mohandass <divagar.mohandass(a)intel.com> --- src/mainboard/google/cyan/smihandler.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 04cc899..9b363ca 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -28,6 +28,8 @@ /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0 +#define GPIO_SUS7_WAKE_MASK (1 << 12) +#define GPIO_SUS1_WAKE_MASK (1 << 13) int mainboard_io_trap_handler(int smif) { @@ -96,6 +98,9 @@ void mainboard_smi_gpi(uint32_t alt_gpio_smi) void mainboard_smi_sleep(uint8_t slp_typ) { + void *addr; + uint32_t mask; + /* Disable USB charging if required */ switch (slp_typ) { case 3: @@ -125,6 +130,16 @@ void mainboard_smi_sleep(uint8_t slp_typ) /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); #endif + + /* Disabling wake from SUS_GPIO1 (TOUCH INT) and + * SUS_GPIO7 (TRACKPAD INT) in North bank as they are not + * valid S5 wake sources + */ + addr = (void *)(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPNORTH + + GPIO_WAKE_MASK_REG0); + mask = ~(GPIO_SUS1_WAKE_MASK | GPIO_SUS7_WAKE_MASK); + write32(addr, read32(addr) & mask); + break; }

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New patch to review for coreboot: intel/strago: Fix for Crossystem "wpsw_cur" status
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13424 -gerrit commit 93005dd647e8f014f13f2e3ec71c26a0b88fc0a4 Author: Kumar, Gomathi <gomathi.kumar(a)intel.com> Date: Fri Aug 7 16:39:48 2015 +0530 intel/strago: Fix for Crossystem "wpsw_cur" status The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East community are in two ranges - 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26] The discontinuity was not accounted for, hence the error.Original offset was 0x16 whereas it should be 0x13 TEST=Run crossystem and test wpsw_cur entry. If screw is present, it should be 1 and if not present, it should be 0 Change-Id: I29e19589b3a358a42818afbc6d017d6cbc6a9c4c Original-Signed-off-by: Kumar, Gomathi <gomathi.kumar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291572 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Icarus W Sparry <icarus.w.sparry(a)intel.com> --- src/mainboard/intel/strago/acpi/chromeos.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/strago/acpi/chromeos.asl b/src/mainboard/intel/strago/acpi/chromeos.asl index 84c1313..c470ca3 100644 --- a/src/mainboard/intel/strago/acpi/chromeos.asl +++ b/src/mainboard/intel/strago/acpi/chromeos.asl @@ -23,11 +23,11 @@ * * Note: We need to encode gpios within the 4 separate banks * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded - * as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. + * as 0x10013 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. */ Name(OIPG, Package() { /* No physical recovery button */ Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, - Package () { 0x0003, 1, 0x10016, "Braswell" }, + Package () { 0x0003, 1, 0x10013, "Braswell" }, })

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New patch to review for coreboot: intel/strago: Disable unused devices.
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13423 -gerrit commit b4f9ef8dde54ecefc0ee169b82bd257d0c75c095 Author: Divagar Mohandass <divagar.mohandass(a)intel.com> Date: Mon Sep 21 11:51:07 2015 +0530 intel/strago: Disable unused devices. This change will disable unused devices in device tree to improve boot performance. TEST=Build/Flash CB and boot to OS. verify Touch screen, Audio, WIFI and Track pad functionality. Change-Id: Ib5ae31c96d75f9a5b0f8d8b72d058e18fe7d7e67 Signed-off-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/300943 Original-Reviewed-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Gomathi Kumar <gomathi.kumar(a)intel.com> --- src/mainboard/intel/strago/devicetree.cb | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index b2d5115..9133787 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -29,11 +29,11 @@ chip soc/intel/braswell register "PcdEnableDma1" = "1" register "PcdEnableI2C0" = "1" register "PcdEnableI2C1" = "1" - register "PcdEnableI2C2" = "1" - register "PcdEnableI2C3" = "1" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" register "PcdEnableI2C4" = "1" register "PcdEnableI2C5" = "1" - register "PcdEnableI2C6" = "1" + register "PcdEnableI2C6" = "0" register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" register "PcdEmmcMode" = "PCH_ACPI_MODE" @@ -95,7 +95,7 @@ chip soc/intel/braswell # EDS Table 24-4, Figure 24-5 device pci 00.0 on end # 8086 2280 - SoC transaction router device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 on end # 8086 22b8 - Camera and Image Processor + device pci 03.0 off end # 8086 22b8 - Camera and Image Processor device pci 0b.0 on end # 8086 22dc - ? device pci 10.0 on end # 8086 2294 - MMC Port device pci 11.0 off end # 8086 0F15 - SDIO Port @@ -107,25 +107,25 @@ chip soc/intel/braswell device pci 18.0 on end # 8086 22c0 - SIO - DMA device pci 18.1 on end # 8086 22c1 - I2C Port 1 device pci 18.2 on end # 8086 22c2 - I2C Port 2 - device pci 18.3 on end # 8086 22c3 - I2C Port 3 - device pci 18.4 on end # 8086 22c4 - I2C Port 4 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 device pci 18.5 on end # 8086 22c5 - I2C Port 5 device pci 18.6 on end # 8086 22c6 - I2C Port 6 - device pci 18.7 on end # 8086 22c7 - I2C Port 7 - device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine device pci 1b.0 on end # 8086 0F04 - HD Audio device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 - device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 + device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 device pci 1e.0 on end # 8086 2286 - SIO - DMA device pci 1e.1 off end # 8086 0F08 - PWM 1 device pci 1e.2 off end # 8086 0F09 - PWM 2 device pci 1e.3 on end # 8086 228a - HSUART 1 - device pci 1e.4 on end # 8086 228c - HSUART 2 + device pci 1e.4 off end # 8086 228c - HSUART 2 device pci 1e.5 on end # 8086 228e - SPI 1 - device pci 1e.6 on end # 8086 2290 - SPI 2 - device pci 1e.7 on end # 8086 22ac - SPI 3 + device pci 1e.6 off end # 8086 2290 - SPI 2 + device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm # Rising edge interrupt

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coreboot-gerrit January 2016