coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

1 participants
2471 discussions

New patch to review for coreboot: intel/strago: Cleanup GPIO config
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13431 -gerrit commit cc784d5085399cfaad9b67ef4f4a3e31c6143a8e Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jan 25 14:25:23 2016 -0800 intel/strago: Cleanup GPIO config Fix GPIO config for this board Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 8b6a0e7..ad038a3 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -17,8 +17,6 @@ #include "irqroute.h" #include <soc/gpio.h> #include <stdlib.h> -#include <boardid.h> -#include "onboard.h" #include "gpio.h" /* South East Community */ @@ -74,7 +72,9 @@ static const struct soc_gpio_map gpse_gpio_map[] = { Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPI(trig_edge_both, L1, P_20K_H, non_maskable, + en_edge_detect, NA , NA), + /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr asummed gpio number */ Native_M1, /* 83 SUSPWRDNACK */ SPARE_PIN,/* 84 spare pin */ @@ -112,11 +112,11 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ GPIO_NC, /* 49 I2C_NFC_SDA */ - GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ GPIO_NC, /* 52 I2C_NFC_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ @@ -128,7 +128,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + GPIO_NC, /* 76 GPI SATA_GP1 */ Native_M1, /* 77 SATA_LEDN */ GPIO_NC, /* 80 SATA_GP3 */ @@ -169,9 +169,11 @@ static const struct soc_gpio_map gpn_gpio_map[] = { /* 17 GPIO_SUS3 */ GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + GPI(trig_edge_high, L2, P_20K_H, non_maskable, + en_edge_rx_data, NA , NA), /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 22 GPIO_SUS4 */ GPIO_NC,

1 0

Patch set updated for coreboot: intel/strago: Clean up DDR configuration.
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13122 -gerrit commit ee1cf2752981f6578d4b2a2594cf769348519ab4 Author: Divagar Mohandass <divagar.mohandass(a)intel.com> Date: Tue Sep 8 15:03:45 2015 +0530 intel/strago: Clean up DDR configuration. This change includes following changes: - Clean up the DDR configuration and flow. - Removing support for non LPDDR3 boards. - Supporting only LPDDR3 and PMIC config. TEST=Build/flash CB and boot the platform to OS. Change-Id: I8369443da728a4c07e0c1a82040d94034c3542da Signed-off-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297941 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Jenny Tc <jenny.tc(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/Kconfig | 6 -- src/mainboard/intel/strago/Makefile.inc | 2 - src/mainboard/intel/strago/ramstage.c | 6 +- src/mainboard/intel/strago/romstage.c | 26 +---- src/mainboard/intel/strago/smihandler.c | 8 +- src/mainboard/intel/strago/spd/Makefile.inc | 38 ------- .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 ------ ...nix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 32 ------ .../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 32 ------ src/mainboard/intel/strago/spd/spd.c | 116 --------------------- 10 files changed, 6 insertions(+), 292 deletions(-) diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 204534a..f23a86c 100755 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -21,12 +21,6 @@ config CHROMEOS select VBOOT_DYNAMIC_WORK_BUFFER select VIRTUAL_DEV_SWITCH -config DISPLAY_SPD_DATA - bool "Display Memory Serial Presence Detect Data" - default n - help - When enabled displays the memory configuration data. - config DYNAMIC_VNN_SUPPORT bool "Enables support for Dynamic VNN" default n diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index d53cd84..9c21bed 100755 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -14,8 +14,6 @@ ## GNU General Public License for more details. ## -subdirs-y += spd - romstage-y += boardid.c romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c diff --git a/src/mainboard/intel/strago/ramstage.c b/src/mainboard/intel/strago/ramstage.c index c5cff68..a05cd90 100644 --- a/src/mainboard/intel/strago/ramstage.c +++ b/src/mainboard/intel/strago/ramstage.c @@ -19,8 +19,6 @@ void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { - if (board_id() == BOARD_BCRD2) { - params->ChvSvidConfig = SVID_PMIC_CONFIG; - params->PMIC_I2CBus = BCRD2_PMIC_I2C_BUS; - } + params->ChvSvidConfig = SVID_PMIC_CONFIG; + params->PMIC_I2CBus = BCRD2_PMIC_I2C_BUS; } diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index e582b56..56ab9a7 100755 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -25,32 +25,8 @@ #include "onboard.h" #include <boardid.h> -/* All FSP specific code goes in this block */ -void mainboard_romstage_entry(struct romstage_params *rp) -{ - struct pei_data *ps = rp->pei_data; - - mainboard_fill_spd_data(ps); - - /* Call back into chipset code with platform values updated. */ - romstage_common(rp); -} - void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - int id; - id = board_id(); - if (id == BOARD_BCRD2) { - memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - memory_params->PcdDvfsEnable = 0; - } else { - memory_params->PcdMemoryTypeEnable = MEM_DDR3; - memory_params->PcdMemorySpdPtr = - (u32)params->pei_data->spd_data_ch0; - memory_params->PcdMemChannel0Config = - params->pei_data->spd_ch0_config; - memory_params->PcdMemChannel1Config = - params->pei_data->spd_ch1_config; - } + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; } diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index b465e3a..0f77bf3 100755 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -139,11 +139,9 @@ void mainboard_smi_sleep(uint8_t slp_typ) while (google_chromeec_get_event() != 0) ; - if (smm_get_gnvs()->bdid == BOARD_DVT) { - /* Set LPC lines to low power in S3/S5. */ - if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5)) - lpc_set_low_power(); - } + /* Set LPC lines to low power in S3/S5. */ + if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5)) + lpc_set_low_power(); #endif } diff --git a/src/mainboard/intel/strago/spd/Makefile.inc b/src/mainboard/intel/strago/spd/Makefile.inc deleted file mode 100755 index 440735c..0000000 --- a/src/mainboard/intel/strago/spd/Makefile.inc +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += spd.c - -SPD_BIN = $(obj)/spd.bin - -SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 -SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR -SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 -SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex deleted file mode 100755 index ff4fd29..0000000 --- a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 12 0b 03 04 19 02 02 -03 52 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -20 08 3c 3c 01 40 83 01 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 11 62 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 ad 01 -00 00 00 00 00 00 ff ab -48 4d 54 34 32 35 53 36 -41 46 52 36 41 2d 50 42 -20 20 4e 30 80 ad 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex deleted file mode 100755 index fdd1a43..0000000 --- a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 13 0B 03 04 19 02 02 -03 52 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 -20 08 3C 3C 01 40 83 01 -00 00 00 00 00 00 00 00 -00 88 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0F 11 62 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 AD 01 -00 00 00 00 00 00 C9 C0 -48 4D 54 34 32 35 53 36 -43 46 52 36 41 2D 50 42 -20 20 4E 30 80 AD 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF diff --git a/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex deleted file mode 100755 index e0b0ac5..0000000 --- a/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 12 0B 03 04 19 02 02 -03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 -20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 -88 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 -00 00 00 00 00 00 6C F9 -4D 34 37 31 42 35 36 37 -34 51 48 30 2D 59 4B 30 -20 20 00 00 80 CE 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/strago/spd/spd.c b/src/mainboard/intel/strago/spd/spd.c deleted file mode 100755 index a711049..0000000 --- a/src/mainboard/intel/strago/spd/spd.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <console/console.h> -#include <lib.h> -#include <soc/gpio.h> -#include <soc/romstage.h> -#include <string.h> - -#define SPD_SIZE 256 -#define SATA_GP3_PAD_CFG0 0x5828 -#define I2C3_SCL_PAD_CFG0 0x5438 -#define MF_PLT_CLK1_PAD_CFG0 0x4410 -#define I2C3_SDA_PAD_CFG0 0x5420 - -/* - * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz - * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz - * 0b0010- 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz - * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz - */ -static const uint32_t dual_channel_config = (1 << 0); - -static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) -{ - int ram_id = 0; - ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0; - ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1; - ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0) - << 2; - ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3; - - /* - * There are only 2 SPDs supported on Cyan Board: - * Samsung 4G:0000 & Hynix 2G:0011 - */ - - /* - * RAMID0 on the first boot does not read the correct value,so checking - * bit 1 is enough as WA - */ - if (ram_id > 0) - ram_id = 3; - printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); - - if (ram_id >= total_spds) - return NULL; - - /* Single channel configs */ - if (dual_channel_config & (1 << ram_id)) - *dual = 1; - - return &spd_file_content[SPD_SIZE * ram_id]; -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *ps) -{ - char *spd_file; - size_t spd_file_len; - void *spd_content; - int dual_channel = 0; - - /* Find the SPD data in CBFS. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < SPD_SIZE) - die("Missing SPD data."); - - /* - * Both channels are always present in SPD data. Always use matched - * DIMMs so use the same SPD data for each DIMM. - */ - spd_content = get_spd_pointer(spd_file, - spd_file_len / SPD_SIZE, - &dual_channel); - if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) { - printk(BIOS_DEBUG, "SPD Data:\n"); - hexdump(spd_content, SPD_SIZE); - printk(BIOS_DEBUG, "\n"); - } - - /* - * Set SPD and memory configuration: - * Memory type: 0=DimmInstalled, - * 1=SolderDownMemory, - * 2=DimmDisabled - */ - if (spd_content != NULL) { - ps->spd_data_ch0 = spd_content; - ps->spd_ch0_config = 1; - if (dual_channel) { - ps->spd_data_ch1 = spd_content; - ps->spd_ch1_config = 1; - } else { - ps->spd_ch1_config = 2; - } - } -}

1 0

Patch set updated for coreboot: src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig files
by Martin Roth 25 Jan '16

25 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13427 -gerrit commit 79f41a01ebe8b95c0c0a84934027b42c996fdbdf Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 25 14:48:44 2016 -0700 src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig files Some trivial cleanup. Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/cyan/Makefile.inc | 0 src/mainboard/google/cyan/acpi/dptf.asl | 0 src/mainboard/google/cyan/acpi/mainboard.asl | 0 src/mainboard/google/cyan/acpi/superio.asl | 0 src/mainboard/google/cyan/acpi_tables.c | 0 src/mainboard/google/cyan/devicetree.cb | 0 src/mainboard/google/cyan/dsdt.asl | 0 src/mainboard/google/cyan/ec.c | 0 src/mainboard/google/cyan/ec.h | 0 src/mainboard/google/cyan/mainboard.c | 0 src/mainboard/google/cyan/onboard.h | 0 src/mainboard/google/cyan/romstage.c | 0 src/mainboard/google/lars/gpio.h | 0 src/mainboard/intel/kunimitsu/gpio.h | 0 src/mainboard/intel/strago/Kconfig | 0 src/mainboard/intel/strago/Makefile.inc | 0 src/mainboard/intel/strago/acpi/dptf.asl | 0 src/mainboard/intel/strago/acpi/ec.asl | 0 src/mainboard/intel/strago/acpi/mainboard.asl | 0 src/mainboard/intel/strago/acpi/superio.asl | 0 src/mainboard/intel/strago/acpi_tables.c | 0 src/mainboard/intel/strago/chromeos.c | 0 src/mainboard/intel/strago/com_init.c | 0 src/mainboard/intel/strago/devicetree.cb | 0 src/mainboard/intel/strago/dsdt.asl | 0 src/mainboard/intel/strago/ec.c | 0 src/mainboard/intel/strago/ec.h | 0 src/mainboard/intel/strago/fadt.c | 0 src/mainboard/intel/strago/gpio.c | 0 src/mainboard/intel/strago/gpio_dvt.c | 0 src/mainboard/intel/strago/mainboard.c | 0 src/mainboard/intel/strago/onboard.h | 0 src/mainboard/intel/strago/romstage.c | 0 src/mainboard/intel/strago/smihandler.c | 0 src/mainboard/intel/strago/spd/Makefile.inc | 0 src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 0 .../intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 0 src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 0 src/mainboard/intel/strago/spd/spd.c | 0 src/mainboard/intel/strago/w25q64.c | 0 src/soc/broadcom/cygnus/ddr_init.c | 0 src/soc/broadcom/cygnus/include/soc/config.h | 0 src/soc/broadcom/cygnus/include/soc/ddr_bist.h | 0 src/soc/broadcom/cygnus/include/soc/reg_utils.h | 0 src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h | 0 src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_reg_access.h | 0 src/soc/broadcom/cygnus/include/soc/shmoo_and28/shmoo_and28.h | 0 src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h | 0 src/soc/broadcom/cygnus/phy_reg_access.c | 0 src/soc/broadcom/cygnus/shmoo_and28.c | 0 src/soc/broadcom/cygnus/ydc_ddr_bist.c | 0 src/soc/intel/braswell/gpio.c | 0 src/soc/intel/fsp_baytrail/chip.h | 0 src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 0 src/vendorcode/amd/pi/00730F01/Include/PlatformMemoryConfiguration.h | 0 src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h | 0 56 files changed, 0 insertions(+), 0 deletions(-) diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/ec.h b/src/mainboard/google/cyan/ec.h old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c old mode 100755 new mode 100644 diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/acpi/dptf.asl b/src/mainboard/intel/strago/acpi/dptf.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/acpi/ec.asl b/src/mainboard/intel/strago/acpi/ec.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/acpi/superio.asl b/src/mainboard/intel/strago/acpi/superio.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/ec.h b/src/mainboard/intel/strago/ec.h old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/fadt.c b/src/mainboard/intel/strago/fadt.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/gpio_dvt.c b/src/mainboard/intel/strago/gpio_dvt.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/spd/Makefile.inc b/src/mainboard/intel/strago/spd/Makefile.inc old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/spd/spd.c b/src/mainboard/intel/strago/spd/spd.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/w25q64.c b/src/mainboard/intel/strago/w25q64.c old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/config.h b/src/soc/broadcom/cygnus/include/soc/config.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/ddr_bist.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/reg_utils.h b/src/soc/broadcom/cygnus/include/soc/reg_utils.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_reg_access.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_reg_access.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/shmoo_and28.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/shmoo_and28.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/phy_reg_access.c b/src/soc/broadcom/cygnus/phy_reg_access.c old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/shmoo_and28.c b/src/soc/broadcom/cygnus/shmoo_and28.c old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/ydc_ddr_bist.c b/src/soc/broadcom/cygnus/ydc_ddr_bist.c old mode 100755 new mode 100644 diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c old mode 100755 new mode 100644 diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h old mode 100755 new mode 100644 diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c old mode 100755 new mode 100644 diff --git a/src/vendorcode/amd/pi/00730F01/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/pi/00730F01/Include/PlatformMemoryConfiguration.h old mode 100755 new mode 100644 diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h old mode 100755 new mode 100644

1 0

New patch to review for coreboot: src/: Chmod 644 all .c, .h, .asl, .inc, .cb, & Kconfig files
by Martin Roth 25 Jan '16

25 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13427 -gerrit commit c2a06cc07ffbf9b267bac8184b623408551605e7 Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 25 14:48:44 2016 -0700 src/: Chmod 644 all .c, .h, .asl, .inc, .cb, & Kconfig files Some trivial cleanup. Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/cyan/Makefile.inc | 0 src/mainboard/google/cyan/acpi/dptf.asl | 0 src/mainboard/google/cyan/acpi/mainboard.asl | 0 src/mainboard/google/cyan/acpi/superio.asl | 0 src/mainboard/google/cyan/acpi_tables.c | 0 src/mainboard/google/cyan/devicetree.cb | 0 src/mainboard/google/cyan/dsdt.asl | 0 src/mainboard/google/cyan/ec.c | 0 src/mainboard/google/cyan/ec.h | 0 src/mainboard/google/cyan/mainboard.c | 0 src/mainboard/google/cyan/onboard.h | 0 src/mainboard/google/cyan/romstage.c | 0 src/mainboard/google/lars/gpio.h | 0 src/mainboard/intel/kunimitsu/gpio.h | 0 src/mainboard/intel/strago/Kconfig | 0 src/mainboard/intel/strago/Makefile.inc | 0 src/mainboard/intel/strago/acpi/dptf.asl | 0 src/mainboard/intel/strago/acpi/ec.asl | 0 src/mainboard/intel/strago/acpi/mainboard.asl | 0 src/mainboard/intel/strago/acpi/superio.asl | 0 src/mainboard/intel/strago/acpi_tables.c | 0 src/mainboard/intel/strago/chromeos.c | 0 src/mainboard/intel/strago/com_init.c | 0 src/mainboard/intel/strago/devicetree.cb | 0 src/mainboard/intel/strago/dsdt.asl | 0 src/mainboard/intel/strago/ec.c | 0 src/mainboard/intel/strago/ec.h | 0 src/mainboard/intel/strago/fadt.c | 0 src/mainboard/intel/strago/gpio.c | 0 src/mainboard/intel/strago/gpio_dvt.c | 0 src/mainboard/intel/strago/mainboard.c | 0 src/mainboard/intel/strago/onboard.h | 0 src/mainboard/intel/strago/romstage.c | 0 src/mainboard/intel/strago/smihandler.c | 0 src/mainboard/intel/strago/spd/Makefile.inc | 0 src/mainboard/intel/strago/spd/spd.c | 0 src/mainboard/intel/strago/w25q64.c | 0 src/soc/broadcom/cygnus/ddr_init.c | 0 src/soc/broadcom/cygnus/include/soc/config.h | 0 src/soc/broadcom/cygnus/include/soc/ddr_bist.h | 0 src/soc/broadcom/cygnus/include/soc/reg_utils.h | 0 src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h | 0 src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_reg_access.h | 0 src/soc/broadcom/cygnus/include/soc/shmoo_and28/shmoo_and28.h | 0 src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h | 0 src/soc/broadcom/cygnus/phy_reg_access.c | 0 src/soc/broadcom/cygnus/shmoo_and28.c | 0 src/soc/broadcom/cygnus/ydc_ddr_bist.c | 0 src/soc/intel/braswell/gpio.c | 0 src/soc/intel/fsp_baytrail/chip.h | 0 src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 0 src/vendorcode/amd/pi/00730F01/Include/PlatformMemoryConfiguration.h | 0 src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h | 0 53 files changed, 0 insertions(+), 0 deletions(-) diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/ec.h b/src/mainboard/google/cyan/ec.h old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h old mode 100755 new mode 100644 diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c old mode 100755 new mode 100644 diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/acpi/dptf.asl b/src/mainboard/intel/strago/acpi/dptf.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/acpi/ec.asl b/src/mainboard/intel/strago/acpi/ec.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/acpi/superio.asl b/src/mainboard/intel/strago/acpi/superio.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/ec.h b/src/mainboard/intel/strago/ec.h old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/fadt.c b/src/mainboard/intel/strago/fadt.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/gpio_dvt.c b/src/mainboard/intel/strago/gpio_dvt.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/spd/Makefile.inc b/src/mainboard/intel/strago/spd/Makefile.inc old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/spd/spd.c b/src/mainboard/intel/strago/spd/spd.c old mode 100755 new mode 100644 diff --git a/src/mainboard/intel/strago/w25q64.c b/src/mainboard/intel/strago/w25q64.c old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/config.h b/src/soc/broadcom/cygnus/include/soc/config.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/ddr_bist.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/reg_utils.h b/src/soc/broadcom/cygnus/include/soc/reg_utils.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_reg_access.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_reg_access.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/shmoo_and28.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/shmoo_and28.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/phy_reg_access.c b/src/soc/broadcom/cygnus/phy_reg_access.c old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/shmoo_and28.c b/src/soc/broadcom/cygnus/shmoo_and28.c old mode 100755 new mode 100644 diff --git a/src/soc/broadcom/cygnus/ydc_ddr_bist.c b/src/soc/broadcom/cygnus/ydc_ddr_bist.c old mode 100755 new mode 100644 diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c old mode 100755 new mode 100644 diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h old mode 100755 new mode 100644 diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c old mode 100755 new mode 100644 diff --git a/src/vendorcode/amd/pi/00730F01/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/pi/00730F01/Include/PlatformMemoryConfiguration.h old mode 100755 new mode 100644 diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h old mode 100755 new mode 100644

1 0

Patch set updated for coreboot: soc/apollolake/gpio.c: Take global pad offsets in configure_pad()
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13316 -gerrit commit d7830fcaa4ad5adae3af25c08b295d5b68871d24 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Oct 22 17:49:15 2015 -0700 soc/apollolake/gpio.c: Take global pad offsets in configure_pad() This allows a user to use the pad macros in gpio_defs.h, without having to worry in which specific community the pad resides. The early UART driver is also updated to use this new mechanism. Change-Id: If3755fdb7bded522fac3035904232ae43fd02546 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/gpio.c | 36 ++++++++++++++++++++++++++--- src/soc/intel/apollolake/include/soc/gpio.h | 3 +-- src/soc/intel/apollolake/uart_early.c | 9 +++----- 3 files changed, 37 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index 2796e42..c60a39c 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -13,9 +13,39 @@ #include <soc/gpio.h> #include <soc/iosf.h> +/* This list must be in order, from highest pad numbers, to lowest pad numbers*/ +static const struct pad_community { + uint16_t first_pad; + uint8_t port; +} gpio_communities[] = { + { + .port = GPIO_SOUTHWEST, + .first_pad = SW_OFFSET, + }, { + .port = GPIO_WEST, + .first_pad = W_OFFSET, + }, { + .port = GPIO_NORTHWEST, + .first_pad = NW_OFFSET, + }, { + .port = GPIO_NORTH, + .first_pad = 0, + } +}; + +static const struct pad_community *gpio_get_community(uint16_t pad) +{ + const struct pad_community *map = gpio_communities; + + while (map->first_pad > pad) + map++; + + return map; +} void gpio_configure_pad(const struct pad_config *cfg) { - uint16_t config_offset = PAD_CFG_OFFSET(cfg->pad); - iosf_write(cfg->community, config_offset, cfg->config[0]); - iosf_write(cfg->community, config_offset + 4, cfg->config[1]); + const struct pad_community *comm = gpio_get_community(cfg->pad); + uint16_t config_offset = PAD_CFG_OFFSET(cfg->pad - comm->first_pad); + iosf_write(comm->port, config_offset, cfg->config[0]); + iosf_write(comm->port, config_offset + 4, cfg->config[1]); } diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 5744f72..43a242c 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -17,9 +17,8 @@ #include <soc/gpio_defs.h> struct pad_config { - uint8_t community; - uint8_t pad; uint32_t config[2]; + uint16_t pad; }; /* diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c index bc02776..aba23b0 100644 --- a/src/soc/intel/apollolake/uart_early.c +++ b/src/soc/intel/apollolake/uart_early.c @@ -17,16 +17,13 @@ static const struct pad_config uart_tx_pad_configs[] = { { - .community = GPIO_NORTH, - .pad = 39, + .pad = GPIO_39, .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE}, }, { - .community = GPIO_NORTH, - .pad = 42, + .pad = GPIO_42, .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE}, }, { - .community = GPIO_NORTH, - .pad = 47, + .pad = GPIO_47, .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE}, }, };

1 0

Patch set updated for coreboot: soc/apollolake: Refactor GPIO macros to better match skylake
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13317 -gerrit commit 7f00091fb96bae5bd7875c7ebc35402387f238a9 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Oct 26 16:01:59 2015 -0700 soc/apollolake: Refactor GPIO macros to better match skylake Apollolake GPIO subsystem is very similar to the one on skylake. Aaron wants the GPIO configuration tables to be consistent between skylake and apollolake boards. so we try to immitate the macros from skylake. Change-Id: I806896718fd12a46c1c5fc477de264756fb81273 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/gpio.c | 4 +-- src/soc/intel/apollolake/include/soc/gpio.h | 31 +++++++++++++++++++++++- src/soc/intel/apollolake/include/soc/gpio_defs.h | 14 ++++++----- src/soc/intel/apollolake/uart_early.c | 13 +++------- 4 files changed, 43 insertions(+), 19 deletions(-) diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index c60a39c..43e0b9b 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -46,6 +46,6 @@ void gpio_configure_pad(const struct pad_config *cfg) { const struct pad_community *comm = gpio_get_community(cfg->pad); uint16_t config_offset = PAD_CFG_OFFSET(cfg->pad - comm->first_pad); - iosf_write(comm->port, config_offset, cfg->config[0]); - iosf_write(comm->port, config_offset + 4, cfg->config[1]); + iosf_write(comm->port, config_offset, cfg->config0); + iosf_write(comm->port, config_offset + 4, cfg->config1); } diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 43a242c..3c8d475 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -16,8 +16,37 @@ #include <types.h> #include <soc/gpio_defs.h> +#define PAD_FUNC(value) PAD_CFG0_MODE_##value +#define PAD_RESET(value) PAD_CFG0_RESET_##value +#define PAD_PULL(value) PAD_CFG1_PULL_##value + +#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ + { \ + .pad = __pad, \ + .config0 = __config0, \ + .config1 = __config1, \ + } + +/* Native function configuration */ +#define PAD_CFG_NF(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull)) + +/* General purpose output, no pullup/down. */ +#define PAD_CFG_GPO(pad, val, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(NONE)) + +/* General purpose input */ +#define PAD_CFG_GPI(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull)) + + struct pad_config { - uint32_t config[2]; + uint32_t config0; + uint16_t config1; uint16_t pad; }; diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index f2bf00b..a1c3186 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -23,6 +23,9 @@ #define PAD_CFG0_MODE_MASK (7 << 10) #define PAD_CFG0_MODE_GPIO (0 << 10) #define PAD_CFG0_MODE_FUNC(x) ((x) << 10) +#define PAD_CFG0_MODE_NF1 (1 << 10) +#define PAD_CFG0_MODE_NF2 (2 << 10) +#define PAD_CFG0_MODE_NF3 (3 << 10) #define PAD_CFG0_ROUTE_NMI (1 << 17) #define PAD_CFG0_ROUTE_SMI (1 << 18) #define PAD_CFG0_ROUTE_SCI (1 << 19) @@ -34,10 +37,10 @@ #define PAD_CFG0_TRIG_OFF (2 << 25) #define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25) #define PAD_CFG0_RESET_MASK (3 << 30) -#define PAD_CFG0_RESET_STICKY (0 << 30) +#define PAD_CFG0_RESET_PWROK (0 << 30) #define PAD_CFG0_RESET_DEEP (1 << 30) -#define PAD_CFG0_RESET_GPIOR (2 << 30) -#define PAD_CFG0_RESET_INACTIVE (3 << 30) +#define PAD_CFG0_RESET_PLTRST (2 << 30) +#define PAD_CFG0_RESET_RSMRST (3 << 30) #define PAD_CFG1_PULL_MASK (0xf << 12) #define PAD_CFG1_PULL_NONE (0x0 << 12) @@ -323,11 +326,10 @@ #define PAD_SW(pad) (pad - SW_OFFSET) /* Default configurations */ -#define PAD_CFG0_DEFAULT_FUNC(x) (0x44000000 | PAD_CFG0_MODE_FUNC(x)) +#define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP | PAD_CFG0_MODE_FUNC(x)) #define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1) -#define PAD_CFG1_DEFAULT_NOPULL PAD_CFG1_PULL_NONE #define PAD_CFG1_DEFAULT_PULLUP PAD_CFG1_PULL_UP_20K -#define PAD_CFG1_DEFAULT_NATIVE PAD_CFG1_PULL_NATIVE +#define PAD_CFG1_DEFAULT_NATIVE PAD_CFG1_PULL_NATIVE #endif /* _SOC_APOLLOLAKE_GPIO_DEFS_H_ */ diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c index aba23b0..be36023 100644 --- a/src/soc/intel/apollolake/uart_early.c +++ b/src/soc/intel/apollolake/uart_early.c @@ -16,16 +16,9 @@ #include <soc/uart.h> static const struct pad_config uart_tx_pad_configs[] = { - { - .pad = GPIO_39, - .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE}, - }, { - .pad = GPIO_42, - .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE}, - }, { - .pad = GPIO_47, - .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE}, - }, + PAD_CFG_NF(GPIO_39, NATIVE, DEEP, NF1), /* UART0 TX*/ + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 TX*/ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX*/ }; static void lpss_uart_write(uint16_t reg, uint32_t val)

1 0

Patch set updated for coreboot: soc/apollolake/gpio: Add function to configure a list of pads
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13318 -gerrit commit 7c2c1142ad35920d4be8dbf0d5cf98935402b15f Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Oct 26 18:04:56 2015 -0700 soc/apollolake/gpio: Add function to configure a list of pads Change-Id: I90bb600dde3b3632293f00631ada008c1b51d875 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/gpio.c | 7 +++++++ src/soc/intel/apollolake/include/soc/gpio.h | 1 + 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index 43e0b9b..3bc64e2 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -42,6 +42,7 @@ static const struct pad_community *gpio_get_community(uint16_t pad) return map; } + void gpio_configure_pad(const struct pad_config *cfg) { const struct pad_community *comm = gpio_get_community(cfg->pad); @@ -49,3 +50,9 @@ void gpio_configure_pad(const struct pad_config *cfg) iosf_write(comm->port, config_offset, cfg->config0); iosf_write(comm->port, config_offset + 4, cfg->config1); } + +void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) +{ + while (num_pads--) + gpio_configure_pad(cfg + num_pads); +} diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 3c8d475..6393d8f 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -56,5 +56,6 @@ struct pad_config { * pad configuration functionality. */ void gpio_configure_pad(const struct pad_config *cfg); +void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); #endif /* _SOC_APOLLOLAKE_GPIO_H_ */

1 0

Patch set updated for coreboot: arch/x86: Add option to disable default mmap_boot implementation
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13319 -gerrit commit 7553d4155ee5bf64fbc8b19b768fc183a8abf5a4 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 27 10:27:30 2015 -0700 arch/x86: Add option to disable default mmap_boot implementation On certain platforms, the boot media is either not memory-mapped, or not mapped at the top of 4G. This makes the default mmap_boot implementation uinsuitable. Add an option to allow such platforms to define their own mapping implementation. Change-Id: I8293126fd9cc1fd3d75072f7811e659765348e4a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/arch/x86/Kconfig | 6 ++++++ src/arch/x86/Makefile.inc | 8 ++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 738e7d1..d3d33b4 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -77,6 +77,12 @@ config RAMBASE hex default 0x100000 +# This indicates the boot media is mapped at top of 4G. This variable is used +# to decide whether to pull in the default mmap_boot.c implementation. +config X86_TOP4G_BOOTMEDIA_MAP + bool + default y + # This is something you almost certainly don't want to mess with. # How many SIPIs do we send when starting up APs and cores? # The answer in 2000 or so was '2'. Nowadays, on many systems, diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index bd9e348..75f06df 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -107,7 +107,7 @@ CFLAGS_bootblock+=-Wa,--divide bootblock-y += boot.c bootblock-y += memcpy.c bootblock-y += memset.c -bootblock-y += mmap_boot.c +bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-y += id.S $(obj)/arch/x86/id.bootblock.o: $(obj)/build.h @@ -356,7 +356,7 @@ romstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c romstage-y += memset.c romstage-y += memcpy.c romstage-y += memmove.c -romstage-y += mmap_boot.c +romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -386,7 +386,7 @@ ramstage-y += memset.c ramstage-y += memcpy.c ramstage-y += memmove.c ramstage-y += ebda.c -ramstage-y += mmap_boot.c +ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -394,7 +394,7 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c smm-y += memset.c smm-y += memcpy.c smm-y += memmove.c -smm-y += mmap_boot.c +smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) rmodules_x86_32-y += memset.c

1 0

Patch set updated for coreboot: soc/apollolake: clear whole contents of cache-as-ram
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13312 -gerrit commit 4c3feb6b0c608d469ffffcb8bf48192b98969ac2 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 22 09:41:07 2015 -0700 soc/apollolake: clear whole contents of cache-as-ram Some code makes assumption on memory to be cleared. In particular we must clear area occupied by car.data. FSP seems to be also making assumption stack memory is zeroed. This can be further reworked to clear only areas that have to be cleared for the sake of saving cycles. Change-Id: I9d75cb0a15f2bebf47d53daf7e4d76865a4c166b Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index e451f66..5bbf6cc 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -104,15 +104,11 @@ clear_var_mtrr: post_code(0x26) - /* Write something to each cache line */ - mov eax, 0xcafebabe + /* Clear the cache memory region. This will also fill up the cache */ mov edi, CONFIG_DCACHE_RAM_BASE - mov ecx, (0x80000 >> 6) -cache_init_loop: - mov [edi], eax - sfence - add edi, 64 - loop cache_init_loop + mov ecx, CONFIG_DCACHE_RAM_SIZE >> 2 + xor eax, eax + rep stos dword ptr es:[edi], eax post_code(0x27)

1 0

Patch set updated for coreboot: soc/apollolake/cache_as_ram: 'call' don't 'jmp' to bootblock_main
by Alexandru Gagniuc 25 Jan '16

25 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13313 -gerrit commit b6a687e76978ccf8e14088a56c21e82c5661a407 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Oct 22 09:21:34 2015 -0700 soc/apollolake/cache_as_ram: 'call' don't 'jmp' to bootblock_main After working without a stack for so long, it's easy to overlook that you have a stack, and that it works. The tendency to manually control the stack still exists. Just call 'bootblock_car_main', and avoid manually setting up a return pointer. Change-Id: I257ba497dfa69902eff0686a5d2169db9b13434a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 5bbf6cc..6ecfa86 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -135,9 +135,8 @@ car_init_done: before_carstage: post_code(0x2b) - /* Call romstage.c main function. */ - push .halt_forever /* In case bootblock_car_main returns */ - jmp bootblock_car_main + /* Call bootblock C environment main function. */ + call bootblock_car_main /* Never reached */

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2016