coreboot-gerrit July 2015

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Patch set updated for coreboot: vendorcode: 64bit fixes for AMD CIMX SB800
by Stefan Reinauer 17 Jul '15

17 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10573 -gerrit commit f81483645f4c82a30f8359fae6f2f2b78708e1b9 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jun 17 16:05:05 2015 -0700 vendorcode: 64bit fixes for AMD CIMX SB800 Make SB800 code compile with x64 compiler These fixes probably apply 1:1 to the other SB components in that directory. Change-Id: I9ff9f27dff5074d2faf41ebc14bfe50871d9c7f7 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/vendorcode/amd/cimx/sb800/DISPATCHER.c | 8 ++------ src/vendorcode/amd/cimx/sb800/Makefile.inc | 5 +++++ src/vendorcode/amd/cimx/sb800/SBMAIN.c | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c index 84bbccb..8b35047 100644 --- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c +++ b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c @@ -183,11 +183,7 @@ LocateImage ( ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1); while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) { -#ifdef x64 - 12346789 -#else - Result = VerifyImage (Signature, (VOID*) ImagePtr); -#endif + Result = VerifyImage (Signature, (VOID*)(UINTN)ImagePtr); if ( Result != NULL ) { return Result; } @@ -244,7 +240,7 @@ saveConfigPointer ( UINT8 i; UINT32 ddValue; - ddValue = (UINT32) (UINTN)pConfig; + ddValue = (UINT32) (UINTN)pConfig; // Needs to live below 4G dbReg = SB_ECMOS_REG08; for ( i = 0; i <= 3; i++ ) { diff --git a/src/vendorcode/amd/cimx/sb800/Makefile.inc b/src/vendorcode/amd/cimx/sb800/Makefile.inc index 96cae03..fde6239 100644 --- a/src/vendorcode/amd/cimx/sb800/Makefile.inc +++ b/src/vendorcode/amd/cimx/sb800/Makefile.inc @@ -22,6 +22,11 @@ CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/cimx/sb800 CPPFLAGS_x86_32 += -I$(src)/include/cpu/amd/common CPPFLAGS_x86_32 += -I$(src)/vendorcode/amd/cimx/sb800 +CPPFLAGS_x86_64 += -I$(src)/mainboard/$(MAINBOARDDIR) +CPPFLAGS_x86_64 += -I$(src)/southbridge/amd/cimx/sb800 +CPPFLAGS_x86_64 += -I$(src)/include/cpu/amd/common +CPPFLAGS_x86_64 += -I$(src)/vendorcode/amd/cimx/sb800 + romstage-y += ACPILIB.c romstage-y += AZALIA.c romstage-y += DISPATCHER.c diff --git a/src/vendorcode/amd/cimx/sb800/SBMAIN.c b/src/vendorcode/amd/cimx/sb800/SBMAIN.c index eb21770..a494d30 100644 --- a/src/vendorcode/amd/cimx/sb800/SBMAIN.c +++ b/src/vendorcode/amd/cimx/sb800/SBMAIN.c @@ -240,7 +240,7 @@ sbSmmAcpiOn ( * @param[in] Data Callback specific data. * @param[in] pConfig Southbridge configuration structure pointer. */ -UINTN +UINT32 CallBackToOEM ( IN UINT32 Func, IN UINT32 Data,

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Patch set updated for coreboot: cpu: port amd/agesa to 64bit
by Stefan Reinauer 17 Jul '15

17 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10579 -gerrit commit baa58e810ec253cebab6978de94cca4c6641d274 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:14:01 2015 -0700 cpu: port amd/agesa to 64bit Change-Id: I8644b04f4b57db5fc95ec155d3f78d53c63c9831 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/cpu/amd/agesa/Makefile.inc | 4 + src/cpu/amd/agesa/cache_as_ram64.inc | 159 +++++++++++++++++++++++++++++++++++ src/cpu/amd/agesa/s3_resume.c | 7 ++ 3 files changed, 170 insertions(+) diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 153b2db..485d107 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -27,7 +27,11 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb romstage-y += s3_resume.c ramstage-y += s3_mtrr.c +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc +else +cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram64.inc +endif romstage-y += heapmanager.c ramstage-y += heapmanager.c diff --git a/src/cpu/amd/agesa/cache_as_ram64.inc b/src/cpu/amd/agesa/cache_as_ram64.inc new file mode 100644 index 0000000..de3a9bc --- /dev/null +++ b/src/cpu/amd/agesa/cache_as_ram64.inc @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/****************************************************************************** + * AMD Generic Encapsulated Software Architecture + * + * $Workfile:: cache_as_ram.inc + * + * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier + * + ****************************************************************************** + */ + +#include "gcccar.inc" +#include <cpu/x86/cache.h> + +/* + * XMM map: + * xmm0: BIST + * xmm1: backup ebx -- cpu_init_detected + */ + +.code32 +.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out + +cache_as_ram_setup: + + post_code(0xa0) + + /* enable SSE2 128bit instructions */ + /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ + + movl %cr4, %eax + orl $(3<<9), %eax + movl %eax, %cr4 + + /* Get the cpu_init_detected */ + mov $1, %eax + cpuid + shr $24, %ebx + + /* Save the BIST result */ + cvtsi2sd %ebp, %xmm0 + + /* for normal part %ebx already contain cpu_init_detected from fallback call */ + + /* Save the cpu_init_detected */ + cvtsi2sd %ebx, %xmm1 + + post_code(0xa1) + // AMD_ENABLE_STACK + + post_code(0xa1) + + /* switch to 64 bit long mode */ + .intel_syntax noprefix + + mov ecx, esi + add ecx, 0 # core number + xor eax, eax + lea edi, [ecx+0x1000+0x23] + mov dword ptr [ecx+0], edi + mov dword ptr [ecx+4], eax + + lea edi, [ecx+0x1000] + mov dword ptr [edi+0x00], 0x000000e3 + mov dword ptr [edi+0x04], eax + mov dword ptr [edi+0x08], 0x400000e3 + mov dword ptr [edi+0x0c], eax + mov dword ptr [edi+0x10], 0x800000e3 + mov dword ptr [edi+0x14], eax + mov dword ptr [edi+0x18], 0xc00000e3 + mov dword ptr [edi+0x1c], eax + + # load rom based identity mapped page tables + mov eax, ecx + mov cr3,eax + + # enable PAE + mov eax, cr4 + bts eax, 5 + mov cr4, eax + + # enable long mode + mov ecx, 0xC0000080 + rdmsr + bts eax, 8 + wrmsr + + # enable paging + mov eax, cr0 + bts eax, 31 + mov cr0, eax + + # use call far to switch to 64-bit code segment + jmp 0x18,.+7 + + /* Pass the BIST result */ + cvtsd2si esi, xmm1 + + /* Pass the cpu_init_detected */ + cvtsd2si edi, xmm0 + + /* align the stack */ + and esp, 0xFFFFFFF0 + + .code64 + call cache_as_ram_main + .code32 + + .att_syntax prefix + + /* Should never see this postcode */ + post_code(0xaf) +stop: + jmp stop + +disable_cache_as_ram: + /* Save return stack */ + movd 0(%esp), %xmm1 + movd %esp, %xmm0 + + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + AMD_DISABLE_STACK + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff, %eax + movl %eax, %cr0 + xorl %eax, %eax + + /* Restore the return stack */ + wbinvd + movd %xmm0, %esp + movd %xmm1, (%esp) + ret + +cache_as_ram_setup_out: +.code64 diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 5e07d7a..98671f4 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -56,10 +56,17 @@ static void move_stack_high_mem(void) memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); /* TODO: We only switch stack on BSP. */ +#ifdef __x86_64__ + __asm__ + volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g" + (high_stack - BSP_STACK_BASE_ADDR) + :); +#else __asm__ volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" (high_stack - BSP_STACK_BASE_ADDR) :); +#endif } static void set_resume_cache(void)

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Patch set updated for coreboot: SB800: Port to 64bit
by Stefan Reinauer 17 Jul '15

17 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10582 -gerrit commit b36ac2d3552c5598a49509c840b930b53a7c1d3e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:17:38 2015 -0700 SB800: Port to 64bit Change-Id: I944fb254e9470c80b13c9eef9d6b1177a56e615f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/southbridge/amd/cimx/sb800/fadt.c | 25 +++++++++++++++++++------ src/southbridge/amd/cimx/sb800/gpio_oem.h | 6 +++--- src/southbridge/amd/cimx/sb800/late.c | 8 ++++---- src/southbridge/amd/cimx/sb800/spi.c | 2 +- 4 files changed, 27 insertions(+), 14 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 70173b6..d8fdd6f 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -63,8 +63,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; + if ((uintptr_t)facs > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n"); + else + fadt->firmware_ctrl = (uintptr_t)facs; + + if ((uintptr_t)dsdt > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n"); + else + fadt->dsdt = (uintptr_t)dsdt; + fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 – ACPI SCI */ @@ -153,10 +161,15 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; + + fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; +#ifdef __x86_64__ + fadt->x_firmware_ctl_h = ((uintptr_t)facs) >> 32; +#endif + fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; +#ifdef __x86_64__ + fadt->x_dsdt_h = ((uintptr_t)dsdt) >> 32; +#endif fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/southbridge/amd/cimx/sb800/gpio_oem.h b/src/southbridge/amd/cimx/sb800/gpio_oem.h index a9f59e3..e2c81fc 100644 --- a/src/southbridge/amd/cimx/sb800/gpio_oem.h +++ b/src/southbridge/amd/cimx/sb800/gpio_oem.h @@ -11,9 +11,9 @@ #define SB_GPIO_REG28 28 /* FCH GPIO access helpers */ -#define FCH_IOMUX(gpio_nr) (*(u8*)(ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr))) -#define FCH_PMIO(reg_nr) (*(u8*)(ACPI_MMIO_BASE+PMIO_BASE+(reg_nr))) -#define FCH_GPIO(gpio_nr) (*(volatile u8*)(ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr))) +#define FCH_IOMUX(gpio_nr) (*(u8*)((uintptr_t)ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr))) +#define FCH_PMIO(reg_nr) (*(u8*)((uintptr_t)ACPI_MMIO_BASE+PMIO_BASE+(reg_nr))) +#define FCH_GPIO(gpio_nr) (*(volatile u8*)((uintptr_t)ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr))) static inline u8 fch_gpio_state(unsigned int gpio_nr) { diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 0ada673..01900fe 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -108,15 +108,15 @@ static void ahci_raid_init(struct device *dev) bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); - caps = *(volatile u32 *)(bar5 + HOST_CAP); + caps = *(volatile u32 *)((uintptr_t)bar5 + HOST_CAP); caps = (caps & 0x1F) + 1; - ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); + ports= *(volatile u32 *)((uintptr_t)bar5 + HOST_PORTS_IMPL); printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); /* make sure ahci is enabled */ - val = *(volatile u32 *)(bar5 + HOST_CTL); + val = *(volatile u32 *)((uintptr_t)bar5 + HOST_CTL); if (!(val & HOST_CTL_AHCI_EN)) { - *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; + *(volatile u32 *)((uintptr_t)bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; } dev->command |= PCI_COMMAND_MASTER; diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 1ce7fcd..694a3b7 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -35,7 +35,7 @@ static int bus_claimed = 0; #define AMD_SB_SPI_TX_LEN 8 -static u32 spibar; +static uintptr_t spibar; static void reset_internal_fifo_pointer(void) {

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Patch set updated for coreboot: Port Fam14 northbridge code to 64bit
by Stefan Reinauer 17 Jul '15

17 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10583 -gerrit commit 0ca45abcda599e1876a78d7c8d3e722a32398fbb Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:18:09 2015 -0700 Port Fam14 northbridge code to 64bit Change-Id: I694b739a29e9d82d153d9fb3b729dc250bd4901e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/northbridge/amd/agesa/family14/northbridge.c | 6 +++--- src/northbridge/amd/agesa/oem_s3.c | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index fcc0d87..691fdf6 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -529,7 +529,7 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); + printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev); unsigned long mmio_basek; u32 pci_tolm; @@ -741,11 +741,11 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 0, (void *)((uintptr_t)addr + 2), *(UINT16 *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 1, (void *)((uintptr_t)addr + 2), *(UINT16 *)addr - 2); return (unsigned long)current; } diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index 77bab67..5f02815 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -39,7 +39,7 @@ typedef enum { #error "Please increase the value of S3_DATA_SIZE" #endif -static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) +static void get_s3nv_data(S3_DATA_TYPE S3DataType, uintptr_t *pos, uintptr_t *len) { /* FIXME: Find file from CBFS. */ u32 s3_data = CONFIG_S3_DATA_POS; @@ -65,7 +65,7 @@ static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams) { AMD_S3_PARAMS *dataBlock = &ResumeParams->S3DataBlock; - u32 pos, size; + uintptr_t pos, size; get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); @@ -126,7 +126,7 @@ AGESA_STATUS OemS3Save(void *vS3SaveParams) #endif u8 MTRRStorage[S3_DATA_MTRR_SIZE]; u32 MTRRStorageSize = 0; - u32 pos, size; + uintptr_t pos, size; if (HIGH_ROMSTAGE_STACK_SIZE) cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE); @@ -157,7 +157,7 @@ AGESA_STATUS OemS3Save(void *vS3SaveParams) const void *OemS3Saved_MTRR_Storage(void) { - u32 pos, size; + uintptr_t pos, size; get_s3nv_data(S3DataTypeMTRR, &pos, &size); if (!size) return NULL;

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Patch set updated for coreboot: vendorcode: Port AMD Agesa for Fam14 to 64bit
by Stefan Reinauer 17 Jul '15

17 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10581 -gerrit commit 31f0b54730619d83ded6ded92485022257958173 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:16:40 2015 -0700 vendorcode: Port AMD Agesa for Fam14 to 64bit Change-Id: Ic6b3c3382a6d3fdc6d716ea899db598910b4fe3e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 46 +++++++++++------------ src/vendorcode/amd/agesa/f14/Makefile.inc | 6 +++ src/vendorcode/amd/agesa/f14/gcccar.inc | 4 ++ 3 files changed, 33 insertions(+), 23 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 7d90f8b..9ae45c3 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -27,11 +27,11 @@ */ #if defined (__GNUC__) - +#include <stdint.h> /* I/O intrin functions. */ -static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port) +static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port) { - unsigned char value; + uint8_t value; __asm__ __volatile__ ( "in %1, %0" @@ -42,9 +42,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned return value; } -static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port) +static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port) { - unsigned short value; + uint16_t value; __asm__ __volatile__ ( "in %1, %0" @@ -55,9 +55,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne return value; } -static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port) +static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port) { - unsigned long value; + uint32_t value; __asm__ __volatile__ ( "in %1, %0" @@ -68,7 +68,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne } -static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data) +static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data) { __asm__ __volatile__ ( "out %0, %1" @@ -77,7 +77,7 @@ static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short P ); } -static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data) +static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data) { __asm__ __volatile__ ( "out %0, %1" @@ -86,7 +86,7 @@ static __inline__ __attribute__((always_inline)) void __outword(unsigned short P ); } -static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data) +static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data) { __asm__ __volatile__ ( "out %0, %1" @@ -95,7 +95,7 @@ static __inline__ __attribute__((always_inline)) void __outdword(unsigned short ); } -static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; insb" @@ -104,7 +104,7 @@ static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned sh ); } -static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; insw" @@ -113,7 +113,7 @@ static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned sh ); } -static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; insl" @@ -122,7 +122,7 @@ static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned s ); } -static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; outsb" @@ -131,7 +131,7 @@ static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned s ); } -static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; outsw" @@ -140,7 +140,7 @@ static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned s ); } -static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; outsl" @@ -525,7 +525,7 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source) } static __inline__ __attribute__((always_inline)) void -__writefsbyte(const unsigned long Offset, const unsigned char Data) +__writefsbyte(const unsigned long Offset, const uint8_t Data) { __asm__ ("movb %[Data], %%fs:%a[Offset]" : @@ -533,7 +533,7 @@ __writefsbyte(const unsigned long Offset, const unsigned char Data) } static __inline__ __attribute__((always_inline)) void -__writefsword(const unsigned long Offset, const unsigned short Data) +__writefsword(const unsigned long Offset, const uint16_t Data) { __asm__ ("movw %[Data], %%fs:%a[Offset]" : @@ -541,14 +541,14 @@ __writefsword(const unsigned long Offset, const unsigned short Data) } static __inline__ __attribute__((always_inline)) void -__writefsdword(const unsigned long Offset, const unsigned long Data) +__writefsdword(const unsigned long Offset, const uint32_t Data) { __asm__ ("movl %[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "ir" (Data)); } -static __inline__ __attribute__((always_inline)) unsigned char +static __inline__ __attribute__((always_inline)) uint8_t __readfsbyte(const unsigned long Offset) { unsigned char value; @@ -558,7 +558,7 @@ __readfsbyte(const unsigned long Offset) return value; } -static __inline__ __attribute__((always_inline)) unsigned short +static __inline__ __attribute__((always_inline)) uint16_t __readfsword(const unsigned long Offset) { unsigned short value; @@ -568,11 +568,11 @@ __readfsword(const unsigned long Offset) return value; } -static __inline__ __attribute__((always_inline)) unsigned long +static __inline__ __attribute__((always_inline)) uint32_t __readfsdword(unsigned long Offset) { unsigned long value; - __asm__ ("movl %%fs:%a[Offset], %[value]" + __asm__ ("mov %%fs:%a[Offset], %[value]" : [value] "=r" (value) : [Offset] "ir" (Offset)); return value; diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index f62f276..a5f7561 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -64,15 +64,21 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing +CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### classes-y += libagesa +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call create_class_compiler,libagesa,x86_32)) +else +$(eval $(call create_class_compiler,libagesa,x86_64)) +endif libagesa-y = Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 2104c27..394087b 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -42,7 +42,11 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +#ifdef __x86_64__ CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ +#else +CORE1_STACK_SIZE = 0x2000 /* 4KB for each AP cores */ +#endif APIC_BASE_ADDRESS = 0x0000001B APIC_BSC = 8 /* Boot Strap Core */

1 0

Patch set updated for coreboot: amd: raminit sysinfo offset fix
by Aaron Durbin 16 Jul '15

16 Jul '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10961 -gerrit commit 9162437a87e88645a1b25b7887dd36f5d01370f3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 16 16:07:02 2015 -0500 amd: raminit sysinfo offset fix Change-Id: I6500fa7b005dc082c4c0b3382ee2c3a138d9ac31 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/early_variables.h | 16 ++++++++++++++++ src/cpu/amd/car/post_cache_as_ram.c | 12 ++---------- src/cpu/x86/car.c | 9 +++------ src/northbridge/amd/amdk8/f.h | 3 ++- src/northbridge/amd/amdk8/pre_f.h | 3 ++- src/northbridge/amd/amdk8/raminit.c | 3 --- src/northbridge/amd/amdk8/raminit_f.c | 3 --- src/northbridge/amd/amdk8/raminit_f_dqs.c | 8 ++++++++ 8 files changed, 33 insertions(+), 24 deletions(-) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index d9f1cd7..7ccb340 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -20,6 +20,8 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H +#include <stdlib.h> + #if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM) asm(".section .car.global_data,\"w\",@nobits"); asm(".previous"); @@ -43,6 +45,20 @@ void *car_sync_var_ptr(void *var); #define car_set_var(var, val) \ do { car_get_var(var) = (val); } while(0) +extern char _car_data_start[]; +extern char _car_data_end[]; + +static inline size_t car_data_size(void) +{ + size_t car_size = &_car_data_end[0] - &_car_data_start[0]; + return ALIGN(car_size, 64); +} + +static inline size_t car_object_offset(void *ptr) +{ + return (char *)ptr - &_car_data_start[0]; +} + #else #define CAR_GLOBAL static inline void *car_get_var_ptr(void *var) { return var; } diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 6c32090..96df3e7 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -3,6 +3,7 @@ */ #include <string.h> #include <arch/stages.h> +#include <arch/early_variables.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> @@ -22,18 +23,9 @@ #define print_car_debug(x) #endif -extern char _car_data_start[]; -extern char _car_data_end[]; - -static size_t car_data_size(void) -{ - size_t car_size = &_car_data_end[0] - &_car_data_start[0]; - return ALIGN(car_size, 64); -} - static size_t backup_size(void) { - size_t car_size = &_car_data_end[0] - &_car_data_start[0]; + size_t car_size = car_data_size(); return ALIGN(car_size + 1024, 1024); } diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index b0a86b1..3db6858 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -30,9 +30,6 @@ typedef void (* const car_migration_func_t)(void); extern car_migration_func_t _car_migrate_start; -extern char _car_data_start[]; -extern char _car_data_end[]; - /* * The car_migrated global variable determines if the cache-as-ram space has * been migrated to real RAM. It does this by assuming the following things: @@ -117,20 +114,20 @@ void *car_sync_var_ptr(void *var) static void do_car_migrate_variables(void) { void *migrated_base; - size_t car_data_size = &_car_data_end[0] - &_car_data_start[0]; + size_t car_size = car_data_size(); /* Check if already migrated. */ if (car_migrated) return; - migrated_base = cbmem_add(CBMEM_ID_CAR_GLOBALS, car_data_size); + migrated_base = cbmem_add(CBMEM_ID_CAR_GLOBALS, car_size); if (migrated_base == NULL) { printk(BIOS_ERR, "Could not migrate CAR data!\n"); return; } - memcpy(migrated_base, &_car_data_start[0], car_data_size); + memcpy(migrated_base, &_car_data_start[0], car_size); /* Mark that the data has been moved. */ car_migrated = ~0; diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index 4f958c5..af4658d 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -519,7 +519,8 @@ struct sys_info { } __attribute__((packed)); #ifdef __PRE_RAM__ -extern struct sys_info sysinfo_car; +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; #endif #include <reset.h> diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index 0e0f9f4..c413b5b 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -263,7 +263,8 @@ struct sys_info { } __attribute__((packed)); #ifdef __PRE_RAM__ -extern struct sys_info sysinfo_car; +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; #endif #endif /* AMDK8_PRE_F_H */ diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index c58abb1..fbcb887 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -17,9 +17,6 @@ #include "option_table.h" #endif -#include <arch/early_variables.h> -struct sys_info sysinfo_car CAR_GLOBAL; - void setup_resource_map(const unsigned int *register_values, int max) { int i; diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 1c1a6ea..a116d76 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -42,9 +42,6 @@ #endif -#include <arch/early_variables.h> -struct sys_info sysinfo_car CAR_GLOBAL; - #include "f_pci.c" diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index ee3b609..d13954a 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -2074,7 +2074,15 @@ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if(coreid) return; // only do it on core0 +#if 0 struct sys_info *sysinfox = (void *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); +#else + struct sys_info *sysinfox; + uintptr_t migrated_base = CONFIG_RAMTOP - car_data_size(); + + sysinfox = (void *)(migrated_base + car_object_offset(&sysinfo_car)); +#endif + wait_till_sysinfo_in_ram(); // use pci to get it if(sysinfox->mem_trained[nodeid] == 0x80) {

1 0

Patch set updated for coreboot: amd: raminit sysinfo offset fix
by Aaron Durbin 16 Jul '15

16 Jul '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10961 -gerrit commit 78a1172ef6157580967d2f16593a35dafabdbd05 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 16 16:07:02 2015 -0500 amd: raminit sysinfo offset fix Change-Id: I6500fa7b005dc082c4c0b3382ee2c3a138d9ac31 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/early_variables.h | 16 ++++++++++++++++ src/cpu/amd/car/post_cache_as_ram.c | 9 --------- src/cpu/x86/car.c | 9 +++------ src/northbridge/amd/amdk8/f.h | 3 ++- src/northbridge/amd/amdk8/pre_f.h | 3 ++- src/northbridge/amd/amdk8/raminit.c | 3 --- src/northbridge/amd/amdk8/raminit_f.c | 3 --- src/northbridge/amd/amdk8/raminit_f_dqs.c | 8 ++++++++ 8 files changed, 31 insertions(+), 23 deletions(-) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index d9f1cd7..7ccb340 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -20,6 +20,8 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H +#include <stdlib.h> + #if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM) asm(".section .car.global_data,\"w\",@nobits"); asm(".previous"); @@ -43,6 +45,20 @@ void *car_sync_var_ptr(void *var); #define car_set_var(var, val) \ do { car_get_var(var) = (val); } while(0) +extern char _car_data_start[]; +extern char _car_data_end[]; + +static inline size_t car_data_size(void) +{ + size_t car_size = &_car_data_end[0] - &_car_data_start[0]; + return ALIGN(car_size, 64); +} + +static inline size_t car_object_offset(void *ptr) +{ + return (char *)ptr - &_car_data_start[0]; +} + #else #define CAR_GLOBAL static inline void *car_get_var_ptr(void *var) { return var; } diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 6c32090..b41047d 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -22,15 +22,6 @@ #define print_car_debug(x) #endif -extern char _car_data_start[]; -extern char _car_data_end[]; - -static size_t car_data_size(void) -{ - size_t car_size = &_car_data_end[0] - &_car_data_start[0]; - return ALIGN(car_size, 64); -} - static size_t backup_size(void) { size_t car_size = &_car_data_end[0] - &_car_data_start[0]; diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index b0a86b1..3db6858 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -30,9 +30,6 @@ typedef void (* const car_migration_func_t)(void); extern car_migration_func_t _car_migrate_start; -extern char _car_data_start[]; -extern char _car_data_end[]; - /* * The car_migrated global variable determines if the cache-as-ram space has * been migrated to real RAM. It does this by assuming the following things: @@ -117,20 +114,20 @@ void *car_sync_var_ptr(void *var) static void do_car_migrate_variables(void) { void *migrated_base; - size_t car_data_size = &_car_data_end[0] - &_car_data_start[0]; + size_t car_size = car_data_size(); /* Check if already migrated. */ if (car_migrated) return; - migrated_base = cbmem_add(CBMEM_ID_CAR_GLOBALS, car_data_size); + migrated_base = cbmem_add(CBMEM_ID_CAR_GLOBALS, car_size); if (migrated_base == NULL) { printk(BIOS_ERR, "Could not migrate CAR data!\n"); return; } - memcpy(migrated_base, &_car_data_start[0], car_data_size); + memcpy(migrated_base, &_car_data_start[0], car_size); /* Mark that the data has been moved. */ car_migrated = ~0; diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index 4f958c5..af4658d 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -519,7 +519,8 @@ struct sys_info { } __attribute__((packed)); #ifdef __PRE_RAM__ -extern struct sys_info sysinfo_car; +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; #endif #include <reset.h> diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index 0e0f9f4..c413b5b 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -263,7 +263,8 @@ struct sys_info { } __attribute__((packed)); #ifdef __PRE_RAM__ -extern struct sys_info sysinfo_car; +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; #endif #endif /* AMDK8_PRE_F_H */ diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index c58abb1..fbcb887 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -17,9 +17,6 @@ #include "option_table.h" #endif -#include <arch/early_variables.h> -struct sys_info sysinfo_car CAR_GLOBAL; - void setup_resource_map(const unsigned int *register_values, int max) { int i; diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 1c1a6ea..a116d76 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -42,9 +42,6 @@ #endif -#include <arch/early_variables.h> -struct sys_info sysinfo_car CAR_GLOBAL; - #include "f_pci.c" diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index ee3b609..d13954a 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -2074,7 +2074,15 @@ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if(coreid) return; // only do it on core0 +#if 0 struct sys_info *sysinfox = (void *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); +#else + struct sys_info *sysinfox; + uintptr_t migrated_base = CONFIG_RAMTOP - car_data_size(); + + sysinfox = (void *)(migrated_base + car_object_offset(&sysinfo_car)); +#endif + wait_till_sysinfo_in_ram(); // use pci to get it if(sysinfox->mem_trained[nodeid] == 0x80) {

1 0

New patch to review for coreboot: amd: raminit sysinfo offset fix
by Aaron Durbin 16 Jul '15

16 Jul '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10961 -gerrit commit 6020e26cc26451e5bbf1505bd7a3014801565bb5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 16 16:07:02 2015 -0500 amd: raminit sysinfo offset fix Change-Id: I6500fa7b005dc082c4c0b3382ee2c3a138d9ac31 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/early_variables.h | 16 ++++++++++++++++ src/cpu/amd/car/post_cache_as_ram.c | 9 --------- src/cpu/amd/model_10xxx/init_cpus.c | 1 + src/cpu/x86/car.c | 9 +++------ src/northbridge/amd/amdk8/f.h | 3 ++- src/northbridge/amd/amdk8/pre_f.h | 3 ++- src/northbridge/amd/amdk8/raminit.c | 3 --- src/northbridge/amd/amdk8/raminit_f.c | 3 --- src/northbridge/amd/amdk8/raminit_f_dqs.c | 8 ++++++++ 9 files changed, 32 insertions(+), 23 deletions(-) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index d9f1cd7..7ccb340 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -20,6 +20,8 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H +#include <stdlib.h> + #if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM) asm(".section .car.global_data,\"w\",@nobits"); asm(".previous"); @@ -43,6 +45,20 @@ void *car_sync_var_ptr(void *var); #define car_set_var(var, val) \ do { car_get_var(var) = (val); } while(0) +extern char _car_data_start[]; +extern char _car_data_end[]; + +static inline size_t car_data_size(void) +{ + size_t car_size = &_car_data_end[0] - &_car_data_start[0]; + return ALIGN(car_size, 64); +} + +static inline size_t car_object_offset(void *ptr) +{ + return (char *)ptr - &_car_data_start[0]; +} + #else #define CAR_GLOBAL static inline void *car_get_var_ptr(void *var) { return var; } diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 6c32090..b41047d 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -22,15 +22,6 @@ #define print_car_debug(x) #endif -extern char _car_data_start[]; -extern char _car_data_end[]; - -static size_t car_data_size(void) -{ - size_t car_size = &_car_data_end[0] - &_car_data_start[0]; - return ALIGN(car_size, 64); -} - static size_t backup_size(void) { size_t car_size = &_car_data_end[0] - &_car_data_start[0]; diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 4c72848..ed190f2 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -17,6 +17,7 @@ * Foundation, Inc. */ +#include "global_binding.h" #include "cpu/amd/car/post_cache_as_ram.c" #include "defaults.h" #include <stdlib.h> diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index b0a86b1..3db6858 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -30,9 +30,6 @@ typedef void (* const car_migration_func_t)(void); extern car_migration_func_t _car_migrate_start; -extern char _car_data_start[]; -extern char _car_data_end[]; - /* * The car_migrated global variable determines if the cache-as-ram space has * been migrated to real RAM. It does this by assuming the following things: @@ -117,20 +114,20 @@ void *car_sync_var_ptr(void *var) static void do_car_migrate_variables(void) { void *migrated_base; - size_t car_data_size = &_car_data_end[0] - &_car_data_start[0]; + size_t car_size = car_data_size(); /* Check if already migrated. */ if (car_migrated) return; - migrated_base = cbmem_add(CBMEM_ID_CAR_GLOBALS, car_data_size); + migrated_base = cbmem_add(CBMEM_ID_CAR_GLOBALS, car_size); if (migrated_base == NULL) { printk(BIOS_ERR, "Could not migrate CAR data!\n"); return; } - memcpy(migrated_base, &_car_data_start[0], car_data_size); + memcpy(migrated_base, &_car_data_start[0], car_size); /* Mark that the data has been moved. */ car_migrated = ~0; diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index 4f958c5..af4658d 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -519,7 +519,8 @@ struct sys_info { } __attribute__((packed)); #ifdef __PRE_RAM__ -extern struct sys_info sysinfo_car; +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; #endif #include <reset.h> diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index 0e0f9f4..c413b5b 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -263,7 +263,8 @@ struct sys_info { } __attribute__((packed)); #ifdef __PRE_RAM__ -extern struct sys_info sysinfo_car; +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; #endif #endif /* AMDK8_PRE_F_H */ diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index c58abb1..fbcb887 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -17,9 +17,6 @@ #include "option_table.h" #endif -#include <arch/early_variables.h> -struct sys_info sysinfo_car CAR_GLOBAL; - void setup_resource_map(const unsigned int *register_values, int max) { int i; diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 1c1a6ea..a116d76 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -42,9 +42,6 @@ #endif -#include <arch/early_variables.h> -struct sys_info sysinfo_car CAR_GLOBAL; - #include "f_pci.c" diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index ee3b609..d13954a 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -2074,7 +2074,15 @@ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if(coreid) return; // only do it on core0 +#if 0 struct sys_info *sysinfox = (void *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); +#else + struct sys_info *sysinfox; + uintptr_t migrated_base = CONFIG_RAMTOP - car_data_size(); + + sysinfox = (void *)(migrated_base + car_object_offset(&sysinfo_car)); +#endif + wait_till_sysinfo_in_ram(); // use pci to get it if(sysinfox->mem_trained[nodeid] == 0x80) {

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Patch merged into coreboot/master: libpayload: usb: dwc2: support split transaction
by gerrit＠coreboot.org 16 Jul '15

16 Jul '15

the following patch was just integrated into master: commit ebd3da7dba7d72b0d7a4fa50ffbad61259562447 Author: Yunzhi Li <lyz(a)rock-chips.com> Date: Thu Jul 2 15:28:11 2015 +0800 libpayload: usb: dwc2: support split transaction With split transaction, dwc2 host controller can handle full- and low-speed devices on hub in high-speed mode. This commit adds support for split control and interrupt transfers BUG=None TEST=Connect usb keyboard through hub, usb keyboard can work BRANCH=None Change-Id: If7a00db21c8ad4c635f39581382b877603075d1a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4fb514b7f7f7e414fa94bfce05420957b1c57019 Original-Change-Id: I07e64064c6182d33905ae4efb13712645de7cf93 Original-Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283282 Original-Tested-by: Lin Huang <hl(a)rock-chips.com> Original-Commit-Queue: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/10956 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10956 for details. -gerrit

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Patch merged into coreboot/master: t210: new sdram_lp0_save_params() function
by gerrit＠coreboot.org 16 Jul '15

16 Jul '15

the following patch was just integrated into master: commit ae3d71a4d10b28bb5da1b3399358988acdcf1ace Author: Yen Lin <yelin(a)nvidia.com> Date: Mon Jun 1 15:32:09 2015 -0700 t210: new sdram_lp0_save_params() function New sdram_lp0_save_params() function for T210. Due to its size, move the function from romstage to ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Smaug; and check scratch registers Change-Id: I420ac4c15262f2c6307bcd84beb6c5da0310c7c0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 38860895938c40062a9f860f75e31a539f15992b Original-Change-Id: Iaa478969458946faedd295578fe7d72b5a32e701 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277022 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/10952 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10952 for details. -gerrit

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coreboot-gerrit July 2015