coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

1 participants
1048 discussions

New patch to review for coreboot: smaug: correct odmdata in odmdata.cfg
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10954 -gerrit commit dea860e55b92e1810906ecd63bb9c35ece19d9d8 Author: Yen Lin <yelin(a)nvidia.com> Date: Thu Jun 11 12:01:52 2015 -0700 smaug: correct odmdata in odmdata.cfg So odmdata has the correct UART port of 0. BUG=chrome-os-partner:40741 BRANCH=None TEST=build Smaug ok; and check scratch20 register Change-Id: I59154daa5b5627d3b594ff9505e4f02de0d4d7aa Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 814cd164ab9ed9bf2e072f3728e89ea8d7cf0343 Original-Change-Id: I2252b728775cf2550d666ead0085c0ab3b72e40b Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277024 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/smaug/bct/odmdata.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/smaug/bct/odmdata.cfg b/src/mainboard/google/smaug/bct/odmdata.cfg index 45648af..c5938f3 100644 --- a/src/mainboard/google/smaug/bct/odmdata.cfg +++ b/src/mainboard/google/smaug/bct/odmdata.cfg @@ -1 +1 @@ -OdmData = 0x00294000; +OdmData = 0x00284000;

1 0

New patch to review for coreboot: t210: correct odmdata location in bct
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10953 -gerrit commit 0db9d758626b1aab5e56f56d72dec51144eec842 Author: Yen Lin <yelin(a)nvidia.com> Date: Fri May 29 16:47:30 2015 -0700 t210: correct odmdata location in bct Correct the odmdata location in bct for T210. BUG=chrome-os-partner:40741 BRANCH=None TEST=build ok on Smaug Change-Id: I2258556ec5cf5d25782e60e084f3d5657b441c86 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 288a5d71c35fbea1812ad0c91f2c6c5f5a022363 Original-Change-Id: I0efb033442c2aafc7f44898c16b3e91946e092d5 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277023 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/bootblock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index 2e26fbf..a6aa584 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -30,8 +30,8 @@ #include <soc/power.h> #include <timestamp.h> -#define BCT_OFFSET_IN_BIT 0x50 -#define ODMDATA_OFFSET_IN_BCT 0x6A8 +#define BCT_OFFSET_IN_BIT 0x4c +#define ODMDATA_OFFSET_IN_BCT 0x508 #define TEGRA_SRAM_MAX (TEGRA_SRAM_BASE + TEGRA_SRAM_SIZE) static void save_odmdata(void)

1 0

New patch to review for coreboot: t210: new sdram_lp0_save_params() function
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10952 -gerrit commit 01a7a222aac60257c0935783d7ae41b653913002 Author: Yen Lin <yelin(a)nvidia.com> Date: Mon Jun 1 15:32:09 2015 -0700 t210: new sdram_lp0_save_params() function New sdram_lp0_save_params() function for T210. Due to its size, move the function from romstage to ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Smaug; and check scratch registers Change-Id: I420ac4c15262f2c6307bcd84beb6c5da0310c7c0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 38860895938c40062a9f860f75e31a539f15992b Original-Change-Id: Iaa478969458946faedd295578fe7d72b5a32e701 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277022 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/Makefile.inc | 3 +- src/soc/nvidia/tegra210/sdram.c | 3 - src/soc/nvidia/tegra210/sdram_lp0.c | 1499 ++++++++++++++++++++++------------ src/soc/nvidia/tegra210/soc.c | 6 + 4 files changed, 965 insertions(+), 546 deletions(-) diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index 8d7e1fc..2d5bf58 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -54,9 +54,7 @@ romstage-y += power.c romstage-y += ram_code.c ifneq ($(CONFIG_BOOTROM_SDRAM_INIT),y) romstage-y += sdram.c - ifeq ($(CONFIG_LP0_SUPPORT),y) romstage-y += sdram_lp0.c - endif endif romstage-y += ../tegra/gpio.c romstage-y += ../tegra/i2c.c @@ -78,6 +76,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += ./jdi_25x18_display/panel-jdi-lpm102 ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += dp.c ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += sor.c +ramstage-y += sdram_lp0.c ramstage-y += soc.c ramstage-y += spi.c ramstage-y += i2c.c diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c index 786caa4..53a2c49 100644 --- a/src/soc/nvidia/tegra210/sdram.c +++ b/src/soc/nvidia/tegra210/sdram.c @@ -1076,7 +1076,4 @@ void sdram_init(const struct sdram_params *param) sdram_set_refresh(param, emc); sdram_enable_arbiter(param); sdram_lock_carveouts(param, mc); -#if defined(CONFIG_LP0) - sdram_lp0_save_params(param); -#endif } diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c index c63b823..f3f2af3 100644 --- a/src/soc/nvidia/tegra210/sdram_lp0.c +++ b/src/soc/nvidia/tegra210/sdram_lp0.c @@ -18,30 +18,18 @@ #include <arch/cache.h> #include <console/console.h> #include <soc/addressmap.h> -#include <soc/clk_rst.h> #include <soc/pmc.h> #include <soc/sdram.h> #include <stdlib.h> /* - * This function reads SDRAM parameters (and a few CLK_RST regsiter values) from - * the common BCT format and writes them into PMC scratch registers (where the - * BootROM expects them on LP0 resume). Since those store the same values in a - * different format, we follow a "translation table" taken from Nvidia's U-Boot - * implementation to shift bits into the right position. - * - * Contrary to U-Boot, we transform the same macros directly into hardcoded - * assignments (without any pesky function calls or volatile qualifiers) to give - * the compiler as much room for optimization as possible. For that reason, we - * also intentionally avoid <arch/io.h> read/write macros, under the assumption - * that PMC scratch register accesses should not have side effects and can be - * arbitrarily reordered. For the few accesses that do have side-effects, the - * code must contain explicit memory barriers. + * This function reads SDRAM parameters from the common BCT format and + * writes them into PMC scratch registers (where the BootROM expects them + * on LP0 resume). */ void sdram_lp0_save_params(const struct sdram_params *sdram) { struct tegra_pmc_regs * pmc = (void *)TEGRA_PMC_BASE; - struct clk_rst_ctlr * clk_rst = (void *)TEGRA_CLK_RST_BASE; #define pack(src, src_bits, dst, dst_bits) { \ _Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \ @@ -56,448 +44,714 @@ void sdram_lp0_save_params(const struct sdram_params *sdram) #define s(param, src_bits, pmcreg, dst_bits) \ pack(sdram->param, src_bits, pmc->pmcreg, dst_bits) -#define m(clkreg, src_bits, pmcreg, dst_bits) \ - pack(clk_rst->clkreg, src_bits, pmc->pmcreg, dst_bits) - #define c(value, pmcreg, dst_bits) \ pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits) +/* 32 bits version of s macro */ +#define s32(param, pmcreg) pmc->pmcreg = sdram->param + +/* 32 bits version c macro */ +#define c32(value, pmcreg) pmc->pmcreg = value + s(EmcClockSource, 7:0, scratch6, 15:8); - s(EmcClockSource, 31:29, scratch6, 18:16); - s(EmcClockSource, 26:26, scratch6, 19:19); - s(EmcOdtWrite, 5:0, scratch6, 25:20); - s(EmcOdtWrite, 11:8, scratch6, 29:26); - s(EmcOdtWrite, 30:30, scratch6, 30:30); - s(EmcOdtWrite, 31:31, scratch6, 31:31); - s(EmcXm2DqPadCtrl2, 18:16, scratch7, 22:20); - s(EmcXm2DqPadCtrl2, 22:20, scratch7, 25:23); - s(EmcXm2DqPadCtrl2, 26:24, scratch7, 28:26); - s(EmcXm2DqPadCtrl2, 30:28, scratch7, 31:29); - s(EmcXm2DqPadCtrl3, 18:16, scratch8, 22:20); - s(EmcXm2DqPadCtrl3, 22:20, scratch8, 25:23); - s(EmcXm2DqPadCtrl3, 26:24, scratch8, 28:26); - s(EmcXm2DqPadCtrl3, 30:28, scratch8, 31:29); - s(EmcTxsrDll, 11:0, scratch9, 31:20); - c(0, scratch10, 31:0); - s(EmcDsrVttgenDrv, 5:0, scratch10, 25:20); - s(EmcDsrVttgenDrv, 18:16, scratch10, 28:26); - s(EmcDsrVttgenDrv, 26:24, scratch10, 31:29); - s(EmcFbioSpare, 31:24, scratch11, 7:0); - s(EmcFbioSpare, 23:16, scratch11, 15:8); - s(EmcFbioSpare, 15:8, scratch11, 23:16); - s(EmcFbioSpare, 7:0, scratch11, 31:24); - s(EmcCfgRsv, 31:0, scratch12, 31:0); - s(EmcCdbCntl2, 31:0, scratch13, 31:0); - s(McEmemArbDaTurns, 31:0, scratch14, 31:0); - s(EmcCfgDigDll, 0:0, scratch17, 0:0); - s(EmcCfgDigDll, 25:2, scratch17, 24:1); - s(EmcCfgDigDll, 31:27, scratch17, 29:25); - s(EmcCdbCntl1, 29:0, scratch18, 29:0); - s(McEmemArbMisc0, 14:0, scratch19, 14:0); - s(McEmemArbMisc0, 30:16, scratch19, 29:15); - s(EmcXm2DqsPadCtrl, 4:0, scratch22, 4:0); - s(EmcXm2DqsPadCtrl, 12:8, scratch22, 9:5); - s(EmcXm2DqsPadCtrl, 31:14, scratch22, 27:10); - s(EmcRrd, 3:0, scratch22, 31:28); - s(EmcXm2DqPadCtrl, 31:4, scratch23, 27:0); - s(EmcRext, 3:0, scratch23, 31:28); - s(EmcXm2CompPadCtrl, 16:0, scratch24, 16:0); - s(EmcXm2CompPadCtrl, 24:20, scratch24, 21:17); - s(EmcXm2CompPadCtrl, 27:27, scratch24, 22:22); - s(EmcXm2CompPadCtrl, 31:28, scratch24, 26:23); - s(EmcR2w, 4:0, scratch24, 31:27); - s(EmcCfg, 9:1, scratch25, 8:0); - s(EmcCfg, 26:16, scratch25, 19:9); - s(EmcCfg, 31:28, scratch25, 23:20); - s(EmcXm2VttGenPadCtrl, 0:0, scratch25, 24:24); - s(EmcXm2VttGenPadCtrl, 2:2, scratch25, 25:25); - s(EmcXm2VttGenPadCtrl, 18:16, scratch25, 28:26); - s(EmcXm2VttGenPadCtrl, 26:24, scratch25, 31:29); - s(EmcZcalInterval, 23:10, scratch26, 13:0); - s(EmcZcalInterval, 9:0, scratch26, 23:14); - s(EmcSelDpdCtrl, 5:2, scratch26, 27:24); - s(EmcSelDpdCtrl, 8:8, scratch26, 28:28); - s(EmcSelDpdCtrl, 18:16, scratch26, 31:29); - s(EmcXm2VttGenPadCtrl3, 22:0, scratch27, 22:0); - s(EmcXm2VttGenPadCtrl3, 24:24, scratch27, 23:23); - s(EmcSwizzleRank0ByteCfg, 1:0, scratch27, 25:24); - s(EmcSwizzleRank0ByteCfg, 5:4, scratch27, 27:26); - s(EmcSwizzleRank0ByteCfg, 9:8, scratch27, 29:28); - s(EmcSwizzleRank0ByteCfg, 13:12, scratch27, 31:30); - s(EmcXm2ClkPadCtrl2, 5:0, scratch28, 5:0); - s(EmcXm2ClkPadCtrl2, 13:8, scratch28, 11:6); - s(EmcXm2ClkPadCtrl2, 20:16, scratch28, 16:12); - s(EmcXm2ClkPadCtrl2, 23:23, scratch28, 17:17); - s(EmcXm2ClkPadCtrl2, 28:24, scratch28, 22:18); - s(EmcXm2ClkPadCtrl2, 31:31, scratch28, 23:23); - s(EmcSwizzleRank1ByteCfg, 1:0, scratch28, 25:24); - s(EmcSwizzleRank1ByteCfg, 5:4, scratch28, 27:26); - s(EmcSwizzleRank1ByteCfg, 9:8, scratch28, 29:28); - s(EmcSwizzleRank1ByteCfg, 13:12, scratch28, 31:30); - s(McEmemArbDaCovers, 23:0, scratch29, 23:0); - s(McEmemArbRsv, 7:0, scratch29, 31:24); - s(EmcAutoCalConfig, 4:0, scratch30, 4:0); - s(EmcAutoCalConfig, 12:8, scratch30, 9:5); - s(EmcAutoCalConfig, 18:16, scratch30, 12:10); - s(EmcAutoCalConfig, 25:20, scratch30, 18:13); - s(EmcAutoCalConfig, 31:28, scratch30, 22:19); - s(EmcRfc, 8:0, scratch30, 31:23); - s(EmcXm2DqsPadCtrl2, 21:0, scratch31, 21:0); - s(EmcXm2DqsPadCtrl2, 24:24, scratch31, 22:22); - s(EmcAr2Pden, 8:0, scratch31, 31:23); - s(EmcXm2ClkPadCtrl, 0:0, scratch32, 0:0); - s(EmcXm2ClkPadCtrl, 4:2, scratch32, 3:1); - s(EmcXm2ClkPadCtrl, 7:7, scratch32, 4:4); - s(EmcXm2ClkPadCtrl, 31:14, scratch32, 22:5); - s(EmcRfcSlr, 8:0, scratch32, 31:23); - s(EmcXm2DqsPadCtrl3, 0:0, scratch33, 0:0); - s(EmcXm2DqsPadCtrl3, 5:5, scratch33, 1:1); - s(EmcXm2DqsPadCtrl3, 12:8, scratch33, 6:2); - s(EmcXm2DqsPadCtrl3, 18:14, scratch33, 11:7); - s(EmcXm2DqsPadCtrl3, 24:20, scratch33, 16:12); - s(EmcXm2DqsPadCtrl3, 30:26, scratch33, 21:17); - s(EmcTxsr, 9:0, scratch33, 31:22); - s(McEmemArbCfg, 8:0, scratch40, 8:0); - s(McEmemArbCfg, 20:16, scratch40, 13:9); - s(McEmemArbCfg, 27:24, scratch40, 17:14); - s(McEmemArbCfg, 31:28, scratch40, 21:18); - s(EmcMc2EmcQ, 2:0, scratch40, 24:22); - s(EmcMc2EmcQ, 10:8, scratch40, 27:25); - s(EmcMc2EmcQ, 27:24, scratch40, 31:28); - s(EmcAutoCalInterval, 20:0, scratch42, 20:0); - s(McEmemArbOutstandingReq, 8:0, scratch42, 29:21); - s(McEmemArbOutstandingReq, 31:30, scratch42, 31:30); - s(EmcMrsWaitCnt2, 9:0, scratch44, 9:0); - s(EmcMrsWaitCnt2, 25:16, scratch44, 19:10); - s(EmcTxdsrvttgen, 11:0, scratch44, 31:20); - s(EmcMrsWaitCnt, 9:0, scratch45, 9:0); - s(EmcMrsWaitCnt, 25:16, scratch45, 19:10); - s(EmcCfgPipe, 1:0, scratch45, 21:20); - s(EmcCfgPipe, 9:4, scratch45, 27:22); - s(EmcCfgPipe, 15:12, scratch45, 31:28); - s(EmcXm2DqsPadCtrl4, 22:18, scratch46, 4:0); - s(EmcXm2DqsPadCtrl4, 16:12, scratch46, 9:5); - s(EmcXm2DqsPadCtrl4, 10:6, scratch46, 14:10); - s(EmcXm2DqsPadCtrl4, 4:0, scratch46, 19:15); - s(EmcZcalWaitCnt, 9:0, scratch46, 29:20); - s(EmcXm2DqsPadCtrl5, 22:18, scratch47, 4:0); - s(EmcXm2DqsPadCtrl5, 16:12, scratch47, 9:5); - s(EmcXm2DqsPadCtrl5, 10:6, scratch47, 14:10); - s(EmcXm2DqsPadCtrl5, 4:0, scratch47, 19:15); - s(EmcXm2VttGenPadCtrl2, 5:0, scratch47, 25:20); - s(EmcXm2VttGenPadCtrl2, 31:28, scratch47, 29:26); - s(EmcXm2DqsPadCtrl6, 12:8, scratch48, 4:0); - s(EmcXm2DqsPadCtrl6, 18:14, scratch48, 9:5); - s(EmcXm2DqsPadCtrl6, 24:20, scratch48, 14:10); - s(EmcXm2DqsPadCtrl6, 30:26, scratch48, 19:15); - s(EmcAutoCalConfig3, 4:0, scratch48, 24:20); - s(EmcAutoCalConfig3, 12:8, scratch48, 29:25); - s(EmcFbioCfg5, 1:0, scratch48, 31:30); - s(EmcDllXformQUse8, 4:0, scratch50, 4:0); - s(EmcDllXformQUse8, 22:8, scratch50, 19:5); - s(McEmemArbRing1Throttle, 4:0, scratch50, 24:20); - s(McEmemArbRing1Throttle, 20:16, scratch50, 29:25); - s(EmcFbioCfg5, 3:2, scratch50, 31:30); - s(EmcDllXformQUse9, 4:0, scratch51, 4:0); - s(EmcDllXformQUse9, 22:8, scratch51, 19:5); - s(EmcCttTermCtrl, 2:0, scratch51, 22:20); - s(EmcCttTermCtrl, 12:8, scratch51, 27:23); - s(EmcCttTermCtrl, 31:31, scratch51, 28:28); - s(EmcFbioCfg6, 2:0, scratch51, 31:29); - s(EmcDllXformQUse10, 4:0, scratch56, 4:0); - s(EmcDllXformQUse10, 22:8, scratch56, 19:5); - s(EmcXm2CmdPadCtrl, 10:3, scratch56, 27:20); - s(EmcXm2CmdPadCtrl, 28:28, scratch56, 28:28); - s(EmcPutermAdj, 1:0, scratch56, 30:29); - s(EmcPutermAdj, 7:7, scratch56, 31:31); - s(EmcDllXformQUse11, 4:0, scratch57, 4:0); - s(EmcDllXformQUse11, 22:8, scratch57, 19:5); - s(EmcWdv, 3:0, scratch57, 31:28); - s(EmcDllXformQUse12, 4:0, scratch58, 4:0); - s(EmcDllXformQUse12, 22:8, scratch58, 19:5); - s(EmcBurstRefreshNum, 3:0, scratch58, 31:28); - s(EmcDllXformQUse13, 4:0, scratch59, 4:0); - s(EmcDllXformQUse13, 22:8, scratch59, 19:5); - s(EmcWext, 3:0, scratch59, 31:28); - s(EmcDllXformQUse14, 4:0, scratch60, 4:0); - s(EmcDllXformQUse14, 22:8, scratch60, 19:5); - s(EmcClkenOverride, 3:1, scratch60, 30:28); - s(EmcClkenOverride, 6:6, scratch60, 31:31); - s(EmcDllXformQUse15, 4:0, scratch61, 4:0); - s(EmcDllXformQUse15, 22:8, scratch61, 19:5); - s(EmcR2r, 3:0, scratch61, 31:28); - s(EmcDllXformDq4, 4:0, scratch62, 4:0); - s(EmcDllXformDq4, 22:8, scratch62, 19:5); - s(EmcRc, 6:0, scratch62, 26:20); - s(EmcW2r, 4:0, scratch62, 31:27); - s(EmcDllXformDq5, 4:0, scratch63, 4:0); - s(EmcDllXformDq5, 22:8, scratch63, 19:5); - s(EmcTfaw, 6:0, scratch63, 26:20); - s(EmcR2p, 4:0, scratch63, 31:27); - s(EmcDllXformDq6, 4:0, scratch64, 4:0); - s(EmcDllXformDq6, 22:8, scratch64, 19:5); - s(EmcDliTrimTxDqs0, 6:0, scratch64, 26:20); - s(EmcQSafe, 4:0, scratch64, 31:27); - s(EmcDllXformDq7, 4:0, scratch65, 4:0); - s(EmcDllXformDq7, 22:8, scratch65, 19:5); - s(EmcDliTrimTxDqs1, 6:0, scratch65, 26:20); - s(EmcTClkStable, 4:0, scratch65, 31:27); - s(EmcAutoCalConfig2, 4:0, scratch66, 4:0); - s(EmcAutoCalConfig2, 12:8, scratch66, 9:5); - s(EmcAutoCalConfig2, 20:16, scratch66, 14:10); - s(EmcAutoCalConfig2, 28:24, scratch66, 19:15); - s(EmcDliTrimTxDqs2, 6:0, scratch66, 26:20); - s(EmcTClkStop, 4:0, scratch66, 31:27); - s(McEmemArbMisc1, 1:0, scratch67, 1:0); - s(McEmemArbMisc1, 12:4, scratch67, 10:2); - s(McEmemArbMisc1, 25:21, scratch67, 15:11); - s(McEmemArbMisc1, 31:28, scratch67, 19:16); - s(EmcDliTrimTxDqs3, 6:0, scratch67, 26:20); - s(EmcEInputDuration, 4:0, scratch67, 31:27); - s(EmcZcalMrwCmd, 7:0, scratch68, 7:0); - s(EmcZcalMrwCmd, 23:16, scratch68, 15:8); - s(EmcZcalMrwCmd, 31:30, scratch68, 17:16); - s(EmcTRefBw, 13:0, scratch68, 31:18); - s(EmcXm2CmdPadCtrl2, 31:14, scratch69, 17:0); - s(EmcDliTrimTxDqs4, 6:0, scratch69, 24:18); - s(EmcDliTrimTxDqs5, 6:0, scratch69, 31:25); - s(EmcXm2CmdPadCtrl3, 31:14, scratch70, 17:0); - s(EmcDliTrimTxDqs6, 6:0, scratch70, 24:18); - s(EmcDliTrimTxDqs7, 6:0, scratch70, 31:25); - s(EmcXm2CmdPadCtrl5, 2:0, scratch71, 2:0); - s(EmcXm2CmdPadCtrl5, 6:4, scratch71, 5:3); - s(EmcXm2CmdPadCtrl5, 10:8, scratch71, 8:6); - s(EmcXm2CmdPadCtrl5, 14:12, scratch71, 11:9); - s(EmcXm2CmdPadCtrl5, 18:16, scratch71, 14:12); - s(EmcXm2CmdPadCtrl5, 22:20, scratch71, 17:15); - s(EmcDliTrimTxDqs8, 6:0, scratch71, 24:18); - s(EmcDliTrimTxDqs9, 6:0, scratch71, 31:25); - s(EmcCdbCntl3, 17:0, scratch72, 17:0); - s(EmcDliTrimTxDqs10, 6:0, scratch72, 24:18); - s(EmcDliTrimTxDqs11, 6:0, scratch72, 31:25); - s(EmcSwizzleRank0Byte0, 2:0, scratch73, 2:0); - s(EmcSwizzleRank0Byte0, 6:4, scratch73, 5:3); - s(EmcSwizzleRank0Byte0, 10:8, scratch73, 8:6); - s(EmcSwizzleRank0Byte0, 14:12, scratch73, 11:9); - s(EmcSwizzleRank0Byte0, 18:16, scratch73, 14:12); - s(EmcSwizzleRank0Byte0, 22:20, scratch73, 17:15); - s(EmcDliTrimTxDqs12, 6:0, scratch73, 24:18); - s(EmcDliTrimTxDqs13, 6:0, scratch73, 31:25); - s(EmcSwizzleRank0Byte1, 2:0, scratch74, 2:0); - s(EmcSwizzleRank0Byte1, 6:4, scratch74, 5:3); - s(EmcSwizzleRank0Byte1, 10:8, scratch74, 8:6); - s(EmcSwizzleRank0Byte1, 14:12, scratch74, 11:9); - s(EmcSwizzleRank0Byte1, 18:16, scratch74, 14:12); - s(EmcSwizzleRank0Byte1, 22:20, scratch74, 17:15); - s(EmcDliTrimTxDqs14, 6:0, scratch74, 24:18); - s(EmcDliTrimTxDqs15, 6:0, scratch74, 31:25); - s(EmcSwizzleRank0Byte2, 2:0, scratch75, 2:0); - s(EmcSwizzleRank0Byte2, 6:4, scratch75, 5:3); - s(EmcSwizzleRank0Byte2, 10:8, scratch75, 8:6); - s(EmcSwizzleRank0Byte2, 14:12, scratch75, 11:9); - s(EmcSwizzleRank0Byte2, 18:16, scratch75, 14:12); - s(EmcSwizzleRank0Byte2, 22:20, scratch75, 17:15); - s(McEmemArbTimingRp, 6:0, scratch75, 24:18); - s(McEmemArbTimingRc, 6:0, scratch75, 31:25); - s(EmcSwizzleRank0Byte3, 2:0, scratch76, 2:0); - s(EmcSwizzleRank0Byte3, 6:4, scratch76, 5:3); - s(EmcSwizzleRank0Byte3, 10:8, scratch76, 8:6); - s(EmcSwizzleRank0Byte3, 14:12, scratch76, 11:9); - s(EmcSwizzleRank0Byte3, 18:16, scratch76, 14:12); - s(EmcSwizzleRank0Byte3, 22:20, scratch76, 17:15); - s(McEmemArbTimingFaw, 6:0, scratch76, 24:18); - s(McEmemArbTimingWap2Pre, 6:0, scratch76, 31:25); - s(EmcSwizzleRank1Byte0, 2:0, scratch77, 2:0); - s(EmcSwizzleRank1Byte0, 6:4, scratch77, 5:3); - s(EmcSwizzleRank1Byte0, 10:8, scratch77, 8:6); - s(EmcSwizzleRank1Byte0, 14:12, scratch77, 11:9); - s(EmcSwizzleRank1Byte0, 18:16, scratch77, 14:12); - s(EmcSwizzleRank1Byte0, 22:20, scratch77, 17:15); - s(EmcRas, 5:0, scratch77, 23:18); - s(EmcRp, 5:0, scratch77, 29:24); - s(EmcCfg2, 9:8, scratch77, 31:30); - s(EmcSwizzleRank1Byte1, 2:0, scratch78, 2:0); - s(EmcSwizzleRank1Byte1, 6:4, scratch78, 5:3); - s(EmcSwizzleRank1Byte1, 10:8, scratch78, 8:6); - s(EmcSwizzleRank1Byte1, 14:12, scratch78, 11:9); - s(EmcSwizzleRank1Byte1, 18:16, scratch78, 14:12); - s(EmcSwizzleRank1Byte1, 22:20, scratch78, 17:15); - s(EmcW2p, 5:0, scratch78, 23:18); - s(EmcRdRcd, 5:0, scratch78, 29:24); - s(EmcCfg2, 27:26, scratch78, 31:30); - s(EmcSwizzleRank1Byte2, 2:0, scratch79, 2:0); - s(EmcSwizzleRank1Byte2, 6:4, scratch79, 5:3); - s(EmcSwizzleRank1Byte2, 10:8, scratch79, 8:6); - s(EmcSwizzleRank1Byte2, 14:12, scratch79, 11:9); - s(EmcSwizzleRank1Byte2, 18:16, scratch79, 14:12); - s(EmcSwizzleRank1Byte2, 22:20, scratch79, 17:15); - s(EmcWrRcd, 5:0, scratch79, 23:18); - s(EmcQUse, 5:0, scratch79, 29:24); - s(EmcFbioCfg5, 4:4, scratch79, 31:31); - s(EmcSwizzleRank1Byte3, 2:0, scratch80, 2:0); - s(EmcSwizzleRank1Byte3, 6:4, scratch80, 5:3); - s(EmcSwizzleRank1Byte3, 10:8, scratch80, 8:6); - s(EmcSwizzleRank1Byte3, 14:12, scratch80, 11:9); - s(EmcSwizzleRank1Byte3, 18:16, scratch80, 14:12); - s(EmcSwizzleRank1Byte3, 22:20, scratch80, 17:15); - s(EmcQRst, 5:0, scratch80, 23:18); - s(EmcRdv, 5:0, scratch80, 29:24); - s(EmcFbioCfg5, 6:5, scratch80, 31:30); - s(EmcDynSelfRefControl, 15:0, scratch81, 15:0); - s(EmcDynSelfRefControl, 31:31, scratch81, 16:16); - s(EmcPdEx2Wr, 5:0, scratch81, 22:17); - s(EmcPdEx2Rd, 5:0, scratch81, 28:23); - s(EmcRefresh, 5:0, scratch82, 5:0); - s(EmcRefresh, 15:6, scratch82, 15:6); - s(EmcCmdQ, 4:0, scratch82, 20:16); - s(EmcCmdQ, 10:8, scratch82, 23:21); - s(EmcCmdQ, 14:12, scratch82, 26:24); - s(EmcCmdQ, 28:24, scratch82, 31:27); - s(EmcAcpdControl, 15:0, scratch83, 15:0); - s(EmcCfgDigDllPeriod, 15:0, scratch83, 31:16); - s(EmcDllXformDqs0, 4:0, scratch84, 4:0); - s(EmcDllXformDqs0, 22:12, scratch84, 15:5); - s(EmcDllXformDqs1, 4:0, scratch84, 20:16); - s(EmcDllXformDqs1, 22:12, scratch84, 31:21); - s(EmcDllXformDqs2, 4:0, scratch85, 4:0); - s(EmcDllXformDqs2, 22:12, scratch85, 15:5); - s(EmcDllXformDqs3, 4:0, scratch85, 20:16); - s(EmcDllXformDqs3, 22:12, scratch85, 31:21); - s(EmcDllXformDqs4, 4:0, scratch86, 4:0); - s(EmcDllXformDqs4, 22:12, scratch86, 15:5); - s(EmcDllXformDqs5, 4:0, scratch86, 20:16); - s(EmcDllXformDqs5, 22:12, scratch86, 31:21); - s(EmcDllXformDqs6, 4:0, scratch87, 4:0); - s(EmcDllXformDqs6, 22:12, scratch87, 15:5); - s(EmcDllXformDqs7, 4:0, scratch87, 20:16); - s(EmcDllXformDqs7, 22:12, scratch87, 31:21); - s(EmcDllXformDqs8, 4:0, scratch88, 4:0); - s(EmcDllXformDqs8, 22:12, scratch88, 15:5); - s(EmcDllXformDqs9, 4:0, scratch88, 20:16); - s(EmcDllXformDqs9, 22:12, scratch88, 31:21); - s(EmcDllXformDqs10, 4:0, scratch89, 4:0); - s(EmcDllXformDqs10, 22:12, scratch89, 15:5); - s(EmcDllXformDqs11, 4:0, scratch89, 20:16); - s(EmcDllXformDqs11, 22:12, scratch89, 31:21); - s(EmcDllXformDqs12, 4:0, scratch90, 4:0); - s(EmcDllXformDqs12, 22:12, scratch90, 15:5); - s(EmcDllXformDqs13, 4:0, scratch90, 20:16); - s(EmcDllXformDqs13, 22:12, scratch90, 31:21); - s(EmcDllXformDqs14, 4:0, scratch91, 4:0); - s(EmcDllXformDqs14, 22:12, scratch91, 15:5); - s(EmcDllXformDqs15, 4:0, scratch91, 20:16); - s(EmcDllXformDqs15, 22:12, scratch91, 31:21); - s(EmcDllXformQUse0, 4:0, scratch92, 4:0); - s(EmcDllXformQUse0, 22:12, scratch92, 15:5); - s(EmcDllXformQUse1, 4:0, scratch92, 20:16); - s(EmcDllXformQUse1, 22:12, scratch92, 31:21); - s(EmcDllXformQUse2, 4:0, scratch93, 4:0); - s(EmcDllXformQUse2, 22:12, scratch93, 15:5); - s(EmcDllXformQUse3, 4:0, scratch93, 20:16); - s(EmcDllXformQUse3, 22:12, scratch93, 31:21); - s(EmcDllXformQUse4, 4:0, scratch94, 4:0); - s(EmcDllXformQUse4, 22:12, scratch94, 15:5); - s(EmcDllXformQUse5, 4:0, scratch94, 20:16); - s(EmcDllXformQUse5, 22:12, scratch94, 31:21); - s(EmcDllXformQUse6, 4:0, scratch95, 4:0); - s(EmcDllXformQUse6, 22:12, scratch95, 15:5); - s(EmcDllXformQUse7, 4:0, scratch95, 20:16); - s(EmcDllXformQUse7, 22:12, scratch95, 31:21); - s(EmcDllXformDq0, 4:0, scratch96, 4:0); - s(EmcDllXformDq0, 22:12, scratch96, 15:5); - s(EmcDllXformDq1, 4:0, scratch96, 20:16); - s(EmcDllXformDq1, 22:12, scratch96, 31:21); - s(EmcDllXformDq2, 4:0, scratch97, 4:0); - s(EmcDllXformDq2, 22:12, scratch97, 15:5); - s(EmcDllXformDq3, 4:0, scratch97, 20:16); - s(EmcDllXformDq3, 22:12, scratch97, 31:21); - s(EmcPreRefreshReqCnt, 15:0, scratch98, 15:0); - s(EmcDllXformAddr0, 4:0, scratch98, 20:16); - s(EmcDllXformAddr0, 22:12, scratch98, 31:21); - s(EmcDllXformAddr1, 4:0, scratch99, 4:0); - s(EmcDllXformAddr1, 22:12, scratch99, 15:5); - s(EmcDllXformAddr2, 4:0, scratch99, 20:16); - s(EmcDllXformAddr2, 22:12, scratch99, 31:21); - s(EmcDllXformAddr3, 4:0, scratch100, 4:0); - s(EmcDllXformAddr3, 22:12, scratch100, 15:5); - s(EmcDllXformAddr4, 4:0, scratch100, 20:16); - s(EmcDllXformAddr4, 22:12, scratch100, 31:21); - s(EmcDllXformAddr5, 4:0, scratch101, 4:0); - s(EmcDllXformAddr5, 22:12, scratch101, 15:5); - s(EmcPChg2Pden, 5:0, scratch102, 5:0); - s(EmcAct2Pden, 5:0, scratch102, 11:6); - s(EmcRw2Pden, 5:0, scratch102, 17:12); - s(EmcTcke, 5:0, scratch102, 23:18); - s(EmcTrpab, 5:0, scratch102, 29:24); - s(EmcFbioCfg5, 8:7, scratch102, 31:30); - s(EmcCtt, 5:0, scratch103, 5:0); - s(EmcEInput, 5:0, scratch103, 11:6); - s(EmcPutermExtra, 21:16, scratch103, 17:12); - s(EmcTckesr, 5:0, scratch103, 23:18); - s(EmcTpd, 5:0, scratch103, 29:24); - s(EmcFbioCfg5, 10:9, scratch103, 31:30); - s(EmcRdvMask, 5:0, scratch104, 5:0); - s(EmcXm2CmdPadCtrl4, 0:0, scratch104, 6:6); - s(EmcXm2CmdPadCtrl4, 2:2, scratch104, 7:7); - s(EmcXm2CmdPadCtrl4, 4:4, scratch104, 8:8); - s(EmcXm2CmdPadCtrl4, 6:6, scratch104, 9:9); - s(EmcXm2CmdPadCtrl4, 8:8, scratch104, 10:10); - s(EmcXm2CmdPadCtrl4, 10:10, scratch104, 11:11); - s(EmcQpop, 5:0, scratch104, 17:12); - s(McEmemArbTimingRcd, 5:0, scratch104, 23:18); - s(McEmemArbTimingRas, 5:0, scratch104, 29:24); - s(EmcFbioCfg5, 12:11, scratch104, 31:30); - s(McEmemArbTimingRap2Pre, 5:0, scratch105, 5:0); - s(McEmemArbTimingR2W, 5:0, scratch105, 11:6); - s(McEmemArbTimingW2R, 5:0, scratch105, 17:12); - s(EmcIbdly, 4:0, scratch105, 22:18); - s(McEmemArbTimingR2R, 4:0, scratch105, 27:23); - s(EmcW2w, 3:0, scratch105, 31:28); - s(McEmemArbTimingW2W, 4:0, scratch106, 4:0); - s(McEmemArbOverride, 27:27, scratch106, 5:5); - s(McEmemArbOverride, 26:26, scratch106, 6:6); - s(McEmemArbOverride, 16:16, scratch106, 7:7); - s(McEmemArbOverride, 10:10, scratch106, 8:8); - s(McEmemArbOverride, 4:4, scratch106, 9:9); - s(EmcWdvMask, 3:0, scratch106, 13:10); - s(EmcCttDuration, 3:0, scratch106, 17:14); - s(EmcQuseWidth, 3:0, scratch106, 21:18); - s(EmcPutermWidth, 3:0, scratch106, 25:22); - s(EmcBgbiasCtl0, 3:0, scratch106, 29:26); - s(EmcFbioCfg5, 25:24, scratch106, 31:30); - s(McEmemArbTimingRrd, 3:0, scratch107, 3:0); - s(EmcFbioCfg5, 23:20, scratch107, 10:7); - s(EmcFbioCfg5, 15:13, scratch107, 13:11); - s(EmcCfg2, 5:3, scratch107, 16:14); - s(EmcFbioCfg5, 26:26, scratch107, 17:17); - s(EmcFbioCfg5, 28:28, scratch107, 18:18); - s(EmcCfg2, 2:0, scratch107, 21:19); - s(EmcCfg2, 7:6, scratch107, 23:22); - s(EmcCfg2, 15:10, scratch107, 29:24); - s(EmcCfg2, 23:22, scratch107, 31:30); - s(EmcCfg2, 25:24, scratch108, 1:0); - s(EmcCfg2, 31:28, scratch108, 5:2); - s(BootRomPatchData, 31:0, scratch15, 31:0); - s(BootRomPatchControl, 31:0, scratch16, 31:0); - s(EmcDevSelect, 1:0, scratch17, 31:30); - s(EmcZcalWarmColdBootEnables, 1:0, scratch18, 31:30); - s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch19, 31:30); - s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch46, 30:30); - s(McClkenOverrideAllWarmBoot, 0:0, scratch46, 31:31); - s(EmcClkenOverrideAllWarmBoot, 0:0, scratch47, 30:30); - s(EmcMrsWarmBootEnable, 0:0, scratch47, 31:31); - s(EmcTimingControlWait, 7:0, scratch57, 27:20); - s(EmcZcalWarmBootWait, 7:0, scratch58, 27:20); - s(EmcAutoCalWait, 7:0, scratch59, 27:20); - s(WarmBootWait, 7:0, scratch60, 27:20); - s(EmcPinProgramWait, 7:0, scratch61, 27:20); - s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch79, 30:30); - s(EmcExtraRefreshNum, 2:0, scratch81, 31:29); - s(SwizzleRankByteEncode, 15:0, scratch101, 31:16); - s(MemoryType, 2:0, scratch107, 6:4); + s(EmcClockSourceDll, 7:0, scratch6, 23:16); + s(EmcClockSource, 31:29, scratch6, 26:24); + s(EmcClockSourceDll, 31:29, scratch6, 29:27); + s(EmcClockSourceDll, 11:10, scratch6, 31:30); + s(ClkRstControllerPllmMisc2Override, 9:8, scratch7, 1:0); + s(ClkRstControllerPllmMisc2Override, 2:1, scratch7, 3:2); + s(EmcZqCalLpDdr4WarmBoot, 31:30, scratch7, 5:4); + s(EmcClockSource, 15:15, scratch7, 6:6); + s(EmcClockSource, 26:26, scratch7, 7:7); + s(EmcClockSource, 20:20, scratch7, 8:8); + s(EmcClockSource, 19:19, scratch7, 9:9); + s(ClkRstControllerPllmMisc2Override, 13:13, scratch7, 10:10); + s(ClkRstControllerPllmMisc2Override, 12:12, scratch7, 11:11); + s(ClkRstControllerPllmMisc2Override, 11:11, scratch7, 12:12); + s(ClkRstControllerPllmMisc2Override, 10:10, scratch7, 13:13); + s(ClkRstControllerPllmMisc2Override, 5:5, scratch7, 14:14); + s(ClkRstControllerPllmMisc2Override, 4:4, scratch7, 15:15); + s(ClkRstControllerPllmMisc2Override, 3:3, scratch7, 16:16); + s(ClkRstControllerPllmMisc2Override, 0:0, scratch7, 17:17); + s(EmcZqCalLpDdr4WarmBoot, 1:0, scratch7, 19:18); + s(EmcZqCalLpDdr4WarmBoot, 4:4, scratch7, 20:20); + s(EmcOdtWrite, 5:0, scratch7, 26:21); + s(EmcOdtWrite, 11:8, scratch7, 30:27); + s(EmcOdtWrite, 31:31, scratch7, 31:31); + s(EmcFdpdCtrlCmdNoRamp, 0:0, scratch13, 30:30); + s(EmcCfgPipeClk, 0:0, scratch13, 31:31); + s(McEmemArbMisc2, 0:0, scratch14, 30:30); + s(McDaCfg0, 0:0, scratch14, 31:31); + s(EmcQRst, 6:0, scratch15, 26:20); + s(EmcQRst, 20:16, scratch15, 31:27); + s(EmcPmacroCmdTxDrv, 5:0, scratch16, 25:20); + s(EmcPmacroCmdTxDrv, 13:8, scratch16, 31:26); + s(EmcPmacroAutocalCfg0, 2:0, scratch17, 22:20); + s(EmcPmacroAutocalCfg0, 10:8, scratch17, 25:23); + s(EmcPmacroAutocalCfg0, 18:16, scratch17, 28:26); + s(EmcPmacroAutocalCfg0, 26:24, scratch17, 31:29); + s(EmcPmacroAutocalCfg1, 2:0, scratch18, 22:20); + s(EmcPmacroAutocalCfg1, 10:8, scratch18, 25:23); + s(EmcPmacroAutocalCfg1, 18:16, scratch18, 28:26); + s(EmcPmacroAutocalCfg1, 26:24, scratch18, 31:29); + s(EmcPmacroAutocalCfg2, 2:0, scratch19, 22:20); + s(EmcPmacroAutocalCfg2, 10:8, scratch19, 25:23); + s(EmcPmacroAutocalCfg2, 18:16, scratch19, 28:26); + s(EmcPmacroAutocalCfg2, 26:24, scratch19, 31:29); + s32(EmcCfgRsv,scratch22); + s32(EmcAutoCalConfig, scratch23); + s32(EmcAutoCalVrefSel0, scratch24); + s32(EmcPmacroBrickCtrlRfu1, scratch25); + s32(EmcPmacroBrickCtrlRfu2, scratch26); + s32(EmcPmcScratch1, scratch27); + s32(EmcPmcScratch2, scratch28); + s32(EmcPmcScratch3, scratch29); + s32(McEmemArbDaTurns, scratch30); + s(EmcFbioSpare, 31:24, scratch58, 7:0); + s(EmcFbioSpare, 23:16, scratch58, 15:8); + s(EmcFbioSpare, 15:8, scratch58, 23:16); + s(EmcFbioSpare, 7:2, scratch58, 29:24); + s(EmcFbioSpare, 0:0, scratch58, 30:30); + s(EmcDllCfg0, 29:0, scratch59, 29:0); + s(EmcPmacroDdllBypass, 11:0, scratch60, 11:0); + s(EmcPmacroDdllBypass, 27:13, scratch60, 26:12); + s(EmcPmacroDdllBypass, 31:29, scratch60, 29:27); + s(McEmemArbMisc0, 14:0, scratch61, 14:0); + s(McEmemArbMisc0, 30:16, scratch61, 29:15); + s(EmcFdpdCtrlCmd, 16:0, scratch62, 16:0); + s(EmcFdpdCtrlCmd, 31:20, scratch62, 28:17); + s(EmcAutoCalConfig2, 27:0, scratch63, 27:0); + s(EmcBurstRefreshNum, 3:0, scratch63, 31:28); + s(EmcPmacroZctrl, 27:0, scratch64, 27:0); + s(EmcTppd, 3:0, scratch64, 31:28); + s(EmcCfgDigDll, 10:0, scratch65, 10:0); + s(EmcCfgDigDll, 25:12, scratch65, 24:11); + s(EmcCfgDigDll, 27:27, scratch65, 25:25); + s(EmcCfgDigDll, 31:30, scratch65, 27:26); + s(EmcR2r, 3:0, scratch65, 31:28); + s(EmcFdpdCtrlDq, 16:0, scratch66, 16:0); + s(EmcFdpdCtrlDq, 28:20, scratch66, 25:17); + s(EmcFdpdCtrlDq, 31:30, scratch66, 27:26); + s(EmcW2w, 3:0, scratch66, 31:28); + s(EmcPmacroTxPwrd4, 13:0, scratch67, 13:0); + s(EmcPmacroTxPwrd4, 29:16, scratch67, 27:14); + s(EmcPmacroCommonPadTxCtrl, 3:0, scratch67, 31:28); + s(EmcPmacroTxPwrd5, 13:0, scratch68, 13:0); + s(EmcPmacroTxPwrd5, 29:16, scratch68, 27:14); + s(EmcPmacroDdllPwrd0, 4:0, scratch69, 4:0); + s(EmcPmacroDdllPwrd0, 12:6, scratch69, 11:5); + s(EmcPmacroDdllPwrd0, 20:14, scratch69, 18:12); + s(EmcPmacroDdllPwrd0, 28:22, scratch69, 25:19); + s(EmcPmacroDdllPwrd0, 31:30, scratch69, 27:26); + s(EmcCfg, 4:4, scratch69, 31:31); + s(EmcPmacroDdllPwrd1, 4:0, scratch70, 4:0); + s(EmcPmacroDdllPwrd1, 12:6, scratch70, 11:5); + s(EmcPmacroDdllPwrd1, 20:14, scratch70, 18:12); + s(EmcPmacroDdllPwrd1, 28:22, scratch70, 25:19); + s(EmcPmacroDdllPwrd1, 31:30, scratch70, 27:26); + s(EmcCfg, 5:5, scratch70, 31:31); + s(EmcPmacroDdllPwrd2, 4:0, scratch71, 4:0); + s(EmcPmacroDdllPwrd2, 12:6, scratch71, 11:5); + s(EmcPmacroDdllPwrd2, 20:14, scratch71, 18:12); + s(EmcPmacroDdllPwrd2, 28:22, scratch71, 25:19); + s(EmcPmacroDdllPwrd2, 31:30, scratch71, 27:26); + s(EmcFbioCfg5, 23:20, scratch71, 31:28); + s(EmcPmacroIbVrefDq_0, 6:0, scratch72, 6:0); + s(EmcPmacroIbVrefDq_0, 14:8, scratch72, 13:7); + s(EmcPmacroIbVrefDq_0, 22:16, scratch72, 20:14); + s(EmcPmacroIbVrefDq_0, 30:24, scratch72, 27:21); + s(EmcFbioCfg5, 15:13, scratch72, 30:28); + s(EmcCfg, 6:6, scratch72, 31:31); + s(EmcPmacroIbVrefDq_1, 6:0, scratch73, 6:0); + s(EmcPmacroIbVrefDq_1, 14:8, scratch73, 13:7); + s(EmcPmacroIbVrefDq_1, 22:16, scratch73, 20:14); + s(EmcPmacroIbVrefDq_1, 30:24, scratch73, 27:21); + s(EmcCfg2, 5:3, scratch73, 30:28); + s(EmcCfg, 7:7, scratch73, 31:31); + s(EmcPmacroIbVrefDqs_0, 6:0, scratch74, 6:0); + s(EmcPmacroIbVrefDqs_0, 14:8, scratch74, 13:7); + s(EmcPmacroIbVrefDqs_0, 22:16, scratch74, 20:14); + s(EmcPmacroIbVrefDqs_0, 30:24, scratch74, 27:21); + s(EmcCfg, 17:16, scratch74, 29:28); + s(EmcFbioCfg5, 1:0, scratch74, 31:30); + s(EmcPmacroIbVrefDqs_1, 6:0, scratch75, 6:0); + s(EmcPmacroIbVrefDqs_1, 14:8, scratch75, 13:7); + s(EmcPmacroIbVrefDqs_1, 22:16, scratch75, 20:14); + s(EmcPmacroIbVrefDqs_1, 30:24, scratch75, 27:21); + s(EmcFbioCfg5, 3:2, scratch75, 29:28); + s(EmcCfg2, 27:26, scratch75, 31:30); + s(EmcPmacroDdllShortCmd_0, 6:0, scratch76, 6:0); + s(EmcPmacroDdllShortCmd_0, 14:8, scratch76, 13:7); + s(EmcPmacroDdllShortCmd_0, 22:16, scratch76, 20:14); + s(EmcPmacroDdllShortCmd_0, 30:24, scratch76, 27:21); + s(EmcPmacroCmdPadTxCtrl, 3:2, scratch76, 29:28); + s(EmcPmacroCmdPadTxCtrl, 7:6, scratch76, 31:30); + s(EmcPmacroDdllShortCmd_1, 6:0, scratch77, 6:0); + s(EmcPmacroDdllShortCmd_1, 14:8, scratch77, 13:7); + s(EmcPmacroDdllShortCmd_1, 22:16, scratch77, 20:14); + s(EmcPmacroDdllShortCmd_1, 30:24, scratch77, 27:21); + s(EmcPmacroCmdPadTxCtrl, 11:10, scratch77, 29:28); + s(EmcPmacroCmdPadTxCtrl, 15:14, scratch77, 31:30); + s(EmcAutoCalChannel, 5:0, scratch78, 5:0); + s(EmcAutoCalChannel, 11:8, scratch78, 9:6); + s(EmcAutoCalChannel, 27:16, scratch78, 21:10); + s(EmcAutoCalChannel, 31:29, scratch78, 24:22); + s(EmcConfigSampleDelay, 6:0, scratch78, 31:25); + s(EmcPmacroRxTerm, 5:0, scratch79, 5:0); + s(EmcPmacroRxTerm, 13:8, scratch79, 11:6); + s(EmcPmacroRxTerm, 21:16, scratch79, 17:12); + s(EmcPmacroRxTerm, 29:24, scratch79, 23:18); + s(EmcRc, 7:0, scratch79, 31:24); + s(EmcPmacroDqTxDrv, 5:0, scratch80, 5:0); + s(EmcPmacroDqTxDrv, 13:8, scratch80, 11:6); + s(EmcPmacroDqTxDrv, 21:16, scratch80, 17:12); + s(EmcPmacroDqTxDrv, 29:24, scratch80, 23:18); + s(EmcSelDpdCtrl, 5:2, scratch80, 27:24); + s(EmcSelDpdCtrl, 8:8, scratch80, 28:28); + s(EmcSelDpdCtrl, 18:16, scratch80, 31:29); + s(EmcPmacroCaTxDrv, 5:0, scratch81, 5:0); + s(EmcPmacroCaTxDrv, 13:8, scratch81, 11:6); + s(EmcPmacroCaTxDrv, 21:16, scratch81, 17:12); + s(EmcPmacroCaTxDrv, 29:24, scratch81, 23:18); + s(EmcObdly, 5:0, scratch81, 29:24); + s(EmcObdly, 29:28, scratch81, 31:30); + s(EmcZcalInterval, 23:10, scratch82, 13:0); + s(EmcZcalInterval, 9:0, scratch82, 23:14); + s(EmcPmacroCmdRxTermMode, 1:0, scratch82, 25:24); + s(EmcPmacroCmdRxTermMode, 5:4, scratch82, 27:26); + s(EmcPmacroCmdRxTermMode, 9:8, scratch82, 29:28); + s(EmcPmacroCmdRxTermMode, 13:12, scratch82, 31:30); + s(EmcDataBrlshft0, 23:0, scratch83, 23:0); + s(EmcPmacroDataRxTermMode, 1:0, scratch83, 25:24); + s(EmcPmacroDataRxTermMode, 5:4, scratch83, 27:26); + s(EmcPmacroDataRxTermMode, 9:8, scratch83, 29:28); + s(EmcPmacroDataRxTermMode, 13:12, scratch83, 31:30); + s(EmcDataBrlshft1, 23:0, scratch84, 23:0); + s(McEmemArbTimingRc, 7:0, scratch84, 31:24); + s(EmcDqsBrlshft0, 23:0, scratch85, 23:0); + s(McEmemArbRsv, 7:0, scratch85, 31:24); + s(EmcDqsBrlshft1, 23:0, scratch86, 23:0); + s(EmcCfgPipe2, 11:0, scratch87, 11:0); + s(EmcCfgPipe2, 27:16, scratch87, 23:12); + s(EmcCfgPipe1, 11:0, scratch88, 11:0); + s(EmcCfgPipe1, 27:16, scratch88, 23:12); + s(EmcPmacroCmdCtrl0, 5:0, scratch89, 5:0); + s(EmcPmacroCmdCtrl0, 13:8, scratch89, 11:6); + s(EmcPmacroCmdCtrl0, 21:16, scratch89, 17:12); + s(EmcPmacroCmdCtrl0, 29:24, scratch89, 23:18); + s(EmcPmacroCmdCtrl1, 5:0, scratch90, 5:0); + s(EmcPmacroCmdCtrl1, 13:8, scratch90, 11:6); + s(EmcPmacroCmdCtrl1, 21:16, scratch90, 17:12); + s(EmcPmacroCmdCtrl1, 29:24, scratch90, 23:18); + s(EmcRas, 6:0, scratch90, 30:24); + s(EmcCfg, 8:8, scratch90, 31:31); + s(EmcPmacroVttgenCtrl2, 23:0, scratch91, 23:0); + s(EmcW2p, 6:0, scratch91, 30:24); + s(EmcCfg, 9:9, scratch91, 31:31); + s(EmcPmacroCmdPadRxCtrl, 2:0, scratch92, 2:0); + s(EmcPmacroCmdPadRxCtrl, 5:4, scratch92, 4:3); + s(EmcPmacroCmdPadRxCtrl, 10:8, scratch92, 7:5); + s(EmcPmacroCmdPadRxCtrl, 22:12, scratch92, 18:8); + s(EmcPmacroCmdPadRxCtrl, 28:24, scratch92, 23:19); + s(EmcQSafe, 6:0, scratch92, 30:24); + s(EmcCfg, 18:18, scratch92, 31:31); + s(EmcPmacroDataPadRxCtrl, 2:0, scratch93, 2:0); + s(EmcPmacroDataPadRxCtrl, 5:4, scratch93, 4:3); + s(EmcPmacroDataPadRxCtrl, 10:8, scratch93, 7:5); + s(EmcPmacroDataPadRxCtrl, 22:12, scratch93, 18:8); + s(EmcPmacroDataPadRxCtrl, 28:24, scratch93, 23:19); + s(EmcRdv, 6:0, scratch93, 30:24); + s(EmcCfg, 21:21, scratch93, 31:31); + s(McEmemArbDaCovers, 23:0, scratch94, 23:0); + s(EmcRw2Pden, 6:0, scratch94, 30:24); + s(EmcCfg, 22:22, scratch94, 31:31); + s(EmcPmacroCmdCtrl2, 5:0, scratch95, 5:0); + s(EmcPmacroCmdCtrl2, 13:9, scratch95, 10:6); + s(EmcPmacroCmdCtrl2, 21:16, scratch95, 16:11); + s(EmcPmacroCmdCtrl2, 29:24, scratch95, 22:17); + s(EmcRfcPb, 8:0, scratch95, 31:23); + s(EmcPmacroQuseDdllRank0_0, 10:0, scratch96, 10:0); + s(EmcPmacroQuseDdllRank0_0, 26:16, scratch96, 21:11); + s(EmcCfgUpdate, 2:0, scratch96, 24:22); + s(EmcCfgUpdate, 10:8, scratch96, 27:25); + s(EmcCfgUpdate, 31:28, scratch96, 31:28); + s(EmcPmacroQuseDdllRank0_1, 10:0, scratch97, 10:0); + s(EmcPmacroQuseDdllRank0_1, 26:16, scratch97, 21:11); + s(EmcRfc, 9:0, scratch97, 31:22); + s(EmcPmacroQuseDdllRank0_2, 10:0, scratch98, 10:0); + s(EmcPmacroQuseDdllRank0_2, 26:16, scratch98, 21:11); + s(EmcTxsr, 9:0, scratch98, 31:22); + s(EmcPmacroQuseDdllRank0_3, 10:0, scratch99, 10:0); + s(EmcPmacroQuseDdllRank0_3, 26:16, scratch99, 21:11); + s(EmcMc2EmcQ, 2:0, scratch99, 24:22); + s(EmcMc2EmcQ, 10:8, scratch99, 27:25); + s(EmcMc2EmcQ, 27:24, scratch99, 31:28); + s(EmcPmacroQuseDdllRank0_4, 10:0, scratch100, 10:0); + s(EmcPmacroQuseDdllRank0_4, 26:16, scratch100, 21:11); + s(McEmemArbRing1Throttle, 4:0, scratch100, 26:22); + s(McEmemArbRing1Throttle, 20:16, scratch100, 31:27); + s(EmcPmacroQuseDdllRank0_5, 10:0, scratch101, 10:0); + s(EmcPmacroQuseDdllRank0_5, 26:16, scratch101, 21:11); + s(EmcPmacroQuseDdllRank1_0, 10:0, scratch102, 10:0); + s(EmcPmacroQuseDdllRank1_0, 26:16, scratch102, 21:11); + s(EmcAr2Pden, 8:0, scratch102, 30:22); + s(EmcCfg, 23:23, scratch102, 31:31); + s(EmcPmacroQuseDdllRank1_1, 10:0, scratch103, 10:0); + s(EmcPmacroQuseDdllRank1_1, 26:16, scratch103, 21:11); + s(EmcRfcSlr, 8:0, scratch103, 30:22); + s(EmcCfg, 24:24, scratch103, 31:31); + s(EmcPmacroQuseDdllRank1_2, 10:0, scratch104, 10:0); + s(EmcPmacroQuseDdllRank1_2, 26:16, scratch104, 21:11); + s(EmcIbdly, 6:0, scratch104, 28:22); + s(EmcIbdly, 29:28, scratch104, 30:29); + s(EmcCfg, 25:25, scratch104, 31:31); + s(EmcPmacroQuseDdllRank1_3, 10:0, scratch105, 10:0); + s(EmcPmacroQuseDdllRank1_3, 26:16, scratch105, 21:11); + s(McEmemArbTimingRFCPB, 8:0, scratch105, 30:22); + s(EmcCfg, 26:26, scratch105, 31:31); + s(EmcPmacroQuseDdllRank1_4, 10:0, scratch106, 10:0); + s(EmcPmacroQuseDdllRank1_4, 26:16, scratch106, 21:11); + s(EmcTfaw, 6:0, scratch106, 28:22); + s(EmcPmacroDataPadTxCtrl, 3:2, scratch106, 30:29); + s(EmcCfg, 28:28, scratch106, 31:31); + s(EmcPmacroQuseDdllRank1_5, 10:0, scratch107, 10:0); + s(EmcPmacroQuseDdllRank1_5, 26:16, scratch107, 21:11); + s(EmcTClkStable, 6:0, scratch107, 28:22); + s(EmcPmacroDataPadTxCtrl, 7:6, scratch107, 30:29); + s(EmcCfg, 29:29, scratch107, 31:31); + s(EmcPmacroObDdllLongDqRank0_0, 10:0, scratch108, 10:0); + s(EmcPmacroObDdllLongDqRank0_0, 26:16, scratch108, 21:11); + s(EmcPdex2Mrr, 6:0, scratch108, 28:22); + s(EmcPmacroDataPadTxCtrl, 11:10, scratch108, 30:29); + s(EmcCfg, 30:30, scratch108, 31:31); + s(EmcPmacroObDdllLongDqRank0_1, 10:0, scratch109, 10:0); + s(EmcPmacroObDdllLongDqRank0_1, 26:16, scratch109, 21:11); + s(EmcRdvMask, 6:0, scratch109, 28:22); + s(EmcPmacroDataPadTxCtrl, 15:14, scratch109, 30:29); + s(EmcCfg, 31:31, scratch109, 31:31); + s(EmcPmacroObDdllLongDqRank0_2, 10:0, scratch110, 10:0); + s(EmcPmacroObDdllLongDqRank0_2, 26:16, scratch110, 21:11); + s(EmcRdvEarlyMask, 6:0, scratch110, 28:22); + s(EmcFbioCfg5, 4:4, scratch110, 29:29); + s(EmcFbioCfg5, 8:8, scratch110, 30:30); + s(EmcFbioCfg5, 10:10, scratch110, 31:31); + s(EmcPmacroObDdllLongDqRank0_3, 10:0, scratch111, 10:0); + s(EmcPmacroObDdllLongDqRank0_3, 26:16, scratch111, 21:11); + s(EmcRdvEarly, 6:0, scratch111, 28:22); + s(EmcFbioCfg5, 12:12, scratch111, 29:29); + s(EmcFbioCfg5, 25:24, scratch111, 31:30); + s(EmcPmacroObDdllLongDqRank0_4, 10:0, scratch112, 10:0); + s(EmcPmacroObDdllLongDqRank0_4, 26:16, scratch112, 21:11); + s(EmcPmacroDdllShortCmd_2, 6:0, scratch112, 28:22); + s(EmcFbioCfg5, 28:26, scratch112, 31:29); + s(EmcPmacroObDdllLongDqRank0_5, 10:0, scratch113, 10:0); + s(EmcPmacroObDdllLongDqRank0_5, 26:16, scratch113, 21:11); + s(McEmemArbTimingRp, 6:0, scratch113, 28:22); + s(EmcFbioCfg5, 31:30, scratch113, 30:29); + s(EmcCfg2, 0:0, scratch113, 31:31); + s(EmcPmacroObDdllLongDqRank1_0, 10:0, scratch114, 10:0); + s(EmcPmacroObDdllLongDqRank1_0, 26:16, scratch114, 21:11); + s(McEmemArbTimingRas, 6:0, scratch114, 28:22); + s(EmcCfg2, 2:1, scratch114, 30:29); + s(EmcCfg2, 7:7, scratch114, 31:31); + s(EmcPmacroObDdllLongDqRank1_1, 10:0, scratch115, 10:0); + s(EmcPmacroObDdllLongDqRank1_1, 26:16, scratch115, 21:11); + s(McEmemArbTimingFaw, 6:0, scratch115, 28:22); + s(EmcCfg2, 11:10, scratch115, 30:29); + s(EmcCfg2, 14:14, scratch115, 31:31); + s(EmcPmacroObDdllLongDqRank1_2, 10:0, scratch123, 10:0); + s(EmcPmacroObDdllLongDqRank1_2, 26:16, scratch123, 21:11); + s(McEmemArbTimingRap2Pre, 6:0, scratch123, 28:22); + s(EmcCfg2, 16:15, scratch123, 30:29); + s(EmcCfg2, 20:20, scratch123, 31:31); + s(EmcPmacroObDdllLongDqRank1_3, 10:0, scratch124, 10:0); + s(EmcPmacroObDdllLongDqRank1_3, 26:16, scratch124, 21:11); + s(McEmemArbTimingWap2Pre, 6:0, scratch124, 28:22); + s(EmcCfg2, 24:22, scratch124, 31:29); + s(EmcPmacroObDdllLongDqRank1_4, 10:0, scratch125, 10:0); + s(EmcPmacroObDdllLongDqRank1_4, 26:16, scratch125, 21:11); + s(McEmemArbTimingR2W, 6:0, scratch125, 28:22); + s(EmcCfg2, 25:25, scratch125, 29:29); + s(EmcCfg2, 29:28, scratch125, 31:30); + s(EmcPmacroObDdllLongDqRank1_5, 10:0, scratch126, 10:0); + s(EmcPmacroObDdllLongDqRank1_5, 26:16, scratch126, 21:11); + s(McEmemArbTimingW2R, 6:0, scratch126, 28:22); + s(EmcCfg2, 31:30, scratch126, 30:29); + s(EmcCfgPipe, 0:0, scratch126, 31:31); + s(EmcPmacroObDdllLongDqsRank0_0, 10:0, scratch127, 10:0); + s(EmcPmacroObDdllLongDqsRank0_0, 26:16, scratch127, 21:11); + s(EmcRp, 5:0, scratch127, 27:22); + s(EmcCfgPipe, 4:1, scratch127, 31:28); + s(EmcPmacroObDdllLongDqsRank0_1, 10:0, scratch128, 10:0); + s(EmcPmacroObDdllLongDqsRank0_1, 26:16, scratch128, 21:11); + s(EmcR2w, 5:0, scratch128, 27:22); + s(EmcCfgPipe, 8:5, scratch128, 31:28); + s(EmcPmacroObDdllLongDqsRank0_2, 10:0, scratch129, 10:0); + s(EmcPmacroObDdllLongDqsRank0_2, 26:16, scratch129, 21:11); + s(EmcW2r, 5:0, scratch129, 27:22); + s(EmcCfgPipe, 11:9, scratch129, 30:28); + s(EmcCfgPipe, 16:16, scratch129, 31:31); + s(EmcPmacroObDdllLongDqsRank0_3, 10:0, scratch130, 10:0); + s(EmcPmacroObDdllLongDqsRank0_3, 26:16, scratch130, 21:11); + s(EmcR2p, 5:0, scratch130, 27:22); + s(EmcCfgPipe, 20:17, scratch130, 31:28); + s(EmcPmacroObDdllLongDqsRank0_4, 10:0, scratch131, 10:0); + s(EmcPmacroObDdllLongDqsRank0_4, 26:16, scratch131, 21:11); + s(EmcCcdmw, 5:0, scratch131, 27:22); + s(EmcCfgPipe, 24:21, scratch131, 31:28); + s(EmcPmacroObDdllLongDqsRank0_5, 10:0, scratch132, 10:0); + s(EmcPmacroObDdllLongDqsRank0_5, 26:16, scratch132, 21:11); + s(EmcRdRcd, 5:0, scratch132, 27:22); + s(EmcCfgPipe, 27:25, scratch132, 30:28); + s(EmcPmacroTxPwrd0, 0:0, scratch132, 31:31); + s(EmcPmacroObDdllLongDqsRank1_0, 10:0, scratch133, 10:0); + s(EmcPmacroObDdllLongDqsRank1_0, 26:16, scratch133, 21:11); + s(EmcWrRcd, 5:0, scratch133, 27:22); + s(EmcPmacroTxPwrd0, 4:1, scratch133, 31:28); + s(EmcPmacroObDdllLongDqsRank1_1, 10:0, scratch134, 10:0); + s(EmcPmacroObDdllLongDqsRank1_1, 26:16, scratch134, 21:11); + s(EmcWdv, 5:0, scratch134, 27:22); + s(EmcPmacroTxPwrd0, 8:5, scratch134, 31:28); + s(EmcPmacroObDdllLongDqsRank1_2, 10:0, scratch135, 10:0); + s(EmcPmacroObDdllLongDqsRank1_2, 26:16, scratch135, 21:11); + s(EmcQUse, 5:0, scratch135, 27:22); + s(EmcPmacroTxPwrd0, 12:9, scratch135, 31:28); + s(EmcPmacroObDdllLongDqsRank1_3, 10:0, scratch136, 10:0); + s(EmcPmacroObDdllLongDqsRank1_3, 26:16, scratch136, 21:11); + s(EmcPdEx2Wr, 5:0, scratch136, 27:22); + s(EmcPmacroTxPwrd0, 13:13, scratch136, 28:28); + s(EmcPmacroTxPwrd0, 18:16, scratch136, 31:29); + s(EmcPmacroObDdllLongDqsRank1_4, 10:0, scratch137, 10:0); + s(EmcPmacroObDdllLongDqsRank1_4, 26:16, scratch137, 21:11); + s(EmcPdEx2Rd, 5:0, scratch137, 27:22); + s(EmcPmacroTxPwrd0, 22:19, scratch137, 31:28); + s(EmcPmacroObDdllLongDqsRank1_5, 10:0, scratch138, 10:0); + s(EmcPmacroObDdllLongDqsRank1_5, 26:16, scratch138, 21:11); + s(EmcPdex2Cke, 5:0, scratch138, 27:22); + s(EmcPmacroTxPwrd0, 26:23, scratch138, 31:28); + s(EmcPmacroIbDdllLongDqsRank0_0, 10:0, scratch139, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_0, 26:16, scratch139, 21:11); + s(EmcPChg2Pden, 5:0, scratch139, 27:22); + s(EmcPmacroTxPwrd0, 29:27, scratch139, 30:28); + s(EmcPmacroTxPwrd1, 0:0, scratch139, 31:31); + s(EmcPmacroIbDdllLongDqsRank0_1, 10:0, scratch140, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_1, 26:16, scratch140, 21:11); + s(EmcAct2Pden, 5:0, scratch140, 27:22); + s(EmcPmacroTxPwrd1, 4:1, scratch140, 31:28); + s(EmcPmacroIbDdllLongDqsRank0_2, 10:0, scratch141, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_2, 26:16, scratch141, 21:11); + s(EmcCke2Pden, 5:0, scratch141, 27:22); + s(EmcPmacroTxPwrd1, 8:5, scratch141, 31:28); + s(EmcPmacroIbDdllLongDqsRank0_3, 10:0, scratch142, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_3, 26:16, scratch142, 21:11); + s(EmcTcke, 5:0, scratch142, 27:22); + s(EmcPmacroTxPwrd1, 12:9, scratch142, 31:28); + s(EmcPmacroIbDdllLongDqsRank1_0, 10:0, scratch143, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_0, 26:16, scratch143, 21:11); + s(EmcTrpab, 5:0, scratch143, 27:22); + s(EmcPmacroTxPwrd1, 13:13, scratch143, 28:28); + s(EmcPmacroTxPwrd1, 18:16, scratch143, 31:29); + s(EmcPmacroIbDdllLongDqsRank1_1, 10:0, scratch144, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_1, 26:16, scratch144, 21:11); + s(EmcClkenOverride, 3:1, scratch144, 24:22); + s(EmcClkenOverride, 8:6, scratch144, 27:25); + s(EmcPmacroTxPwrd1, 22:19, scratch144, 31:28); + s(EmcPmacroIbDdllLongDqsRank1_2, 10:0, scratch145, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_2, 26:16, scratch145, 21:11); + s(EmcEInput, 5:0, scratch145, 27:22); + s(EmcPmacroTxPwrd1, 26:23, scratch145, 31:28); + s(EmcPmacroIbDdllLongDqsRank1_3, 10:0, scratch146, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_3, 26:16, scratch146, 21:11); + s(EmcEInputDuration, 5:0, scratch146, 27:22); + s(EmcPmacroTxPwrd1, 29:27, scratch146, 30:28); + s(EmcPmacroTxPwrd2, 0:0, scratch146, 31:31); + s(EmcPmacroDdllLongCmd_0, 10:0, scratch147, 10:0); + s(EmcPmacroDdllLongCmd_0, 26:16, scratch147, 21:11); + s(EmcPutermExtra, 5:0, scratch147, 27:22); + s(EmcPmacroTxPwrd2, 4:1, scratch147, 31:28); + s(EmcPmacroDdllLongCmd_1, 10:0, scratch148, 10:0); + s(EmcPmacroDdllLongCmd_1, 26:16, scratch148, 21:11); + s(EmcTckesr, 5:0, scratch148, 27:22); + s(EmcPmacroTxPwrd2, 8:5, scratch148, 31:28); + s(EmcPmacroDdllLongCmd_2, 10:0, scratch149, 10:0); + s(EmcPmacroDdllLongCmd_2, 26:16, scratch149, 21:11); + s(EmcTpd, 5:0, scratch149, 27:22); + s(EmcPmacroTxPwrd2, 12:9, scratch149, 31:28); + s(EmcPmacroDdllLongCmd_3, 10:0, scratch150, 10:0); + s(EmcPmacroDdllLongCmd_3, 26:16, scratch150, 21:11); + s(EmcWdvMask, 5:0, scratch150, 27:22); + s(EmcPmacroTxPwrd2, 13:13, scratch150, 28:28); + s(EmcPmacroTxPwrd2, 18:16, scratch150, 31:29); + s(McEmemArbCfg, 8:0, scratch151, 8:0); + s(McEmemArbCfg, 20:16, scratch151, 13:9); + s(McEmemArbCfg, 31:24, scratch151, 21:14); + s(EmcWdvChk, 5:0, scratch151, 27:22); + s(EmcPmacroTxPwrd2, 22:19, scratch151, 31:28); + s(McEmemArbMisc1, 12:0, scratch152, 12:0); + s(McEmemArbMisc1, 25:21, scratch152, 17:13); + s(McEmemArbMisc1, 31:28, scratch152, 21:18); + s(EmcCmdBrlshft0, 5:0, scratch152, 27:22); + s(EmcPmacroTxPwrd2, 26:23, scratch152, 31:28); + s(EmcMrsWaitCnt2, 9:0, scratch153, 9:0); + s(EmcMrsWaitCnt2, 26:16, scratch153, 20:10); + s(EmcPmacroIbRxrt, 10:0, scratch153, 31:21); + s(EmcMrsWaitCnt, 9:0, scratch154, 9:0); + s(EmcMrsWaitCnt, 26:16, scratch154, 20:10); + s(EmcPmacroDdllLongCmd_4, 10:0, scratch154, 31:21); + s(EmcAutoCalInterval, 20:0, scratch155, 20:0); + s(McEmemArbOutstandingReq, 8:0, scratch155, 29:21); + s(McEmemArbOutstandingReq, 31:30, scratch155, 31:30); + s(McEmemArbRefpbHpCtrl, 6:0, scratch156, 6:0); + s(McEmemArbRefpbHpCtrl, 14:8, scratch156, 13:7); + s(McEmemArbRefpbHpCtrl, 22:16, scratch156, 20:14); + s(EmcCmdBrlshft1, 5:0, scratch156, 26:21); + s(EmcRrd, 4:0, scratch156, 31:27); + s(EmcQuseBrlshft0, 19:0, scratch157, 19:0); + s(EmcFbioCfg8, 27:16, scratch157, 31:20); + s(EmcQuseBrlshft1, 19:0, scratch158, 19:0); + s(EmcTxsrDll, 11:0, scratch158, 31:20); + s(EmcQuseBrlshft2, 19:0, scratch159, 19:0); + s(EmcTxdsrvttgen, 11:0, scratch159, 31:20); + s(EmcQuseBrlshft3, 19:0, scratch160, 19:0); + s(EmcPmacroVttgenCtrl0, 3:0, scratch160, 23:20); + s(EmcPmacroVttgenCtrl0, 11:8, scratch160, 27:24); + s(EmcPmacroVttgenCtrl0, 19:16, scratch160, 31:28); + s(EmcPmacroVttgenCtrl1, 19:0, scratch161, 19:0); + s(EmcCmdBrlshft2, 5:0, scratch161, 25:20); + s(EmcCmdBrlshft3, 5:0, scratch161, 31:26); + s(EmcAutoCalConfig3, 5:0, scratch162, 5:0); + s(EmcAutoCalConfig3, 13:8, scratch162, 11:6); + s(EmcAutoCalConfig3, 18:16, scratch162, 14:12); + s(EmcAutoCalConfig3, 22:20, scratch162, 17:15); + s(EmcTRefBw, 13:0, scratch162, 31:18); + s(EmcAutoCalConfig4, 5:0, scratch163, 5:0); + s(EmcAutoCalConfig4, 13:8, scratch163, 11:6); + s(EmcAutoCalConfig4, 18:16, scratch163, 14:12); + s(EmcAutoCalConfig4, 22:20, scratch163, 17:15); + s(EmcQpop, 6:0, scratch163, 24:18); + s(EmcQpop, 22:16, scratch163, 31:25); + s(EmcAutoCalConfig5, 5:0, scratch164, 5:0); + s(EmcAutoCalConfig5, 13:8, scratch164, 11:6); + s(EmcAutoCalConfig5, 18:16, scratch164, 14:12); + s(EmcAutoCalConfig5, 22:20, scratch164, 17:15); + s(EmcPmacroAutocalCfgCommon, 5:0, scratch164, 23:18); + s(EmcPmacroAutocalCfgCommon, 13:8, scratch164, 29:24); + s(EmcPmacroAutocalCfgCommon, 16:16, scratch164, 30:30); + s(EmcPmacroTxPwrd2, 27:27, scratch164, 31:31); + s(EmcAutoCalConfig6, 5:0, scratch165, 5:0); + s(EmcAutoCalConfig6, 13:8, scratch165, 11:6); + s(EmcAutoCalConfig6, 18:16, scratch165, 14:12); + s(EmcAutoCalConfig6, 22:20, scratch165, 17:15); + s(EmcWev, 5:0, scratch165, 23:18); + s(EmcWsv, 5:0, scratch165, 29:24); + s(EmcPmacroTxPwrd2, 29:28, scratch165, 31:30); + s(EmcAutoCalConfig7, 5:0, scratch166, 5:0); + s(EmcAutoCalConfig7, 13:8, scratch166, 11:6); + s(EmcAutoCalConfig7, 18:16, scratch166, 14:12); + s(EmcAutoCalConfig7, 22:20, scratch166, 17:15); + s(EmcCfg3, 2:0, scratch166, 20:18); + s(EmcCfg3, 6:4, scratch166, 23:21); + s(EmcQuseWidth, 3:0, scratch166, 27:24); + s(EmcQuseWidth, 29:28, scratch166, 29:28); + s(EmcPmacroTxPwrd3, 1:0, scratch166, 31:30); + s(EmcAutoCalConfig8, 5:0, scratch167, 5:0); + s(EmcAutoCalConfig8, 13:8, scratch167, 11:6); + s(EmcAutoCalConfig8, 18:16, scratch167, 14:12); + s(EmcAutoCalConfig8, 22:20, scratch167, 17:15); + s(EmcPmacroBgBiasCtrl0, 2:0, scratch167, 20:18); + s(EmcPmacroBgBiasCtrl0, 6:4, scratch167, 23:21); + s(McEmemArbTimingRcd, 5:0, scratch167, 29:24); + s(EmcPmacroTxPwrd3, 3:2, scratch167, 31:30); + s(EmcXm2CompPadCtrl2, 17:0, scratch168, 17:0); + s(McEmemArbTimingCcdmw, 5:0, scratch168, 23:18); + s(McEmemArbOverride, 27:27, scratch168, 24:24); + s(McEmemArbOverride, 26:26, scratch168, 25:25); + s(McEmemArbOverride, 16:16, scratch168, 26:26); + s(McEmemArbOverride, 10:10, scratch168, 27:27); + s(McEmemArbOverride, 4:4, scratch168, 28:28); + s(McEmemArbOverride, 3:3, scratch168, 29:29); + s(EmcPmacroTxPwrd3, 5:4, scratch168, 31:30); + s(EmcXm2CompPadCtrl3, 17:0, scratch169, 17:0); + s(EmcRext, 4:0, scratch169, 22:18); + s(EmcTClkStop, 4:0, scratch169, 27:23); + s(EmcPmacroTxPwrd3, 9:6, scratch169, 31:28); + s(EmcZcalWaitCnt, 10:0, scratch170, 10:0); + s(EmcZcalWaitCnt, 21:16, scratch170, 16:11); + s(EmcZcalWaitCnt, 31:31, scratch170, 17:17); + s(EmcWext, 4:0, scratch170, 22:18); + s(EmcRefctrl2, 0:0, scratch170, 23:23); + s(EmcRefctrl2, 26:24, scratch170, 26:24); + s(EmcRefctrl2, 31:31, scratch170, 27:27); + s(EmcPmacroTxPwrd3, 13:10, scratch170, 31:28); + s(EmcZcalMrwCmd, 7:0, scratch171, 7:0); + s(EmcZcalMrwCmd, 23:16, scratch171, 15:8); + s(EmcZcalMrwCmd, 31:30, scratch171, 17:16); + s(EmcWeDuration, 4:0, scratch171, 22:18); + s(EmcWsDuration, 4:0, scratch171, 27:23); + s(EmcPmacroTxPwrd3, 19:16, scratch171, 31:28); + s(EmcSwizzleRank0Byte0, 2:0, scratch172, 2:0); + s(EmcSwizzleRank0Byte0, 6:4, scratch172, 5:3); + s(EmcSwizzleRank0Byte0, 10:8, scratch172, 8:6); + s(EmcSwizzleRank0Byte0, 14:12, scratch172, 11:9); + s(EmcSwizzleRank0Byte0, 18:16, scratch172, 14:12); + s(EmcSwizzleRank0Byte0, 22:20, scratch172, 17:15); + s(EmcPutermWidth, 31:31, scratch172, 18:18); + s(EmcPutermWidth, 3:0, scratch172, 22:19); + s(McEmemArbTimingRrd, 4:0, scratch172, 27:23); + s(EmcPmacroTxPwrd3, 23:20, scratch172, 31:28); + s(EmcSwizzleRank0Byte1, 2:0, scratch173, 2:0); + s(EmcSwizzleRank0Byte1, 6:4, scratch173, 5:3); + s(EmcSwizzleRank0Byte1, 10:8, scratch173, 8:6); + s(EmcSwizzleRank0Byte1, 14:12, scratch173, 11:9); + s(EmcSwizzleRank0Byte1, 18:16, scratch173, 14:12); + s(EmcSwizzleRank0Byte1, 22:20, scratch173, 17:15); + s(McEmemArbTimingR2R, 4:0, scratch173, 22:18); + s(McEmemArbTimingW2W, 4:0, scratch173, 27:23); + s(EmcPmacroTxPwrd3, 27:24, scratch173, 31:28); + s(EmcSwizzleRank0Byte2, 2:0, scratch174, 2:0); + s(EmcSwizzleRank0Byte2, 6:4, scratch174, 5:3); + s(EmcSwizzleRank0Byte2, 10:8, scratch174, 8:6); + s(EmcSwizzleRank0Byte2, 14:12, scratch174, 11:9); + s(EmcSwizzleRank0Byte2, 18:16, scratch174, 14:12); + s(EmcSwizzleRank0Byte2, 22:20, scratch174, 17:15); + s(EmcPmacroTxPwrd3, 29:28, scratch174, 19:18); + s(EmcPmacroTxSelClkSrc0, 11:0, scratch174, 31:20); + s(EmcSwizzleRank0Byte3, 2:0, scratch175, 2:0); + s(EmcSwizzleRank0Byte3, 6:4, scratch175, 5:3); + s(EmcSwizzleRank0Byte3, 10:8, scratch175, 8:6); + s(EmcSwizzleRank0Byte3, 14:12, scratch175, 11:9); + s(EmcSwizzleRank0Byte3, 18:16, scratch175, 14:12); + s(EmcSwizzleRank0Byte3, 22:20, scratch175, 17:15); + s(EmcPmacroTxSelClkSrc0, 27:16, scratch175, 29:18); + s(EmcPmacroTxSelClkSrc1, 1:0, scratch175, 31:30); + s(EmcSwizzleRank1Byte0, 2:0, scratch176, 2:0); + s(EmcSwizzleRank1Byte0, 6:4, scratch176, 5:3); + s(EmcSwizzleRank1Byte0, 10:8, scratch176, 8:6); + s(EmcSwizzleRank1Byte0, 14:12, scratch176, 11:9); + s(EmcSwizzleRank1Byte0, 18:16, scratch176, 14:12); + s(EmcSwizzleRank1Byte0, 22:20, scratch176, 17:15); + s(EmcPmacroTxSelClkSrc1, 11:2, scratch176, 27:18); + s(EmcPmacroTxSelClkSrc1, 19:16, scratch176, 31:28); + s(EmcSwizzleRank1Byte1, 2:0, scratch177, 2:0); + s(EmcSwizzleRank1Byte1, 6:4, scratch177, 5:3); + s(EmcSwizzleRank1Byte1, 10:8, scratch177, 8:6); + s(EmcSwizzleRank1Byte1, 14:12, scratch177, 11:9); + s(EmcSwizzleRank1Byte1, 18:16, scratch177, 14:12); + s(EmcSwizzleRank1Byte1, 22:20, scratch177, 17:15); + s(EmcPmacroTxSelClkSrc1, 27:20, scratch177, 25:18); + s(EmcPmacroTxSelClkSrc3, 5:0, scratch177, 31:26); + s(EmcSwizzleRank1Byte2, 2:0, scratch178, 2:0); + s(EmcSwizzleRank1Byte2, 6:4, scratch178, 5:3); + s(EmcSwizzleRank1Byte2, 10:8, scratch178, 8:6); + s(EmcSwizzleRank1Byte2, 14:12, scratch178, 11:9); + s(EmcSwizzleRank1Byte2, 18:16, scratch178, 14:12); + s(EmcSwizzleRank1Byte2, 22:20, scratch178, 17:15); + s(EmcPmacroTxSelClkSrc3, 11:6, scratch178, 23:18); + s(EmcPmacroTxSelClkSrc3, 23:16, scratch178, 31:24); + s(EmcSwizzleRank1Byte3, 2:0, scratch179, 2:0); + s(EmcSwizzleRank1Byte3, 6:4, scratch179, 5:3); + s(EmcSwizzleRank1Byte3, 10:8, scratch179, 8:6); + s(EmcSwizzleRank1Byte3, 14:12, scratch179, 11:9); + s(EmcSwizzleRank1Byte3, 18:16, scratch179, 14:12); + s(EmcSwizzleRank1Byte3, 22:20, scratch179, 17:15); + s(EmcPmacroTxSelClkSrc3, 27:24, scratch179, 21:18); + s(EmcPmacroTxSelClkSrc2, 9:0, scratch179, 31:22); + s(EmcPmacroCmdBrickCtrlFdpd, 17:0, scratch180, 17:0); + s(EmcPmacroTxSelClkSrc2, 11:10, scratch180, 19:18); + s(EmcPmacroTxSelClkSrc2, 27:16, scratch180, 31:20); + s(EmcPmacroDataBrickCtrlFdpd, 17:0, scratch181, 17:0); + s(EmcPmacroTxSelClkSrc4, 11:0, scratch181, 29:18); + s(EmcPmacroTxSelClkSrc4, 17:16, scratch181, 31:30); + s(EmcFbioCfg7, 16:0, scratch182, 16:0); + s(McEmemArbRefpbBankCtrl, 6:0, scratch182, 23:17); + s(McEmemArbRefpbBankCtrl, 14:8, scratch182, 30:24); + s(McEmemArbRefpbBankCtrl, 31:31, scratch182, 31:31); + s(EmcDynSelfRefControl, 15:0, scratch183, 15:0); + s(EmcDynSelfRefControl, 31:31, scratch183, 16:16); + s(EmcPmacroTxSelClkSrc4, 27:18, scratch183, 26:17); + s(EmcPmacroTxSelClkSrc5, 4:0, scratch183, 31:27); + s(EmcDllCfg1, 16:0, scratch184, 16:0); + s(EmcPmacroTxSelClkSrc5, 11:5, scratch184, 23:17); + s(EmcPmacroTxSelClkSrc5, 23:16, scratch184, 31:24); + s(EmcPmacroPadCfgCtrl, 1:0, scratch185, 1:0); + s(EmcPmacroPadCfgCtrl, 6:5, scratch185, 3:2); + s(EmcPmacroPadCfgCtrl, 11:9, scratch185, 6:4); + s(EmcPmacroPadCfgCtrl, 13:13, scratch185, 7:7); + s(EmcPmacroPadCfgCtrl, 17:16, scratch185, 9:8); + s(EmcPmacroPadCfgCtrl, 21:20, scratch185, 11:10); + s(EmcPmacroPadCfgCtrl, 25:24, scratch185, 13:12); + s(EmcPmacroPadCfgCtrl, 30:28, scratch185, 16:14); + s(EmcPmacroTxSelClkSrc5, 27:24, scratch185, 20:17); + s(EmcPmacroCmdPadTxCtrl, 1:0, scratch185, 22:21); + s(EmcPmacroCmdPadTxCtrl, 5:4, scratch185, 24:23); + s(EmcPmacroCmdPadTxCtrl, 9:8, scratch185, 26:25); + s(EmcPmacroCmdPadTxCtrl, 13:12, scratch185, 28:27); + s(EmcPmacroCmdPadTxCtrl, 16:16, scratch185, 29:29); + s(EmcPmacroCmdPadTxCtrl, 21:20, scratch185, 31:30); + s(EmcRefresh, 15:0, scratch186, 15:0); + s(EmcCmdQ, 4:0, scratch186, 20:16); + s(EmcCmdQ, 10:8, scratch186, 23:21); + s(EmcCmdQ, 14:12, scratch186, 26:24); + s(EmcCmdQ, 28:24, scratch186, 31:27); + s(EmcAcpdControl, 15:0, scratch187, 15:0); + s(EmcAutoCalVrefSel1, 15:0, scratch187, 31:16); + s(EmcXm2CompPadCtrl, 1:0, scratch188, 1:0); + s(EmcXm2CompPadCtrl, 6:3, scratch188, 5:2); + s(EmcXm2CompPadCtrl, 9:9, scratch188, 6:6); + s(EmcXm2CompPadCtrl, 19:11, scratch188, 15:7); + s(EmcCfgDigDllPeriod, 15:0, scratch188, 31:16); + s(EmcCfgDigDll_1, 15:0, scratch189, 15:0); + s(EmcPreRefreshReqCnt, 15:0, scratch189, 31:16); + s(EmcPmacroCmdPadTxCtrl, 27:24, scratch190, 19:16); + s(EmcPmacroDataPadTxCtrl, 1:0, scratch190, 21:20); + s(EmcPmacroDataPadTxCtrl, 5:4, scratch190, 23:22); + s(EmcPmacroDataPadTxCtrl, 9:8, scratch190, 25:24); + s(EmcPmacroDataPadTxCtrl, 13:12, scratch190, 27:26); + s(EmcPmacroDataPadTxCtrl, 16:16, scratch190, 28:28); + s(EmcPmacroDataPadTxCtrl, 21:20, scratch190, 30:29); + s(EmcPmacroDataPadTxCtrl, 24:24, scratch190, 31:31); + s(EmcPmacroDataPadTxCtrl, 27:25, scratch191, 2:0); + + s(EmcPinGpio, 1:0, scratch8, 31:30); + s(EmcPinGpioEn, 1:0, scratch9, 31:30); + s(EmcDevSelect, 1:0, scratch10, 31:30); + s(EmcZcalWarmColdBootEnables, 1:0, scratch11, 31:30); + s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch12, 31:30); + s32(EmcBctSpare13, scratch31); + s32(EmcBctSpare12, scratch32); + s32(EmcBctSpare7, scratch33); + s32(EmcBctSpare6, scratch40); + s32(EmcBctSpare5, scratch42); + s32(EmcBctSpare4, scratch44); + s32(SwizzleRankByteEncode, scratch45); + s32(EmcBctSpare1, scratch47); + s32(EmcBctSpare0, scratch48); + s32(EmcBctSpare9, scratch50); + s32(EmcBctSpare8, scratch51); + s32(BootRomPatchData, scratch56); + s32(BootRomPatchControl, scratch57); + s(McClkenOverrideAllWarmBoot, 0:0, scratch58, 31:31); + s(EmcClkenOverrideAllWarmBoot, 0:0, scratch59, 30:30); + s(EmcMrsWarmBootEnable, 0:0, scratch59, 31:31); + s(ClearClk2Mc1, 0:0, scratch60, 30:30); + s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch60, 31:31); + s(ClkRstControllerPllmMisc2OverrideEnable, 0:0, scratch61, 30:30); + s(EmcDbgWriteMux, 0:0, scratch61, 31:31); + s(EmcExtraRefreshNum, 2:0, scratch62, 31:29); + s(PmcIoDpd3ReqWait, 2:0, scratch68, 30:28); + s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch68, 31:31); + s(MemoryType, 2:0, scratch69, 30:28); + s(PmcIoDpd4ReqWait, 2:0, scratch70, 30:28); + s(EmcTimingControlWait, 7:0, scratch86, 31:24); + s(EmcZcalWarmBootWait, 7:0, scratch87, 31:24); + s(WarmBootWait, 7:0, scratch88, 31:24); + s(EmcPinProgramWait, 7:0, scratch89, 31:24); + s(EmcAutoCalWait, 9:0, scratch101, 31:22); + s(SwizzleRankByteEncode, 15:0, scratch190, 15:0); switch (sdram->MemoryType) { case NvBootMemoryType_LpDdr2: + case NvBootMemoryType_LpDdr4: s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0); s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8); s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16); @@ -506,40 +760,58 @@ void sdram_lp0_save_params(const struct sdram_params *sdram) s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2); s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4); s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6); - s(EmcMrw1, 7:0, scratch7, 7:0); - s(EmcMrw1, 23:16, scratch7, 15:8); - s(EmcMrw1, 27:26, scratch7, 17:16); - s(EmcMrw1, 31:30, scratch7, 19:18); - s(EmcMrw2, 7:0, scratch8, 7:0); - s(EmcMrw2, 23:16, scratch8, 15:8); - s(EmcMrw2, 27:26, scratch8, 17:16); - s(EmcMrw2, 31:30, scratch8, 19:18); - s(EmcMrw3, 7:0, scratch9, 7:0); - s(EmcMrw3, 23:16, scratch9, 15:8); - s(EmcMrw3, 27:26, scratch9, 17:16); - s(EmcMrw3, 31:30, scratch9, 19:18); - s(EmcMrw4, 7:0, scratch10, 7:0); - s(EmcMrw4, 23:16, scratch10, 15:8); - s(EmcMrw4, 27:26, scratch10, 17:16); - s(EmcMrw4, 31:30, scratch10, 19:18); + s(EmcMrw6, 27:0, scratch8, 27:0); + s(EmcMrw6, 31:30, scratch8, 29:28); + s(EmcMrw8, 27:0, scratch9, 27:0); + s(EmcMrw8, 31:30, scratch9, 29:28); + s(EmcMrw9, 27:0, scratch10, 27:0); + s(EmcMrw9, 31:30, scratch10, 29:28); + s(EmcMrw10, 27:0, scratch11, 27:0); + s(EmcMrw10, 31:30, scratch11, 29:28); + s(EmcMrw12, 27:0, scratch12, 27:0); + s(EmcMrw12, 31:30, scratch12, 29:28); + s(EmcMrw13, 27:0, scratch13, 27:0); + s(EmcMrw13, 31:30, scratch13, 29:28); + s(EmcMrw14, 27:0, scratch14, 27:0); + s(EmcMrw14, 31:30, scratch14, 29:28); + s(EmcMrw1, 7:0, scratch15, 7:0); + s(EmcMrw1, 23:16, scratch15, 15:8); + s(EmcMrw1, 27:26, scratch15, 17:16); + s(EmcMrw1, 31:30, scratch15, 19:18); + s(EmcWarmBootMrwExtra, 7:0, scratch16, 7:0); + s(EmcWarmBootMrwExtra, 23:16, scratch16, 15:8); + s(EmcWarmBootMrwExtra, 27:26, scratch16, 17:16); + s(EmcWarmBootMrwExtra, 31:30, scratch16, 19:18); + s(EmcMrw2, 7:0, scratch17, 7:0); + s(EmcMrw2, 23:16, scratch17, 15:8); + s(EmcMrw2, 27:26, scratch17, 17:16); + s(EmcMrw2, 31:30, scratch17, 19:18); + s(EmcMrw3, 7:0, scratch18, 7:0); + s(EmcMrw3, 23:16, scratch18, 15:8); + s(EmcMrw3, 27:26, scratch18, 17:16); + s(EmcMrw3, 31:30, scratch18, 19:18); + s(EmcMrw4, 7:0, scratch19, 7:0); + s(EmcMrw4, 23:16, scratch19, 15:8); + s(EmcMrw4, 27:26, scratch19, 17:16); + s(EmcMrw4, 31:30, scratch19, 19:18); break; case NvBootMemoryType_Ddr3: s(EmcMrs, 13:0, scratch5, 13:0); s(EmcEmrs, 13:0, scratch5, 27:14); s(EmcMrs, 21:20, scratch5, 29:28); s(EmcMrs, 31:30, scratch5, 31:30); - s(EmcEmrs2, 13:0, scratch7, 13:0); - s(EmcEmrs, 21:20, scratch7, 15:14); - s(EmcEmrs, 31:30, scratch7, 17:16); - s(EmcEmrs2, 21:20, scratch7, 19:18); - s(EmcEmrs3, 13:0, scratch8, 13:0); - s(EmcEmrs2, 31:30, scratch8, 15:14); - s(EmcEmrs3, 21:20, scratch8, 17:16); - s(EmcEmrs3, 31:30, scratch8, 19:18); + s(EmcEmrs2, 13:0, scratch8, 13:0); + s(EmcEmrs3, 13:0, scratch8, 27:14); + s(EmcEmrs, 21:20, scratch8, 29:28); s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0); - s(EmcWarmBootMrsExtra, 31:30, scratch9, 15:14); - s(EmcWarmBootMrsExtra, 21:20, scratch9, 17:16); - s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 19:18); + s(EmcEmrs, 31:30, scratch9, 15:14); + s(EmcEmrs2, 21:20, scratch9, 17:16); + s(EmcEmrs2, 31:30, scratch9, 19:18); + s(EmcEmrs3, 21:20, scratch9, 21:20); + s(EmcEmrs3, 31:30, scratch9, 23:22); + s(EmcWarmBootMrsExtra, 31:30, scratch9, 25:24); + s(EmcWarmBootMrsExtra, 21:20, scratch9, 27:26); + s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 29:28); s(EmcMrs, 27:26, scratch10, 1:0); s(EmcEmrs, 27:26, scratch10, 3:2); s(EmcEmrs2, 27:26, scratch10, 5:4); @@ -548,81 +820,226 @@ void sdram_lp0_save_params(const struct sdram_params *sdram) s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9); s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10); s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11); - c(0, scratch116, 31:0); - c(0, scratch117, 31:0); break; default: printk(BIOS_CRIT, "ERROR: %s() unrecognized MemoryType %d!\n", __func__, sdram->MemoryType); } - s(McVideoProtectGpuOverride0, 31:0, secure_scratch8, 31:0); - s(McVideoProtectVprOverride, 3:0, secure_scratch9, 3:0); - s(McVideoProtectVprOverride, 11:6, secure_scratch9, 9:4); - s(McVideoProtectVprOverride, 23:14, secure_scratch9, 19:10); - s(McVideoProtectVprOverride, 26:26, secure_scratch9, 20:20); - s(McVideoProtectVprOverride, 31:29, secure_scratch9, 23:21); - s(EmcFbioCfg5, 19:16, secure_scratch9, 27:24); - s(McDisplaySnapRing, 1:0, secure_scratch9, 29:28); - s(McDisplaySnapRing, 31:31, secure_scratch9, 30:30); - s(EmcAdrCfg, 0:0, secure_scratch9, 31:31); - s(McVideoProtectGpuOverride1, 15:0, secure_scratch10, 15:0); - s(McEmemAdrCfgBankMask0, 15:0, secure_scratch10, 31:16); - s(McEmemAdrCfgBankMask1, 15:0, secure_scratch11, 15:0); - s(McEmemAdrCfgBankMask2, 15:0, secure_scratch11, 31:16); - s(McEmemCfg, 13:0, secure_scratch12, 13:0); - s(McEmemCfg, 31:31, secure_scratch12, 14:14); - s(McVideoProtectBom, 31:20, secure_scratch12, 26:15); - s(McVideoProtectVprOverride1, 1:0, secure_scratch12, 28:27); - s(McVideoProtectVprOverride1, 4:4, secure_scratch12, 29:29); - s(McVideoProtectBomAdrHi, 1:0, secure_scratch12, 31:30); - s(McVideoProtectSizeMb, 11:0, secure_scratch13, 11:0); - s(McSecCarveoutBom, 31:20, secure_scratch13, 23:12); - s(McEmemAdrCfgBankSwizzle3, 2:0, secure_scratch13, 26:24); - s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 28:27); - s(McSecCarveoutAdrHi, 1:0, secure_scratch13, 30:29); - s(McEmemAdrCfg, 0:0, secure_scratch13, 31:31); - s(McSecCarveoutSizeMb, 11:0, secure_scratch14, 11:0); - s(McMtsCarveoutBom, 31:20, secure_scratch14, 23:12); - s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 25:24); - s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch14, 26:26); - s(McMtsCarveoutRegCtrl, 0:0, secure_scratch14, 27:27); - s(McMtsCarveoutSizeMb, 11:0, secure_scratch15, 11:0); - s(McEmemAdrCfgDev0, 2:0, secure_scratch15, 14:12); - s(McEmemAdrCfgDev0, 9:8, secure_scratch15, 16:15); - s(McEmemAdrCfgDev0, 19:16, secure_scratch15, 20:17); - s(McEmemAdrCfgDev1, 2:0, secure_scratch15, 23:21); - s(McEmemAdrCfgDev1, 9:8, secure_scratch15, 25:24); - s(McEmemAdrCfgDev1, 19:16, secure_scratch15, 29:26); + s32(EmcCmdMappingByte, secure_scratch8); + s32(EmcPmacroBrickMapping0, secure_scratch9); + s32(EmcPmacroBrickMapping1, secure_scratch10); + s32(EmcPmacroBrickMapping2, secure_scratch11); + s32(McVideoProtectGpuOverride0, secure_scratch12); + s(EmcCmdMappingCmd0_0, 6:0, secure_scratch13, 6:0); + s(EmcCmdMappingCmd0_0, 14:8, secure_scratch13, 13:7); + s(EmcCmdMappingCmd0_0, 22:16, secure_scratch13, 20:14); + s(EmcCmdMappingCmd0_0, 30:24, secure_scratch13, 27:21); + s(McVideoProtectBomAdrHi, 1:0, secure_scratch13, 29:28); + s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 31:30); + s(EmcCmdMappingCmd0_1, 6:0, secure_scratch14, 6:0); + s(EmcCmdMappingCmd0_1, 14:8, secure_scratch14, 13:7); + s(EmcCmdMappingCmd0_1, 22:16, secure_scratch14, 20:14); + s(EmcCmdMappingCmd0_1, 30:24, secure_scratch14, 27:21); + s(McSecCarveoutAdrHi, 1:0, secure_scratch14, 29:28); + s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 31:30); + s(EmcCmdMappingCmd1_0, 6:0, secure_scratch15, 6:0); + s(EmcCmdMappingCmd1_0, 14:8, secure_scratch15, 13:7); + s(EmcCmdMappingCmd1_0, 22:16, secure_scratch15, 20:14); + s(EmcCmdMappingCmd1_0, 30:24, secure_scratch15, 27:21); + s(McGeneralizedCarveout5BomHi, 1:0, secure_scratch15, 29:28); + s(McGeneralizedCarveout3BomHi, 1:0, secure_scratch15, 31:30); + s(EmcCmdMappingCmd1_1, 6:0, secure_scratch16, 6:0); + s(EmcCmdMappingCmd1_1, 14:8, secure_scratch16, 13:7); + s(EmcCmdMappingCmd1_1, 22:16, secure_scratch16, 20:14); + s(EmcCmdMappingCmd1_1, 30:24, secure_scratch16, 27:21); + s(McGeneralizedCarveout2BomHi, 1:0, secure_scratch16, 29:28); + s(McGeneralizedCarveout4BomHi, 1:0, secure_scratch16, 31:30); + s(EmcCmdMappingCmd2_0, 6:0, secure_scratch17, 6:0); + s(EmcCmdMappingCmd2_0, 14:8, secure_scratch17, 13:7); + s(EmcCmdMappingCmd2_0, 22:16, secure_scratch17, 20:14); + s(EmcCmdMappingCmd2_0, 30:24, secure_scratch17, 27:21); + s(McGeneralizedCarveout1BomHi, 1:0, secure_scratch17, 29:28); + s(EmcAdrCfg, 0:0, secure_scratch17, 30:30); + s(EmcFbioSpare, 1:1, secure_scratch17, 31:31); + s(EmcCmdMappingCmd2_1, 6:0, secure_scratch18, 6:0); + s(EmcCmdMappingCmd2_1, 14:8, secure_scratch18, 13:7); + s(EmcCmdMappingCmd2_1, 22:16, secure_scratch18, 20:14); + s(EmcCmdMappingCmd2_1, 30:24, secure_scratch18, 27:21); + s(EmcFbioCfg8, 15:15, secure_scratch18, 28:28); + s(McEmemAdrCfg, 0:0, secure_scratch18, 29:29); + s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch18, 30:30); + s(McMtsCarveoutRegCtrl, 0:0, secure_scratch18, 31:31); + s(EmcCmdMappingCmd3_0, 6:0, secure_scratch19, 6:0); + s(EmcCmdMappingCmd3_0, 14:8, secure_scratch19, 13:7); + s(EmcCmdMappingCmd3_0, 22:16, secure_scratch19, 20:14); + s(EmcCmdMappingCmd3_0, 30:24, secure_scratch19, 27:21); + s(McGeneralizedCarveout2Cfg0, 6:3, secure_scratch19, 31:28); + s(EmcCmdMappingCmd3_1, 6:0, secure_scratch20, 6:0); + s(EmcCmdMappingCmd3_1, 14:8, secure_scratch20, 13:7); + s(EmcCmdMappingCmd3_1, 22:16, secure_scratch20, 20:14); + s(EmcCmdMappingCmd3_1, 30:24, secure_scratch20, 27:21); + s(McGeneralizedCarveout2Cfg0, 10:7, secure_scratch20, 31:28); + s(McGeneralizedCarveout4Cfg0, 26:0, secure_scratch39, 26:0); + s(McGeneralizedCarveout2Cfg0, 17:14, secure_scratch39, 30:27); + s(McVideoProtectVprOverride, 0:0, secure_scratch39, 31:31); + s(McGeneralizedCarveout5Cfg0, 26:0, secure_scratch40, 26:0); + s(McGeneralizedCarveout2Cfg0, 21:18, secure_scratch40, 30:27); + s(McVideoProtectVprOverride, 1:1, secure_scratch40, 31:31); + s(EmcCmdMappingCmd0_2, 6:0, secure_scratch41, 6:0); + s(EmcCmdMappingCmd0_2, 14:8, secure_scratch41, 13:7); + s(EmcCmdMappingCmd0_2, 22:16, secure_scratch41, 20:14); + s(EmcCmdMappingCmd0_2, 27:24, secure_scratch41, 24:21); + s(McGeneralizedCarveout1Cfg0, 6:3, secure_scratch41, 28:25); + s(McGeneralizedCarveout2Cfg0, 13:11, secure_scratch41, 31:29); + s(EmcCmdMappingCmd1_2, 6:0, secure_scratch42, 6:0); + s(EmcCmdMappingCmd1_2, 14:8, secure_scratch42, 13:7); + s(EmcCmdMappingCmd1_2, 22:16, secure_scratch42, 20:14); + s(EmcCmdMappingCmd1_2, 27:24, secure_scratch42, 24:21); + s(McGeneralizedCarveout1Cfg0, 13:7, secure_scratch42, 31:25); + s(EmcCmdMappingCmd2_2, 6:0, secure_scratch43, 6:0); + s(EmcCmdMappingCmd2_2, 14:8, secure_scratch43, 13:7); + s(EmcCmdMappingCmd2_2, 22:16, secure_scratch43, 20:14); + s(EmcCmdMappingCmd2_2, 27:24, secure_scratch43, 24:21); + s(McGeneralizedCarveout1Cfg0, 17:14, secure_scratch43, 28:25); + s(McGeneralizedCarveout3Cfg0, 13:11, secure_scratch43, 31:29); + s(EmcCmdMappingCmd3_2, 6:0, secure_scratch44, 6:0); + s(EmcCmdMappingCmd3_2, 14:8, secure_scratch44, 13:7); + s(EmcCmdMappingCmd3_2, 22:16, secure_scratch44, 20:14); + s(EmcCmdMappingCmd3_2, 27:24, secure_scratch44, 24:21); + s(McGeneralizedCarveout1Cfg0, 21:18, secure_scratch44, 28:25); + s(McVideoProtectVprOverride, 3:2, secure_scratch44, 30:29); + s(McVideoProtectVprOverride, 6:6, secure_scratch44, 31:31); + s(McEmemAdrCfgChannelMask, 31:9, secure_scratch45, 22:0); + s(McEmemAdrCfgDev0, 2:0, secure_scratch45, 25:23); + s(McEmemAdrCfgDev0, 9:8, secure_scratch45, 27:26); + s(McEmemAdrCfgDev0, 19:16, secure_scratch45, 31:28); + s(McEmemAdrCfgBankMask0, 31:10, secure_scratch46, 21:0); + s(McEmemAdrCfgDev1, 2:0, secure_scratch46, 24:22); + s(McEmemAdrCfgDev1, 9:8, secure_scratch46, 26:25); + s(McEmemAdrCfgDev1, 19:16, secure_scratch46, 30:27); + s(McVideoProtectVprOverride, 7:7, secure_scratch46, 31:31); + s(McEmemAdrCfgBankMask1, 31:10, secure_scratch47, 21:0); + s(McGeneralizedCarveout3Cfg0, 10:3, secure_scratch47, 29:22); + s(McVideoProtectVprOverride, 9:8, secure_scratch47, 31:30); + s(McEmemAdrCfgBankMask2, 31:10, secure_scratch48, 21:0); + s(McGeneralizedCarveout3Cfg0, 21:14, secure_scratch48, 29:22); + s(McVideoProtectVprOverride, 11:11, secure_scratch48, 30:30); + s(McVideoProtectVprOverride, 14:14, secure_scratch48, 31:31); + s(McVideoProtectGpuOverride1, 15:0, secure_scratch49, 15:0); + s(McEmemCfg, 13:0, secure_scratch49, 29:16); + s(McEmemCfg, 31:31, secure_scratch49, 30:30); + s(McVideoProtectVprOverride, 15:15, secure_scratch49, 31:31); + s(McGeneralizedCarveout3Bom, 31:17, secure_scratch50, 14:0); + s(McGeneralizedCarveout1Bom, 31:17, secure_scratch50, 29:15); + s(McVideoProtectVprOverride, 18:17, secure_scratch50, 31:30); + s(McGeneralizedCarveout4Bom, 31:17, secure_scratch51, 14:0); + s(McGeneralizedCarveout2Bom, 31:17, secure_scratch51, 29:15); + s(McVideoProtectVprOverride, 20:19, secure_scratch51, 31:30); + s(McGeneralizedCarveout5Bom, 31:17, secure_scratch52, 14:0); + s(McVideoProtectBom, 31:20, secure_scratch52, 26:15); + s(McVideoProtectVprOverride, 23:21, secure_scratch52, 29:27); + s(McVideoProtectVprOverride, 26:26, secure_scratch52, 30:30); + s(McVideoProtectVprOverride, 29:29, secure_scratch52, 31:31); + s(McVideoProtectSizeMb, 11:0, secure_scratch53, 11:0); + s(McSecCarveoutBom, 31:20, secure_scratch53, 23:12); + s(McVideoProtectVprOverride, 31:30, secure_scratch53, 25:24); + s(McVideoProtectVprOverride1, 1:0, secure_scratch53, 27:26); + s(McVideoProtectVprOverride1, 7:4, secure_scratch53, 31:28); + s(McSecCarveoutSizeMb, 11:0, secure_scratch54, 11:0); + s(McMtsCarveoutBom, 31:20, secure_scratch54, 23:12); + s(McVideoProtectVprOverride1, 15:8, secure_scratch54, 31:24); + s(McMtsCarveoutSizeMb, 11:0, secure_scratch55, 11:0); + s(McGeneralizedCarveout4Size128kb, 11:0, secure_scratch55, 23:12); + s(McVideoProtectVprOverride1, 16:16, secure_scratch55, 24:24); + s(McGeneralizedCarveout2Cfg0, 2:0, secure_scratch55, 27:25); + s(McGeneralizedCarveout2Cfg0, 25:22, secure_scratch55, 31:28); + s(McGeneralizedCarveout3Size128kb, 11:0, secure_scratch56, 11:0); + s(McGeneralizedCarveout2Size128kb, 11:0, secure_scratch56, 23:12); + s(McGeneralizedCarveout2Cfg0, 26:26, secure_scratch56, 24:24); + s(McGeneralizedCarveout1Cfg0, 2:0, secure_scratch56, 27:25); + s(McGeneralizedCarveout1Cfg0, 25:22, secure_scratch56, 31:28); + s(McGeneralizedCarveout1Size128kb, 11:0, secure_scratch57, 11:0); + s(McGeneralizedCarveout5Size128kb, 11:0, secure_scratch57, 23:12); + s(McGeneralizedCarveout1Cfg0, 26:26, secure_scratch57, 24:24); + s(McGeneralizedCarveout3Cfg0, 2:0, secure_scratch57, 27:25); + s(McGeneralizedCarveout3Cfg0, 25:22, secure_scratch57, 31:28); + s(McGeneralizedCarveout3Cfg0, 26:26, secure_scratch58, 0:0); + + s32(McGeneralizedCarveout1Access0, secure_scratch59); + s32(McGeneralizedCarveout1Access1, secure_scratch60); + s32(McGeneralizedCarveout1Access2, secure_scratch61); + s32(McGeneralizedCarveout1Access3, secure_scratch62); + s32(McGeneralizedCarveout1Access4, secure_scratch63); + s32(McGeneralizedCarveout2Access0, secure_scratch64); + s32(McGeneralizedCarveout2Access1, secure_scratch65); + s32(McGeneralizedCarveout2Access2, secure_scratch66); + s32(McGeneralizedCarveout2Access3, secure_scratch67); + s32(McGeneralizedCarveout2Access4, secure_scratch68); + s32(McGeneralizedCarveout3Access0, secure_scratch69); + s32(McGeneralizedCarveout3Access1, secure_scratch70); + s32(McGeneralizedCarveout3Access2, secure_scratch71); + s32(McGeneralizedCarveout3Access3, secure_scratch72); + s32(McGeneralizedCarveout3Access4, secure_scratch73); + s32(McGeneralizedCarveout4Access0, secure_scratch74); + s32(McGeneralizedCarveout4Access1, secure_scratch75); + s32(McGeneralizedCarveout4Access2, secure_scratch76); + s32(McGeneralizedCarveout4Access3, secure_scratch77); + s32(McGeneralizedCarveout4Access4, secure_scratch78); + s32(McGeneralizedCarveout5Access0, secure_scratch79); + s32(McGeneralizedCarveout5Access1, secure_scratch80); + s32(McGeneralizedCarveout5Access2, secure_scratch81); + s32(McGeneralizedCarveout5Access3, secure_scratch82); + s32(McGeneralizedCarveout1ForceInternalAccess0, secure_scratch84); + s32(McGeneralizedCarveout1ForceInternalAccess1, secure_scratch85); + s32(McGeneralizedCarveout1ForceInternalAccess2, secure_scratch86); + s32(McGeneralizedCarveout1ForceInternalAccess3, secure_scratch87); + s32(McGeneralizedCarveout1ForceInternalAccess4, secure_scratch88); + s32(McGeneralizedCarveout2ForceInternalAccess0, secure_scratch89); + s32(McGeneralizedCarveout2ForceInternalAccess1, secure_scratch90); + s32(McGeneralizedCarveout2ForceInternalAccess2, secure_scratch91); + s32(McGeneralizedCarveout2ForceInternalAccess3, secure_scratch92); + s32(McGeneralizedCarveout2ForceInternalAccess4, secure_scratch93); + s32(McGeneralizedCarveout3ForceInternalAccess0, secure_scratch94); + s32(McGeneralizedCarveout3ForceInternalAccess1, secure_scratch95); + s32(McGeneralizedCarveout3ForceInternalAccess2, secure_scratch96); + s32(McGeneralizedCarveout3ForceInternalAccess3, secure_scratch97); + s32(McGeneralizedCarveout3ForceInternalAccess4, secure_scratch98); + s32(McGeneralizedCarveout4ForceInternalAccess0, secure_scratch99); + s32(McGeneralizedCarveout4ForceInternalAccess1, secure_scratch100); + s32(McGeneralizedCarveout4ForceInternalAccess2, secure_scratch101); + s32(McGeneralizedCarveout4ForceInternalAccess3, secure_scratch102); + s32(McGeneralizedCarveout4ForceInternalAccess4, secure_scratch103); + s32(McGeneralizedCarveout5ForceInternalAccess0, secure_scratch104); + s32(McGeneralizedCarveout5ForceInternalAccess1, secure_scratch105); + s32(McGeneralizedCarveout5ForceInternalAccess2, secure_scratch106); + s32(McGeneralizedCarveout5ForceInternalAccess3, secure_scratch107); - c(0x1555555, sec_disable2, 25:0); + /* Locking PMC secure scratch register (8 ~ 15) for writing */ + c(0x5555, sec_disable2, 15:0); + /* Locking PMC secure scratch register (4~ 7) for both reading and writing */ c(0xff, sec_disable, 19:12); - c(0, scratch2, 31:0); - m(pllm_base, 15:0, scratch2, 15:0); - m(pllm_base, 20:20, scratch2, 16:16); - m(pllm_misc2, 2:0, scratch2, 19:17); - c(0, scratch35, 31:0); - m(pllm_misc1, 23:0, scratch35, 23:0); - m(pllm_misc1, 30:28, scratch35, 30:28); - c(0, scratch3, 31:0); + c32(0, scratch2); + s(PllMInputDivider, 7:0, scratch2, 7:0); + s(PllMFeedbackDivider, 7:0, scratch2, 15:8); + s(PllMPostDivider, 4:0, scratch2, 20:16); + s(PllMKVCO, 0:0, scratch2, 21:21); + s(PllMKCP, 1:0, scratch2, 23:22); + + c32(0, scratch35); + s(PllMSetupControl, 15:0, scratch35, 15:0); + + c32(0, scratch3); s(PllMInputDivider, 7:0, scratch3, 7:0); c(0x3e, scratch3, 15:8); - c(0, scratch3, 19:16); - s(PllMKVCO, 0:0, scratch3, 20:20); - s(PllMKCP, 1:0, scratch3, 22:21); - c(0, scratch36, 31:0); - s(PllMSetupControl, 23:0, scratch36, 23:0); - c(0, scratch4, 31:0); - s(PllMStableTime, 9:0, scratch4, 9:0); - s(PllMStableTime, 9:0, scratch4, 19:10); + c(0, scratch3, 20:16); + s(PllMKVCO, 0:0, scratch3, 21:21); + s(PllMKCP, 1:0, scratch3, 23:22); - s(PllMSelectDiv2, 0:0, pllm_wb0_override2, 27:27); - s(PllMKVCO, 0:0, pllm_wb0_override2, 26:26); - s(PllMKCP, 1:0, pllm_wb0_override2, 25:24); - s(PllMSetupControl, 23:0, pllm_wb0_override2, 23:0); - s(PllMFeedbackDivider, 7:0, pllm_wb0_override_freq, 15:8); - s(PllMInputDivider, 7:0, pllm_wb0_override_freq, 7:0); + c32(0, scratch36); + s(PllMSetupControl, 23:0, scratch36, 23:0); - c(3, pllp_wb0_override, 12:11); + c32(0, scratch4); + s(PllMStableTime, 9:0, scratch4, 9:0); } diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index 7d91bc5..829acb2 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -36,6 +36,8 @@ #include <string.h> #include <timer.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <soc/sdram.h> +#include <soc/sdram_configs.h> #include "chip.h" @@ -144,6 +146,10 @@ static void tegra210_init(void *chip_info) printk(BIOS_INFO, "chip %x rev %02x.%x\n", rev.chip_id, rev.major, rev.minor); + + /* Save sdram parameters to scratch regs to be used in LP0 resume */ + sdram_lp0_save_params(get_sdram_config()); + printk(BIOS_INFO, "sdram params saved.\n"); } struct chip_operations soc_nvidia_tegra210_ops = {

1 0

New patch to review for coreboot: foster: add sdram_configs.c
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10951 -gerrit commit 553c9dcb9f8a1f1c5e473e82751e848281afcc57 Author: Yen Lin <yelin(a)nvidia.com> Date: Wed Jun 17 17:06:23 2015 -0700 foster: add sdram_configs.c Add sdram_configs.c to both romstage and ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Foster Signed-off-by: Yen Lin <yelin(a)nvidi.com> Change-Id: Ib270c837ebe355c8d16072186c2b27d1c469fd48 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 73bc1abf2821176c21179880774887eec7c858b1 Original-Change-Id: Ia80a57a81e44542ee3d5437866071d50c8c5b8cb Original-Reviewed-on: https://chromium-review.googlesource.com/280290 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Tested-by: Yen Lin <yelin(a)nvidia.com> Original-Commit-Queue: Yen Lin <yelin(a)nvidia.com> --- src/mainboard/google/foster/Makefile.inc | 2 ++ src/mainboard/google/foster/sdram_configs.c | 42 +++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/src/mainboard/google/foster/Makefile.inc b/src/mainboard/google/foster/Makefile.inc index f9fd32b..7b2329e 100644 --- a/src/mainboard/google/foster/Makefile.inc +++ b/src/mainboard/google/foster/Makefile.inc @@ -39,11 +39,13 @@ verstage-y += reset.c romstage-y += reset.c romstage-y += romstage.c romstage-y += chromeos.c +romstage-y += sdram_configs.c ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-y += reset.c ramstage-y += chromeos.c +ramstage-y += sdram_configs.c bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/mainboard/google/foster/sdram_configs.c b/src/mainboard/google/foster/sdram_configs.c new file mode 100644 index 0000000..633a0bf --- /dev/null +++ b/src/mainboard/google/foster/sdram_configs.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <soc/sdram_configs.h> + +static struct sdram_params sdram_configs[] = { +#include "bct/sdram-samsung-3GB-204.inc" /* ram_code = 0000 */ +#include "bct/sdram-unused.inc" /* ram_code = 0001 */ +#include "bct/sdram-unused.inc" /* ram_code = 0010 */ +#include "bct/sdram-unused.inc" /* ram_code = 0011 */ +}; + +const struct sdram_params *get_sdram_config() +{ + uint32_t ramcode = sdram_get_ram_code(); + /* + * If we need to apply some special hacks to RAMCODE mapping (ex, by + * board_id), do that now. + */ + + printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode); + if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) || + sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) { + die("Invalid RAMCODE."); + } + + return &sdram_configs[ramcode]; +}

1 0

New patch to review for coreboot: smaug: ramstage: include sdram_configs.c
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10950 -gerrit commit 12de3144357f527db01043ff1bdc184eae9bf40b Author: Yen Lin <yelin(a)nvidia.com> Date: Fri Jun 12 15:40:52 2015 -0700 smaug: ramstage: include sdram_configs.c get_sdram_config() (in sdram_configs.c) will be needed in ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Smaug Change-Id: I2920f8687b6a801a91dc5b5b50fc5637057e4321 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4d3092e360b26cbda41549452aeeba9ffc0b92ed Original-Change-Id: I43a20f3178cbf5b57a3a9ca7391856787aa8cdb8 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277373 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/smaug/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/smaug/Makefile.inc b/src/mainboard/google/smaug/Makefile.inc index 1e84d54..b2284fd 100644 --- a/src/mainboard/google/smaug/Makefile.inc +++ b/src/mainboard/google/smaug/Makefile.inc @@ -45,6 +45,7 @@ ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-y += reset.c ramstage-y += pmic.c +ramstage-y += sdram_configs.c bootblock-y += memlayout.ld romstage-y += memlayout.ld

1 0

New patch to review for coreboot: smaug: Use VNBN_FLASH instead of VBNV_EC
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10949 -gerrit commit c03ed7b62cc95badbb9a6a618d7005f08a2dbe6a Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 13 20:46:40 2015 -0700 smaug: Use VNBN_FLASH instead of VBNV_EC CQ-DEPEND=CL:285312 BUG=chrome-os-partner:36613 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ib90333e3331a90b4539d49e1a72833fe3385879f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 042fc1a451081780f8af35af6943130f6412ca5f Original-Change-Id: I729996c04d8bd6a627421803a59037d7c47a3e98 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285345 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/smaug/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index 73a40e1..29dae4f 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -23,13 +23,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_16384 - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_FLASH + select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_I2C select EC_GOOGLE_CHROMEEC_I2C_PROTO3 select EC_SOFTWARE_SYNC select MAINBOARD_DO_NATIVE_VGA_INIT select SPI_FLASH + select SPI_FLASH_WINBOND select SOC_NVIDIA_TEGRA210 select MAINBOARD_DO_DSI_INIT select MAINBOARD_HAS_CHROMEOS

1 0

New patch to review for coreboot: t210: Reorganize memlayout.ld
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10948 -gerrit commit c7624296be1b2cb857830fc6c89e79ac1a5659c2 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 13 20:45:21 2015 -0700 t210: Reorganize memlayout.ld Take up space from PRERAM_CBMEM_CACHE and increase verstage and romstage sizes. BUG=chrome-os-partner:36613 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I7fdd6c08f3ca1998a6220edd80a570816ec65ab5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: cce3d7baa7446e227d3da41341d9e273d4195299 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285344 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Change-Id: I6d97a60b26fbbb29a875285c46724fb43b5fe5ab Original-Reviewed-on: https://chromium-review.googlesource.com/285533 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld index 26c6e34..dc25775 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -33,13 +33,13 @@ SECTIONS { SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 8K) - PRERAM_CBFS_CACHE(0x40002000, 72K) - VBOOT2_WORK(0x40014000, 16K) - STACK(0x40018000, 2K) - TIMESTAMP(0x40018800, 2K) - BOOTBLOCK(0x40019000, 24K) - VERSTAGE(0x4001F000, 52K) - ROMSTAGE(0x4002C000, 80K) + PRERAM_CBFS_CACHE(0x40002000, 36K) + VBOOT2_WORK(0x4000B000, 16K) + STACK(0x4000F000, 2K) + TIMESTAMP(0x4000F800, 2K) + BOOTBLOCK(0x40010000, 24K) + VERSTAGE(0x40016000, 64K) + ROMSTAGE(0x40026000, 104K) SRAM_END(0x40040000) DRAM_START(0x80000000)

1 0

New patch to review for coreboot: t210: SPI driver cleanup
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10947 -gerrit commit 8cd41b901adb7f0f1180a61aa7f06a65e07508aa Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 13 10:14:16 2015 -0700 t210: SPI driver cleanup 1. Get rid of spi_delay - Instead have a tight loop to check for the spi status 2. The first check for SPI operation complete i.e. FIFOs have been processed is the SPI_STATUS_RDY bit. Thus, tegra_spi_wait should check for this bit before reading BLOCK_COUNT or any other fifo count field. 3. Flush both TX and RX FIFOs for SEND and RECV operations for PIO and DMA. 4. No need to check for rx_fifo_count == spi_byte_count to determine pio_finish operation. RDY bit should be sufficient to ensure that the SPI operation is complete. Added assert to ensure we never hit the case of RDY bit being set, yet rx_fifo_count != spi_byte_count for PIO. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test runs successfully for 10K+ iterations. Change-Id: I1adb9672c1503b562309a8bc6c22fe7d2271768e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: de1515605e17e0c6b81874f9f3c49fd0c1b92756 Original-Change-Id: I5853d0df1bfd6020a17e478040bc4c1834563fe4 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285141 Original-Reviewed-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/spi.c | 99 ++++++++++++++++++------------------------- 1 file changed, 41 insertions(+), 58 deletions(-) diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index ffb4d47..5946ef0 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -212,12 +212,6 @@ static struct tegra_spi_channel * const to_tegra_spi(int bus) { return &tegra_spi_channels[bus - 1]; } -static unsigned int tegra_spi_speed(unsigned int bus) -{ - /* FIXME: implement this properly, for now use max value (50MHz) */ - return 50000000; -} - int spi_claim_bus(struct spi_slave *slave) { struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; @@ -329,36 +323,22 @@ static inline unsigned int spi_byte_count(struct tegra_spi_channel *spi) (SPI_STATUS_BLOCK_COUNT << SPI_STATUS_BLOCK_COUNT_SHIFT); } -/* - * This calls udelay() with a calculated value based on the SPI speed and - * number of bytes remaining to be transferred. It assumes that if the - * calculated delay period is less than MIN_DELAY_US then it is probably - * not worth the overhead of yielding. - */ -#define MIN_DELAY_US 250 -static void spi_delay(struct tegra_spi_channel *spi, - unsigned int bytes_remaining) -{ - unsigned int ns_per_byte, delay_us; - - ns_per_byte = 1000000000 / (tegra_spi_speed(spi->slave.bus) / 8); - delay_us = (ns_per_byte * bytes_remaining) / 1000; - - if (delay_us < MIN_DELAY_US) - return; - - udelay(delay_us); -} - static void tegra_spi_wait(struct tegra_spi_channel *spi) { - unsigned int count, dma_blk; + uint32_t dma_blk_count = 1 + (read32(&spi->regs->dma_blk) & + (SPI_DMA_CTL_BLOCK_SIZE_MASK << + SPI_DMA_CTL_BLOCK_SIZE_SHIFT)); - dma_blk = 1 + (read32(&spi->regs->dma_blk) & - (SPI_DMA_CTL_BLOCK_SIZE_MASK << SPI_DMA_CTL_BLOCK_SIZE_SHIFT)); + while ((read32(&spi->regs->trans_status) & SPI_STATUS_RDY) != + SPI_STATUS_RDY) + ; - while ((count = spi_byte_count(spi)) != dma_blk) - spi_delay(spi, dma_blk - count); + /* + * If RDY bit is set, we should never encounter the condition that + * blocks processed is not equal to the number programmed in dma_blk + * register. + */ + ASSERT(spi_byte_count(spi) == dma_blk_count); } @@ -367,24 +347,32 @@ static int fifo_error(struct tegra_spi_channel *spi) return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; } +static void flush_fifos(struct tegra_spi_channel *spi) +{ + const uint32_t flush_mask = SPI_FIFO_STATUS_TX_FIFO_FLUSH | + SPI_FIFO_STATUS_RX_FIFO_FLUSH; + + uint32_t fifo_status = read32(&spi->regs->fifo_status); + fifo_status |= flush_mask; + write32(&spi->regs->fifo_status, flush_mask); + + while (read32(&spi->regs->fifo_status) & flush_mask) + ; +} + static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, unsigned int bytes, enum spi_direction dir) { u8 *p = spi->out_buf; unsigned int todo = MIN(bytes, SPI_MAX_TRANSFER_BYTES_FIFO); - u32 flush_mask, enable_mask; + u32 enable_mask; - if (dir == SPI_SEND) { - flush_mask = SPI_FIFO_STATUS_TX_FIFO_FLUSH; + flush_fifos(spi); + + if (dir == SPI_SEND) enable_mask = SPI_CMD1_TX_EN; - } else { - flush_mask = SPI_FIFO_STATUS_RX_FIFO_FLUSH; + else enable_mask = SPI_CMD1_RX_EN; - } - - setbits_le32(&spi->regs->fifo_status, flush_mask); - while (read32(&spi->regs->fifo_status) & flush_mask) - ; /* * BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and @@ -439,24 +427,17 @@ static inline u32 rx_fifo_count(struct tegra_spi_channel *spi) static int tegra_spi_pio_finish(struct tegra_spi_channel *spi) { u8 *p = spi->in_buf; - struct stopwatch sw; clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); - /* - * Allow some time in case the Rx FIFO does not yet have - * all packets pushed into it. See chrome-os-partner:24215. - */ - stopwatch_init_usecs_expire(&sw, SPI_FIFO_XFER_TIMEOUT_US); - do { - if (rx_fifo_count(spi) == spi_byte_count(spi)) - break; - } while (!stopwatch_expired(&sw)); + ASSERT(rx_fifo_count(spi) == spi_byte_count(spi)); - while (!(read32(&spi->regs->fifo_status) & - SPI_FIFO_STATUS_RX_FIFO_EMPTY)) { - *p = read8(&spi->regs->rx_fifo); - p++; + if (p) { + while (!(read32(&spi->regs->fifo_status) & + SPI_FIFO_STATUS_RX_FIFO_EMPTY)) { + *p = read8(&spi->regs->rx_fifo); + p++; + } } if (fifo_error(spi)) { @@ -509,6 +490,8 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, todo = ALIGN_DOWN(todo, TEGRA_DMA_ALIGN_BYTES); wcount = ALIGN_DOWN(todo - TEGRA_DMA_ALIGN_BYTES, TEGRA_DMA_ALIGN_BYTES); + flush_fifos(spi); + if (dir == SPI_SEND) { spi->dma_out = dma_claim(); if (!spi->dma_out) @@ -605,7 +588,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) if (spi->dma_in) { while ((read32(&spi->dma_in->regs->dma_byte_sta) < todo) || dma_busy(spi->dma_in)) - ; /* this shouldn't take long, no udelay */ + ; dma_stop(spi->dma_in); clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); /* Disable secure access for the channel. */ @@ -617,7 +600,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) if (spi->dma_out) { while ((read32(&spi->dma_out->regs->dma_byte_sta) < todo) || dma_busy(spi->dma_out)) - spi_delay(spi, todo - spi_byte_count(spi)); + ; clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); dma_stop(spi->dma_out); /* Disable secure access for the channel. */

1 0

New patch to review for coreboot: t210: Correct dma_busy function
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10946 -gerrit commit 22f574f24111ff42e20d863313e6fe4bc193464d Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 13 09:48:52 2015 -0700 t210: Correct dma_busy function In case of continuous mode, use STA_ACTIVITY bit to determine if DMA operation is complete. However, in case of ONCE mode, use STA_BSY bit to determine if DMA operation on the channel is complete. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test runs fine for 10K+ iterations Change-Id: If98f195481b18c402bd9cac353080c317e0e1168 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 927026db6fd910dac32dc218f28efcbc7b788b4e Original-Change-Id: Ib66bedfb413f948728a4f9cffce9d9c3feb0bfda Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285140 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/dma.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c index 9f04e97..fb98692 100644 --- a/src/soc/nvidia/tegra210/dma.c +++ b/src/soc/nvidia/tegra210/dma.c @@ -69,9 +69,21 @@ int dma_busy(struct apb_dma_channel * const channel) * In continuous mode, the BSY_n bit in APB_DMA_STATUS and * BSY in APBDMACHAN_CHANNEL_n_STA_0 will remain set as '1' so long * as the channel is enabled. So for this function we'll use the - * DMA_ACTIVITY bit. + * DMA_ACTIVITY bit in case of continuous mode. + * + * However, for ONCE mode, the BSY_n bit in APB_DMA_STATUS will be used + * to determine end of dma operation. */ - return read32(&channel->regs->sta) & APB_STA_DMA_ACTIVITY ? 1 : 0; + uint32_t bit; + + if (read32(&channel->regs->csr) & APB_CSR_ONCE) + /* Once mode */ + bit = APB_STA_BSY; + else + /* Continuous mode */ + bit = APB_STA_DMA_ACTIVITY; + + return read32(&channel->regs->sta) & bit ? 1 : 0; } /* claim a DMA channel */ struct apb_dma_channel * const dma_claim(void)

1 0

New patch to review for coreboot: smaug: Increase drive strength for QSPI Pinmux
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10945 -gerrit commit bb259358dc034e241d0b83cd294d2c4a82229acd Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 13 09:46:56 2015 -0700 smaug: Increase drive strength for QSPI Pinmux Change the drive strength for QSPI Pinmux to DRIVE_STRENGTH_2 as per recommendations from nVidia hardware engineers. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5a7b94acb57bbc21d277a49fd0a6b892638fc0ca Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 58d085e6acbcd0fd355b1c7efc10606312caf8e8 Original-Change-Id: I03dd288d2e335d40c83feaec7efbf10a7d3bf1e6 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284959 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/smaug/bootblock.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/smaug/bootblock.c b/src/mainboard/google/smaug/bootblock.c index ee535c2..77c8441 100644 --- a/src/mainboard/google/smaug/bootblock.c +++ b/src/mainboard/google/smaug/bootblock.c @@ -42,12 +42,16 @@ static const struct pad_config pmic_pads[] = { /********************** SPI Flash *****************************/ static const struct pad_config spiflash_pads[] = { /* QSPI fLash: mosi, miso, clk, cs0, hold, wp */ - PAD_CFG_SFIO(QSPI_IO0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI), - PAD_CFG_SFIO(QSPI_IO1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI), - PAD_CFG_SFIO(QSPI_SCK, PINMUX_INPUT_ENABLE, QSPI), - PAD_CFG_SFIO(QSPI_CS_N, PINMUX_INPUT_ENABLE, QSPI), - PAD_CFG_SFIO(QSPI_IO2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI), - PAD_CFG_SFIO(QSPI_IO3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI), + PAD_CFG_SFIO(QSPI_IO0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP | + PINMUX_DRIVE_2X, QSPI), + PAD_CFG_SFIO(QSPI_IO1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP | + PINMUX_DRIVE_2X, QSPI), + PAD_CFG_SFIO(QSPI_SCK, PINMUX_INPUT_ENABLE | PINMUX_DRIVE_2X, QSPI), + PAD_CFG_SFIO(QSPI_CS_N, PINMUX_INPUT_ENABLE | PINMUX_DRIVE_2X, QSPI), + PAD_CFG_SFIO(QSPI_IO2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP | + PINMUX_DRIVE_2X, QSPI), + PAD_CFG_SFIO(QSPI_IO3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP | + PINMUX_DRIVE_2X, QSPI), }; /********************* TPM ************************************/

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2015