coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: t210: Add PINMUX macros for drive strength
by gerrit＠coreboot.org 16 Jul '15

16 Jul '15

the following patch was just integrated into master: commit 0aa1d50be7731fb7010543c3a63c06e29d6bfbd8 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 13 09:48:06 2015 -0700 t210: Add PINMUX macros for drive strength BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ic606838639d33242b227fece9cbb019d8f3b3729 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 805831489ad80e4ed335ece458f81238af704876 Original-Change-Id: I54a730c3b97c3603a5b1981089913c58af2a42db Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284958 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/10944 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10944 for details. -gerrit

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Patch merged into coreboot/master: toolchain: Add -mgeneral-regs-only to CFLAGS for arm64
by gerrit＠coreboot.org 16 Jul '15

16 Jul '15

the following patch was just integrated into master: commit 5668e262ffa14ea202e65d6f50e37efe1670d965 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 14 12:03:11 2015 -0700 toolchain: Add -mgeneral-regs-only to CFLAGS for arm64 BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel prompt on smaug Change-Id: I7eb75b215798a63157bae04d9d44dbd6f95a5715 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6e5ecf9b45fa35e3c87bf6ef4bd2ea01680c8826 Original-Change-Id: I36a20d65d7ccaa21fdeb6070d43c2bb0ae22a16b Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285553 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/10959 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10959 for details. -gerrit

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Patch set updated for coreboot: intel raminit: support two DIMMs per channel
by Patrick Rudolph 16 Jul '15

16 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10960 -gerrit commit b604e0c7888575ec5790df14115cf67d1e75ab95 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Jul 16 20:48:16 2015 +0200 intel raminit: support two DIMMs per channel Issue observed: Two memory DIMMs are placed in the same channel, but only one shows up. The SPD is read and printed, but the first DIMM isn't recognized any more. Due to an existing but unconfigured memory DIMM the timB test failed. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H * DIMMs: * crucial 2GB 256Mx64 CT2566aBA160BJ * corsair 8GB CMZ16GX3M2A1866C9 Problem description: The channel's rankmap was overwritten by the second slot's rankmap. Problem solution: Logical OR the channel's rankmap with every slot's rankmap. Final testing result: The DIMM is recognized and can be properly configured and used. The timB test doesn't fail any more. Change-Id: I17a205ff4d344c13d9ddfe71aaae2f3cef047665 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 850ce93..0708f47 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -280,7 +280,7 @@ static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, ctrl->auto_self_refresh &= dimm->dimm[channel][slot].flags.asr; ctrl->extended_temperature_range &= dimm->dimm[channel][slot].flags.ext_temp_refresh; - ctrl->rankmap[channel] = ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); + ctrl->rankmap[channel] |= ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); printk(BIOS_DEBUG, "rankmap[%d] = 0x%x\n", channel, ctrl->rankmap[channel]); } if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc)

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New patch to review for coreboot: intel raminit: support two DIMMs per channel
by Patrick Rudolph 16 Jul '15

16 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10960 -gerrit commit 6df08d5d3efa0f47ad125f973514f02e0e68fedb Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Jul 16 20:48:16 2015 +0200 intel raminit: support two DIMMs per channel Issue observed: Two memory DIMMs are placed in the same channel, but only one shows up. The SPD is read and printed, but the first DIMM isn't recognized any more. Due to an existing but unconfigured memory DIMM the timB tests failed. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H * DIMMs: * crucial 2GB 256Mx64 CT2566aBA160BJ * corsair 8GB CMZ16GX3M2A1866C9 Problem description: The channel's rankmap was overwritten by the second slot's rankmap. Problem solution: Logical OR the channel's rankmap with every slot's rankmap. Final testing result: The DIMM is recognized and can be properly configured and used. The timB tests doesn't fail any more. Change-Id: I17a205ff4d344c13d9ddfe71aaae2f3cef047665 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index d56d60d..790f47c 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -280,7 +280,7 @@ static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, ctrl->auto_self_refresh &= dimm->dimm[channel][slot].flags.asr; ctrl->extended_temperature_range &= dimm->dimm[channel][slot].flags.ext_temp_refresh; - ctrl->rankmap[channel] = ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); + ctrl->rankmap[channel] |= ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); printk(BIOS_DEBUG, "rankmap[%d] = 0x%x\n", channel, ctrl->rankmap[channel]); } if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc)

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Patch set updated for coreboot: intel raminit: rewrite timB high adjust calculation
by Patrick Rudolph 16 Jul '15

16 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10890 -gerrit commit 4395d87649780c3534fb5a629662e3d38bd3c2ec Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jul 12 17:01:42 2015 +0200 intel raminit: rewrite timB high adjust calculation Found while doing code review. Simplify the code by using a loop for positive and negative phase adjustments. Change-Id: I0980443d0d2815bccef969709fddecc07d61a788 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 23 +++++++++++----------- 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 850ce93..d56d60d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -2288,18 +2288,17 @@ static int get_timB_high_adjust(u64 val) if (val == 0xffffffffffffffffLL) return 0; - if (val >= 0xfffffffffffff000LL) - return 3; - if (val >= 0xfffffffffff00000LL) - return -1; - if (val >= 0xfffffff000000000LL) - return -2; - if (val >= 0xfff0000000000000LL) - return -3; - - for (i = 0; i < 8; i++) - if (val >> (8 * (7 - i) + 4)) - return i; + if (val >= 0xf000000000000000LL) { + /* needs negative adjustment */ + for (i = 0; i < 8; i++) + if (val << (8 * (7 - i) + 4)) + return -i; + } else { + /* needs positive adjustment */ + for (i = 0; i < 8; i++) + if (val >> (8 * (7 - i) + 4)) + return i; + } return 8; }

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New patch to review for coreboot: toolchain: Add -mgeneral-regs-only to CFLAGS for arm64
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10959 -gerrit commit 5e19016f1785c3fc07af6d40d71b76821f22aaf4 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 14 12:03:11 2015 -0700 toolchain: Add -mgeneral-regs-only to CFLAGS for arm64 BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel prompt on smaug Change-Id: I7eb75b215798a63157bae04d9d44dbd6f95a5715 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6e5ecf9b45fa35e3c87bf6ef4bd2ea01680c8826 Original-Change-Id: I36a20d65d7ccaa21fdeb6070d43c2bb0ae22a16b Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285553 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- toolchain.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchain.inc b/toolchain.inc index 47e407f..89bc55c 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -64,7 +64,7 @@ ARCHDIR-mips := mips CFLAGS_arm += -ffunction-sections -fdata-sections -CFLAGS_arm64 += -ffunction-sections -fdata-sections +CFLAGS_arm64 += -ffunction-sections -fdata-sections -mgeneral-regs-only CFLAGS_mips += -mips32r2 -G 0 -ffunction-sections -fdata-sections CFLAGS_mips += -mno-abicalls -fno-pic

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New patch to review for coreboot: libpayload: usb: Add support for SuperSpeed hubs
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10958 -gerrit commit e60c821b68cb703536d84dd159db62e57c5144ce Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Jul 9 16:29:10 2015 -0700 libpayload: usb: Add support for SuperSpeed hubs This patch adds support for the SuperSpeed half of USB 3.0 hubs, which previously prevented SuperSpeed devices behind those hubs from working. BRANCH=None BUG=chrome-os-partner:39877 TEST=Played around with multiple hubs and devices on Oak and Falco, can no longer find a combination that doesn't work. Change-Id: I20815be95769e33d399b7ad91c3020687234e059 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3db96ece20d2304e7f6f6aa333cf114037c48a3e Original-Change-Id: I2dd6c9c3607a24a7d78c308911e3d254d5f8d91d Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284577 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: chunfeng yun <chunfeng.yun(a)mediatek.com> --- payloads/libpayload/drivers/usb/usb.c | 12 +++----- payloads/libpayload/drivers/usb/usbhub.c | 42 ++++++++++++++++++++++---- payloads/libpayload/drivers/usb/xhci_debug.c | 4 +-- payloads/libpayload/drivers/usb/xhci_devconf.c | 6 ++-- 4 files changed, 46 insertions(+), 18 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index e00d92f..69d1c39 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -556,17 +556,13 @@ set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr) #endif break; case hub_device: - if (speed < SUPER_SPEED) { - usb_debug ("hub (2.0)\n"); + usb_debug ("hub\n"); #if IS_ENABLED(CONFIG_LP_USB_HUB) - dev->init = usb_hub_init; - return dev->address; + dev->init = usb_hub_init; + return dev->address; #else - usb_debug ("NOTICE: USB hub support not compiled in\n"); + usb_debug ("NOTICE: USB hub support not compiled in\n"); #endif - } else { - usb_debug ("hub (3.0) - not yet supported!\n"); - } break; case cdc_device: usb_debug("CDC\n"); diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c index e12fd92..f75141e 100644 --- a/payloads/libpayload/drivers/usb/usbhub.c +++ b/payloads/libpayload/drivers/usb/usbhub.c @@ -42,6 +42,8 @@ #define SEL_PORT_RESET 0x4 #define SEL_PORT_POWER 0x8 #define SEL_C_PORT_CONNECTION 0x10 +/* request type (USB 3.0 hubs only) */ +#define SET_HUB_DEPTH 12 static int usb_hub_port_status_changed(usbdev_t *const dev, const int port) @@ -93,17 +95,21 @@ usb_hub_port_speed(usbdev_t *const dev, const int port) unsigned short buf[2]; int ret = get_status (dev, port, DR_PORT, sizeof(buf), buf); if (ret >= 0 && (buf[0] & PORT_ENABLE)) { - /* bit 10 9 + /* SuperSpeed hubs can only have SuperSpeed devices. */ + if (dev->speed == SUPER_SPEED) + return SUPER_SPEED; + + /*[bit] 10 9 (USB 2.0 port status word) * 0 0 full speed * 0 1 low speed * 1 0 high speed - * 1 1 super speed (hack, not in spec!) + * 1 1 invalid */ ret = (buf[0] >> 9) & 0x3; - } else { - ret = -1; + if (ret != 0x3) + return ret; } - return ret; + return -1; } static int @@ -118,6 +124,27 @@ usb_hub_start_port_reset(usbdev_t *const dev, const int port) return set_feature (dev, port, SEL_PORT_RESET, DR_PORT); } +static void usb_hub_set_hub_depth(usbdev_t *const dev) +{ + dev_req_t dr = { + .bmRequestType = gen_bmRequestType(host_to_device, + class_type, dev_recp), + .bRequest = SET_HUB_DEPTH, + .wValue = 0, + .wIndex = 0, + .wLength = 0, + }; + usbdev_t *parent = dev; + while (parent->hub > 0) { + parent = dev->controller->devices[parent->hub]; + dr.wValue++; + } + int ret = dev->controller->control(dev, OUT, sizeof(dr), &dr, 0, NULL); + if (ret < 0) + usb_debug("Failed SET_HUB_DEPTH(%d) on hub %d: %d\n", + dr.wValue, dev->address, ret); +} + static const generic_hub_ops_t usb_hub_ops = { .hub_status_changed = NULL, .port_status_changed = usb_hub_port_status_changed, @@ -134,13 +161,16 @@ static const generic_hub_ops_t usb_hub_ops = { void usb_hub_init(usbdev_t *const dev) { + int type = dev->speed == SUPER_SPEED ? 0x2a : 0x29; /* similar enough */ hub_descriptor_t desc; /* won't fit the whole thing, we don't care */ if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type, - dev_recp), 0x29, 0, &desc, sizeof(desc)) != sizeof(desc)) { + dev_recp), type, 0, &desc, sizeof(desc)) != sizeof(desc)) { usb_debug("get_descriptor(HUB) failed\n"); usb_detach_device(dev->controller, dev->address); return; } + if (dev->speed == SUPER_SPEED) + usb_hub_set_hub_depth(dev); generic_hub_init(dev, desc.bNbrPorts, &usb_hub_ops); } diff --git a/payloads/libpayload/drivers/usb/xhci_debug.c b/payloads/libpayload/drivers/usb/xhci_debug.c index d50f6db..f8d2309 100644 --- a/payloads/libpayload/drivers/usb/xhci_debug.c +++ b/payloads/libpayload/drivers/usb/xhci_debug.c @@ -80,8 +80,8 @@ xhci_dump_devctx(const devctx_t *const dc, const u32 ctx_mask) int i; if (ctx_mask & 1) xhci_dump_slotctx(dc->slot); - for (i = 0; i < SC_GET(CTXENT, dc->slot); ++i) { - if (ctx_mask & (2 << i)) + for (i = 1; i <= SC_GET(CTXENT, dc->slot); ++i) { + if (ctx_mask & (1 << i)) xhci_dump_epctx(dc->ep[i]); } } diff --git a/payloads/libpayload/drivers/usb/xhci_devconf.c b/payloads/libpayload/drivers/usb/xhci_devconf.c index 32cd291..ead130e 100644 --- a/payloads/libpayload/drivers/usb/xhci_devconf.c +++ b/payloads/libpayload/drivers/usb/xhci_devconf.c @@ -267,10 +267,11 @@ _free_ic_return: static int xhci_finish_hub_config(usbdev_t *const dev, inputctx_t *const ic) { + int type = dev->speed == SUPER_SPEED ? 0x2a : 0x29; /* similar enough */ hub_descriptor_t desc; if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type, - dev_recp), 0x29, 0, &desc, sizeof(desc)) != sizeof(desc)) { + dev_recp), type, 0, &desc, sizeof(desc)) != sizeof(desc)) { xhci_debug("Failed to fetch hub descriptor\n"); return COMMUNICATION_ERROR; } @@ -386,8 +387,9 @@ xhci_finish_device_config(usbdev_t *const dev) ic->dev.slot->f1 = di->ctx.slot->f1; ic->dev.slot->f2 = di->ctx.slot->f2; ic->dev.slot->f3 = di->ctx.slot->f3; + /* f4 *must* be 0 in the Input Context... yeah, it's weird, I know. */ - if (dev->descriptor->bDeviceClass == 0x09 && dev->speed < SUPER_SPEED) { + if (dev->descriptor->bDeviceClass == 0x09) { ret = xhci_finish_hub_config(dev, ic); if (ret) goto _free_return;

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New patch to review for coreboot: libpayload: usb: xhci: Prevent address reuse
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10957 -gerrit commit 1695a08013188177e536d75748ffdb2eddadbcfb Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Jul 8 22:36:00 2015 -0700 libpayload: usb: xhci: Prevent address reuse We have been trying to avoid reassigning previously used USB addresses to different devices since CL:197420, because some devices seem to take issue with that. Unfortunately, that patch doesn't affect XHCI: those controllers insist on chosing addresses on their own. The only way to prevent them from reusing a previously assigned address is to not disable that slot at all. This patch implements address reuse avoidance on XHCI by not disabling slots when a device is detatched (which may occur both on physical detachment or if we simply couldn't find a driver for that device). Instead, we just release as many resources as we can for detached devices (by dropping all endpoint contexts) and defer the final cleanup until the point where the controller actually runs out of resources (a point that we probably don't often reach in most firmware scenarios). BRANCH=none BUG=chrome-os-partner:42181 TEST=Booted an Oak plugged into a Servo without having a driver for the SMSC network chip, observed that it could still enumerate the next device afterwards. Kept unplugging/replugging stuff until the cleanup triggered and made sure the controller still worked after that. Also played around a bit on a Falco without issues. Change-Id: Idfbab39abbc5bc5eff822bedf9c8d5bd4cad8cd2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 88c6bcbc41156729c3c38937c8a4adebc66f1ccb Original-Change-Id: I0653a4f6a02c02498210a70ffdda9d986592813b Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284175 Original-Tested-by: Nicolas Boichat <drinkcat(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/drivers/usb/xhci_devconf.c | 77 ++++++++++++++++++++++---- payloads/libpayload/drivers/usb/xhci_private.h | 5 +- 2 files changed, 70 insertions(+), 12 deletions(-) diff --git a/payloads/libpayload/drivers/usb/xhci_devconf.c b/payloads/libpayload/drivers/usb/xhci_devconf.c index 5b5bb5e..32cd291 100644 --- a/payloads/libpayload/drivers/usb/xhci_devconf.c +++ b/payloads/libpayload/drivers/usb/xhci_devconf.c @@ -75,6 +75,31 @@ xhci_get_tt(xhci_t *const xhci, const usb_speed speed, return *tt != 0; } +static void +xhci_reap_slots(xhci_t *const xhci, int skip_slot) +{ + int i; + + xhci_debug("xHC resource shortage, trying to reap old slots...\n"); + for (i = 1; i <= xhci->max_slots_en; i++) { + if (i == skip_slot) + continue; /* don't reap slot we were working on */ + if (xhci->dev[i].transfer_rings[1]) + continue; /* slot still in use */ + if (!xhci->dev[i].ctx.raw) + continue; /* slot already disabled */ + + const int cc = xhci_cmd_disable_slot(xhci, i); + if (cc != CC_SUCCESS) + xhci_debug("Failed to disable slot %d: %d\n", i, cc); + else + xhci_spew("Successfully reaped slot %d\n", i); + xhci->dcbaa[i] = 0; + free(xhci->dev[i].ctx.raw); + xhci->dev[i].ctx.raw = NULL; + } +} + static inputctx_t * xhci_make_inputctx(const size_t ctxsize) { @@ -119,6 +144,10 @@ xhci_set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr) int slot_id; int cc = xhci_cmd_enable_slot(xhci, &slot_id); + if (cc == CC_NO_SLOTS_AVAILABLE) { + xhci_reap_slots(xhci, 0); + cc = xhci_cmd_enable_slot(xhci, &slot_id); + } if (cc != CC_SUCCESS) { xhci_debug("Enable slot failed: %d\n", cc); goto _free_return; @@ -163,6 +192,10 @@ xhci_set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr) xhci->dcbaa[slot_id] = virt_to_phys(di->ctx.raw); cc = xhci_cmd_address_device(xhci, slot_id, ic); + if (cc == CC_RESOURCE_ERROR) { + xhci_reap_slots(xhci, slot_id); + cc = xhci_cmd_address_device(xhci, slot_id, ic); + } if (cc != CC_SUCCESS) { xhci_debug("Address device failed: %d\n", cc); goto _disable_return; @@ -199,6 +232,10 @@ xhci_set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr) *ic->add = (1 << 1); /* EP0 Context */ EC_SET(MPS, ic->dev.ep0, dev->endpoints[0].maxpacketsize); cc = xhci_cmd_evaluate_context(xhci, slot_id, ic); + if (cc == CC_RESOURCE_ERROR) { + xhci_reap_slots(xhci, slot_id); + cc = xhci_cmd_evaluate_context(xhci, slot_id, ic); + } if (cc != CC_SUCCESS) { xhci_debug("Context evaluation failed: %d\n", cc); goto _disable_return; @@ -216,8 +253,10 @@ _free_return: if (tr) free((void *)tr->ring); free(tr); - if (di) + if (di) { free(di->ctx.raw); + di->ctx.raw = 0; + } _free_ic_return: if (ic) free(ic->raw); @@ -330,7 +369,8 @@ int xhci_finish_device_config(usbdev_t *const dev) { xhci_t *const xhci = XHCI_INST(dev->controller); - devinfo_t *const di = &xhci->dev[dev->address]; + int slot_id = dev->address; + devinfo_t *const di = &xhci->dev[slot_id]; int i, ret = 0; @@ -363,8 +403,11 @@ xhci_finish_device_config(usbdev_t *const dev) const int config_id = dev->configuration->bConfigurationValue; xhci_debug("config_id: %d\n", config_id); - const int cc = - xhci_cmd_configure_endpoint(xhci, dev->address, config_id, ic); + int cc = xhci_cmd_configure_endpoint(xhci, slot_id, config_id, ic); + if (cc == CC_RESOURCE_ERROR || cc == CC_BANDWIDTH_ERROR) { + xhci_reap_slots(xhci, slot_id); + cc = xhci_cmd_configure_endpoint(xhci, slot_id, config_id, ic); + } if (cc != CC_SUCCESS) { xhci_debug("Configure endpoint failed: %d\n", cc); ret = CONTROLLER_ERROR; @@ -396,19 +439,31 @@ xhci_destroy_dev(hci_t *const controller, const int slot_id) if (slot_id <= 0 || slot_id > xhci->max_slots_en) return; - int i; - - const int cc = xhci_cmd_disable_slot(xhci, slot_id); + inputctx_t *const ic = xhci_make_inputctx(CTXSIZE(xhci)); + if (!ic) { + xhci_debug("Out of memory, leaking resources!\n"); + return; + } + const int num_eps = controller->devices[slot_id]->num_endp; + *ic->add = 0; /* Leave Slot/EP0 state as it is for now. */ + *ic->drop = (1 << num_eps) - 1; /* Drop all endpoints we can. */ + *ic->drop &= ~(1 << 1 | 1 << 0); /* Not allowed to drop EP0 or Slot. */ + int cc = xhci_cmd_evaluate_context(xhci, slot_id, ic); + if (cc != CC_SUCCESS) + xhci_debug("Failed to quiesce slot %d: %d\n", slot_id, cc); + cc = xhci_cmd_stop_endpoint(xhci, slot_id, 1); if (cc != CC_SUCCESS) - xhci_debug("Failed to disable slot %d: %d\n", slot_id, cc); + xhci_debug("Failed to stop EP0 on slot %d: %d\n", slot_id, cc); + int i; devinfo_t *const di = &xhci->dev[slot_id]; - for (i = 1; i < 31; ++i) { + for (i = 1; i < num_eps; ++i) { if (di->transfer_rings[i]) free((void *)di->transfer_rings[i]->ring); free(di->transfer_rings[i]); - free(di->interrupt_queues[i]); } - xhci->dcbaa[slot_id] = 0; + + xhci_spew("Stopped slot %d, but not disabling it yet.\n", slot_id); + di->transfer_rings[1] = NULL; } diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index f01a37f..26f7666 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -55,6 +55,9 @@ #define CC_SUCCESS 1 #define CC_TRB_ERROR 5 #define CC_STALL_ERROR 6 +#define CC_RESOURCE_ERROR 7 +#define CC_BANDWIDTH_ERROR 8 +#define CC_NO_SLOTS_AVAILABLE 9 #define CC_SHORT_PACKET 13 #define CC_EVENT_RING_FULL_ERROR 21 #define CC_COMMAND_RING_STOPPED 24 @@ -307,7 +310,7 @@ typedef struct intrq { typedef struct devinfo { devctx_t ctx; transfer_ring_t *transfer_rings[NUM_EPS]; - intrq_t *interrupt_queues[32]; + intrq_t *interrupt_queues[NUM_EPS]; } devinfo_t; typedef struct erst_entry {

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New patch to review for coreboot: libpayload: usb: dwc2: support split transaction
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10956 -gerrit commit 7fec532945610895aadfc7d3e624a515dab6e5cd Author: Yunzhi Li <lyz(a)rock-chips.com> Date: Thu Jul 2 15:28:11 2015 +0800 libpayload: usb: dwc2: support split transaction With split transaction, dwc2 host controller can handle full- and low-speed devices on hub in high-speed mode. This commit adds support for split control and interrupt transfers BUG=None TEST=Connect usb keyboard through hub, usb keyboard can work BRANCH=None Change-Id: If7a00db21c8ad4c635f39581382b877603075d1a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4fb514b7f7f7e414fa94bfce05420957b1c57019 Original-Change-Id: I07e64064c6182d33905ae4efb13712645de7cf93 Original-Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283282 Original-Tested-by: Lin Huang <hl(a)rock-chips.com> Original-Commit-Queue: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/drivers/usb/dwc2.c | 134 +++++++++++++++++++++-- payloads/libpayload/drivers/usb/dwc2_private.h | 8 ++ payloads/libpayload/drivers/usb/ehci.c | 24 ---- payloads/libpayload/drivers/usb/usb.c | 26 +++++ payloads/libpayload/include/usb/dwc2_registers.h | 24 ++++ payloads/libpayload/include/usb/usb.h | 2 + 6 files changed, 182 insertions(+), 36 deletions(-) diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c index fa0fd34..a3979e5 100644 --- a/payloads/libpayload/drivers/usb/dwc2.c +++ b/payloads/libpayload/drivers/usb/dwc2.c @@ -164,16 +164,20 @@ wait_for_complete(endpoint_t *ep, uint32_t ch_num) if (hcint.chhltd) { writel(hcint.d32, &reg->host.hchn[ch_num].hcintn); - if (hcint.xfercomp) + if (hcint.xfercomp || hcint.ack) return hctsiz.xfersize; else if (hcint.nak || hcint.frmovrun) - return hctsiz.xfersize; + return -HCSTAT_NAK; else if (hcint.xacterr) return -HCSTAT_XFERERR; else if (hcint.bblerr) return -HCSTAT_BABBLE; else if (hcint.stall) return -HCSTAT_STALL; + else if (hcint.ack) + return -HCSTAT_ACK; + else if (hcint.nyet) + return -HCSTAT_NYET; else return -HCSTAT_UNKNOW; } @@ -204,7 +208,7 @@ wait_for_complete(endpoint_t *ep, uint32_t ch_num) } static int -dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, +dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, uint32_t ch_num, u8 *data_buf) { uint32_t do_copy; @@ -241,6 +245,8 @@ dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, hcchar.devaddr = ep->dev->address; hcchar.chdis = 0; hcchar.chen = 1; + if (ep->dev->speed == LOW_SPEED) + hcchar.lspddev = 1; if (size > DMA_SIZE) { usb_debug("Transfer too large: %d\n", size); @@ -285,6 +291,110 @@ dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, } static int +dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, + uint32_t ch_num, u8 *data_buf, split_info_t *split) +{ + dwc2_reg_t *reg = DWC2_REG(ep->dev->controller); + hfnum_t hfnum; + hcsplit_t hcsplit = { .d32 = 0 }; + int ret, transferred = 0; + + hcsplit.hubaddr = split->hubaddr; + hcsplit.prtaddr = split->hubport; + hcsplit.spltena = 1; + writel(hcsplit.d32, &reg->host.hchn[ch_num].hcspltn); + + /* Wait for next frame boundary */ + do { + hfnum.d32 = readl(&reg->host.hfnum); + } while (hfnum.frnum % 8 != 0); + + /* Handle Start-Split */ + ret = dwc2_do_xfer(ep, dir == EPDIR_IN ? 0 : size, pid, dir, ch_num, + data_buf); + if (ret < 0) + goto out; + + hcsplit.spltena = 1; + hcsplit.compsplt = 1; + writel(hcsplit.d32, &reg->host.hchn[ch_num].hcspltn); + ep->toggle = pid; + + if (dir == EPDIR_OUT) + transferred += ret; + + /* Handle Complete-Split */ + do { + ret = dwc2_do_xfer(ep, dir == EPDIR_OUT ? 0 : size, ep->toggle, + dir, ch_num, data_buf); + } while (ret == -HCSTAT_NYET); + + if (dir == EPDIR_IN) + transferred += ret; + +out: + /* Clear hcsplit reg */ + hcsplit.spltena = 0; + hcsplit.compsplt = 0; + writel(hcsplit.d32, &reg->host.hchn[ch_num].hcspltn); + + if (ret < 0) + return ret; + + return transferred; +} + +static int dwc2_need_split(usbdev_t *dev, split_info_t *split) +{ + if (dev->speed == HIGH_SPEED) + return 0; + + if (closest_usb2_hub(dev, &split->hubaddr, &split->hubport)) + return 0; + + return 1; +} + +static int +dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, uint32_t ch_num, + u8 *src, uint8_t skip_nak) +{ + split_info_t split; + int ret, transferred = 0, timeout = 3000; + + ep->toggle = pid; + + do { + if (dwc2_need_split(ep->dev, &split)) { +nak_retry: + ret = dwc2_split_transfer(ep, size, ep->toggle, dir, 0, + src, &split); + + /* + * dwc2_split_transfer() waits for the next FullSpeed + * frame boundary, so we have one try per millisecond. + * It's 3s timeout for each split transfer. + */ + if (ret == -HCSTAT_NAK && !skip_nak && --timeout) { + udelay(500); + goto nak_retry; + } + } else { + ret = dwc2_do_xfer(ep, size, pid, dir, 0, src); + } + + if (ret < 0) + return ret; + + size -= ret; + src += ret; + transferred += ret; + } while (size > 0); + + return transferred; +} + +static int dwc2_bulk(endpoint_t *ep, int size, u8 *src, int finalize) { ep_dir_t data_dir; @@ -296,7 +406,7 @@ dwc2_bulk(endpoint_t *ep, int size, u8 *src, int finalize) else return -1; - return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src); + return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src, 0); } static int @@ -304,8 +414,8 @@ dwc2_control(usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen, u8 *src) { int ret = 0; - ep_dir_t data_dir; + endpoint_t *ep = &dev->endpoints[0]; if (dir == IN) data_dir = EPDIR_IN; @@ -315,19 +425,19 @@ dwc2_control(usbdev_t *dev, direction_t dir, int drlen, void *setup, return -1; /* Setup Phase */ - if (dwc2_transfer(&dev->endpoints[0], drlen, PID_SETUP, EPDIR_OUT, 0, - setup) < 0) + if (dwc2_transfer(ep, drlen, PID_SETUP, EPDIR_OUT, 0, setup, 0) < 0) return -1; + /* Data Phase */ + ep->toggle = PID_DATA1; if (dalen > 0) { - ret = dwc2_transfer(&dev->endpoints[0], dalen, PID_DATA1, - data_dir, 0, src); + ret = dwc2_transfer(ep, dalen, ep->toggle, data_dir, 0, src, 0); if (ret < 0) return -1; } + /* Status Phase */ - if (dwc2_transfer(&dev->endpoints[0], 0, PID_DATA1, !data_dir, 0, - NULL) < 0) + if (dwc2_transfer(ep, 0, PID_DATA1, !data_dir, 0, NULL, 0) < 0) return -1; return ret; @@ -345,7 +455,7 @@ dwc2_intr(endpoint_t *ep, int size, u8 *src) else return -1; - return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src); + return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src, 1); } static u32 dwc2_intr_get_timestamp(intr_queue_t *q) diff --git a/payloads/libpayload/drivers/usb/dwc2_private.h b/payloads/libpayload/drivers/usb/dwc2_private.h index c109042..5b1a547 100644 --- a/payloads/libpayload/drivers/usb/dwc2_private.h +++ b/payloads/libpayload/drivers/usb/dwc2_private.h @@ -36,6 +36,11 @@ typedef struct { u32 timestamp; } intr_queue_t; +typedef struct { + int hubaddr; + int hubport; +} split_info_t; + #define DWC2_INST(controller) ((dwc_ctrl_t *)((controller)->instance)) #define DWC2_REG(controller) ((dwc2_reg_t *)((controller)->reg_base)) @@ -44,6 +49,9 @@ typedef enum { HCSTAT_XFERERR, HCSTAT_BABBLE, HCSTAT_STALL, + HCSTAT_ACK, + HCSTAT_NAK, + HCSTAT_NYET, HCSTAT_UNKNOW, HCSTAT_TIMEOUT, } hcstat_t; diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 0aa799d..4636e7c 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -194,30 +194,6 @@ static void ehci_shutdown (hci_t *controller) enum { EHCI_OUT=0, EHCI_IN=1, EHCI_SETUP=2 }; -/* - * returns the address of the closest USB2.0 hub, which is responsible for - * split transactions, along with the number of the used downstream port - */ -static int closest_usb2_hub(const usbdev_t *dev, int *const addr, int *const port) -{ - const usbdev_t *usb1dev; - do { - usb1dev = dev; - if ((dev->hub >= 0) && (dev->hub < 128)) - dev = dev->controller->devices[dev->hub]; - else - dev = NULL; - } while (dev && (dev->speed < 2)); - if (dev) { - *addr = usb1dev->hub; - *port = usb1dev->port; - return 0; - } else { - usb_debug("ehci: Couldn't find closest USB2.0 hub.\n"); - return 1; - } -} - /* returns handled bytes. assumes that the fields it writes are empty on entry */ static int fill_td(qtd_t *td, void* data, int datalen) { diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 6174d63..e00d92f 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -653,3 +653,29 @@ usb_generic_init (usbdev_t *dev) usb_detach_device(dev->controller, dev->address); } } + +/* + * returns the address of the closest USB2.0 hub, which is responsible for + * split transactions, along with the number of the used downstream port + */ +int closest_usb2_hub(const usbdev_t *dev, int *const addr, int *const port) +{ + const usbdev_t *usb1dev; + + do { + usb1dev = dev; + if ((dev->hub >= 0) && (dev->hub < 128)) + dev = dev->controller->devices[dev->hub]; + else + dev = NULL; + } while (dev && (dev->speed < 2)); + + if (dev) { + *addr = usb1dev->hub; + *port = usb1dev->port; + return 0; + } + + usb_debug("Couldn't find closest USB2.0 hub.\n"); + return 1; +} diff --git a/payloads/libpayload/include/usb/dwc2_registers.h b/payloads/libpayload/include/usb/dwc2_registers.h index 0e46985..b44a5ac 100644 --- a/payloads/libpayload/include/usb/dwc2_registers.h +++ b/payloads/libpayload/include/usb/dwc2_registers.h @@ -597,6 +597,30 @@ typedef union { }; } hcchar_t; +/** + * This union represents the bit fields in the Host Channel-n Split Control + * Register. + */ +typedef union { + /* raw register data */ + uint32_t d32; + + /* register bits */ + struct { + /** Port Address */ + unsigned prtaddr:7; + /** Hub Address */ + unsigned hubaddr:7; + /** Transaction Position */ + unsigned xactpos:2; + /** Do Complete Split */ + unsigned compsplt:1; + unsigned reserved:14; + /** Split Enable */ + unsigned spltena:1; + }; +} hcsplit_t; + typedef enum { EPDIR_OUT = 0, EPDIR_IN, diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index df507db..cf52a4a 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -277,6 +277,8 @@ void usb_hid_init (usbdev_t *dev); void usb_msc_init (usbdev_t *dev); void usb_generic_init (usbdev_t *dev); +int closest_usb2_hub(const usbdev_t *dev, int *const addr, int *const port); + static inline unsigned char gen_bmRequestType (dev_req_dir dir, dev_req_type type, dev_req_recp recp) {

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New patch to review for coreboot: foster: correct odmdata in odmdata.cfg
by Patrick Georgi 16 Jul '15

16 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10955 -gerrit commit 380dbc1e86688342474972d0182b33dae943e384 Author: Yen Lin <yelin(a)nvidia.com> Date: Wed Jun 17 17:20:42 2015 -0700 foster: correct odmdata in odmdata.cfg So odmdata has the correct UART port of 0 BUG=chrome-os-partner:40741 BRANCH=None TEST=build Foster ok; and check scratch20 register Change-Id: I2c203317e6305214b74430780f2fe7b15652873a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0a0a99ac9c7db267129e4bc3478f9bb1ece08507 Original-Change-Id: I7be10d5deb5118f1cf3e339afca94893610437f2 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280291 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/foster/bct/odmdata.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/foster/bct/odmdata.cfg b/src/mainboard/google/foster/bct/odmdata.cfg index 45648af..c5938f3 100644 --- a/src/mainboard/google/foster/bct/odmdata.cfg +++ b/src/mainboard/google/foster/bct/odmdata.cfg @@ -1 +1 @@ -OdmData = 0x00294000; +OdmData = 0x00284000;

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coreboot-gerrit July 2015