coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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1048 discussions

New patch to review for coreboot: Braswell: Remove GOP from normal boot mode.
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10990 -gerrit commit b7dbb9d22b839fc168a1cc14b97453a527f0b212 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Mon Jul 13 16:12:31 2015 -0700 Braswell: Remove GOP from normal boot mode. Removing GOP initialization in normal mode since we don't need to show splash screen in normal mode. GOP will get initialized in dev and recovery mode. BRANCH=none BUG=None TEST=Splash screen will come only in dev or recovery mode. Change-Id: Ia5e12cf45d723f2f14c447e29b78119552d5e1ea Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 79d1c877343704ea51143b922d9ac9209be4d4b5 Original-Change-Id: Id5ca99757427206413483d07b4f422b4c0abfa5d Original-Signed-off-by: Abhay <abhay.kumar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285300 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/common/vbt.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 61eeaeb..0e46b70 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -24,6 +24,7 @@ #include <lib.h> #include <soc/intel/common/ramstage.h> #include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> /* Locate VBT and pass it to FSP GOP */ void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params) @@ -36,12 +37,15 @@ void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params) vbt_data = NULL; printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n"); } else { - /* Get VBT data */ - vbt_data = fsp_get_vbt(&vbt_len); - if (vbt_data != NULL) - printk(BIOS_DEBUG, "Passing VBT to GOP\n"); - else - printk(BIOS_DEBUG, "VBT not found!\n"); + if (developer_mode_enabled() || recovery_mode_enabled()) { + /* Get VBT data */ + vbt_data = fsp_get_vbt(&vbt_len); + if (vbt_data != NULL) + printk(BIOS_DEBUG, "Passing VBT to GOP\n"); + else + printk(BIOS_DEBUG, "VBT not found!\n"); + } else + vbt_data = NULL; } params->PcdGraphicsConfigPtr = (u32)vbt_data; }

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New patch to review for coreboot: skylake: re-enable PCIe L1 sub states
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10989 -gerrit commit 4fae9ba9540c3dea5b6a640aab846a716057016a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 13 13:50:34 2015 -0500 skylake: re-enable PCIe L1 sub states All boards should have their L1 sub states workig now so re-enable the defaults. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built and booted glados into OS. PCIe devices show up still. Change-Id: Ic040fa108a662e15bb97cf8b0961f0f56683e146 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 380491f8267e60c3c6bc62486aaf21e201fcfd36 Original-Change-Id: Idc6923b1fdd1c20d463eb7782be112f90b9adbfd Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285170 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 24fd961..207816d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -31,8 +31,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM - # External devices not working on glados - #select PCIEXP_L1_SUB_STATE + select PCIEXP_L1_SUB_STATE select PLATFORM_USES_FSP1_1 select REG_SCRIPT select RELOCATABLE_MODULES

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New patch to review for coreboot: Sklrvp: Select PCIEXP_L1_SUB_STATE config symbol
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10988 -gerrit commit 664847745511dda4f905a0263b3991792fe0a3d4 Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Mon Jul 6 16:42:56 2015 +0530 Sklrvp: Select PCIEXP_L1_SUB_STATE config symbol This patch selects the config symbol PCIEXP_L1_SUB_STATE to enable L1 substate for PCIe. BRANCH=None BUG=chrome-os-partner:42331 TEST=Build for sklrvp; boot and check "dmesg | grep iwl" shows "L1 enabled and LTR enabled" Change-Id: I97552c7700649a9f5d8646a03027c5c5e0b477b4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d3115816fbdd11c7f8ff418e0b5c86b8650c8b83 Original-Change-Id: Iaf307cb2d623cc1ce97b01d15a6b42569fd0c0c4 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284775 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> --- src/mainboard/intel/sklrvp/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/sklrvp/Kconfig b/src/mainboard/intel/sklrvp/Kconfig index 4c764c0..22ce473 100644 --- a/src/mainboard/intel/sklrvp/Kconfig +++ b/src/mainboard/intel/sklrvp/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MARK_GRAPHICS_MEM_WRCOMB select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR + select PCIEXP_L1_SUB_STATE select INTEL_PCH_UART_CONSOLE select SOC_INTEL_SKYLAKE select VBOOT_DYNAMIC_WORK_BUFFER

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New patch to review for coreboot: skylake: honor pcie root port settings already in chip.h
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10987 -gerrit commit 44defe03bb81c056eec5307abe645409cc498abb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 13 14:03:41 2015 -0500 skylake: honor pcie root port settings already in chip.h For some unkonwn reason the pcie root port settings weren't being honored in the device tree. Fix that omission. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree settings were being honored. Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257 Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285027 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/romstage/romstage.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 6d1310a..4230664 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -90,6 +90,13 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params) for (i = 0; i < PchSerialIoIndexMax; i++) params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; + memcpy(params->PcieRpEnable, config->PcieRpEnable, + sizeof(params->PcieRpEnable)); + memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, + sizeof(params->PcieRpClkReqSupport)); + memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, + sizeof(params->PcieRpClkReqNumber)); + params->MmioSize = 0x800; /* 2GB in MB */ params->TsegSize = CONFIG_SMM_TSEG_SIZE; params->IedSize = config->IedSize;

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New patch to review for coreboot: skylake: Show SPI controller if enabled in devicetree.cb
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10986 -gerrit commit 51fbdd9eb02da29d9ee9450969646a9d558c8cd3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 13 09:34:37 2015 -0700 skylake: Show SPI controller if enabled in devicetree.cb Unhide the SPI controller PCI device if it is enabled in devicetree.cb so flashrom can do its job. BUG=chrome-os-partner:37711 BRANCH=none TEST=run flashrom -r on glados Change-Id: Ie567f970149700d29df0ae09db4962f36cf24219 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 172eac55ad6134fe5e347e37c055b383e3b03245 Original-Change-Id: Ia77b559cc607794aecc25d6d469224d855199568 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284948 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/chip.h | 3 --- src/soc/intel/skylake/romstage/romstage.c | 4 ++++ 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 15e211e..d397c4e 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -199,9 +199,6 @@ struct soc_intel_skylake_config { /* Integrated Sensor */ u8 IshEnable; - /* SPI related */ - u8 ShowSpiController; - u8 PttSwitch; u8 HeciTimeouts; u8 HsioMessaging; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index e8bb877..6d1310a 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -111,6 +111,10 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params) params->IoBufferOwnership = config->IoBufferOwnership; params->DspEnable = config->DspEnable; params->XdciEnable = config->XdciEnable; + + /* Show SPI controller if enabled in devicetree.cb */ + dev = dev_find_slot(0, PCH_DEVFN_SPI); + params->ShowSpiController = dev->enabled; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,

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New patch to review for coreboot: cyan: Enable EC software sync
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10985 -gerrit commit ba42b722a8a5d9aedb4170495ee3f8f6aec9debe Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Tue Jul 7 08:22:11 2015 -0700 cyan: Enable EC software sync BUG=chrome-os-partner:40526 BRANCH=None TEST=Verify that system boots when used with coreboot and EC versions that also have Software Sync enabled. Change-Id: I6ed562fa51d83ddf16fc74d35db7c0004f57c79e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 090a66c50fac21808c4721a32b1728cc904f1b00 Original-Change-Id: Ia4d87d9a177c579567c03ae113889a277ffecee0 Original-Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283573 Original-Commit-Queue: Divya Jyothi <divya.jyothi(a)intel.com> Original-Tested-by: Divya Jyothi <divya.jyothi(a)intel.com> Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> --- src/mainboard/google/cyan/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 1dca237..988002c 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP -# select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC select ENABLE_BUILTIN_COM1 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE

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Patch set updated for coreboot: nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10h
by Jonathan A. Kollasch 20 Jul '15

20 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10984 -gerrit commit 42df9b152ffa9146496f7a7f6ae8b864c3cd8015 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 20 09:51:34 2015 -0500 nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10h Based on the observations that AMD Fam10h with both Nvidia CK804 (Asus KFSN4-DRE) and MCP55 (Sun Ultra 40 M2) need to avoid adjusting the LPC bridge register 0x78 (particularly the 0x7b byte) to get to ramstage: Assume that there's something about this register that adjusting it the way we do for K8 is something that can/should be universally avoided on all Fam10h systems with these chipsets. Change-Id: I1eceeb20ecaefef4c61c11e19d1f5a59f91a0a2f Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/asus/kfsn4-dre/romstage.c | 9 --------- src/southbridge/nvidia/ck804/early_setup.c | 14 ++++++++++++++ src/southbridge/nvidia/ck804/early_setup_car.c | 14 +++++++++++++- src/southbridge/nvidia/mcp55/early_setup_car.c | 10 ++++++++++ 4 files changed, 37 insertions(+), 10 deletions(-) diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index aa72021..cf36a72 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -67,15 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -/* - * Avoid crash (complete with severe memory corruption!) during initial CAR boot - * in ck804_early_setup_x(). - * Interestingly once the system is fully booted into Linux this can be set, but - * not before! Apparently something isn't initialized but the amount of effort - * required to fix this is non-negligible and of unknown real-world benefit - */ -#define CK804_SKIP_PCI_REG_78_INIT 1 - #define CK804_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index c0a8766..9c0a783 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -152,10 +152,24 @@ static void ck804_early_setup(void) RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, #endif +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + /* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in ck804_early_setup_x() on Fam10h systems by not touching 0x78. + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#else RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, +#endif RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, #if CONFIG_CK804_NUM > 1 + /* + * Avoid touching 0x78 for CONFIG_NORTHBRIDGE_AMD_AMDFAM10 for + * non-primary chain too??? + */ RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff, diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 8065d20..87fdbdd 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -142,7 +142,15 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, CK804_MB_SETUP #endif -#ifndef CK804_SKIP_PCI_REG_78_INIT +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + /* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in ck804_early_setup_x() on Fam10h systems by not touching 0x78. + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#else RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x19000000, #endif RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000100, @@ -239,6 +247,10 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x00440000, RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000, + /* + * Avoid touching 0x78 for CONFIG_NORTHBRIDGE_AMD_AMDFAM10 for + * non-primary chains too??? + */ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x20000000, RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000000, RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe8), 0xffffff00, 0x000000ff, diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 4970a4c..d919610 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -242,7 +242,17 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + /* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in mcp55_early_setup_x() on Fam10h systems by not touching 0x78. + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#else RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, +#endif #if CONFIG_MCP55_USE_AZA RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,

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Patch set updated for coreboot: amd/model_fxx: set CPU_ADDR_BITS to 40 on all K8 machines
by Jonathan A. Kollasch 20 Jul '15

20 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10963 -gerrit commit c3f0123806521d89a20589a0afbd4d2be2dc6c46 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Jul 17 07:47:41 2015 -0500 amd/model_fxx: set CPU_ADDR_BITS to 40 on all K8 machines Moves the K8 CPU_ADDR_BITS definition from socket to model. Previously socket_F was not setting CPU_ADDR_BITS correctly. Tested on Sun Ultra 40 M2 with two 2nd-gen Opterons w/ 2x4x2GiB DIMMs. Most if not all K8-based chips support 40-bit physical addresses, with possible exception of IA32-only K8-based Athlon XP-M chips. Probably irrelevant, unless your machine has enough memory (at least 60 to 64GiB before MMIO hoisting) to exceed the CPU_ADDR_BITS default of 36 from src/cpu/x86/Kconfig. Change-Id: I01a2a59fa902280171840c36ca2e631476d3d603 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/cpu/amd/model_fxx/Kconfig | 4 ++++ src/cpu/amd/socket_754/Kconfig | 4 ---- src/cpu/amd/socket_940/Kconfig | 4 ---- src/cpu/amd/socket_S1G1/Kconfig | 4 ---- 4 files changed, 4 insertions(+), 12 deletions(-) diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 9ee2bf7..1172d29 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -12,6 +12,10 @@ config CPU_AMD_MODEL_FXX select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX +config CPU_ADDR_BITS + int + default 40 + config UDELAY_IO bool default n diff --git a/src/cpu/amd/socket_754/Kconfig b/src/cpu/amd/socket_754/Kconfig index aeda421..ec3ab70 100644 --- a/src/cpu/amd/socket_754/Kconfig +++ b/src/cpu/amd/socket_754/Kconfig @@ -8,10 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS select CPU_AMD_MODEL_FXX select X86_AMD_FIXED_MTRRS -config CPU_ADDR_BITS - int - default 40 - config DCACHE_RAM_BASE hex default 0xc8000 diff --git a/src/cpu/amd/socket_940/Kconfig b/src/cpu/amd/socket_940/Kconfig index a8eef61..47b455b 100644 --- a/src/cpu/amd/socket_940/Kconfig +++ b/src/cpu/amd/socket_940/Kconfig @@ -9,10 +9,6 @@ config SOCKET_SPECIFIC_OPTIONS select CPU_AMD_MODEL_FXX select X86_AMD_FIXED_MTRRS -config CPU_ADDR_BITS - int - default 40 - config DCACHE_RAM_BASE hex default 0xc8000 diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index 01d84a1..3338677 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -19,10 +19,6 @@ config DIMM_SUPPORT hex default 0x0204 -config CPU_ADDR_BITS - int - default 40 - config DCACHE_RAM_BASE hex default 0xc8000

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Patch merged into coreboot/master: northbridge/amd/pi: Add support for memory settings
by gerrit＠coreboot.org 20 Jul '15

20 Jul '15

the following patch was just integrated into master: commit 406effd59075cab212c5bf9c1a12759c8fad50a4 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed May 20 10:33:51 2015 -0600 northbridge/amd/pi: Add support for memory settings This adds support for binarypi based boards that have to make adjustments to the memory configuration settings. A PlatformMemoryConfiguration[] table that describes the memory configuration must be defined in the mainboard folder. Change-Id: I5e4b476a4adf3dd1f3b7843274a81ecb243d10ab Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/10672 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10672 for details. -gerrit

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Patch set updated for coreboot: AMD K8: Avoid duplicate variables in SSDT on multisocket systems
by Jonathan A. Kollasch 20 Jul '15

20 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10912 -gerrit commit 86e0efc1f913d54692a1ca668e7a4cbf909670fa Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 13 21:03:10 2015 -0500 AMD K8: Avoid duplicate variables in SSDT on multisocket systems Related-to: I3175c8b29e94a27a2db6b11f8fc9e1d91bde11f9 (ACPI: Fix corrupt SSDT table on multiprocessor AMD Family 10h systems) Change-Id: I0b5f265278d90cbaeddc6fc4432933856050f784 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/northbridge/amd/amdk8/acpi.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 10228cf..ce49b90 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -282,6 +282,17 @@ static void k8acpi_write_pci_data(int dlen, const char *name, int offset) { void k8acpi_write_vars(device_t device) { + /* + * If more than one physical CPU is installed k8acpi_write_vars() + * is called more than once. If we don't prevent it, a SSDT table + * with duplicate variables will cause some ACPI parsers to be + * confused enough to fail. + */ + static uint8_t ssdt_generated = 0; + if (ssdt_generated) + return; + ssdt_generated = 1; + msr_t msr; char pscope[] = "\\_SB.PCI0";

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coreboot-gerrit July 2015