coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: Sklrvp: Update Serial IO modes in devicetree
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11000 -gerrit commit 9c4f3147d0600b20248035296f2b00460d157bd5 Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Thu Jul 9 17:59:58 2015 +0530 Sklrvp: Update Serial IO modes in devicetree This patch updates the Serial IO modes for UART 1 and 2 in devicetree for sklrvp boards. UART1 is disabled and UART2 is in PCI mode. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp and tested LPSS logs on RVP3. Change-Id: I59a657d6a3744040ec6be290ba966672e0e5f17e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5a20a70801d66abd87d4214e1ef187b86eed99da Original-Change-Id: I381374272e1824ca8887ea5c5662215dde2c0a56 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284824 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> --- src/mainboard/intel/sklrvp/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/sklrvp/devicetree.cb b/src/mainboard/intel/sklrvp/devicetree.cb index 6cae727..66c1f18 100644 --- a/src/mainboard/intel/sklrvp/devicetree.cb +++ b/src/mainboard/intel/sklrvp/devicetree.cb @@ -11,8 +11,8 @@ chip soc/intel/skylake [PchSerialIoIndexSpi0] = PchSerialIoPci, \ [PchSerialIoIndexSpi1] = PchSerialIoPci, \ [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoPci, \ - [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoPci, \ }" # Enable eDP Hotplug with 6ms pulse

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New patch to review for coreboot: intel/skylake: support 32bit uart8250_mem driver in romstage
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10999 -gerrit commit 4586ef4fdad858aebd967ec9d9b4944478ffb295 Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Mon May 18 21:25:52 2015 +0530 intel/skylake: support 32bit uart8250_mem driver in romstage This patch adds 32bit uart8250_mem functionality in romstage console for arch/x86. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp; verified romstage logs on RVP3 board. Change-Id: I6f13216b7f5ba8de48c781cd1791d0fa7ae0d921 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a17efdeec5524cbfc78015c358d1cf4f67485765 Original-Change-Id: I8b4e44c59bfd609a06807243df338763054b5865 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271800 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> --- src/soc/intel/skylake/romstage/uart.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c index c53643a..afc8c63 100644 --- a/src/soc/intel/skylake/romstage/uart.c +++ b/src/soc/intel/skylake/romstage/uart.c @@ -57,8 +57,9 @@ void pch_uart_init(void) write32(base + SIO_REG_PPR_CLOCK, tmp); /* Put UART2 in byte access mode for 16550 compatibility */ - pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, - SIO_PCH_LEGACY_UART2); + if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32)) + pcr_andthenor32(PID_SERIALIO, + R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2); /* Configure GPIO for UART2 in native mode*/ uartgpioinit(FALSE);

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New patch to review for coreboot: console: Add UART8250MEM 32bit support
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10998 -gerrit commit 56ef509c9508cc586cbf1578934e442444f4126a Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Wed Jul 8 14:23:06 2015 +0530 console: Add UART8250MEM 32bit support This patch adds UART8250MEM_32 feature flag to support UART8250 compatible with 32bit access in memory mapped mode. [pg: rebuilt to reuse the existing UART8250 8bit access driver which reduces code duplication.] Change-Id: I310e70dfab81dcca575e9931e0ccf93af70efa40 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0c3b2c628b854e8334540ff5158c2587dbfabf95 Original-Change-Id: I07ee256f25e48480372af9a9255bf487c331e51d Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy(a)intel.com> Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271759 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> --- src/drivers/uart/Kconfig | 5 +++++ src/drivers/uart/uart8250mem.c | 12 ++++++++++++ 2 files changed, 17 insertions(+) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index fef745e..cbfd479 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -17,6 +17,11 @@ config DRIVERS_UART_8250MEM bool default n +config DRIVERS_UART_8250MEM_32 + bool + default n + depends on DRIVERS_UART_8250MEM + config HAVE_UART_SPECIAL bool default n diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 2f341f2..d276fd0 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -34,6 +34,17 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32) +static uint8_t uart8250_read(void *base, uint8_t reg) +{ + return read32(base + 4 * reg) & 0xff; +} + +static void uart8250_write(void *base, uint8_t reg, uint8_t data) +{ + write32(base + 4 * reg, data); +} +#else static uint8_t uart8250_read(void *base, uint8_t reg) { return read8(base + reg); @@ -43,6 +54,7 @@ static void uart8250_write(void *base, uint8_t reg, uint8_t data) { write8(base + reg, data); } +#endif static int uart8250_mem_can_tx_byte(void *base) {

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New patch to review for coreboot: google/glados: add new board
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10997 -gerrit commit 3d209487437e6ea48141ee9d44b77a4a97801000 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 20 22:01:32 2015 +0200 google/glados: add new board Change-Id: I0c196ff84484717c59c59d11bb7230b5920e0654 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/glados/Kconfig | 52 ++++ src/mainboard/google/glados/Kconfig.name | 2 + src/mainboard/google/glados/Makefile.inc | 33 +++ src/mainboard/google/glados/abuild.disabled | 2 + src/mainboard/google/glados/acpi/chromeos.asl | 23 ++ src/mainboard/google/glados/acpi/ec.asl | 27 ++ src/mainboard/google/glados/acpi/mainboard.asl | 95 +++++++ src/mainboard/google/glados/acpi/superio.asl | 28 ++ src/mainboard/google/glados/acpi_tables.c | 62 ++++ src/mainboard/google/glados/chromeos.c | 72 +++++ src/mainboard/google/glados/cmos.layout | 140 +++++++++ src/mainboard/google/glados/devicetree.cb | 108 +++++++ src/mainboard/google/glados/dsdt.asl | 57 ++++ src/mainboard/google/glados/ec.c | 55 ++++ src/mainboard/google/glados/ec.h | 70 +++++ src/mainboard/google/glados/fadt.c | 51 ++++ src/mainboard/google/glados/gpio.h | 315 +++++++++++++++++++++ src/mainboard/google/glados/mainboard.c | 42 +++ src/mainboard/google/glados/pei_data.c | 56 ++++ src/mainboard/google/glados/ramstage.c | 27 ++ src/mainboard/google/glados/romstage.c | 71 +++++ src/mainboard/google/glados/smihandler.c | 147 ++++++++++ src/mainboard/google/glados/spd/Makefile.inc | 41 +++ src/mainboard/google/glados/spd/empty.spd.hex | 16 ++ .../spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex | 16 ++ src/mainboard/google/glados/spd/spd.c | 117 ++++++++ src/mainboard/google/glados/spd/spd.h | 36 +++ src/mainboard/google/glados/thermal.h | 35 +++ 28 files changed, 1796 insertions(+) diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig new file mode 100644 index 0000000..c7df2a3 --- /dev/null +++ b/src/mainboard/google/glados/Kconfig @@ -0,0 +1,52 @@ +if BOARD_GOOGLE_GLADOS + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_16384 + select CACHE_ROM + select CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + select CHROMEOS_VBNV_CMOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_MEC + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP + select EC_SOFTWARE_SYNC + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select LID_SWITCH + select MAINBOARD_HAS_CHROMEOS + select MARK_GRAPHICS_MEM_WRCOMB + select MMCONF_SUPPORT + select MONOTONIC_TIMER_MSR + select SOC_INTEL_SKYLAKE + select VBOOT_OPROM_MATTERS + select VIRTUAL_DEV_SWITCH + +config IRQ_SLOT_COUNT + int + default 18 + +config BOOT_MEDIA_SPI_BUS + int + default 0 + +config MAINBOARD_DIR + string + default "google/glados" + +config MAINBOARD_PART_NUMBER + string + default "Glados" + +config MAX_CPUS + int + default 8 + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + +endif diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name new file mode 100644 index 0000000..24f70ea --- /dev/null +++ b/src/mainboard/google/glados/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_KUNIMITSU + bool "Kunimitsu" diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc new file mode 100644 index 0000000..93fc3d6 --- /dev/null +++ b/src/mainboard/google/glados/Makefile.inc @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +subdirs-y += spd + +romstage-y += pei_data.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c + +ramstage-y += mainboard.c +ramstage-y += pei_data.c +ramstage-y += ramstage.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/glados/abuild.disabled b/src/mainboard/google/glados/abuild.disabled new file mode 100644 index 0000000..7d1725a --- /dev/null +++ b/src/mainboard/google/glados/abuild.disabled @@ -0,0 +1,2 @@ +Successful builds for this board require the Skylake FSP binary and header files +along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/glados/acpi/chromeos.asl b/src/mainboard/google/glados/acpi/chromeos.asl new file mode 100644 index 0000000..2d8146c --- /dev/null +++ b/src/mainboard/google/glados/acpi/chromeos.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Name (OIPG, Package() { + Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button + Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect +}) diff --git a/src/mainboard/google/glados/acpi/ec.asl b/src/mainboard/google/glados/acpi/ec.asl new file mode 100644 index 0000000..8e7532d --- /dev/null +++ b/src/mainboard/google/glados/acpi/ec.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* mainboard configuration */ +#include <mainboard/google/glados/ec.h> + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl new file mode 100644 index 0000000..ab40d62 --- /dev/null +++ b/src/mainboard/google/glados/acpi/mainboard.asl @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#define BOARD_TRACKPAD_I2C_ADDR 0x15 +#define BOARD_TRACKPAD_IRQ 0x33 + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId("PNP0C0D")) + Method (_LID, 0) + { + Return (\_SB.PCI0.LPCB.EC0.LIDS) + } + } + + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } + + /* Keyboard Backlight interface via EC */ + Device (KBLT) { + Name (_HID, "GOOG0002") + Name (_UID, 1) + + /* Read current backlight value */ + Method (KBQC, 0) + { + Return (\_SB.PCI0.LPCB.EC0.KBLV) + } + + /* Write new backlight value */ + Method (KBCM, 1) + { + Store (Arg0, \_SB.PCI0.LPCB.EC0.KBLV) + } + } +} + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} + +/* Trackpad */ +Scope (\_SB.PCI0.I2C1) +{ + Device (ELAN) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (_S0W, 4) + Name (ISTP, 1) /* TouchPad */ + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TRACKPAD_I2C_ADDR, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.PCI0.I2C1", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + Method (_STA) + { + Return (0xF) + } + } +} diff --git a/src/mainboard/google/glados/acpi/superio.asl b/src/mainboard/google/glados/acpi/superio.asl new file mode 100644 index 0000000..932fef7 --- /dev/null +++ b/src/mainboard/google/glados/acpi/superio.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* mainboard configuration */ +#include <mainboard/google/glados/ec.h> + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/glados/acpi_tables.c b/src/mainboard/google/glados/acpi_tables.c new file mode 100644 index 0000000..cb0afc4 --- /dev/null +++ b/src/mainboard/google/glados/acpi_tables.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <soc/acpi.h> +#include <soc/nvs.h> +#include "thermal.h" + +extern const unsigned char AmlCode[]; + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + + gnvs->tmps = TEMPERATURE_SENSOR_ID; + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c new file mode 100644 index 0000000..f1ff43b --- /dev/null +++ b/src/mainboard/google/glados/chromeos.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <rules.h> +#include <soc/gpio.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", + get_recovery_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", + get_lid_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); +} +#endif /* ENV_RAMSTAGE */ + +int get_lid_switch(void) +{ + return 1; +} +/* The dev-switch is virtual */ +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/mainboard/google/glados/cmos.layout b/src/mainboard/google/glados/cmos.layout new file mode 100644 index 0000000..20afaf7 --- /dev/null +++ b/src/mainboard/google/glados/cmos.layout @@ -0,0 +1,140 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb new file mode 100644 index 0000000..2060866 --- /dev/null +++ b/src/mainboard/google/glados/devicetree.cb @@ -0,0 +1,108 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable" = "1" + register "deep_s5_enable" = "1" + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \ + }" + + # Enable Root port 1 and 5. + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkReqNumber[4]" = "2" + + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "1" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + + register "ProbelessTrace" = "0" + register "EnableTraceHub" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "IshEnable" = "0" + register "XdciEnable" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "0" + register "Cio2Enable" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + + # Embedded Controller host command window + register "gen1_dec" = "0x00fc0801" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB 3.0 xHCI Controller + device pci 14.1 off end # USB Device Controller (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C Controller #0 + device pci 15.1 on end # I2C Controller #1 + device pci 15.2 off end # I2C Controller #2 + device pci 15.3 off end # I2C Controller #3 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Intel MEI #3 + device pci 17.0 on end # SATA Controller + device pci 19.0 on end # UART Controller #2 + device pci 19.1 off end # I2C Controller #5 + device pci 19.2 on end # I2C Controller #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.6 on end # SDCard + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel High Definition Audio + device pci 1f.4 off end # SMBus Controller + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE Controller + end +end diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl new file mode 100644 index 0000000..6ac0be4 --- /dev/null +++ b/src/mainboard/google/glados/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chrome OS specific + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/google/glados/ec.c b/src/mainboard/google/glados/ec.c new file mode 100644 index 0000000..c491ad5 --- /dev/null +++ b/src/mainboard/google/glados/ec.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +void mainboard_ec_init(void) +{ + printk(BIOS_DEBUG, "mainboard_ec_init\n"); + post_code(0xf0); + + /* Restore SCI event mask on resume. */ + if (acpi_slp_type == 3) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + /* + * Set SCI mask.OS may not generate SMI event to set + * this on S3 resume. + */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); + post_code(0xf1); +} diff --git a/src/mainboard/google/glados/ec.h b/src/mainboard/google/glados/ec.h new file mode 100644 index 0000000..9da9d9f --- /dev/null +++ b/src/mainboard/google/glados/ec.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +/* GPP_E16 is EC_SCI_L */ +#define EC_SCI_GPI 16 /* TODO: Update this */ +/* GPP_E15 is EC_SMI_L */ +#define EC_SMI_GPI 15 /* TODO: Update this */ + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/google/glados/fadt.c b/src/mainboard/google/glados/fadt.c new file mode 100644 index 0000000..7948f93 --- /dev/null +++ b/src/mainboard/google/glados/fadt.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <string.h> +#include <soc/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h new file mode 100644 index 0000000..35b1ae4 --- /dev/null +++ b/src/mainboard/google/glados/gpio.h @@ -0,0 +1,315 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpio.h> + +const GPIO_INIT_CONFIG mainboard_gpio_table[] = { +/* RCIN# */ +{GPIO_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* LAD0 */ +{GPIO_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* LAD1 */ +{GPIO_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioTermNone}}, +/* LAD2 */ +{GPIO_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* LAD3 */ +{GPIO_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* LFRAME# */ +{GPIO_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SERIRQ */ +{GPIO_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* CLKRUN# */ +{GPIO_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* CLKOUT_LPC0 */ +{GPIO_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SUSWARN# tied to SUSACK# */ +{GPIO_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SUS_STAT# TP27 */ +{GPIO_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SUSACK# tied to SUSWARN# */ +{GPIO_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SD_1P8_SEL */ +{GPIO_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SD_PWR_EN# */ +{GPIO_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* TRACKPAD_INT_L */ +{GPIO_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep, + GpioTermNone}}, +/* SRCCLKREQ1# / WLAN_PCIE_CLKREQ_L */ +{GPIO_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* SRCCLKREQ2# / KEPLER_PCIE_CLKREQ_L */ +{GPIO_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* EXT_PWR_GATE# */ +{GPIO_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* SLP_S0# */ +{GPIO_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* PLTRST# */ +{GPIO_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* WLAN_PCIE_WAKE_L */ +{GPIO_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, +/* SMBCLK (XDP) */ +{GPIO_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SMBDATA (XDP) */ +{GPIO_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EC_IN_RW */ +{GPIO_LP_GPP_C6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* EN_PP3300_KEPLER */ +{GPIO_LP_GPP_C11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, +/* PCH_MEM_CONFIG[0] */ +{GPIO_LP_GPP_C12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* PCH_MEM_CONFIG[1] */ +{GPIO_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* PCH_MEM_CONFIG[2] */ +{GPIO_LP_GPP_C14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* PCH_MEM_CONFIG[3] */ +{GPIO_LP_GPP_C15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* I2C0_SDA */ +{GPIO_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* I2C0_SCL */ +{GPIO_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* I2C1 SDA */ +{GPIO_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* I2C1 SDA */ +{GPIO_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* UART2_RXD */ +{GPIO_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* UART2_TXD */ +{GPIO_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EN_PP3300_DX_TOUCHSCREEN */ +{GPIO_LP_GPP_C22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, +/* PCH_WP */ +{GPIO_LP_GPP_C23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermWpu20K}}, +/* EN_PP3300_DX_EMMC */ +{GPIO_LP_GPP_D5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EN_PP1800_DX_EMMC */ +{GPIO_LP_GPP_D6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* USBA_1_ILIM_SEL_L */ +{GPIO_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* USBA_2_ILIM_SEL_L */ +{GPIO_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EN_PP3300_DX_CAM */ +{GPIO_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* DMIC_CLK1 */ +{GPIO_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* DMIC_DATA1 */ +{GPIO_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* DMIC_CLK0 */ +{GPIO_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* DMIC_DATA0 */ +{GPIO_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* I2S_MCLK */ +{GPIO_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* TPM_PIRQ_L */ +{GPIO_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, +/* TOUCHSCREEN_INT_L */ +{GPIO_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep, + GpioTermNone}}, +/* USB2_OC0# */ +{GPIO_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* USB2_OC1# */ +{GPIO_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* USB2_OC2# */ +{GPIO_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* USB2_OC3# */ +{GPIO_LP_GPP_E12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* DDPB_HPD0 */ +{GPIO_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* DDPC_HPD1 */ +{GPIO_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* EC_SMI_L */ +{GPIO_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, +/* EC_SCI_L */ +{GPIO_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, +/* EDP_HPD */ +{GPIO_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* + * The next 4 pads are for bit banging the amplifiers. They are connected + * together with i2s0 signals. For default behavior of i2s make these + * gpio inupts. + */ +/* I2S2_SCLK */ +{GPIO_LP_GPP_F0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* I2S2_SFRM */ +{GPIO_LP_GPP_F1, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* I2S2_TXD */ +{GPIO_LP_GPP_F2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* I2S2_RXD */ +{GPIO_LP_GPP_F3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* I2C4_SDA */ +{GPIO_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* I2C4_SCL */ +{GPIO_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* MIC_INT_L */ +{GPIO_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, + GpioOutDefault, (GpioIntApic | GpioIntEdge), GpioResetDeep, + GpioTermNone}}, +/* EMMC_CMD */ +{GPIO_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EMMC_DATA0 */ +{GPIO_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EMMC_DATA1 */ +{GPIO_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EMMC_DATA2 */ +{GPIO_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EMMC_DATA3 */ +{GPIO_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EMMC_DATA4 */ +{GPIO_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EMMC_DATA5 */ +{GPIO_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EMMC_DATA6 */ +{GPIO_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EMMC_DATA7 */ +{GPIO_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EMMC_RCLK */ +{GPIO_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EMMC_CLK */ +{GPIO_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* EMMC_CMD */ +{GPIO_LP_GPP_F23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SD_CMD */ +{GPIO_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SD_DATA0 */ +{GPIO_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SD_DATA1 */ +{GPIO_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SD_DATA2 */ +{GPIO_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SD_DATA3 */ +{GPIO_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SD_CD# */ +{GPIO_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SD_CLK# */ +{GPIO_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, +/* SD_WP# */ +{GPIO_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, +/* ACPRESENT# */ +{GPIO_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* EC_PCH_WAKE_L */ +{GPIO_LP_GPD2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, +/* PWRBTN# */ +{GPIO_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +/* SLP_S3# */ +{GPIO_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SLP_S4# */ +{GPIO_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SUSCLK */ +{GPIO_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}}, +/* SLP_S5# */ +{GPIO_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}}, +{END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, + GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, +}; + +#endif diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c new file mode 100644 index 0000000..26b622a --- /dev/null +++ b/src/mainboard/google/glados/mainboard.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <device/device.h> +#include "ec.h" + +static void mainboard_init(device_t dev) +{ + if (IS_ENABLED(CONFIG_GOOGLE_CHROME_EC)) + mainboard_ec_init(); +} + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/glados/pei_data.c b/src/mainboard/google/glados/pei_data.c new file mode 100644 index 0000000..677ea32 --- /dev/null +++ b/src/mainboard/google/glados/pei_data.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 , + 0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00}, + {0x33, 0xCC , 0x00, 0xCC , 0x33, 0xCC , + 0x33, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + {0, 1, 3, 2, 4, 5, 6, 7}, + {1, 0, 4, 5, 2, 3, 6, 7} }; + + /* Rcomp resistor*/ + const u16 RcompResistor[3] = {200, 81, 162 }; + + /* Rcomp target*/ + const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; + + pei_data->ec_present = 1; + /* One installed DIMM per channel */ + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + + memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); + memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); + memcpy(pei_data->RcompResistor, RcompResistor, + sizeof(RcompResistor)); + memcpy(pei_data->RcompTarget, RcompTarget, + sizeof(RcompTarget)); +} diff --git a/src/mainboard/google/glados/ramstage.c b/src/mainboard/google/glados/ramstage.c new file mode 100644 index 0000000..f31511e --- /dev/null +++ b/src/mainboard/google/glados/ramstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + params->GpioTablePtr = (UINT32 *)mainboard_gpio_table; +} diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c new file mode 100644 index 0000000..afcad8c --- /dev/null +++ b/src/mainboard/google/glados/romstage.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/romstage.h> +#include "spd/spd.h" + +void mainboard_romstage_entry(struct romstage_params *params) +{ + /* Fill out PEI DATA */ + mainboard_fill_pei_data(params->pei_data); + mainboard_fill_spd_data(params->pei_data); + /* Initliaze memory */ + romstage_common(params); +} + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + if (params->pei_data->spd_data[0][0][0] != 0) { + memory_params->MemorySpdPtr00 = + (UINT32)(params->pei_data->spd_data[0][0]); + memory_params->MemorySpdPtr10 = + (UINT32)(params->pei_data->spd_data[1][0]); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", + memory_params->MemorySpdPtr00); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n", + memory_params->MemorySpdPtr01); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", + memory_params->MemorySpdPtr10); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n", + memory_params->MemorySpdPtr11); + } + memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], + sizeof(params->pei_data->dq_map[0])); + memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], + sizeof(params->pei_data->dq_map[1])); + memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], + sizeof(params->pei_data->dqs_map[0])); + memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], + sizeof(params->pei_data->dqs_map[1])); + memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, + sizeof(params->pei_data->RcompResistor)); + memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, + sizeof(params->pei_data->RcompTarget)); + memory_params->MemorySpdDataLen = SPD_LEN; + memory_params->DqPinsInterleaved = FALSE; +} diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c new file mode 100644 index 0000000..164bd8e --- /dev/null +++ b/src/mainboard/google/glados/smihandler.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <elog.h> +#include <ec/google/chromeec/ec.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <soc/pm.h> +#include <soc/smm.h> +#include "ec.h" + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + return 1; +} + +static u8 mainboard_smi_ec(void) +{ + u8 cmd = 0; +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u32 pm1_cnt; + cmd = google_chromeec_get_event(); + + /* Log this event */ + if (IS_ENABLED(CONFIG_ELOG_GSMI) && cmd) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); + + switch (cmd) { + case EC_HOST_EVENT_LID_CLOSED: + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + + /* Go to S5 */ + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); + break; + } +#endif + return cmd; +} + +/* gpi_sts is GPIO 47:32 */ +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << EC_SMI_GPI)) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0) + ; + } +} + +void mainboard_smi_sleep(u8 slp_typ) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: + if (smm_get_gnvs()->s3u0 == 0) { + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + } + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + break; + case 5: + if (smm_get_gnvs()->s5u0 == 0) { + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + } + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); + break; + } + + /* Disable SCI and SMI events */ + google_chromeec_set_smi_mask(0); + google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + while (google_chromeec_get_event() != 0) + ; +#endif +} + +int mainboard_smi_apmc(u8 apmc) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + break; + case APM_CNT_ACPI_DISABLE: + google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); + break; + } +#endif + return 0; +} diff --git a/src/mainboard/google/glados/spd/Makefile.inc b/src/mainboard/google/glados/spd/Makefile.inc new file mode 100644 index 0000000..d8c0c51 --- /dev/null +++ b/src/mainboard/google/glados/spd/Makefile.inc @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## Copyright (C) 2015 Intel Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +# SPD data by index. No method for board identification yet +SPD_SOURCES = samsung_dimm_K4E6E304EE-EGCF # 0 +SPD_SOURCES += empty # 1 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/glados/spd/empty.spd.hex b/src/mainboard/google/glados/spd/empty.spd.hex new file mode 100644 index 0000000..9ec39f1 --- /dev/null +++ b/src/mainboard/google/glados/spd/empty.spd.hex @@ -0,0 +1,16 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex new file mode 100644 index 0000000..41ee49a --- /dev/null +++ b/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 12 05 0A 03 11 01 08 09 00 50 05 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 80 ca fa 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 +4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c new file mode 100644 index 0000000..5ee12f5 --- /dev/null +++ b/src/mainboard/google/glados/spd/spd.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/romstage.h> +#include "spd.h" + +static void mainboard_print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + break; + case SPD_DRAM_LPDDR3: + printk(BIOS_INFO, "LPDDR3\n"); + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + /* Module Part Number */ + memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); + spd_name[SPD_PART_LEN] = 0; + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, + "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", + banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *pei_data) +{ + char *spd_file; + size_t spd_file_len; + int spd_index; + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Add board SKU detection here. Currently we only support one. */ + spd_index = 0; + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + /* Assume same memory in both channels */ + spd_index *= SPD_LEN; + memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN); + memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN); + + /* Make sure a valid SPD was found */ + if (pei_data->spd_data[0][0][0] == 0) + die("Invalid SPD data."); + + mainboard_print_spd_info(pei_data->spd_data[0][0]); +} diff --git a/src/mainboard/google/glados/spd/spd.h b/src/mainboard/google/glados/spd/spd.h new file mode 100644 index 0000000..abb964e --- /dev/null +++ b/src/mainboard/google/glados/spd/spd.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 + +#endif diff --git a/src/mainboard/google/glados/thermal.h b/src/mainboard/google/glados/thermal.h new file mode 100644 index 0000000..ef03d717 --- /dev/null +++ b/src/mainboard/google/glados/thermal.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _MAINBOARD_THERMAL_H_ +#define _MAINBOARD_THERMAL_H_ + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 99 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 100 + +#endif /* _MAINBOARD_THERMAL_H_ */

1 0

New patch to review for coreboot: Intel/common: remove printk in pre_console_init()
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10996 -gerrit commit edb09e794ea6b5c86c9d7702994b2a258c8da760 Author: rsatapat <rishavnath.satapathy(a)intel.com> Date: Mon Jul 6 21:03:02 2015 +0530 Intel/common: remove printk in pre_console_init() printk called before console init causes sluggish execution because of Rx timeout. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp and tested LPSS logs on RVP3 and Kunimitsu. Change-Id: I61d5c0f5a4e93695bcba90b7ac7d4f68e2d625be Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 77c58702c8279c6d9c6ae1c946bf1b76df20714d Original-Change-Id: Ib85029456059248cc2c88aaccba4fa12cc5a76be Original-Signed-off-by: rsatapat <rishavnath.satapathy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284823 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> --- src/soc/intel/common/romstage.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c index 919de83..370d973 100644 --- a/src/soc/intel/common/romstage.c +++ b/src/soc/intel/common/romstage.c @@ -231,7 +231,6 @@ __attribute__((weak)) void mainboard_check_ec_image( __attribute__((weak)) void mainboard_pre_console_init( struct romstage_params *params) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } /* Board initialization before and after RAM is enabled */

1 0

New patch to review for coreboot: Skylake: Initialize GPIOs for UART2
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10995 -gerrit commit 376d70d7cd4d9da8523854d00e283364fc1ce841 Author: rsatapat <rishavnath.satapathy(a)intel.com> Date: Wed Jun 24 20:49:16 2015 +0530 Skylake: Initialize GPIOs for UART2 FSP will initialize GPIOs during TempRamInit. So, Configure LPSS UART2 GPIOs in native mode after TempRamInit. BRANCH=none BUG=chrome-os-partner:41374 EST=Build and boot on RVP3. Check LPSS logs on UART2 Change-Id: I8016dd76a5bc06e90f9460273be7e83c5e8f8bb1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: eb72e715ef3f566e900727ac8b9494bca1d5971c Original-Change-Id: If1b1a1047ebd5e5f170d91972d11c51aa6fd84a9 Original-Signed-off-by: rsatapat <rishavnath.satapathy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281604 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> --- src/soc/intel/skylake/include/soc/gpio.h | 12 ++++++ src/soc/intel/skylake/romstage/uart.c | 64 +++++++++++++++++++++++++++++++- 2 files changed, 74 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index efc666f..03ed119 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -257,6 +257,18 @@ typedef struct { .owner = GPIO_OWNER_GPIO, \ .conf1 = GPIO_SENSE_DISABLE } +/* Number of pins used by SerialIo controllers */ +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 + +/* Below defines are based on GPIO_CONFIG structure fields */ +#define GPIO_CONF_PAD_MODE_MASK 0xF +#define GPIO_CONF_PAD_MODE_BIT_POS 0 + +/* GPIO Pad Mode */ +#define B_PCH_GPIO_PAD_MODE (0x1000 | 0x800 | 0x400) +#define N_PCH_GPIO_PAD_MODE 10 + struct gpio_config { u8 gpio; u32 conf0; diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c index 8aa1053..c53643a 100644 --- a/src/soc/intel/skylake/romstage/uart.c +++ b/src/soc/intel/skylake/romstage/uart.c @@ -25,6 +25,9 @@ #include <soc/pcr.h> #include <soc/romstage.h> #include <soc/serialio.h> +#include <gpio.h> + +static void uartgpioinit(u8 hwflowcontrol); void pch_uart_init(void) { @@ -32,7 +35,7 @@ void pch_uart_init(void) u32 tmp; u8 *base = (u8 *)CONFIG_TTYS0_BASE; - /* Set configured UART base address */ + /* Set configured UART2 base address */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base); /* Enable memory access and bus master */ @@ -40,7 +43,7 @@ void pch_uart_init(void) tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, tmp); - /* Take UART out of reset */ + /* Take UART2 out of reset */ tmp = read32(base + SIO_REG_PPR_RESETS); tmp |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | SIO_REG_PPR_RESETS_IDMA; @@ -56,4 +59,61 @@ void pch_uart_init(void) /* Put UART2 in byte access mode for 16550 compatibility */ pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2); + + /* Configure GPIO for UART2 in native mode*/ + uartgpioinit(FALSE); +} + +/* + * GPIO modes + */ +typedef struct { + GPIO_PAD pad; + GPIO_PAD_MODE mode; +} GPIO_PAD_NATIVE_FUNCTION; + +/* + * GPP_C Community for UART2 GPIO + * pin order RXD/TXD/RTSB/CTSB + */ +static const GPIO_PAD_NATIVE_FUNCTION uartgpio[] = { + {GPIO_LP_GPP_C20, GpioPadModeNative1}, + {GPIO_LP_GPP_C21, GpioPadModeNative1}, + {GPIO_LP_GPP_C22, GpioPadModeNative1}, + {GPIO_LP_GPP_C23, GpioPadModeNative1} +}; + +/* + * GPIO config registers + */ +static const GPIO_GROUP_INFO gpio_group_info = { + PID_GPIOCOM1, + R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET, + V_PCH_GPIO_GPP_C_PAD_MAX, + R_PCH_PCR_GPIO_GPP_C_SMI_STS, + R_PCH_PCR_GPIO_GPP_C_SMI_EN +}; + +static void uartgpioinit(u8 hwflowcontrol) +{ + u32 index, pinsused, dw0reg, dw0regmask, padcfgreg, padnumber; + + if (hwflowcontrol) + pinsused = PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER; + else + pinsused = PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL; + + for (index = 0; index < pinsused; index++) { + padnumber = GPIO_GET_PAD_NUMBER(uartgpio[index].pad); + padcfgreg = 0x8 * padnumber + gpio_group_info.padcfgoffset; + dw0regmask = (uartgpio[index].mode & GPIO_CONF_PAD_MODE_MASK) + >> GPIO_CONF_PAD_MODE_BIT_POS; + dw0regmask = (GpioHardwareDefault == dw0regmask) ? + 0x0 : B_PCH_GPIO_PAD_MODE; + dw0reg = (((uartgpio[index].mode & GPIO_CONF_PAD_MODE_MASK) >> + (GPIO_CONF_PAD_MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE); + + pcr_andthenor32(gpio_group_info.community, padcfgreg, + ~(u32)dw0regmask, (u32)dw0reg); + } }

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New patch to review for coreboot: Skylake: Only support UART2 as debug port, clean up the rest
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10994 -gerrit commit dbbd53f62d7c8f39ad2f92188926bab33f0d1c7e Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Wed Jul 15 16:02:25 2015 +0530 Skylake: Only support UART2 as debug port, clean up the rest On Skylake, only UART2 is supported as debug port and the macros INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and Glados boards. BRANCH=none BUG=chrome-os-partner:40857 TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2 Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642 Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285793 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> --- src/mainboard/intel/kunimitsu/Kconfig | 5 ----- src/mainboard/intel/sklrvp/Kconfig | 5 ----- src/soc/intel/skylake/Kconfig | 15 ++------------- src/soc/intel/skylake/romstage/Makefile.inc | 2 +- src/soc/intel/skylake/romstage/romstage.c | 3 +-- src/soc/intel/skylake/romstage/uart.c | 26 +++++--------------------- src/soc/intel/skylake/uart.c | 13 +------------ 7 files changed, 10 insertions(+), 59 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 8971d71..78d4081 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER - select INTEL_PCH_UART_CONSOLE select LID_SWITCH select MAINBOARD_HAS_CHROMEOS select MARK_GRAPHICS_MEM_WRCOMB @@ -33,10 +32,6 @@ config BOOT_MEDIA_SPI_BUS int default 0 -config INTEL_PCH_UART_CONSOLE_NUMBER - hex - default 2 - config MAINBOARD_DIR string default "intel/kunimitsu" diff --git a/src/mainboard/intel/sklrvp/Kconfig b/src/mainboard/intel/sklrvp/Kconfig index 22ce473..601efb0 100644 --- a/src/mainboard/intel/sklrvp/Kconfig +++ b/src/mainboard/intel/sklrvp/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select PCIEXP_L1_SUB_STATE - select INTEL_PCH_UART_CONSOLE select SOC_INTEL_SKYLAKE select VBOOT_DYNAMIC_WORK_BUFFER select VIRTUAL_DEV_SWITCH @@ -30,10 +29,6 @@ config BOOT_MEDIA_SPI_BUS int default 0 -config INTEL_PCH_UART_CONSOLE_NUMBER - hex - default 2 - config MAINBOARD_DIR string default "intel/sklrvp" diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 207816d..856b84f 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -17,6 +17,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CACHE_ROM select CAR_MIGRATION + select CONSOLE_SERIAL8250MEM select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_MICROCODE_IN_CBFS @@ -24,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_HARD_RESET select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER + select HAVE_UART_MEMORY_MAPPED select IOAPIC select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT @@ -160,18 +162,6 @@ config IFD_PLATFORM_SECTION string default "" -config INTEL_PCH_UART_CONSOLE - bool "Use Serial IO UART for console" - default n - select HAVE_UART_MEMORY_MAPPED - select CONSOLE_SERIAL8250MEM - depends on !CONFIG_DRIVERS_OXFORD_OXPCIE - -config INTEL_PCH_UART_CONSOLE_NUMBER - hex "Serial IO UART number to use for console" - default "0x0" - depends on INTEL_PCH_UART_CONSOLE - config ME_BIN_PATH string "Path to management engine firmware" depends on HAVE_ME_BIN @@ -222,7 +212,6 @@ config SMM_TSEG_SIZE config TTYS0_BASE hex default 0xfe034000 - depends on INTEL_PCH_UART_CONSOLE config VGA_BIOS_ID string diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 52029fc..68467b5 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -6,4 +6,4 @@ romstage-y += romstage.c romstage-y += smbus.c romstage-y += spi.c romstage-y += systemagent.c -romstage-$(CONFIG_INTEL_PCH_UART_CONSOLE) += uart.c +romstage-y += uart.c diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 4230664..919b747 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -50,8 +50,7 @@ void soc_pre_console_init(struct romstage_params *params) /* System Agent Early Initialization */ systemagent_early_init(); - if (IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)) - pch_uart_init(); + pch_uart_init(); } /* SOC initialization before RAM is enabled */ diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c index 8ddcbad..8aa1053 100644 --- a/src/soc/intel/skylake/romstage/uart.c +++ b/src/soc/intel/skylake/romstage/uart.c @@ -28,27 +28,10 @@ void pch_uart_init(void) { - device_t dev; - u32 tmp, legacy; + device_t dev = PCH_DEV_UART2; + u32 tmp; u8 *base = (u8 *)CONFIG_TTYS0_BASE; - switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { - case 0: - dev = PCH_DEV_UART0; - legacy = SIO_PCH_LEGACY_UART0; - break; - case 1: - dev = PCH_DEV_UART1; - legacy = SIO_PCH_LEGACY_UART1; - break; - case 2: - dev = PCH_DEV_UART2; - legacy = SIO_PCH_LEGACY_UART2; - break; - default: - return; - } - /* Set configured UART base address */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base); @@ -70,6 +53,7 @@ void pch_uart_init(void) (SIO_REG_PPR_CLOCK_M_DIV << 1); write32(base + SIO_REG_PPR_CLOCK, tmp); - /* Put UART in byte access mode for 16550 compatibility */ - pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, legacy); + /* Put UART2 in byte access mode for 16550 compatibility */ + pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, + SIO_PCH_LEGACY_UART2); } diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 36b1b5a..03d2ba6 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -28,18 +28,7 @@ static int pch_uart_is_debug(struct device *dev) { - if (!IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)) - return 0; - - switch (dev->path.pci.devfn) { - case PCH_DEVFN_UART0: - return CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0; - case PCH_DEVFN_UART1: - return CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1; - case PCH_DEVFN_UART2: - return CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 2; - } - return 0; + return dev->path.pci.devfn == PCH_DEVFN_UART2; } static void pch_uart_read_resources(struct device *dev)

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New patch to review for coreboot: intel fsp: remove CHIPSET_RESERVED_MEM_BYTES
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10993 -gerrit commit f788975332b88cdbc9f5936b13ba6449cd45781d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 13 16:55:28 2015 -0500 intel fsp: remove CHIPSET_RESERVED_MEM_BYTES FSP 1.1 platforms should be conforming to the spec. In order to ensure following specification remove the crutch that allows FSP to no conform. BUG=chrome-os-partner:41961 BRANCH=None TEST=Built. Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285187 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/braswell/memmap.c | 2 +- src/soc/intel/braswell/northcluster.c | 2 -- src/soc/intel/common/Kconfig | 12 ------------ src/soc/intel/common/raminit.c | 5 ----- src/soc/intel/skylake/memmap.c | 2 +- src/soc/intel/skylake/systemagent.c | 3 --- 6 files changed, 2 insertions(+), 24 deletions(-) diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 28156a3..d1d784d 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -81,5 +81,5 @@ void *cbmem_top(void) */ smm_region((void **)&smm_base, &smm_size); - return (void *)(smm_base - CONFIG_CHIPSET_RESERVED_MEM_BYTES); + return (void *)smm_base; } diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index d5d7268..7821a2a 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -52,8 +52,6 @@ * +--------------------------+ SMMRRH, IRM0 * | TSEG | * +--------------------------+ SMMRRL - * | FSP Reserved Mem | - * +--------------------------+ SMMRRL - CONFIG_CHIPSET_RESERVED_MEM_BYTES * | Usable DRAM | * +--------------------------+ 0 * diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 3d0c0ef..68d3f5e 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -36,18 +36,6 @@ endif # CACHE_MRC_SETTINGS endif # HAVE_MRC -config CHIPSET_RESERVED_MEM_BYTES - hex "Size in bytes of chipset reserved memory area" - default 0 - help - If insufficient documentation is available to determine the size of - the chipset reserved memory area by walking the chipset registers, - the CHIPSET_RESERVED_MEM_BYTES may be used as a workaround to account - for the missing pieces of memory. The value specified in bytes is: - - value = TSEG base - top of low usable memory - (any sizes determined - by reading chipset registers) - config DISPLAY_MTRRS bool "MTRRs: Display the MTRR settings" default n diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c index 0e764cd..69ae114 100644 --- a/src/soc/intel/common/raminit.c +++ b/src/soc/intel/common/raminit.c @@ -153,8 +153,6 @@ void raminit(struct romstage_params *params) #endif /* Migrate CAR data */ - printk(BIOS_DEBUG, "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n", - CONFIG_CHIPSET_RESERVED_MEM_BYTES); printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); if (pei_ptr->boot_mode != SLEEP_STATE_S3) { cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, @@ -268,9 +266,6 @@ void raminit(struct romstage_params *params) - cbmem_root->PhysicalStart - cbmem_root->ResourceLength; printk(BIOS_DEBUG, - "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n", - CONFIG_CHIPSET_RESERVED_MEM_BYTES); - printk(BIOS_DEBUG, "0x%08x: Chipset reserved bytes reported by FSP\n", (unsigned int)delta_bytes); die("Please verify the chipset reserved size\n"); diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index f8ef01a..bba93cb 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -96,6 +96,6 @@ void *cbmem_top(void) top_of_ram = ALIGN_DOWN(top_of_ram, mmap_region_granluarity()); } - return (void *)(top_of_ram - CONFIG_CHIPSET_RESERVED_MEM_BYTES); + return (void *)top_of_ram; } diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 2034e8e..a1bcfdc 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -351,15 +351,12 @@ static void mc_add_dram_resources(device_t dev) base_k = 0xc0000 >> 10; size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; size_k -= dpr_size >> 10; - size_k -= CONFIG_CHIPSET_RESERVED_MEM_BYTES >> 10; ram_resource(dev, index++, base_k, size_k); /* TSEG - DPR -> BGSM */ resource = new_resource(dev, index++); resource->base = mc_values[TSEG_REG] - dpr_size; resource->size = mc_values[BGSM_REG] - resource->base; - resource->base -= CONFIG_CHIPSET_RESERVED_MEM_BYTES; - resource->size += CONFIG_CHIPSET_RESERVED_MEM_BYTES; resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;

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New patch to review for coreboot: cyan/strago: Disable wwan
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10992 -gerrit commit 8dd14484672cd42d9d90bbaba9d8a88eb7f2af5e Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Tue Jun 23 19:23:25 2015 -0700 cyan/strago: Disable wwan Disabling the wwan gpio line since wwan is not used. BRANCH=none BUG=none TEST=wwan should not connect to network on cyan/strago. Change-Id: I9d2e5d5b185a4622218e894d3b092afe15e09289 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9a20c602b3bb768baa38b17e21cb4e5b0d9249ef Original-Change-Id: Ib8d5fd15a172ef898ce675a85c2ea3e5f5c79144 Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285304 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/cyan/gpio.c | 2 +- src/mainboard/google/cyan/gpio_pre_evt.c | 2 +- src/mainboard/intel/strago/gpio.c | 2 +- src/mainboard/intel/strago/gpio_bcrd2.c | 2 +- src/mainboard/intel/strago/gpio_dvt.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c index 8edbad6..3cd319d 100644 --- a/src/mainboard/google/cyan/gpio.c +++ b/src/mainboard/google/cyan/gpio.c @@ -94,7 +94,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* GPO FST_SPI_CS1_B */ Native_M1, /* 05 FST_SPI_D1 */ Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ GPIO_NC, /* 15 UART1_RTS_B */ Native_M2, /* 16 UART1_RXD */ GPIO_NC, /* 17 UART2_RXD */ diff --git a/src/mainboard/google/cyan/gpio_pre_evt.c b/src/mainboard/google/cyan/gpio_pre_evt.c index 2ccc5d5..eb285ac 100644 --- a/src/mainboard/google/cyan/gpio_pre_evt.c +++ b/src/mainboard/google/cyan/gpio_pre_evt.c @@ -96,7 +96,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* GPO FST_SPI_CS1_B */ Native_M1, /* 05 FST_SPI_D1 */ Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ GPIO_NC, /* 15 UART1_RTS_B */ Native_M2, /* 16 UART1_RXD */ GPIO_NC, /* 17 UART2_RXD */ diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 53d9039..3ca07e6 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -96,7 +96,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* GPO FST_SPI_CS1_B */ Native_M1, /* 05 FST_SPI_D1 */ Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ GPIO_NC, /* 15 UART1_RTS_B */ Native_M2, /* 16 UART1_RXD */ GPIO_NC, /* 17 UART2_RXD */ diff --git a/src/mainboard/intel/strago/gpio_bcrd2.c b/src/mainboard/intel/strago/gpio_bcrd2.c index 3a4123d..b63db0b 100644 --- a/src/mainboard/intel/strago/gpio_bcrd2.c +++ b/src/mainboard/intel/strago/gpio_bcrd2.c @@ -96,7 +96,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* GPO FST_SPI_CS1_B */ Native_M1, /* 05 FST_SPI_D1 */ Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ GPIO_NC, /* 15 UART1_RTS_B */ Native_M2, /* 16 UART1_RXD */ GPIO_NC, /* 17 UART2_RXD */ diff --git a/src/mainboard/intel/strago/gpio_dvt.c b/src/mainboard/intel/strago/gpio_dvt.c index 3c13f45..920c9d4 100755 --- a/src/mainboard/intel/strago/gpio_dvt.c +++ b/src/mainboard/intel/strago/gpio_dvt.c @@ -94,7 +94,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* GPO FST_SPI_CS1_B */ Native_M1, /* 05 FST_SPI_D1 */ Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ GPIO_NC, /* 15 UART1_RTS_B */ Native_M2, /* 16 UART1_RXD */ GPIO_NC, /* 17 UART2_RXD */

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New patch to review for coreboot: braswell: clean up \_PR entries
by Patrick Georgi 20 Jul '15

20 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10991 -gerrit commit a35ab5be0183596a4a17a6a54769f3a8f01df569 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Thu Jul 9 00:32:32 2015 -0700 braswell: clean up \_PR entries All \_PR entries needs to be changed from CPU# to CP## so that it can support more cores. BRANCH=none BUG=chrome-os-partner:38734 TEST=build and boot cyan/strago boards. Change-Id: I80a79ec8edbce46826140470645b7532ae361f91 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ca269a7ffcd2ef16fcef93851e68c2d91104e3e1 Original-Change-Id: I48e73742dc3b11ee6e96f70bcd2d10d01609ad7c Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285700 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/braswell/acpi/cpu.asl | 38 ++++++++++++++++---------------- src/soc/intel/braswell/acpi/dptf/cpu.asl | 38 ++++++++++++++++---------------- 2 files changed, 38 insertions(+), 38 deletions(-) diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl index d487974..0ae51f2 100644 --- a/src/soc/intel/braswell/acpi/cpu.asl +++ b/src/soc/intel/braswell/acpi/cpu.asl @@ -30,22 +30,22 @@ #define DPTF_CPU_ACTIVE_AC4 50 /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) /* _CST */ - Notify (\_PR.CPU1, 0x81) /* _CST */ + Notify (\_PR.CP00, 0x81) /* _CST */ + Notify (\_PR.CP01, 0x81) /* _CST */ } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) /* _CST */ - Notify (\_PR.CPU3, 0x81) /* _CST */ + Notify (\_PR.CP02, 0x81) /* _CST */ + Notify (\_PR.CP03, 0x81) /* _CST */ } } @@ -53,12 +53,12 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) /* _PPC */ - Notify (\_PR.CPU1, 0x80) /* _PPC */ + Notify (\_PR.CP00, 0x80) /* _PPC */ + Notify (\_PR.CP01, 0x80) /* _PPC */ } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) /* _PPC */ - Notify (\_PR.CPU3, 0x80) /* _PPC */ + Notify (\_PR.CP02, 0x80) /* _PPC */ + Notify (\_PR.CP03, 0x80) /* _PPC */ } } @@ -66,12 +66,12 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) /* _TPC */ - Notify (\_PR.CPU1, 0x82) /* _TPC */ + Notify (\_PR.CP00, 0x82) /* _TPC */ + Notify (\_PR.CP01, 0x82) /* _TPC */ } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) /* _TPC */ - Notify (\_PR.CPU3, 0x82) /* _TPC */ + Notify (\_PR.CP02, 0x82) /* _TPC */ + Notify (\_PR.CP03, 0x82) /* _TPC */ } } @@ -79,10 +79,10 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl index 9b1930b..018144c 100644 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -1,8 +1,8 @@ -External (\_PR.CPU0._TSS, MethodObj) -External (\_PR.CPU0._TPC, MethodObj) -External (\_PR.CPU0._PTC, PkgObj) -External (\_PR.CPU0._TSD, PkgObj) -External (\_PR.CPU0._PSS, MethodObj) +External (\_PR.CP00._TSS, MethodObj) +External (\_PR.CP00._TPC, MethodObj) +External (\_PR.CP00._PTC, PkgObj) +External (\_PR.CP00._TSD, PkgObj) +External (\_PR.CP00._PSS, MethodObj) External (\_SB.DPTF.CTOK, MethodObj) Device (B0DB) @@ -24,8 +24,8 @@ Device (B0DB) Method (_TSS) { - If (CondRefOf (\_PR.CPU0._TSS)) { - Return (\_PR.CPU0._TSS) + If (CondRefOf (\_PR.CP00._TSS)) { + Return (\_PR.CP00._TSS) } Else { Return (Package () { @@ -36,8 +36,8 @@ Device (B0DB) Method (_TPC) { - If (CondRefOf (\_PR.CPU0._TPC)) { - Return (\_PR.CPU0._TPC) + If (CondRefOf (\_PR.CP00._TPC)) { + Return (\_PR.CP00._TPC) } Else { Return (0) } @@ -45,8 +45,8 @@ Device (B0DB) Method (_PTC) { - If (CondRefOf (\_PR.CPU0._PTC)) { - Return (\_PR.CPU0._PTC) + If (CondRefOf (\_PR.CP00._PTC)) { + Return (\_PR.CP00._PTC) } Else { Return (Package () { @@ -58,8 +58,8 @@ Device (B0DB) Method (_TSD) { - If (CondRefOf (\_PR.CPU0._TSD)) { - Return (\_PR.CPU0._TSD) + If (CondRefOf (\_PR.CP00._TSD)) { + Return (\_PR.CP00._TSD) } Else { Return (Package () { @@ -70,8 +70,8 @@ Device (B0DB) Method (_TDL) { - If (CondRefOf (\_PR.CPU0._TSS)) { - Store (SizeOf (\_PR.CPU0._TSS ()), Local0) + If (CondRefOf (\_PR.CP00._TSS)) { + Store (SizeOf (\_PR.CP00._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -98,8 +98,8 @@ Device (B0DB) Method (_PSS) { - If (CondRefOf (\_PR.CPU0._PSS)) { - Return (\_PR.CPU0._PSS) + If (CondRefOf (\_PR.CP00._PSS)) { + Return (\_PR.CP00._PSS) } Else { Return (Package () { @@ -113,8 +113,8 @@ Device (B0DB) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CPU0._PSS)) { - Store (SizeOf (\_PR.CPU0._PSS ()), Local0) + } ElseIf (CondRefOf (\_PR.CP00._PSS)) { + Store (SizeOf (\_PR.CP00._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else {

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coreboot-gerrit July 2015