coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: intel/kunimitsu: Fix Kconfig symbol type
by gerrit＠coreboot.org 18 Jul '15

18 Jul '15

the following patch was just integrated into master: commit ef21e77bbcbc32ba0722ba961dfe2d6672bf05d2 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Jul 17 23:31:19 2015 +0200 intel/kunimitsu: Fix Kconfig symbol type BOOT_MEDIA_SPI_BUS is int, not hex. Change-Id: I5cbcc3889a025caab921208037c8a61d224078a7 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10973 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/10973 for details. -gerrit

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Patch set updated for coreboot: vendorcode: 64bit fixes for AMD CIMX SB800
by Stefan Reinauer 18 Jul '15

18 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10573 -gerrit commit 320262ebe99c422783d0f3aadd51c0fa2757cc4f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jun 17 16:05:05 2015 -0700 vendorcode: 64bit fixes for AMD CIMX SB800 Make SB800 code compile with x64 compiler These fixes probably apply 1:1 to the other SB components in that directory. Change-Id: I9ff9f27dff5074d2faf41ebc14bfe50871d9c7f7 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/vendorcode/amd/cimx/sb800/DISPATCHER.c | 8 ++------ src/vendorcode/amd/cimx/sb800/Makefile.inc | 5 +++++ src/vendorcode/amd/cimx/sb800/SBMAIN.c | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c index 84bbccb..8b35047 100644 --- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c +++ b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c @@ -183,11 +183,7 @@ LocateImage ( ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1); while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) { -#ifdef x64 - 12346789 -#else - Result = VerifyImage (Signature, (VOID*) ImagePtr); -#endif + Result = VerifyImage (Signature, (VOID*)(UINTN)ImagePtr); if ( Result != NULL ) { return Result; } @@ -244,7 +240,7 @@ saveConfigPointer ( UINT8 i; UINT32 ddValue; - ddValue = (UINT32) (UINTN)pConfig; + ddValue = (UINT32) (UINTN)pConfig; // Needs to live below 4G dbReg = SB_ECMOS_REG08; for ( i = 0; i <= 3; i++ ) { diff --git a/src/vendorcode/amd/cimx/sb800/Makefile.inc b/src/vendorcode/amd/cimx/sb800/Makefile.inc index 96cae03..fde6239 100644 --- a/src/vendorcode/amd/cimx/sb800/Makefile.inc +++ b/src/vendorcode/amd/cimx/sb800/Makefile.inc @@ -22,6 +22,11 @@ CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/cimx/sb800 CPPFLAGS_x86_32 += -I$(src)/include/cpu/amd/common CPPFLAGS_x86_32 += -I$(src)/vendorcode/amd/cimx/sb800 +CPPFLAGS_x86_64 += -I$(src)/mainboard/$(MAINBOARDDIR) +CPPFLAGS_x86_64 += -I$(src)/southbridge/amd/cimx/sb800 +CPPFLAGS_x86_64 += -I$(src)/include/cpu/amd/common +CPPFLAGS_x86_64 += -I$(src)/vendorcode/amd/cimx/sb800 + romstage-y += ACPILIB.c romstage-y += AZALIA.c romstage-y += DISPATCHER.c diff --git a/src/vendorcode/amd/cimx/sb800/SBMAIN.c b/src/vendorcode/amd/cimx/sb800/SBMAIN.c index eb21770..a494d30 100644 --- a/src/vendorcode/amd/cimx/sb800/SBMAIN.c +++ b/src/vendorcode/amd/cimx/sb800/SBMAIN.c @@ -240,7 +240,7 @@ sbSmmAcpiOn ( * @param[in] Data Callback specific data. * @param[in] pConfig Southbridge configuration structure pointer. */ -UINTN +UINT32 CallBackToOEM ( IN UINT32 Func, IN UINT32 Data,

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Patch set updated for coreboot: cpu: port amd/agesa to 64bit
by Stefan Reinauer 18 Jul '15

18 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10579 -gerrit commit 5fe3e8dcb24bea81cdae415bd1349bb86ea9a448 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:14:01 2015 -0700 cpu: port amd/agesa to 64bit Change-Id: I8644b04f4b57db5fc95ec155d3f78d53c63c9831 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/cpu/amd/agesa/cache_as_ram.inc | 66 ++++++++++++++++++++++++++++++++++++-- src/cpu/amd/agesa/s3_resume.c | 7 ++++ 2 files changed, 71 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index a8dbee8..b19f03b 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -64,9 +64,67 @@ cache_as_ram_setup: cvtsi2sd %ebx, %xmm1 post_code(0xa1) - AMD_ENABLE_STACK - post_code(0xa1) +#ifdef __x86_64__ + /* switch to 64 bit long mode */ + .intel_syntax noprefix + + mov ecx, esi + add ecx, 0 # core number + xor eax, eax + lea edi, [ecx+0x1000+0x23] + mov dword ptr [ecx+0], edi + mov dword ptr [ecx+4], eax + + lea edi, [ecx+0x1000] + mov dword ptr [edi+0x00], 0x000000e3 + mov dword ptr [edi+0x04], eax + mov dword ptr [edi+0x08], 0x400000e3 + mov dword ptr [edi+0x0c], eax + mov dword ptr [edi+0x10], 0x800000e3 + mov dword ptr [edi+0x14], eax + mov dword ptr [edi+0x18], 0xc00000e3 + mov dword ptr [edi+0x1c], eax + + # load rom based identity mapped page tables + mov eax, ecx + mov cr3,eax + + # enable PAE + mov eax, cr4 + bts eax, 5 + mov cr4, eax + + # enable long mode + mov ecx, 0xC0000080 + rdmsr + bts eax, 8 + wrmsr + + # enable paging + mov eax, cr0 + bts eax, 31 + mov cr0, eax + + # use call far to switch to 64-bit code segment + jmp 0x18,.+7 + + /* Pass the BIST result */ + cvtsd2si esi, xmm1 + + /* Pass the cpu_init_detected */ + cvtsd2si edi, xmm0 + + /* align the stack */ + and esp, 0xFFFFFFF0 + + .code64 + call cache_as_ram_main + .code32 + + .att_syntax prefix +#else + AMD_ENABLE_STACK /* Restore the BIST result */ cvtsd2si %xmm0, %edx @@ -77,6 +135,7 @@ cache_as_ram_setup: pushl %ebx /* init detected */ pushl %edx /* bist */ call cache_as_ram_main +#endif /* Should never see this postcode */ post_code(0xaf) @@ -108,3 +167,6 @@ disable_cache_as_ram: ret cache_as_ram_setup_out: +#ifdef __x86_64__ +.code64 +#endif diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 5e07d7a..98671f4 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -56,10 +56,17 @@ static void move_stack_high_mem(void) memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); /* TODO: We only switch stack on BSP. */ +#ifdef __x86_64__ + __asm__ + volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g" + (high_stack - BSP_STACK_BASE_ADDR) + :); +#else __asm__ volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" (high_stack - BSP_STACK_BASE_ADDR) :); +#endif } static void set_resume_cache(void)

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Patch set updated for coreboot: SB800: Port to 64bit
by Stefan Reinauer 18 Jul '15

18 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10582 -gerrit commit 6bc5e4b12ca50cd2c6f795cabce6dd515313a3af Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:17:38 2015 -0700 SB800: Port to 64bit Change-Id: I944fb254e9470c80b13c9eef9d6b1177a56e615f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/southbridge/amd/cimx/sb800/fadt.c | 21 +++++++++++++++------ src/southbridge/amd/cimx/sb800/gpio_oem.h | 6 +++--- src/southbridge/amd/cimx/sb800/late.c | 15 ++++++++------- src/southbridge/amd/cimx/sb800/spi.c | 2 +- 4 files changed, 27 insertions(+), 17 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 70173b6..b6f15a0 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -63,8 +63,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; + if ((uintptr_t)facs > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n"); + else + fadt->firmware_ctrl = (uintptr_t)facs; + + if ((uintptr_t)dsdt > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n"); + else + fadt->dsdt = (uintptr_t)dsdt; + fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 – ACPI SCI */ @@ -153,10 +161,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; + + fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; + fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32; + fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; + fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/southbridge/amd/cimx/sb800/gpio_oem.h b/src/southbridge/amd/cimx/sb800/gpio_oem.h index a9f59e3..e2c81fc 100644 --- a/src/southbridge/amd/cimx/sb800/gpio_oem.h +++ b/src/southbridge/amd/cimx/sb800/gpio_oem.h @@ -11,9 +11,9 @@ #define SB_GPIO_REG28 28 /* FCH GPIO access helpers */ -#define FCH_IOMUX(gpio_nr) (*(u8*)(ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr))) -#define FCH_PMIO(reg_nr) (*(u8*)(ACPI_MMIO_BASE+PMIO_BASE+(reg_nr))) -#define FCH_GPIO(gpio_nr) (*(volatile u8*)(ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr))) +#define FCH_IOMUX(gpio_nr) (*(u8*)((uintptr_t)ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr))) +#define FCH_PMIO(reg_nr) (*(u8*)((uintptr_t)ACPI_MMIO_BASE+PMIO_BASE+(reg_nr))) +#define FCH_GPIO(gpio_nr) (*(volatile u8*)((uintptr_t)ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr))) static inline u8 fch_gpio_state(unsigned int gpio_nr) { diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 0ada673..cf7fb1c 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -92,7 +92,8 @@ static u32 sb800_callout_entry(u32 func, u32 data, void* config) static void ahci_raid_init(struct device *dev) { u8 irq = 0; - u32 bar5, caps, ports, val; + void *bar5; + u32 caps, ports, val; val = pci_read_config16(dev, PCI_CLASS_DEVICE); if (val == PCI_CLASS_STORAGE_SATA) { @@ -105,18 +106,18 @@ static void ahci_raid_init(struct device *dev) } irq = pci_read_config8(dev, PCI_INTERRUPT_LINE); - bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); + bar5 = (void *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "IOMEM base: %p, IRQ: 0x%X\n", bar5, irq); - caps = *(volatile u32 *)(bar5 + HOST_CAP); + caps = read32(bar5 + HOST_CAP); caps = (caps & 0x1F) + 1; - ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); + ports= read32(bar5 + HOST_PORTS_IMPL); printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); /* make sure ahci is enabled */ - val = *(volatile u32 *)(bar5 + HOST_CTL); + val = read32(bar5 + HOST_CTL); if (!(val & HOST_CTL_AHCI_EN)) { - *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; + write32(bar5 + HOST_CTL, val | HOST_CTL_AHCI_EN); } dev->command |= PCI_COMMAND_MASTER; diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 1ce7fcd..694a3b7 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -35,7 +35,7 @@ static int bus_claimed = 0; #define AMD_SB_SPI_TX_LEN 8 -static u32 spibar; +static uintptr_t spibar; static void reset_internal_fifo_pointer(void) {

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Patch set updated for coreboot: vendorcode: Port AMD Agesa for Fam14 to 64bit
by Stefan Reinauer 18 Jul '15

18 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10581 -gerrit commit e812fbdd4f0ef01db4be0ebd6db63440a7112b75 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:16:40 2015 -0700 vendorcode: Port AMD Agesa for Fam14 to 64bit Change-Id: Ic6b3c3382a6d3fdc6d716ea899db598910b4fe3e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 46 +++++++++++------------ src/vendorcode/amd/agesa/f14/Makefile.inc | 6 +++ src/vendorcode/amd/agesa/f14/gcccar.inc | 4 ++ 3 files changed, 33 insertions(+), 23 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 7d90f8b..9ae45c3 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -27,11 +27,11 @@ */ #if defined (__GNUC__) - +#include <stdint.h> /* I/O intrin functions. */ -static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port) +static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port) { - unsigned char value; + uint8_t value; __asm__ __volatile__ ( "in %1, %0" @@ -42,9 +42,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned return value; } -static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port) +static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port) { - unsigned short value; + uint16_t value; __asm__ __volatile__ ( "in %1, %0" @@ -55,9 +55,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne return value; } -static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port) +static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port) { - unsigned long value; + uint32_t value; __asm__ __volatile__ ( "in %1, %0" @@ -68,7 +68,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne } -static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data) +static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data) { __asm__ __volatile__ ( "out %0, %1" @@ -77,7 +77,7 @@ static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short P ); } -static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data) +static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data) { __asm__ __volatile__ ( "out %0, %1" @@ -86,7 +86,7 @@ static __inline__ __attribute__((always_inline)) void __outword(unsigned short P ); } -static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data) +static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data) { __asm__ __volatile__ ( "out %0, %1" @@ -95,7 +95,7 @@ static __inline__ __attribute__((always_inline)) void __outdword(unsigned short ); } -static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; insb" @@ -104,7 +104,7 @@ static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned sh ); } -static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; insw" @@ -113,7 +113,7 @@ static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned sh ); } -static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; insl" @@ -122,7 +122,7 @@ static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned s ); } -static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; outsb" @@ -131,7 +131,7 @@ static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned s ); } -static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; outsw" @@ -140,7 +140,7 @@ static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned s ); } -static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; outsl" @@ -525,7 +525,7 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source) } static __inline__ __attribute__((always_inline)) void -__writefsbyte(const unsigned long Offset, const unsigned char Data) +__writefsbyte(const unsigned long Offset, const uint8_t Data) { __asm__ ("movb %[Data], %%fs:%a[Offset]" : @@ -533,7 +533,7 @@ __writefsbyte(const unsigned long Offset, const unsigned char Data) } static __inline__ __attribute__((always_inline)) void -__writefsword(const unsigned long Offset, const unsigned short Data) +__writefsword(const unsigned long Offset, const uint16_t Data) { __asm__ ("movw %[Data], %%fs:%a[Offset]" : @@ -541,14 +541,14 @@ __writefsword(const unsigned long Offset, const unsigned short Data) } static __inline__ __attribute__((always_inline)) void -__writefsdword(const unsigned long Offset, const unsigned long Data) +__writefsdword(const unsigned long Offset, const uint32_t Data) { __asm__ ("movl %[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "ir" (Data)); } -static __inline__ __attribute__((always_inline)) unsigned char +static __inline__ __attribute__((always_inline)) uint8_t __readfsbyte(const unsigned long Offset) { unsigned char value; @@ -558,7 +558,7 @@ __readfsbyte(const unsigned long Offset) return value; } -static __inline__ __attribute__((always_inline)) unsigned short +static __inline__ __attribute__((always_inline)) uint16_t __readfsword(const unsigned long Offset) { unsigned short value; @@ -568,11 +568,11 @@ __readfsword(const unsigned long Offset) return value; } -static __inline__ __attribute__((always_inline)) unsigned long +static __inline__ __attribute__((always_inline)) uint32_t __readfsdword(unsigned long Offset) { unsigned long value; - __asm__ ("movl %%fs:%a[Offset], %[value]" + __asm__ ("mov %%fs:%a[Offset], %[value]" : [value] "=r" (value) : [Offset] "ir" (Offset)); return value; diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index f62f276..a5f7561 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -64,15 +64,21 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing +CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### classes-y += libagesa +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call create_class_compiler,libagesa,x86_32)) +else +$(eval $(call create_class_compiler,libagesa,x86_64)) +endif libagesa-y = Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 2104c27..4f0f975 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -42,7 +42,11 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +#ifdef __x86_64__ CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ +#else +CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */ +#endif APIC_BASE_ADDRESS = 0x0000001B APIC_BSC = 8 /* Boot Strap Core */

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Patch merged into coreboot/master: skylake: fix whitespace
by gerrit＠coreboot.org 18 Jul '15

18 Jul '15

the following patch was just integrated into master: commit ef6a6a4723a8242e25ce1ec0dfbaf3105fc61c0b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jul 17 13:32:30 2015 -0700 skylake: fix whitespace Found by commit hook. Change-Id: Ic4090106b4b9db7ed9f5de9ed1d439e5bb49039c Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10971 for details. -gerrit

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New patch to review for coreboot: Do not commit: Enable KCONFIG_STRICT mode.
by Stefan Reinauer 18 Jul '15

18 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10978 -gerrit commit 7d68ae4b805f05584c59b38e8f1062abdc80e6ef Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jul 17 17:29:19 2015 -0700 Do not commit: Enable KCONFIG_STRICT mode. Change-Id: I6aa77db1b12a67472302ea39d7433993a6838af6 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index 85a10c0..feac9ab 100644 --- a/Makefile +++ b/Makefile @@ -55,6 +55,7 @@ export KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd export KCONFIG_SPLITCONFIG := $(obj)/config export KCONFIG_TRISTATE := $(obj)/tristate.conf export KCONFIG_NEGATIVES := 1 +export KCONFIG_STRICT := 1 # directory containing the toplevel Makefile.inc TOPLEVEL := .

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New patch to review for coreboot: Kconfig: Add KCONFIG_STRICT mode
by Stefan Reinauer 18 Jul '15

18 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10977 -gerrit commit 5161802f974c95a20ded682a9d9c984043ff7f52 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jul 17 17:26:48 2015 -0700 Kconfig: Add KCONFIG_STRICT mode This is basically a -Werror mode for Kconfig. When exporting KCONFIG_STRICT in the Makefile, warnings in Kconfig will produce errors instead. This will make it easier to spot unclean Kconfig files, settings and dependencies. Change-Id: I941af24c3ccb10b8b9ddc5c98327154749ebbbc6 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/kconfig/confdata.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index 235debf..5804b29 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -358,6 +358,7 @@ load: if (def == S_DEF_USER) { sym = sym_find(line + strlen(CONFIG_)); if (!sym) { + conf_warning("trying to assign non-existent symbol %s", line + strlen(CONFIG_)); sym_add_change_count(1); goto setsym; } @@ -402,6 +403,13 @@ setsym: if (modules_sym) sym_calc_value(modules_sym); + + name = getenv("KCONFIG_STRICT"); + if (name && *name && conf_warnings) { + fprintf(stderr, "\nERROR: %d warnings encountered, and warnings are errors.\n\n", conf_warnings); + return 1; + } + return 0; }

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Patch set updated for coreboot: Makefile: Fix KCONFIG_AUTOHEADER dependencies
by Stefan Reinauer 18 Jul '15

18 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10970 -gerrit commit 3ea7c1add519826e913db2b64f91e03b9a81eb1b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jul 17 13:31:16 2015 -0700 Makefile: Fix KCONFIG_AUTOHEADER dependencies This makes the Makefile more robust when changing the file name or changing the .config outside of make *config Change-Id: Ifc013cc3ef899a7846742a961261ac50bc67e27b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 85a10c0..3a1b83a 100644 --- a/Makefile +++ b/Makefile @@ -138,7 +138,7 @@ real-all: real-target # must come rather early .SECONDEXPANSION: -$(obj)/config.h: +$(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) $(MAKE) oldconfig # Add a new class of source/object files to the build system @@ -218,7 +218,7 @@ define create_cc_template # $4 additional dependencies ifn$(EMPTY)def $(1)-objs_$(2)_template de$(EMPTY)fine $(1)-objs_$(2)_template -$$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $(obj)/config.h $(4) +$$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $(KCONFIG_AUTOHEADER) $(4) @printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" $(CC_$(1)) -MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -MT $$$$(@) $(3) -c -o $$$$@ $$$$< en$(EMPTY)def

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Patch set updated for coreboot: Makefile: use KCONFIG_AUTOHEADER instead of file name
by Stefan Reinauer 18 Jul '15

18 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10970 -gerrit commit 929e16ce1b2da702c28ecbe9fbaa1ba10619cd55 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jul 17 13:31:16 2015 -0700 Makefile: use KCONFIG_AUTOHEADER instead of file name This makes the Makefile more robust when changing the file name. Change-Id: Ifc013cc3ef899a7846742a961261ac50bc67e27b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 85a10c0..3a1b83a 100644 --- a/Makefile +++ b/Makefile @@ -138,7 +138,7 @@ real-all: real-target # must come rather early .SECONDEXPANSION: -$(obj)/config.h: +$(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) $(MAKE) oldconfig # Add a new class of source/object files to the build system @@ -218,7 +218,7 @@ define create_cc_template # $4 additional dependencies ifn$(EMPTY)def $(1)-objs_$(2)_template de$(EMPTY)fine $(1)-objs_$(2)_template -$$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $(obj)/config.h $(4) +$$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $(KCONFIG_AUTOHEADER) $(4) @printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" $(CC_$(1)) -MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -MT $$$$(@) $(3) -c -o $$$$@ $$$$< en$(EMPTY)def

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coreboot-gerrit July 2015