coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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1226 discussions

Patch merged into coreboot/master: cpu: x86 port to 64bit
by gerrit＠coreboot.org 20 Jun '15

20 Jun '15

the following patch was just integrated into master: commit e021dea777e87180d76ad6ac89f9b54b5f1111ad Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:15:27 2015 -0700 cpu: x86 port to 64bit Change-Id: Ib1c6732d3a338f6d898fadc19e5af59032343451 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> Reviewed-on: http://review.coreboot.org/10580 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10580 for details. -gerrit

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Patch merged into coreboot/master: x86: Make ACPI 64bit clean
by gerrit＠coreboot.org 20 Jun '15

20 Jun '15

the following patch was just integrated into master: commit defee17c670c6ec20edfea39afc751cc1c77871f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:11:19 2015 -0700 x86: Make ACPI 64bit clean Change-Id: I29eaba74185711df055cf56c23ef2bdae0c7b43e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10578 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10578 for details. -gerrit

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Patch merged into coreboot/master: x86: Make reading / writing of CRx registers 64bit proof
by gerrit＠coreboot.org 20 Jun '15

20 Jun '15

the following patch was just integrated into master: commit bef400b96cbce8a4947f6b147b4030a9422c2b7f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jun 17 16:11:18 2015 -0700 x86: Make reading / writing of CRx registers 64bit proof Change-Id: I782007fe9754ec3ae0b5dc31e7865f7e46cfbc74 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> Reviewed-on: http://review.coreboot.org/10576 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10576 for details. -gerrit

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Patch merged into coreboot/master: x86: make memcpy 64bit safe
by gerrit＠coreboot.org 20 Jun '15

20 Jun '15

the following patch was just integrated into master: commit 7c35af2bc3152cfc678561465f60884d56380632 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jun 17 16:09:10 2015 -0700 x86: make memcpy 64bit safe This does not optimize memcpy for 64bit, it merely makes it compile. Change-Id: I69ad6bd0c3d5f617d9222643abf7a2ba7c2a0359 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> Reviewed-on: http://review.coreboot.org/10575 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10575 for details. -gerrit

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Patch merged into coreboot/master: xcompile: x86-64-elf wants -Wa, --divide, too
by gerrit＠coreboot.org 20 Jun '15

20 Jun '15

the following patch was just integrated into master: commit 7979dc09a84c653d507b776c0c2bbc1f06c570c5 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jun 17 16:07:38 2015 -0700 xcompile: x86-64-elf wants -Wa,--divide, too Change-Id: I03eb1c0f1e0b0c6213ec6b26cf41dadd4df9b910 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10574 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10574 for details. -gerrit

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New patch to review for coreboot: Kconfig: Remove unnecessary and incorrect MRC_CACHE symbols
by Martin Roth 19 Jun '15

19 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10611 -gerrit commit 8f8793e9a9d8e7567b14044c11fe2180a3ed89b3 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 23:39:38 2015 -0600 Kconfig: Remove unnecessary and incorrect MRC_CACHE symbols Because of a misunderstanding of how Kconfig files are parsed, the OVERRIDE_MRC_CACHE_LOC symbol was added to make sure that the value was correctly set. This is not needed unless for some reason the Kconfig parser is suddenly rewritten to parse everything differently. At some point, the value in the FSP's Kconfig file was updated to OVERRIDE_CACHE_CACHE_LOC, while the entries in the mainboard Kconfig files were not updated. This resulted in the default values not getting set correctly by default on the FSP Baytrail boards. This removes the whole bunch of incorrect and unnecessary symbols and just sets the default for the MRC cache location directly. Change-Id: I1cec758576866b7e0677272b8309bfde8d4a1ee4 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/intel/fsp1_0/Kconfig | 12 ------------ src/drivers/intel/fsp1_1/Kconfig | 12 ------------ src/mainboard/intel/bakersport_fsp/Kconfig | 3 +-- src/mainboard/intel/bayleybay_fsp/Kconfig | 3 +-- src/mainboard/intel/minnowmax/Kconfig | 3 +-- src/mainboard/siemens/mc_tcu3/Kconfig | 3 +-- 6 files changed, 4 insertions(+), 32 deletions(-) diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index d2e144f..020235a 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -82,20 +82,8 @@ config MRC_CACHE_SIZE should be a full sector of the flash ROM chip and nothing else should be included in CBFS in any sector that the fast boot cache data is in. -config OVERRIDE_CACHE_CACHE_LOC - bool - help - Selected by the platform to set a new default location for the - MRC/fast boot cache. - -config MRC_CACHE_LOC_OVERRIDE - hex - help - Sets the override CBFS location of the MRC/fast boot cache. - config MRC_CACHE_LOC hex "Fast Boot Data Cache location in CBFS" - default MRC_CACHE_LOC_OVERRIDE if OVERRIDE_CACHE_CACHE_LOC default 0xfff50000 depends on ENABLE_MRC_CACHE help diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index f722e65..4605711 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -103,7 +103,6 @@ config MRC_CACHE_FILE config MRC_CACHE_LOC hex "Fast Boot Data Cache location in CBFS" - default MRC_CACHE_LOC_OVERRIDE if OVERRIDE_CACHE_CACHE_LOC default 0xfff50000 depends on ENABLE_MRC_CACHE help @@ -113,11 +112,6 @@ config MRC_CACHE_LOC and nothing else should be included in that sector, or IT WILL BE ERASED. -config MRC_CACHE_LOC_OVERRIDE - hex - help - Sets the override CBFS location of the MRC/fast boot cache. - config MRC_CACHE_SIZE hex "Fast Boot Data Cache Size" default 0x10000 @@ -130,12 +124,6 @@ config MRC_CACHE_SIZE should be a full sector of the flash ROM chip and nothing else should be included in CBFS in any sector that the fast boot cache data is in. -config OVERRIDE_CACHE_CACHE_LOC - bool - help - Selected by the platform to set a new default location for the - MRC/fast boot cache. - config VIRTUAL_ROM_SIZE hex "Virtual ROM Size" default ROM_SIZE diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig index edd8803..7f5513a 100644 --- a/src/mainboard/intel/bakersport_fsp/Kconfig +++ b/src/mainboard/intel/bakersport_fsp/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select OVERRIDE_MRC_CACHE_LOC select POST_IO select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT @@ -59,7 +58,7 @@ config FSP_FILE string default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP -config MRC_CACHE_LOC_OVERRIDE +config MRC_CACHE_LOC hex default 0xfff80000 depends on ENABLE_FSP_FAST_BOOT diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 365b3e6..3048126 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select OVERRIDE_MRC_CACHE_LOC select POST_IO select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT @@ -59,7 +58,7 @@ config FSP_FILE string default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" -config MRC_CACHE_LOC_OVERRIDE +config MRC_CACHE_LOC hex default 0xfff80000 depends on ENABLE_FSP_FAST_BOOT diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 86a4fb5..66825c6 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select OVERRIDE_MRC_CACHE_LOC select TSC_MONOTONIC_TIMER select HAVE_ACPI_RESUME @@ -58,7 +57,7 @@ config FSP_FILE string default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" -config MRC_CACHE_LOC_OVERRIDE +config MRC_CACHE_LOC hex default 0xfff80000 depends on ENABLE_FSP_FAST_BOOT diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index 067ccf1..6d01e82 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select OVERRIDE_MRC_CACHE_LOC select INCLUDE_MICROCODE_IN_BUILD select ENABLE_BUILTIN_COM1 select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT @@ -55,7 +54,7 @@ config CACHE_ROM_SIZE_OVERRIDE hex default 0x1000000 -config MRC_CACHE_LOC_OVERRIDE +config MRC_CACHE_LOC hex default 0xfff80000 depends on ENABLE_FSP_FAST_BOOT

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New patch to review for coreboot: Kconfig: Move CBFS_SIZE into Mainboard menu
by Martin Roth 19 Jun '15

19 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10610 -gerrit commit 9639d35517d95b439a6b27d3af1ce885cb77d660 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 23:17:15 2015 -0600 Kconfig: Move CBFS_SIZE into Mainboard menu The CBFS size is really mainboard specific, since it really depends on size of the chip on the mainboard, so it makes sense to have it in the mainboard menu along with the ROM-chip size. - Move the CBFS_SIZE definition up in src/kconfig - Move the Mainboard Menu markers out of src/mainboard/kconfig into src/Kconfig so CBFS_SIZE can live in the mainboard menu. - Add a stupid-long line of default values to do what the chipset directories were previously defaulting the values to. - Update the help text. Change-Id: I2b9eb5a6f7d543f57d9f3b9d0aa44a5462e8b718 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/Kconfig | 28 +++++++++++++++++---------- src/mainboard/Kconfig | 4 ---- src/northbridge/intel/fsp_sandybridge/Kconfig | 11 ----------- src/northbridge/intel/gm45/Kconfig | 11 ----------- src/northbridge/intel/haswell/Kconfig | 12 ------------ src/northbridge/intel/nehalem/Kconfig | 11 ----------- src/northbridge/intel/sandybridge/Kconfig | 12 ------------ src/soc/intel/baytrail/Kconfig | 12 ------------ src/soc/intel/braswell/Kconfig | 12 ------------ src/soc/intel/broadwell/Kconfig | 11 ----------- src/soc/intel/fsp_baytrail/Kconfig | 11 ----------- src/soc/qualcomm/ipq806x/Kconfig | 8 -------- 12 files changed, 18 insertions(+), 125 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index c282d21..2e13e68 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -332,8 +332,26 @@ endmenu source "src/acpi/Kconfig" +menu "Mainboard" + source "src/mainboard/Kconfig" +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default 0x100000 if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL || SOC_INTEL_BROADWELL + default 0x200000 if SOC_INTEL_FSP_BAYTRAIL + default ROM_SIZE + help + This is the part of the ROM actually managed by CBFS, located at the + end of the ROM (passed through cbfstool -o) on x86 and at at the start + of the ROM (passed through cbfstool -s) everywhere else. It defaults + to span the whole ROM on all but Intel systems that use an Intel Firmware + Descriptor. It can be overridden to make coreboot live alongside other + components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE + binaries. + +endmenu + config SYSTEM_TYPE_LAPTOP default n bool @@ -482,16 +500,6 @@ config IOAPIC bool default n -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default ROM_SIZE - help - This is the part of the ROM actually managed by CBFS, located at the - end of the ROM (passed through cbfstool -o) on x86 and at at the start - of the ROM (passed through cbfstool -s) everywhere else. Defaults to - span the whole ROM but can be overwritten to make coreboot live - alongside other components (like ChromeOS's vboot/FMAP). - config CACHE_ROM_SIZE_OVERRIDE hex default 0 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index d7cdc3d..ab8ee26 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -1,5 +1,3 @@ -menu "Mainboard" - choice prompt "Mainboard vendor" default VENDOR_EMULATION @@ -147,5 +145,3 @@ config ENABLE_POWER_BUTTON config ENABLE_POWER_BUTTON def_bool y if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_ENABLE def_bool n if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_DISABLE - -endmenu diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 21d3f65..e1f2e88 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -40,17 +40,6 @@ config VGA_BIOS_ID 0x80860102, 0x8086010a, 0x80860112, 0x80860116 0x80860122, 0x80860126, 0x80860166 -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default 0x100000 - help - On Sandybridge and Ivybridge systems the firmware image may - have to store a lot more than just coreboot, including: - - a firmware descriptor - - Intel Management Engine firmware - This option specifies the maximum size of the CBFS portion in the - firmware image. - # Ivybridge Specific FSP Kconfig source src/northbridge/intel/fsp_sandybridge/fsp/Kconfig diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 9564ea6..2374a1f 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -36,17 +36,6 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/gm45/bootblock.c" -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default 0x100000 - help - On GM45 systems the firmware image may - store a lot more than just coreboot, including: - - a firmware descriptor - - Intel Management Engine firmware - This option allows to limit the size of the CBFS portion in the - firmware image. - config VGA_BIOS_ID string default "8086,2a42" diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index e51ac3c..c5b8088 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -88,18 +88,6 @@ config MRC_FILE The path and filename of the file to use as System Agent binary. -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default 0x100000 - help - On Haswell systems the firmware image has to store a lot more - than just coreboot, including: - - a firmware descriptor - - Intel Management Engine firmware - - MRC cache information - This option allows to limit the size of the CBFS portion in the - firmware image. - config PRE_GRAPHICS_DELAY int "Graphics initialization delay in ms" default 0 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 17c94b6..f115d97 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -49,15 +49,4 @@ config TRAINING_CACHE_SIZE hex default 0x10000 -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default 0x100000 - help - On Nehalem systems the firmware image has to - store a lot more than just coreboot, including: - - a firmware descriptor - - Intel Management Engine firmware - This option allows to limit the size of the CBFS portion in the - firmware image. - endif diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 7eb6948..4dede09 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -110,16 +110,4 @@ config MRC_FILE The path and filename of the file to use as System Agent binary. -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default 0x100000 - help - On Sandybridge and Ivybridge systems the firmware image has to - store a lot more than just coreboot, including: - - a firmware descriptor - - Intel Management Engine firmware - - MRC cache information - This option allows to limit the size of the CBFS portion in the - firmware image. - endif diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5060e45..032a60e 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -146,18 +146,6 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE the system will reset otherwise the ramstage will be reloaded from cbfs. -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default 0x100000 - help - On Bay Trail systems the firmware image has to store a lot more - than just coreboot, including: - - a firmware descriptor - - Intel Management Engine firmware - - MRC cache information - This option allows to limit the size of the CBFS portion in the - firmware image. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index aa191b3..20abff5 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -147,18 +147,6 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE the system will reset otherwise the ramstage will be reloaded from cbfs. -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default 0x100000 - help - On Bay Trail systems the firmware image has to store a lot more - than just coreboot, including: - - a firmware descriptor - - Intel Management Engine firmware - - MRC cache information - This option allows to limit the size of the CBFS portion in the - firmware image. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index a282289..d1f5c71 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -140,17 +140,6 @@ config CACHE_MRC_SETTINGS endif # HAVE_MRC -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default 0x100000 - help - The firmware image has to store more than just coreboot, including: - - a firmware descriptor - - Intel Management Engine firmware - - MRC cache information - This option allows to limit the size of the CBFS portion in the - firmware image. - config PRE_GRAPHICS_DELAY int "Graphics initialization delay in ms" default 0 diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 371ad52..765c57f 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -95,17 +95,6 @@ config CPU_MICROCODE_CBFS_LOC hex default 0xfff10040 -config CBFS_SIZE - hex - default 0x200000 - help - On Bay Trail systems the firmware image has to store a lot more - than just coreboot, including: - - a firmware descriptor - - Intel Trusted Execution Engine firmware - This option specifies the maximum size of the CBFS portion in the - firmware image. - config INCLUDE_ME bool "Include the TXE" default n diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index f07d97b..7f8937c 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -13,14 +13,6 @@ config SOC_QC_IPQ806X if SOC_QC_IPQ806X -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default ROM_SIZE - help - CBFS size needs to match the size of memory allocated to the - coreboot blob elsewhere in the system. Make sure this config option - is fine tuned in the board config file. - config MBN_ENCAPSULATION depends on USE_BLOBS bool "bootblock encapsulation for ipq8064"

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New patch to review for coreboot: Reorder arch & vendorcode in Kconfig
by Martin Roth 19 Jun '15

19 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10609 -gerrit commit 9e73733176c80a45449b97def4758e39eb3a707d Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 22:30:43 2015 -0600 Reorder arch & vendorcode in Kconfig Because Kconfig uses the first valid default that it comes across, the 'source' commands to load sub-Kconfigs should be ordered from the most specific (mainboards) to less specific (chipsets) to least specific (architectures). This allows the mainboards to override chipsets and architecture Kconfig files. Because the architecture files were getting loaded ahead of the chipset and cpu Kconfigs, the preferred defaults values for things such as NUM_IPI_STARTS or RISCV_BOOTBLOCK_CUSTOM could not be set. Change-Id: Ic327452833f012ec06dabb5b5ef661aba3aff464 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/Kconfig | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b7d2e67..c282d21 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -334,10 +334,6 @@ source "src/acpi/Kconfig" source "src/mainboard/Kconfig" -source "src/arch/*/Kconfig" - -source "src/vendorcode/*/Kconfig" - config SYSTEM_TYPE_LAPTOP default n bool @@ -359,6 +355,9 @@ source "src/ec/acpi/Kconfig" source "src/ec/*/*/Kconfig" source "src/drivers/intel/fsp1_0/Kconfig" +source "src/vendorcode/*/Kconfig" +source "src/arch/*/Kconfig" + endmenu source "src/device/Kconfig"

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New patch to review for coreboot: Remove old HAVE_UART_MEMORY_MAPPED select statements
by Martin Roth 19 Jun '15

19 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10608 -gerrit commit c504bec645c0ceba810343c299dc94f59c8d6932 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 21:47:18 2015 -0600 Remove old HAVE_UART_MEMORY_MAPPED select statements The HAVE_UART_MEMORY_MAPPED symbol is no longer present, so these don't actually select anything. Change-Id: I6d0eb610e48a4506ac7449ac677ee67981d0ff0d Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/soc/broadcom/cygnus/Kconfig | 1 - src/soc/imgtec/pistachio/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/nvidia/tegra132/Kconfig | 1 - src/soc/rockchip/rk3288/Kconfig | 1 - 5 files changed, 5 deletions(-) diff --git a/src/soc/broadcom/cygnus/Kconfig b/src/soc/broadcom/cygnus/Kconfig index 5167b4e..7c17bd4 100644 --- a/src/soc/broadcom/cygnus/Kconfig +++ b/src/soc/broadcom/cygnus/Kconfig @@ -28,7 +28,6 @@ config SOC_BROADCOM_CYGNUS select EARLY_CONSOLE select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER - select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL select HAS_PRECBMEM_TIMESTAMP_REGION select RETURN_FROM_VERSTAGE diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 5bb5e1b..7c0f12e 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -22,7 +22,6 @@ config CPU_IMGTEC_PISTACHIO select CPU_MIPS select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER - select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 2ff135c..a789c37 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -174,7 +174,6 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE config INTEL_PCH_UART_CONSOLE bool "Use Serial IO UART for console" default n - select HAVE_UART_MEMORY_MAPPED select CONSOLE_SERIAL8250MEM config INTEL_PCH_UART_CONSOLE_NUMBER diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index a6f076e..be8ae9b 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -11,7 +11,6 @@ config SOC_NVIDIA_TEGRA132 select GENERIC_UDELAY select HAVE_HARD_RESET select HAVE_UART_SPECIAL - select HAVE_UART_MEMORY_MAPPED select EARLY_CONSOLE select ARM_BOOTBLOCK_CUSTOM select SMP diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 103e99b..1b82515 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -26,7 +26,6 @@ config SOC_ROCKCHIP_RK3288 select ARCH_RAMSTAGE_ARMV7 select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY - select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select UNCOMPRESSED_RAMSTAGE

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Patch set updated for coreboot: Remove incorrect Kconfig expressions
by Martin Roth 19 Jun '15

19 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10437 -gerrit commit 7580d9e5dab93d7bb57a5d4b05ba0f93929a6616 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 5 21:01:59 2015 -0600 Remove incorrect Kconfig expressions The symbols used in these expressions were not correct and would never evaluate as true. Change-Id: Ia20177f41505473b14bc7b8e4b6fb16de36cc295 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/soc/intel/broadwell/Kconfig | 1 - src/southbridge/via/vt8237r/Kconfig | 6 ------ 2 files changed, 7 deletions(-) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index a282289..2ff135c 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -176,7 +176,6 @@ config INTEL_PCH_UART_CONSOLE default n select HAVE_UART_MEMORY_MAPPED select CONSOLE_SERIAL8250MEM - depends on !CONFIG_DRIVERS_OXFORD_OXPCIE config INTEL_PCH_UART_CONSOLE_NUMBER hex "Serial IO UART number to use for console" diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index 02cdd34..6019654 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -24,12 +24,6 @@ config SOUTHBRIDGE_VIA_VT8237R if SOUTHBRIDGE_VIA_VT8237R -if NORTHBRIDGE_AMD_K8 || NORTHBRIDGE_AMD_FAM10 -config SOUTH_BRIDGE_OPTIONS # dummy - def_bool y - select HAVE_SMI_HANDLER -endif - config EPIA_VT8237R_INIT bool default n

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coreboot-gerrit June 2015