coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: Remove obsolete EARLY_CONSOLE usage
by Martin Roth 20 Jun '15

20 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10615 -gerrit commit 53f50bcb4b156a9ad4f4ec5041f42216358c69bc Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 20 16:45:30 2015 -0600 Remove obsolete EARLY_CONSOLE usage The EARLY_CONSOLE Kconfig symbol was removed in commit 48713a1b - console: Drop EARLY_CONSOLE option The arm64 and mips directories don't even have early_console.c to include. Change-Id: Idc60ffb2bac2b180f4fdd0adf5c411e1f692a846 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/arch/arm64/Makefile.inc | 1 - src/arch/mips/Makefile.inc | 1 - src/mainboard/emulation/qemu-armv7/Kconfig | 1 - src/soc/broadcom/cygnus/Kconfig | 1 - src/soc/marvell/bg4cd/Kconfig | 1 - src/soc/nvidia/tegra132/Kconfig | 1 - 6 files changed, 6 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 13e8415..f1d0cb3 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -88,7 +88,6 @@ $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld -verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c verstage-y += boot.c verstage-y += div0.c verstage-y += eabi_compat.c diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index cff0151..e3aff0c 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -61,7 +61,6 @@ endif # CONFIG_ARCH_BOOTBLOCK_MIPS ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y) romstage-y += boot.c -romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c romstage-y += cache.c romstage-y += mmu.c romstage-y += stages.c diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 58ddd4e..c6199ea 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_ARMLTD_CORTEX_A9 select DRIVERS_UART_PL011 select BOOTBLOCK_CONSOLE - select EARLY_CONSOLE select CONSOLE_SERIAL select ARM_BOOTBLOCK_ARMV7 select ARM_ROMSTAGE_ARMV7 diff --git a/src/soc/broadcom/cygnus/Kconfig b/src/soc/broadcom/cygnus/Kconfig index 7c17bd4..e6da57c 100644 --- a/src/soc/broadcom/cygnus/Kconfig +++ b/src/soc/broadcom/cygnus/Kconfig @@ -25,7 +25,6 @@ config SOC_BROADCOM_CYGNUS select ARCH_ROMSTAGE_ARMV7 select ARCH_VERSTAGE_ARMV7 select BOOTBLOCK_CONSOLE - select EARLY_CONSOLE select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL diff --git a/src/soc/marvell/bg4cd/Kconfig b/src/soc/marvell/bg4cd/Kconfig index f2cb16f..930645e 100644 --- a/src/soc/marvell/bg4cd/Kconfig +++ b/src/soc/marvell/bg4cd/Kconfig @@ -26,7 +26,6 @@ config SOC_MARVELL_BG4CD select ARCH_VERSTAGE_ARMV7_M select ARM_BOOTBLOCK_CUSTOM if VBOOT_VERIFY_FIRMWARE select BOOTBLOCK_CONSOLE - select EARLY_CONSOLE select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select GENERIC_GPIO_LIB diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index be8ae9b..a5df92a 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -11,7 +11,6 @@ config SOC_NVIDIA_TEGRA132 select GENERIC_UDELAY select HAVE_HARD_RESET select HAVE_UART_SPECIAL - select EARLY_CONSOLE select ARM_BOOTBLOCK_CUSTOM select SMP select ARM64_USE_SECURE_MONITOR

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Patch set updated for coreboot: southbridge/intel: Create common IFD Kconfig and Makefile
by Martin Roth 20 Jun '15

20 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10613 -gerrit commit 20b79644b554477446eceed64f11dd50825b5824 Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 20 16:17:12 2015 -0600 southbridge/intel: Create common IFD Kconfig and Makefile We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC. This is the start of creating a common interface for all of them. This also allows us to reduce the chipset dependencies for CBFS_SIZE. Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/Kconfig | 8 +- src/mainboard/intel/mohonpeak/Kconfig | 8 -- src/southbridge/intel/common/firmware/Kconfig | 94 ++++++++++++++++++++++ src/southbridge/intel/common/firmware/Makefile.inc | 73 +++++++++++++++++ src/southbridge/intel/fsp_bd82x6x/Kconfig | 33 +------- src/southbridge/intel/fsp_bd82x6x/Makefile.inc | 28 +------ src/southbridge/intel/fsp_rangeley/Kconfig | 19 ++--- src/southbridge/intel/fsp_rangeley/Makefile.inc | 16 +--- src/southbridge/intel/lynxpoint/Kconfig | 61 ++------------ src/southbridge/intel/lynxpoint/Makefile.inc | 46 +---------- 10 files changed, 189 insertions(+), 197 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 91a3b29..94b3508 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -338,10 +338,10 @@ source "src/mainboard/Kconfig" config CBFS_SIZE hex "Size of CBFS filesystem in ROM" - default 0x100000 if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \ + default 0x100000 if HAVE_INTEL_FIRMWARE || \ + NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || \ - NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || \ - NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \ + NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || \ NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL || \ SOC_INTEL_BROADWELL default 0x200000 if SOC_INTEL_FSP_BAYTRAIL @@ -378,7 +378,9 @@ source "src/ec/acpi/Kconfig" source "src/ec/*/*/Kconfig" source "src/drivers/intel/fsp1_0/Kconfig" +source "src/southbridge/intel/common/firmware/Kconfig" source "src/vendorcode/*/Kconfig" + source "src/arch/*/Kconfig" endmenu diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 2aaa766..c16aad3 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -36,14 +36,6 @@ config MAINBOARD_DIR string default intel/mohonpeak -config INCLUDE_ME - bool - default n - -config LOCK_MANAGEMENT_ENGINE - bool - default n - config MAINBOARD_PART_NUMBER string default "Mohon Peak CRB" diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig new file mode 100644 index 0000000..1f4d935 --- /dev/null +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -0,0 +1,94 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Google Inc. +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +config HAVE_INTEL_FIRMWARE + bool + help + Chipset uses the Intel Firmware Descriptor to describe the + layout of the SPI ROM chip. + +if HAVE_INTEL_FIRMWARE + +comment "Intel Firmware" + +config HAVE_IFD_BIN + bool "Add Intel descriptor.bin file" + help + The descriptor binary + +config IFD_BIN_PATH + string "Path and filename of the descriptor.bin file" + depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD + +config HAVE_ME_BIN + bool "Add Intel Management Engine firmware" + depends on USES_INTEL_ME && HAVE_IFD_BIN + help + The Intel processor in the selected system requires a special firmware + for an integrated controller called Management Engine (ME). The ME + firmware might be provided in coreboot's 3rdparty/blobs repository. If + not and if you don't have the firmware elsewhere, you can still + build coreboot without it. In this case however, you'll have to make + sure that you don't overwrite your ME firmware on your flash ROM. + +config ME_BIN_PATH + string "Path to management engine firmware" + depends on HAVE_ME_BIN + +##### Fake IFD ##### + +config BUILD_WITH_FAKE_IFD + bool "Build with a fake IFD" if !HAVE_IFD_BIN + help + If you don't have an Intel Firmware Descriptor (descriptor.bin) for your + board, you can select this option and coreboot will build without it. + The resulting coreboot.rom will not contain all parts required + to get coreboot running on your board. You can however write only the + BIOS section to your board's flash ROM and keep the other sections + untouched. Unfortunately the current version of flashrom doesn't + support this yet. But there is a patch pending [1]. + + WARNING: Never write a complete coreboot.rom to your flash ROM if it + was built with a fake IFD. It just won't work. + + [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html + +config IFD_BIOS_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + +config IFD_ME_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + +config IFD_GBE_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + +config IFD_PLATFORM_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + + +endif #INTEL_FIRMWARE diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc new file mode 100644 index 0000000..7a97e37 --- /dev/null +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Google Inc. +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y) + +# Run intermediate steps when producing coreboot.rom +# that adds additional components to the final firmware +# image outside of CBFS + +ifeq ($(CONFIG_HAVE_IFD_BIN),y) +INTERMEDIATE+=add_intel_firmware +endif + +ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) +INTERMEDIATE+=add_intel_firmware +IFD_BIN_PATH := $(objgenerated)/ifdfake.bin +IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ + $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \ + $(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \ + $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) +else +IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) +endif + +add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) +ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) + printf "\n** WARNING **\n" + printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" + printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" + printf "flash ROM! Make sure that you only write valid flash regions.\n\n" + printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" + $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) +endif + printf " DD Adding Intel Firmware Descriptor\n" + dd if=$(IFD_BIN_PATH) \ + of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 +ifeq ($(CONFIG_HAVE_ME_BIN),y) + printf " IFDTOOL me.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + -i ME:$(CONFIG_ME_BIN_PATH) \ + $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +endif +ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) + printf " IFDTOOL Locking Management Engine\n" + $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) + printf " IFDTOOL Unlocking Management Engine\n" + $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +endif + +PHONY+=add_intel_firmware + +endif diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index f60cbb1..fc2b6b3 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -33,6 +33,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select COMMON_FADT + select HAVE_INTEL_FIRMWARE + select USES_INTEL_ME config EHCI_BAR hex @@ -53,35 +55,4 @@ config HPET_MIN_TICKS hex default 0x80 -if HAVE_FSP_BIN - -config INCLUDE_ME - bool - default n - help - Include the me.bin and descriptor.bin for Intel PCH. - This is usually required for the PCH. - -config ME_PATH - string - depends on INCLUDE_ME - help - The path of the ME and Descriptor files. - -config LOCK_MANAGEMENT_ENGINE - bool "Lock Management Engine section" - default n - depends on INCLUDE_ME - help - The Intel Management Engine supports preventing write accesses - from the host to the Management Engine section in the firmware - descriptor. If the ME section is locked, it can only be overwritten - with an external SPI flash programmer. You will want this if you - want to increase security of your ROM image once you are sure - that the ME firmware is no longer going to change. - - If unsure, say N. - -endif # HAVE_FSP_BIN - endif diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc index 44144a0..d96e641 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc +++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc @@ -20,12 +20,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y) -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS -ifeq ($(CONFIG_INCLUDE_ME),y) -INTERMEDIATE+=bd82x6x_add_me -endif +subdirs-y += ../common/firmware ramstage-y += pch.c ramstage-y += azalia.c @@ -51,27 +46,6 @@ smm-$(CONFIG_USBDEBUG) += usb_debug.c romstage-y += reset.c romstage-y += early_spi.c -bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL) - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 - printf " IFDTOOL me.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - -i ME:$(call strip_quotes,$(CONFIG_ME_PATH))/me.bin \ - $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -else - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif - -PHONY += bd82x6x_add_me - CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x endif diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 71782be..2c8ceac 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SPI_FLASH + select HAVE_INTEL_FIRMWARE config EHCI_BAR hex @@ -52,21 +53,11 @@ config HPET_MIN_TICKS hex default 0x80 -if HAVE_FSP_BIN - -config INCLUDE_ME - bool "Add Intel descriptor.bin file" - default n - help - Include the descriptor.bin for rangeley. - -config ME_PATH - string "Path to descriptor.bin file" - depends on INCLUDE_ME +config IFD_BIN_PATH + string + depends on HAVE_IFD_BIN default "../intel/mainboard/intel/rangeley" help - The path of the descriptor.bin file. - -endif # HAVE_FSP_BIN + The path and filename to the descriptor.bin file. endif diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index 0f9f59c..1d35b54 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -20,9 +20,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS +subdirs-y += ../common/firmware ramstage-y += soc.c ramstage-y += lpc.c @@ -39,16 +37,4 @@ romstage-y += romstage.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c - -ifeq ($(CONFIG_INCLUDE_ME),y) -INTERMEDIATE+=rangeley_add_descriptor - -rangeley_add_descriptor: $(obj)/coreboot.pre $(IFDTOOL) - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 -endif - -PHONY += rangeley_add_descriptor - endif diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 2747b21..2c71ab2 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -32,6 +32,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SPI_FLASH + select HAVE_INTEL_FIRMWARE + select USES_INTEL_ME config INTEL_LYNXPOINT_LP bool @@ -59,60 +61,20 @@ config HAVE_IFD_BIN default y config BUILD_WITH_FAKE_IFD - bool "Build with a fake IFD" + bool default y if !HAVE_IFD_BIN - help - If you don't have an Intel Firmware Descriptor (ifd.bin) for your - board, you can select this option and coreboot will build without it. - Though, the resulting coreboot.rom will not contain all parts required - to get coreboot running on your board. You can however write only the - BIOS section to your board's flash ROM and keep the other sections - untouched. Unfortunately the current version of flashrom doesn't - support this yet. But there is a patch pending [1]. - - WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. - - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html - -config IFD_BIOS_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_ME_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_GBE_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_PLATFORM_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" config IFD_BIN_PATH - string "Path to intel firmware descriptor" + string depends on !BUILD_WITH_FAKE_IFD default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" config HAVE_ME_BIN - bool "Add Intel Management Engine firmware" + bool default y - help - The Intel processor in the selected system requires a special firmware - for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty/blobs repository. If - not and if you don't have the firmware elsewhere, you can still - build coreboot without it. In this case however, you'll have to make - sure that you don't overwrite your ME firmware on your flash ROM. config ME_BIN_PATH - string "Path to management engine firmware" + string depends on HAVE_ME_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" @@ -133,16 +95,7 @@ config FINALIZE_USB_ROUTE_XHCI to the XHCI controller during the finalize SMM callback. config LOCK_MANAGEMENT_ENGINE - bool "Lock Management Engine section" + bool default n - help - The Intel Management Engine supports preventing write accesses - from the host to the Management Engine section in the firmware - descriptor. If the ME section is locked, it can only be overwritten - with an external SPI flash programmer. You will want this if you - want to increase security of your ROM image once you are sure - that the ME firmware is no longer going to change. - - If unsure, say N. endif diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index a22251a..a42fe39 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -19,10 +19,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS -INTERMEDIATE:=lynxpoint_add_me +subdirs-y += ../common/firmware ramstage-y += pch.c ramstage-y += azalia.c @@ -66,45 +63,4 @@ ramstage-y += gpio.c smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c endif -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) -IFD_BIN_PATH := $(objgenerated)/ifdfake.bin -IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ - $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \ - $(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \ - $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) -else -IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) -endif - -lynxpoint_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf "\n** WARNING **\n" - printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" - printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" - printf "flash ROM! Make sure that you only write valid flash regions.\n\n" - printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" - $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) -endif - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(IFD_BIN_PATH) \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 -ifeq ($(CONFIG_HAVE_ME_BIN),y) - printf " IFDTOOL me.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - -i ME:$(CONFIG_ME_BIN_PATH) \ - $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif -ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif - -PHONY += lynxpoint_add_me - endif

1 0

Patch set updated for coreboot: Kconfig: Get rid of obsolete CAR_MIGRATION symbols
by Martin Roth 20 Jun '15

20 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10616 -gerrit commit 4dde283601870a60edd648007184a2f6033754dd Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 20 16:40:28 2015 -0600 Kconfig: Get rid of obsolete CAR_MIGRATION symbols CAR_MIGRATION was removed in commit: cbf5bdfe - CBMEM: Always select CAR_MIGRATION ALT_CBFS_LOAD_PAYLOAD was removed in commit: cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD MARK_GRAPHICS_MEM_WRCOMB was removed in commit: 30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB. EXTERNAL_MRC_BLOB was removed in commit: 0aede118 - Drop unused EXTERNAL_MRC_BLOB CACHE_ROM is only in Google's codebase. LID_SWITCH is only in Google's codebase. DEFAULT_POST_DEVICE_LPC is only in Sage's codebase. ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used. HUDSON_NOT_LEGACY_FREE never existed as far as I can tell. MAINBOARD_DO_EDID never existed as far as I can tell. Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/mainboard/apple/macbook21/Kconfig | 1 - src/mainboard/asus/f2a85-m_le/Kconfig | 1 - src/mainboard/google/auron/Kconfig | 4 ---- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/jecht/Kconfig | 1 - src/mainboard/google/panther/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/samus/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/mohonpeak/Kconfig | 1 - src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 3 --- src/soc/intel/fsp_baytrail/Kconfig | 1 - 15 files changed, 20 deletions(-) diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 7ad3f93..e653c08 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select VGA - select MAINBOARD_DO_EDID select INTEL_EDID config MAINBOARD_DIR diff --git a/src/mainboard/asus/f2a85-m_le/Kconfig b/src/mainboard/asus/f2a85-m_le/Kconfig index 3172760..9476b0c 100644 --- a/src/mainboard/asus/f2a85-m_le/Kconfig +++ b/src/mainboard/asus/f2a85-m_le/Kconfig @@ -33,7 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select GFXUMA select HUDSON_DISABLE_IMC - select HUDSON_NOT_LEGACY_FREE choice prompt "DDR3 memory voltage" diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 779e6b3..740afe1 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -14,12 +14,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB - select CACHE_ROM - select MARK_GRAPHICS_MEM_WRCOMB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 - select LID_SWITCH select CHROMEOS_VBNV_CMOS config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 74e1edd..17ec406 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index 5b97259..1234044 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_INT15 diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index fbf61de..ad54b16 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 37a8548..6fb6c5f 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select INTEL_INT15 select PHYSICAL_REC_SWITCH select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 2c1560a..8c7d630 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_DP diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index 06317e9..68d622d 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index cfbce5e..a2dd3d0 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select INTEL_DP select INTEL_DDI select INTEL_INT15 diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 2aaa766..f487e2b 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select MMCONF_SUPPORT select POST_IO - select DEFAULT_POST_DEVICE_LPC select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT config MAINBOARD_DIR diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5060e45..cbf4a1f 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS - select CAR_MIGRATION select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index aa191b3..a7bc046 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS - select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 1ef386b..c9600ea 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -11,15 +11,12 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select ALT_CBFS_LOAD_PAYLOAD select ALWAYS_LOAD_OPROM select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_BIN select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM - select CACHE_ROM - select CAR_MIGRATION select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_MONOTONIC_TIMER diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 371ad52..1ad5891 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -47,7 +47,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS - select ROMSTAGE_RTC_INIT config SOC_INTEL_FSP_BAYTRAIL_MD bool

1 0

Patch set updated for coreboot: southbridge/intel: Create common IFD Kconfig and Makefile
by Martin Roth 20 Jun '15

20 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10613 -gerrit commit 3cc593d32517c84667853dcbd27e14114106285e Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 20 16:17:12 2015 -0600 southbridge/intel: Create common IFD Kconfig and Makefile We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC. This is the start of creating a common interface for all of them. This also allows us to reduce the chipset dependencies for CBFS_SIZE. Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/Kconfig | 8 +- src/mainboard/intel/mohonpeak/Kconfig | 8 -- src/southbridge/intel/common/firmware/Kconfig | 94 ++++++++++++++++++++++ src/southbridge/intel/common/firmware/Makefile.inc | 73 +++++++++++++++++ src/southbridge/intel/fsp_bd82x6x/Kconfig | 33 +------- src/southbridge/intel/fsp_bd82x6x/Makefile.inc | 28 +------ src/southbridge/intel/fsp_rangeley/Kconfig | 19 ++--- src/southbridge/intel/fsp_rangeley/Makefile.inc | 16 +--- src/southbridge/intel/lynxpoint/Kconfig | 61 ++------------ src/southbridge/intel/lynxpoint/Makefile.inc | 46 +---------- 10 files changed, 189 insertions(+), 197 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 91a3b29..94b3508 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -338,10 +338,10 @@ source "src/mainboard/Kconfig" config CBFS_SIZE hex "Size of CBFS filesystem in ROM" - default 0x100000 if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \ + default 0x100000 if HAVE_INTEL_FIRMWARE || \ + NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || \ - NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || \ - NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \ + NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || \ NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL || \ SOC_INTEL_BROADWELL default 0x200000 if SOC_INTEL_FSP_BAYTRAIL @@ -378,7 +378,9 @@ source "src/ec/acpi/Kconfig" source "src/ec/*/*/Kconfig" source "src/drivers/intel/fsp1_0/Kconfig" +source "src/southbridge/intel/common/firmware/Kconfig" source "src/vendorcode/*/Kconfig" + source "src/arch/*/Kconfig" endmenu diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 2aaa766..c16aad3 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -36,14 +36,6 @@ config MAINBOARD_DIR string default intel/mohonpeak -config INCLUDE_ME - bool - default n - -config LOCK_MANAGEMENT_ENGINE - bool - default n - config MAINBOARD_PART_NUMBER string default "Mohon Peak CRB" diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig new file mode 100644 index 0000000..1f4d935 --- /dev/null +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -0,0 +1,94 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Google Inc. +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +config HAVE_INTEL_FIRMWARE + bool + help + Chipset uses the Intel Firmware Descriptor to describe the + layout of the SPI ROM chip. + +if HAVE_INTEL_FIRMWARE + +comment "Intel Firmware" + +config HAVE_IFD_BIN + bool "Add Intel descriptor.bin file" + help + The descriptor binary + +config IFD_BIN_PATH + string "Path and filename of the descriptor.bin file" + depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD + +config HAVE_ME_BIN + bool "Add Intel Management Engine firmware" + depends on USES_INTEL_ME && HAVE_IFD_BIN + help + The Intel processor in the selected system requires a special firmware + for an integrated controller called Management Engine (ME). The ME + firmware might be provided in coreboot's 3rdparty/blobs repository. If + not and if you don't have the firmware elsewhere, you can still + build coreboot without it. In this case however, you'll have to make + sure that you don't overwrite your ME firmware on your flash ROM. + +config ME_BIN_PATH + string "Path to management engine firmware" + depends on HAVE_ME_BIN + +##### Fake IFD ##### + +config BUILD_WITH_FAKE_IFD + bool "Build with a fake IFD" if !HAVE_IFD_BIN + help + If you don't have an Intel Firmware Descriptor (descriptor.bin) for your + board, you can select this option and coreboot will build without it. + The resulting coreboot.rom will not contain all parts required + to get coreboot running on your board. You can however write only the + BIOS section to your board's flash ROM and keep the other sections + untouched. Unfortunately the current version of flashrom doesn't + support this yet. But there is a patch pending [1]. + + WARNING: Never write a complete coreboot.rom to your flash ROM if it + was built with a fake IFD. It just won't work. + + [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html + +config IFD_BIOS_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + +config IFD_ME_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + +config IFD_GBE_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + +config IFD_PLATFORM_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + + +endif #INTEL_FIRMWARE diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc new file mode 100644 index 0000000..c79a1df --- /dev/null +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Google Inc. +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y) + +# Run intermediate steps when producing coreboot.rom +# that adds additional components to the final firmware +# image outside of CBFS + +ifeq ($(CONFIG_HAVE_IFD_BIN),y) +INTERMEDIATE+=add_intel_firmware +endif + +ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) +INTERMEDIATE+=add_intel_firmware_descriptor +IFD_BIN_PATH := $(objgenerated)/ifdfake.bin +IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ + $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \ + $(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \ + $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) +else +IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) +endif + +add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) +ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) + printf "\n** WARNING **\n" + printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" + printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" + printf "flash ROM! Make sure that you only write valid flash regions.\n\n" + printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" + $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) +endif + printf " DD Adding Intel Firmware Descriptor\n" + dd if=$(IFD_BIN_PATH) \ + of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 +ifeq ($(CONFIG_HAVE_ME_BIN),y) + printf " IFDTOOL me.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + -i ME:$(CONFIG_ME_BIN_PATH) \ + $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +endif +ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) + printf " IFDTOOL Locking Management Engine\n" + $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) + printf " IFDTOOL Unlocking Management Engine\n" + $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +endif + +PHONY+=add_intel_firmware + +endif diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index f60cbb1..fc2b6b3 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -33,6 +33,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select COMMON_FADT + select HAVE_INTEL_FIRMWARE + select USES_INTEL_ME config EHCI_BAR hex @@ -53,35 +55,4 @@ config HPET_MIN_TICKS hex default 0x80 -if HAVE_FSP_BIN - -config INCLUDE_ME - bool - default n - help - Include the me.bin and descriptor.bin for Intel PCH. - This is usually required for the PCH. - -config ME_PATH - string - depends on INCLUDE_ME - help - The path of the ME and Descriptor files. - -config LOCK_MANAGEMENT_ENGINE - bool "Lock Management Engine section" - default n - depends on INCLUDE_ME - help - The Intel Management Engine supports preventing write accesses - from the host to the Management Engine section in the firmware - descriptor. If the ME section is locked, it can only be overwritten - with an external SPI flash programmer. You will want this if you - want to increase security of your ROM image once you are sure - that the ME firmware is no longer going to change. - - If unsure, say N. - -endif # HAVE_FSP_BIN - endif diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc index 44144a0..d96e641 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc +++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc @@ -20,12 +20,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y) -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS -ifeq ($(CONFIG_INCLUDE_ME),y) -INTERMEDIATE+=bd82x6x_add_me -endif +subdirs-y += ../common/firmware ramstage-y += pch.c ramstage-y += azalia.c @@ -51,27 +46,6 @@ smm-$(CONFIG_USBDEBUG) += usb_debug.c romstage-y += reset.c romstage-y += early_spi.c -bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL) - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 - printf " IFDTOOL me.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - -i ME:$(call strip_quotes,$(CONFIG_ME_PATH))/me.bin \ - $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -else - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif - -PHONY += bd82x6x_add_me - CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x endif diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 71782be..2c8ceac 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SPI_FLASH + select HAVE_INTEL_FIRMWARE config EHCI_BAR hex @@ -52,21 +53,11 @@ config HPET_MIN_TICKS hex default 0x80 -if HAVE_FSP_BIN - -config INCLUDE_ME - bool "Add Intel descriptor.bin file" - default n - help - Include the descriptor.bin for rangeley. - -config ME_PATH - string "Path to descriptor.bin file" - depends on INCLUDE_ME +config IFD_BIN_PATH + string + depends on HAVE_IFD_BIN default "../intel/mainboard/intel/rangeley" help - The path of the descriptor.bin file. - -endif # HAVE_FSP_BIN + The path and filename to the descriptor.bin file. endif diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index 0f9f59c..1d35b54 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -20,9 +20,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS +subdirs-y += ../common/firmware ramstage-y += soc.c ramstage-y += lpc.c @@ -39,16 +37,4 @@ romstage-y += romstage.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c - -ifeq ($(CONFIG_INCLUDE_ME),y) -INTERMEDIATE+=rangeley_add_descriptor - -rangeley_add_descriptor: $(obj)/coreboot.pre $(IFDTOOL) - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 -endif - -PHONY += rangeley_add_descriptor - endif diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 2747b21..2c71ab2 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -32,6 +32,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SPI_FLASH + select HAVE_INTEL_FIRMWARE + select USES_INTEL_ME config INTEL_LYNXPOINT_LP bool @@ -59,60 +61,20 @@ config HAVE_IFD_BIN default y config BUILD_WITH_FAKE_IFD - bool "Build with a fake IFD" + bool default y if !HAVE_IFD_BIN - help - If you don't have an Intel Firmware Descriptor (ifd.bin) for your - board, you can select this option and coreboot will build without it. - Though, the resulting coreboot.rom will not contain all parts required - to get coreboot running on your board. You can however write only the - BIOS section to your board's flash ROM and keep the other sections - untouched. Unfortunately the current version of flashrom doesn't - support this yet. But there is a patch pending [1]. - - WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. - - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html - -config IFD_BIOS_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_ME_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_GBE_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_PLATFORM_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" config IFD_BIN_PATH - string "Path to intel firmware descriptor" + string depends on !BUILD_WITH_FAKE_IFD default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" config HAVE_ME_BIN - bool "Add Intel Management Engine firmware" + bool default y - help - The Intel processor in the selected system requires a special firmware - for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty/blobs repository. If - not and if you don't have the firmware elsewhere, you can still - build coreboot without it. In this case however, you'll have to make - sure that you don't overwrite your ME firmware on your flash ROM. config ME_BIN_PATH - string "Path to management engine firmware" + string depends on HAVE_ME_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" @@ -133,16 +95,7 @@ config FINALIZE_USB_ROUTE_XHCI to the XHCI controller during the finalize SMM callback. config LOCK_MANAGEMENT_ENGINE - bool "Lock Management Engine section" + bool default n - help - The Intel Management Engine supports preventing write accesses - from the host to the Management Engine section in the firmware - descriptor. If the ME section is locked, it can only be overwritten - with an external SPI flash programmer. You will want this if you - want to increase security of your ROM image once you are sure - that the ME firmware is no longer going to change. - - If unsure, say N. endif diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index a22251a..a42fe39 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -19,10 +19,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS -INTERMEDIATE:=lynxpoint_add_me +subdirs-y += ../common/firmware ramstage-y += pch.c ramstage-y += azalia.c @@ -66,45 +63,4 @@ ramstage-y += gpio.c smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c endif -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) -IFD_BIN_PATH := $(objgenerated)/ifdfake.bin -IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ - $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \ - $(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \ - $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) -else -IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) -endif - -lynxpoint_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf "\n** WARNING **\n" - printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" - printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" - printf "flash ROM! Make sure that you only write valid flash regions.\n\n" - printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" - $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) -endif - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(IFD_BIN_PATH) \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 -ifeq ($(CONFIG_HAVE_ME_BIN),y) - printf " IFDTOOL me.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - -i ME:$(CONFIG_ME_BIN_PATH) \ - $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif -ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif - -PHONY += lynxpoint_add_me - endif

1 0

Patch set updated for coreboot: Kconfig: Get rid of obsolete CAR_MIGRATION symbols
by Martin Roth 20 Jun '15

20 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10616 -gerrit commit 83d32fb461c33fdc2ee197a5e0ded0df88a9402a Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 20 16:40:28 2015 -0600 Kconfig: Get rid of obsolete CAR_MIGRATION symbols CAR_MIGRATION was removed in commit: cbf5bdfe - CBMEM: Always select CAR_MIGRATION CACHE_ROM is only in Google's codebase. DEFAULT_POST_DEVICE_LPC is only in Sage's codebase. Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/mainboard/google/auron/Kconfig | 1 - src/mainboard/intel/mohonpeak/Kconfig | 1 - src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 2 -- 5 files changed, 6 deletions(-) diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 779e6b3..4693d04 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 2aaa766..f487e2b 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select MMCONF_SUPPORT select POST_IO - select DEFAULT_POST_DEVICE_LPC select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT config MAINBOARD_DIR diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5060e45..cbf4a1f 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS - select CAR_MIGRATION select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index aa191b3..a7bc046 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS - select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 1ef386b..84f25f0 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -18,8 +18,6 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM - select CACHE_ROM - select CAR_MIGRATION select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_MONOTONIC_TIMER

1 0

New patch to review for coreboot: Kconfig: Get rid of obsolete CAR_MIGRATION symbols
by Martin Roth 20 Jun '15

20 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10616 -gerrit commit ddb86c172d70d443e4e1f734a6ed00b82280e3d9 Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 20 16:40:28 2015 -0600 Kconfig: Get rid of obsolete CAR_MIGRATION symbols CAR_MIGRATION was removed in commit: cbf5bdfe - CBMEM: Always select CAR_MIGRATION CACHE_ROM is only in Google's codebase. DEFAULT_POST_DEVICE_LPC is only in Sage's codebase. Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/mainboard/google/auron/Kconfig | 1 - src/mainboard/intel/mohonpeak/Kconfig | 1 - src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 2 - src/southbridge/intel/common/firmware/Kconfig | 94 ++++++++++++++++++++++ src/southbridge/intel/common/firmware/Makefile.inc | 73 +++++++++++++++++ 7 files changed, 167 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 779e6b3..4693d04 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 2aaa766..f487e2b 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select MMCONF_SUPPORT select POST_IO - select DEFAULT_POST_DEVICE_LPC select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT config MAINBOARD_DIR diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5060e45..cbf4a1f 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS - select CAR_MIGRATION select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index aa191b3..a7bc046 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS - select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 1ef386b..84f25f0 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -18,8 +18,6 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM - select CACHE_ROM - select CAR_MIGRATION select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_MONOTONIC_TIMER diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig new file mode 100644 index 0000000..1f4d935 --- /dev/null +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -0,0 +1,94 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Google Inc. +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +config HAVE_INTEL_FIRMWARE + bool + help + Chipset uses the Intel Firmware Descriptor to describe the + layout of the SPI ROM chip. + +if HAVE_INTEL_FIRMWARE + +comment "Intel Firmware" + +config HAVE_IFD_BIN + bool "Add Intel descriptor.bin file" + help + The descriptor binary + +config IFD_BIN_PATH + string "Path and filename of the descriptor.bin file" + depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD + +config HAVE_ME_BIN + bool "Add Intel Management Engine firmware" + depends on USES_INTEL_ME && HAVE_IFD_BIN + help + The Intel processor in the selected system requires a special firmware + for an integrated controller called Management Engine (ME). The ME + firmware might be provided in coreboot's 3rdparty/blobs repository. If + not and if you don't have the firmware elsewhere, you can still + build coreboot without it. In this case however, you'll have to make + sure that you don't overwrite your ME firmware on your flash ROM. + +config ME_BIN_PATH + string "Path to management engine firmware" + depends on HAVE_ME_BIN + +##### Fake IFD ##### + +config BUILD_WITH_FAKE_IFD + bool "Build with a fake IFD" if !HAVE_IFD_BIN + help + If you don't have an Intel Firmware Descriptor (descriptor.bin) for your + board, you can select this option and coreboot will build without it. + The resulting coreboot.rom will not contain all parts required + to get coreboot running on your board. You can however write only the + BIOS section to your board's flash ROM and keep the other sections + untouched. Unfortunately the current version of flashrom doesn't + support this yet. But there is a patch pending [1]. + + WARNING: Never write a complete coreboot.rom to your flash ROM if it + was built with a fake IFD. It just won't work. + + [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html + +config IFD_BIOS_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + +config IFD_ME_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + +config IFD_GBE_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + +config IFD_PLATFORM_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + + +endif #INTEL_FIRMWARE diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc new file mode 100644 index 0000000..c79a1df --- /dev/null +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Google Inc. +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y) + +# Run intermediate steps when producing coreboot.rom +# that adds additional components to the final firmware +# image outside of CBFS + +ifeq ($(CONFIG_HAVE_IFD_BIN),y) +INTERMEDIATE+=add_intel_firmware +endif + +ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) +INTERMEDIATE+=add_intel_firmware_descriptor +IFD_BIN_PATH := $(objgenerated)/ifdfake.bin +IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ + $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \ + $(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \ + $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) +else +IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) +endif + +add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) +ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) + printf "\n** WARNING **\n" + printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" + printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" + printf "flash ROM! Make sure that you only write valid flash regions.\n\n" + printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" + $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) +endif + printf " DD Adding Intel Firmware Descriptor\n" + dd if=$(IFD_BIN_PATH) \ + of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 +ifeq ($(CONFIG_HAVE_ME_BIN),y) + printf " IFDTOOL me.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + -i ME:$(CONFIG_ME_BIN_PATH) \ + $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +endif +ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) + printf " IFDTOOL Locking Management Engine\n" + $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) + printf " IFDTOOL Unlocking Management Engine\n" + $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +endif + +PHONY+=add_intel_firmware + +endif

1 0

New patch to review for coreboot: Remove obsolete EARLY_CONSOLE usage
by Martin Roth 20 Jun '15

20 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10615 -gerrit commit 46504a07363c9e05bcfa658cc7bac22bcff86650 Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 20 16:45:30 2015 -0600 Remove obsolete EARLY_CONSOLE usage The EARLY_CONSOLE Kconfig symbol was removed in commit 48713a1b - console: Drop EARLY_CONSOLE option Because the symbol was missing from Kconfig, these platforms had the early console always disabled instead of the intended always enabled. Change-Id: Idc60ffb2bac2b180f4fdd0adf5c411e1f692a846 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/arch/arm64/Makefile.inc | 2 +- src/arch/mips/Makefile.inc | 2 +- src/mainboard/emulation/qemu-armv7/Kconfig | 1 - src/soc/broadcom/cygnus/Kconfig | 1 - src/soc/marvell/bg4cd/Kconfig | 1 - src/soc/nvidia/tegra132/Kconfig | 1 - 6 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 13e8415..c63cb4b 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -88,7 +88,7 @@ $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld -verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c +verstage-y += early_console.c verstage-y += boot.c verstage-y += div0.c verstage-y += eabi_compat.c diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index cff0151..ccbe740 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -61,7 +61,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_MIPS ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y) romstage-y += boot.c -romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c +romstage-y += early_console.c romstage-y += cache.c romstage-y += mmu.c romstage-y += stages.c diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 58ddd4e..c6199ea 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_ARMLTD_CORTEX_A9 select DRIVERS_UART_PL011 select BOOTBLOCK_CONSOLE - select EARLY_CONSOLE select CONSOLE_SERIAL select ARM_BOOTBLOCK_ARMV7 select ARM_ROMSTAGE_ARMV7 diff --git a/src/soc/broadcom/cygnus/Kconfig b/src/soc/broadcom/cygnus/Kconfig index 7c17bd4..e6da57c 100644 --- a/src/soc/broadcom/cygnus/Kconfig +++ b/src/soc/broadcom/cygnus/Kconfig @@ -25,7 +25,6 @@ config SOC_BROADCOM_CYGNUS select ARCH_ROMSTAGE_ARMV7 select ARCH_VERSTAGE_ARMV7 select BOOTBLOCK_CONSOLE - select EARLY_CONSOLE select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL diff --git a/src/soc/marvell/bg4cd/Kconfig b/src/soc/marvell/bg4cd/Kconfig index f2cb16f..930645e 100644 --- a/src/soc/marvell/bg4cd/Kconfig +++ b/src/soc/marvell/bg4cd/Kconfig @@ -26,7 +26,6 @@ config SOC_MARVELL_BG4CD select ARCH_VERSTAGE_ARMV7_M select ARM_BOOTBLOCK_CUSTOM if VBOOT_VERIFY_FIRMWARE select BOOTBLOCK_CONSOLE - select EARLY_CONSOLE select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select GENERIC_GPIO_LIB diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index be8ae9b..a5df92a 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -11,7 +11,6 @@ config SOC_NVIDIA_TEGRA132 select GENERIC_UDELAY select HAVE_HARD_RESET select HAVE_UART_SPECIAL - select EARLY_CONSOLE select ARM_BOOTBLOCK_CUSTOM select SMP select ARM64_USE_SECURE_MONITOR

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New patch to review for coreboot: superio/fintek/Kconfig: add newline at end of file.
by Martin Roth 20 Jun '15

20 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10614 -gerrit commit cc26a14dae953b6e0a40ea7ce92f1d82d92128b0 Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 20 16:32:24 2015 -0600 superio/fintek/Kconfig: add newline at end of file. Kconfig sometimes fails to parse the last line of a file if there's no newline at the end. Add one to be safe. Change-Id: Ia9973a89b12596e1f2a2741ad2e255e886495331 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/superio/fintek/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index 5403e0a..2662a85 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -57,4 +57,4 @@ config SUPERIO_FINTEK_F81865F config SUPERIO_FINTEK_F81866D bool - select SUPERIO_FINTEK_COMMON_ROMSTAGE \ No newline at end of file + select SUPERIO_FINTEK_COMMON_ROMSTAGE

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New patch to review for coreboot: southbridge/intel: Create common IFD Kconfig and Makefile
by Martin Roth 20 Jun '15

20 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10613 -gerrit commit 3c6e16fb8fb13d9e4bd2dd1d36bfba565b7f7683 Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 20 16:17:12 2015 -0600 southbridge/intel: Create common IFD Kconfig and Makefile We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC. This is the start of creating a common interface for all of them. This also allows us to reduce the chipset dependencies for CBFS_SIZE. Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/Kconfig | 8 ++-- src/mainboard/intel/mohonpeak/Kconfig | 8 ---- src/southbridge/intel/fsp_bd82x6x/Kconfig | 33 +------------ src/southbridge/intel/fsp_bd82x6x/Makefile.inc | 28 +----------- src/southbridge/intel/fsp_rangeley/Kconfig | 19 ++------ src/southbridge/intel/fsp_rangeley/Makefile.inc | 16 +------ src/southbridge/intel/lynxpoint/Kconfig | 61 +++---------------------- src/southbridge/intel/lynxpoint/Makefile.inc | 46 +------------------ 8 files changed, 22 insertions(+), 197 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 91a3b29..94b3508 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -338,10 +338,10 @@ source "src/mainboard/Kconfig" config CBFS_SIZE hex "Size of CBFS filesystem in ROM" - default 0x100000 if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \ + default 0x100000 if HAVE_INTEL_FIRMWARE || \ + NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || \ - NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || \ - NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \ + NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || \ NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL || \ SOC_INTEL_BROADWELL default 0x200000 if SOC_INTEL_FSP_BAYTRAIL @@ -378,7 +378,9 @@ source "src/ec/acpi/Kconfig" source "src/ec/*/*/Kconfig" source "src/drivers/intel/fsp1_0/Kconfig" +source "src/southbridge/intel/common/firmware/Kconfig" source "src/vendorcode/*/Kconfig" + source "src/arch/*/Kconfig" endmenu diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 2aaa766..c16aad3 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -36,14 +36,6 @@ config MAINBOARD_DIR string default intel/mohonpeak -config INCLUDE_ME - bool - default n - -config LOCK_MANAGEMENT_ENGINE - bool - default n - config MAINBOARD_PART_NUMBER string default "Mohon Peak CRB" diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index f60cbb1..fc2b6b3 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -33,6 +33,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select COMMON_FADT + select HAVE_INTEL_FIRMWARE + select USES_INTEL_ME config EHCI_BAR hex @@ -53,35 +55,4 @@ config HPET_MIN_TICKS hex default 0x80 -if HAVE_FSP_BIN - -config INCLUDE_ME - bool - default n - help - Include the me.bin and descriptor.bin for Intel PCH. - This is usually required for the PCH. - -config ME_PATH - string - depends on INCLUDE_ME - help - The path of the ME and Descriptor files. - -config LOCK_MANAGEMENT_ENGINE - bool "Lock Management Engine section" - default n - depends on INCLUDE_ME - help - The Intel Management Engine supports preventing write accesses - from the host to the Management Engine section in the firmware - descriptor. If the ME section is locked, it can only be overwritten - with an external SPI flash programmer. You will want this if you - want to increase security of your ROM image once you are sure - that the ME firmware is no longer going to change. - - If unsure, say N. - -endif # HAVE_FSP_BIN - endif diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc index 44144a0..d96e641 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc +++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc @@ -20,12 +20,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y) -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS -ifeq ($(CONFIG_INCLUDE_ME),y) -INTERMEDIATE+=bd82x6x_add_me -endif +subdirs-y += ../common/firmware ramstage-y += pch.c ramstage-y += azalia.c @@ -51,27 +46,6 @@ smm-$(CONFIG_USBDEBUG) += usb_debug.c romstage-y += reset.c romstage-y += early_spi.c -bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL) - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 - printf " IFDTOOL me.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - -i ME:$(call strip_quotes,$(CONFIG_ME_PATH))/me.bin \ - $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -else - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif - -PHONY += bd82x6x_add_me - CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x endif diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 71782be..2c8ceac 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SPI_FLASH + select HAVE_INTEL_FIRMWARE config EHCI_BAR hex @@ -52,21 +53,11 @@ config HPET_MIN_TICKS hex default 0x80 -if HAVE_FSP_BIN - -config INCLUDE_ME - bool "Add Intel descriptor.bin file" - default n - help - Include the descriptor.bin for rangeley. - -config ME_PATH - string "Path to descriptor.bin file" - depends on INCLUDE_ME +config IFD_BIN_PATH + string + depends on HAVE_IFD_BIN default "../intel/mainboard/intel/rangeley" help - The path of the descriptor.bin file. - -endif # HAVE_FSP_BIN + The path and filename to the descriptor.bin file. endif diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index 0f9f59c..1d35b54 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -20,9 +20,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS +subdirs-y += ../common/firmware ramstage-y += soc.c ramstage-y += lpc.c @@ -39,16 +37,4 @@ romstage-y += romstage.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c - -ifeq ($(CONFIG_INCLUDE_ME),y) -INTERMEDIATE+=rangeley_add_descriptor - -rangeley_add_descriptor: $(obj)/coreboot.pre $(IFDTOOL) - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 -endif - -PHONY += rangeley_add_descriptor - endif diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 2747b21..2c71ab2 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -32,6 +32,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SPI_FLASH + select HAVE_INTEL_FIRMWARE + select USES_INTEL_ME config INTEL_LYNXPOINT_LP bool @@ -59,60 +61,20 @@ config HAVE_IFD_BIN default y config BUILD_WITH_FAKE_IFD - bool "Build with a fake IFD" + bool default y if !HAVE_IFD_BIN - help - If you don't have an Intel Firmware Descriptor (ifd.bin) for your - board, you can select this option and coreboot will build without it. - Though, the resulting coreboot.rom will not contain all parts required - to get coreboot running on your board. You can however write only the - BIOS section to your board's flash ROM and keep the other sections - untouched. Unfortunately the current version of flashrom doesn't - support this yet. But there is a patch pending [1]. - - WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. - - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html - -config IFD_BIOS_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_ME_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_GBE_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_PLATFORM_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" config IFD_BIN_PATH - string "Path to intel firmware descriptor" + string depends on !BUILD_WITH_FAKE_IFD default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" config HAVE_ME_BIN - bool "Add Intel Management Engine firmware" + bool default y - help - The Intel processor in the selected system requires a special firmware - for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty/blobs repository. If - not and if you don't have the firmware elsewhere, you can still - build coreboot without it. In this case however, you'll have to make - sure that you don't overwrite your ME firmware on your flash ROM. config ME_BIN_PATH - string "Path to management engine firmware" + string depends on HAVE_ME_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" @@ -133,16 +95,7 @@ config FINALIZE_USB_ROUTE_XHCI to the XHCI controller during the finalize SMM callback. config LOCK_MANAGEMENT_ENGINE - bool "Lock Management Engine section" + bool default n - help - The Intel Management Engine supports preventing write accesses - from the host to the Management Engine section in the firmware - descriptor. If the ME section is locked, it can only be overwritten - with an external SPI flash programmer. You will want this if you - want to increase security of your ROM image once you are sure - that the ME firmware is no longer going to change. - - If unsure, say N. endif diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index a22251a..a42fe39 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -19,10 +19,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS -INTERMEDIATE:=lynxpoint_add_me +subdirs-y += ../common/firmware ramstage-y += pch.c ramstage-y += azalia.c @@ -66,45 +63,4 @@ ramstage-y += gpio.c smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c endif -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) -IFD_BIN_PATH := $(objgenerated)/ifdfake.bin -IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ - $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \ - $(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \ - $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) -else -IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) -endif - -lynxpoint_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf "\n** WARNING **\n" - printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" - printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" - printf "flash ROM! Make sure that you only write valid flash regions.\n\n" - printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" - $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) -endif - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(IFD_BIN_PATH) \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 -ifeq ($(CONFIG_HAVE_ME_BIN),y) - printf " IFDTOOL me.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - -i ME:$(CONFIG_ME_BIN_PATH) \ - $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif -ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif - -PHONY += lynxpoint_add_me - endif

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Patch set updated for coreboot: Reorder arch & vendorcode in Kconfig
by Martin Roth 20 Jun '15

20 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10609 -gerrit commit baad500c9be106cdfed873dfb741f44f0aecf571 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 22:30:43 2015 -0600 Reorder arch & vendorcode in Kconfig Because Kconfig uses the first valid default that it comes across, the 'source' commands to load sub-Kconfigs should be ordered from the most specific (mainboards) to less specific (chipsets) to least specific (architectures). This allows the mainboards to override chipsets and architecture Kconfig files. Because the architecture files were getting loaded ahead of the chipset and cpu Kconfigs, the preferred defaults values for things such as NUM_IPI_STARTS or RISCV_BOOTBLOCK_CUSTOM could not be set. Change-Id: Ic327452833f012ec06dabb5b5ef661aba3aff464 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/Kconfig | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b7d2e67..c282d21 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -334,10 +334,6 @@ source "src/acpi/Kconfig" source "src/mainboard/Kconfig" -source "src/arch/*/Kconfig" - -source "src/vendorcode/*/Kconfig" - config SYSTEM_TYPE_LAPTOP default n bool @@ -359,6 +355,9 @@ source "src/ec/acpi/Kconfig" source "src/ec/*/*/Kconfig" source "src/drivers/intel/fsp1_0/Kconfig" +source "src/vendorcode/*/Kconfig" +source "src/arch/*/Kconfig" + endmenu source "src/device/Kconfig"

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coreboot-gerrit June 2015