coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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1226 discussions

Patch set updated for coreboot: NOTFORMERGE: ec/lenovo/h8: wlan/trackpoint/touchpad/bluetooth/wwan
by Francis Rowe 22 Jun '15

22 Jun '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7058 -gerrit commit 07a971d55e4d6f11a8d8839055ee6e7d07bd8993 Author: Francis Rowe <info(a)gluglug.org.uk> Date: Mon Oct 13 00:14:53 2014 +0100 NOTFORMERGE: ec/lenovo/h8: wlan/trackpoint/touchpad/bluetooth/wwan Permanently enable them. Change-Id: Ic76ab9ab9c865f30312378e18af58bece6c3260a Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/ec/lenovo/h8/h8.c | 21 +++++++++++---------- src/ec/lenovo/pmh7/pmh7.c | 11 ++++------- 2 files changed, 15 insertions(+), 17 deletions(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 46480f4..b6bc406 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -252,9 +252,11 @@ static void h8_enable(struct device *dev) ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); - if (get_option(&val, "wlan") != CB_SUCCESS) - val = 1; - h8_wlan_enable(val); + // Permanently enable wifi + // Intel wifi could be a security risk because it uses firmware. Wlan chip has DMA + // and could leak data over a side-channel. Using another manufacturer is recommended. + // see http://libreboot.org/docs/index.html#recommended_wifi + h8_wlan_enable(1); h8_trackpoint_enable(1); h8_usb_power_enable(1); @@ -262,14 +264,13 @@ static void h8_enable(struct device *dev) if (get_option(&val, "volume") == CB_SUCCESS) ec_write(H8_VOLUME_CONTROL, val); - if (get_option(&val, "bluetooth") != CB_SUCCESS) - val = 1; - h8_bluetooth_enable(val); - - if (get_option(&val, "wwan") != CB_SUCCESS) - val = 1; + // Permanently enable bluetooth. + // NOTE: bluetooth is a potential security risk. Physical removal of the bluetooth module is recommended. + h8_bluetooth_enable(1); - h8_wwan_enable(val); + // Permanently enable wwan. + // NOTE: wwan is a security risk (remove access plus DMA). Physical removal of both the wwan and sim card is recommended. + h8_wwan_enable(1); if (conf->has_uwb) { if (get_option(&val, "uwb") != CB_SUCCESS) diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index cc6e891..38aef16 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -106,7 +106,6 @@ static void enable_dev(struct device *dev) { struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; - u8 val; resource = new_resource(dev, EC_LENOVO_PMH7_INDEX); resource->flags = IORESOURCE_IO | IORESOURCE_FIXED; @@ -118,13 +117,11 @@ static void enable_dev(struct device *dev) pmh7_backlight_enable(conf->backlight_enable); pmh7_dock_event_enable(conf->dock_event_enable); - if (get_option(&val, "touchpad") != CB_SUCCESS) - val = 1; - pmh7_touchpad_enable(val); + // Permanently enable touchpad + pmh7_touchpad_enable(1); - if (get_option(&val, "trackpoint") != CB_SUCCESS) - val = 1; - pmh7_trackpoint_enable(val); + // Permanently enable trackpoint + pmh7_trackpoint_enable(1); } struct chip_operations ec_lenovo_pmh7_ops = {

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Patch set updated for coreboot: NOTFORMERGE: ec/lenovo/h8: wlan/trackpoint/touchpad/bluetooth/wwan
by Francis Rowe 22 Jun '15

22 Jun '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7058 -gerrit commit 43b84826cfd34b81243db2ce23c57270c00e2c1d Author: Francis Rowe <info(a)gluglug.org.uk> Date: Mon Oct 13 00:14:53 2014 +0100 NOTFORMERGE: ec/lenovo/h8: wlan/trackpoint/touchpad/bluetooth/wwan Permanently enable them. Change-Id: Ic76ab9ab9c865f30312378e18af58bece6c3260a Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- 3rdparty/blobs | 2 +- src/ec/lenovo/h8/h8.c | 17 +++++++---------- src/ec/lenovo/pmh7/pmh7.c | 11 ++++------- 3 files changed, 12 insertions(+), 18 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 34b0926..14739c7 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 34b09265063c19ea5d61bd5a2f057b47b5aa2232 +Subproject commit 14739c76936455b18a759dd2789fd4d13b16da67 diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 46480f4..bd55832 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -252,9 +252,9 @@ static void h8_enable(struct device *dev) ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); - if (get_option(&val, "wlan") != CB_SUCCESS) - val = 1; - h8_wlan_enable(val); + // Permanently enable wifi + // see http://libreboot.org/docs/index.html#recommended_wifi + h8_wlan_enable(1); h8_trackpoint_enable(1); h8_usb_power_enable(1); @@ -262,14 +262,11 @@ static void h8_enable(struct device *dev) if (get_option(&val, "volume") == CB_SUCCESS) ec_write(H8_VOLUME_CONTROL, val); - if (get_option(&val, "bluetooth") != CB_SUCCESS) - val = 1; - h8_bluetooth_enable(val); - - if (get_option(&val, "wwan") != CB_SUCCESS) - val = 1; + // Permanently enable bluetooth + h8_bluetooth_enable(1); - h8_wwan_enable(val); + // Permanently enable wwan + h8_wwan_enable(1); if (conf->has_uwb) { if (get_option(&val, "uwb") != CB_SUCCESS) diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index cc6e891..38aef16 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -106,7 +106,6 @@ static void enable_dev(struct device *dev) { struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; - u8 val; resource = new_resource(dev, EC_LENOVO_PMH7_INDEX); resource->flags = IORESOURCE_IO | IORESOURCE_FIXED; @@ -118,13 +117,11 @@ static void enable_dev(struct device *dev) pmh7_backlight_enable(conf->backlight_enable); pmh7_dock_event_enable(conf->dock_event_enable); - if (get_option(&val, "touchpad") != CB_SUCCESS) - val = 1; - pmh7_touchpad_enable(val); + // Permanently enable touchpad + pmh7_touchpad_enable(1); - if (get_option(&val, "trackpoint") != CB_SUCCESS) - val = 1; - pmh7_trackpoint_enable(val); + // Permanently enable trackpoint + pmh7_trackpoint_enable(1); } struct chip_operations ec_lenovo_pmh7_ops = {

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New patch to review for coreboot: broadwell: fix typo
by Patrick Georgi 22 Jun '15

22 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10623 -gerrit commit 8f787a05fe9d1ef2ba575543f6f2bdd523f6428e Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jun 22 14:49:20 2015 +0200 broadwell: fix typo It's guarded by a non-standard configuration option, so didn't trigger. Change-Id: Ib7a9a45befcb7857edde37e20de7d65a60970882 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/broadwell/romstage/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index e950b1e..27fb0f2 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -126,7 +126,7 @@ void romstage_common(struct romstage_params *params) printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); #if CONFIG_LPC_TPM - init_tpm(prev_sleep_state == SLEEP_STATE_S3); + init_tpm(params->power_state->prev_sleep_state == SLEEP_STATE_S3); #endif }

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Patch merged into coreboot/master: superio: use common x86 code on x86-64
by gerrit＠coreboot.org 22 Jun '15

22 Jun '15

the following patch was just integrated into master: commit 36b78852e22fbef1d03ae5929ac8b8453ba561ec Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 22:02:24 2015 -0700 superio: use common x86 code on x86-64 Change-Id: I2ddb5a8b183b21cbd3c3b22c537b815e86bd4738 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10592 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10592 for details. -gerrit

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Patch merged into coreboot/master: device: DDR3 generic code 64bit fix
by gerrit＠coreboot.org 22 Jun '15

22 Jun '15

the following patch was just integrated into master: commit 1e2500e948750270011b133203be0fe1dbcba827 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jun 19 14:59:06 2015 -0700 device: DDR3 generic code 64bit fix Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I5ff309948c36289eedeb8a18030cdd2b4c337690 Reviewed-on: http://review.coreboot.org/10595 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10595 for details. -gerrit

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Patch merged into coreboot/master: oprom: Fix for 64bit
by gerrit＠coreboot.org 22 Jun '15

22 Jun '15

the following patch was just integrated into master: commit 83fa169101e732b35a36f19624979b378a06f3f5 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 22:01:07 2015 -0700 oprom: Fix for 64bit Change-Id: If4c1ab5ae33a64be3e7b14150d410edd291ee4ed Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10591 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10591 for details. -gerrit

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Patch merged into coreboot/master: device: Use x86 specific code on x86-64
by gerrit＠coreboot.org 22 Jun '15

22 Jun '15

the following patch was just integrated into master: commit 0e7b7bb6b3180749c7a799a5beecbf0716a49f93 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:19:14 2015 -0700 device: Use x86 specific code on x86-64 Change-Id: I4763ce32bb0b0e301401daaeb89440524fcc682e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> Reviewed-on: http://review.coreboot.org/10584 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10584 for details. -gerrit

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Patch merged into coreboot/master: x86: make PCI MMIO CFG functions 64bit proof
by gerrit＠coreboot.org 22 Jun '15

22 Jun '15

the following patch was just integrated into master: commit b0bb8a1bb46ec2a9d24f6ae7b6a8a6ee0d5dbf91 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jun 17 16:12:17 2015 -0700 x86: make PCI MMIO CFG functions 64bit proof Change-Id: Ife94f5324971f4fa03e9139f458b985f6fed9d87 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> Reviewed-on: http://review.coreboot.org/10577 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10577 for details. -gerrit

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Patch set updated for coreboot: AMD OemS3Save: refactor for Merlin Falcon
by WANG Siyuan 22 Jun '15

22 Jun '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10526 -gerrit commit d372030fb401293ea52c0f13a2cf5908c8e0e7ee Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Fri Jun 12 16:41:50 2015 +0800 AMD OemS3Save: refactor for Merlin Falcon Merlin Falcon(Carrizo) replaces struct AMD_S3SAVE_PARAMS with struct AMD_RTB_PARAMS and replaces AMD_S3_PARAMS with S3_DATA_BLOCK. Change-Id: If074a8de95d82130d29b2e3cfbd7e35cdb9b929d Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/northbridge/amd/agesa/agesawrapper.h | 2 +- src/northbridge/amd/agesa/oem_s3.c | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index eb1a59c..7e58e79 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -74,6 +74,6 @@ extern const struct OEM_HOOK OemCustomize; /* For suspend-to-ram support. */ AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams); AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams); -AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams); +AGESA_STATUS OemS3Save(void *vS3SaveParams); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index dfc1ebc..77bab67 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -115,9 +115,15 @@ static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) #endif } -AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) +AGESA_STATUS OemS3Save(void *vS3SaveParams) { +#if IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01) + AMD_RTB_PARAMS *S3SaveParams = (AMD_RTB_PARAMS *)vS3SaveParams; + S3_DATA_BLOCK *dataBlock = &S3SaveParams->S3DataBlock; +#else + AMD_S3SAVE_PARAMS *S3SaveParams = (AMD_S3SAVE_PARAMS *)vS3SaveParams; AMD_S3_PARAMS *dataBlock = &S3SaveParams->S3DataBlock; +#endif u8 MTRRStorage[S3_DATA_MTRR_SIZE]; u32 MTRRStorageSize = 0; u32 pos, size;

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New patch to review for coreboot: pcengines/apu1: Remove unused ide.asl
by Tobias Diedrich 21 Jun '15

21 Jun '15

Tobias Diedrich (ranma+coreboot(a)tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10622 -gerrit commit b0c33249fde8f601a75ed0168fa169f1ea0c81bd Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Date: Sun Jun 21 21:02:59 2015 +0200 pcengines/apu1: Remove unused ide.asl The APU1 board has no IDE port, remove ide.asl. Change-Id: I76b926969748de79ac1281ed50b37e9ade1a6771 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- src/mainboard/pcengines/apu1/acpi/ide.asl | 244 ------------------------------ src/mainboard/pcengines/apu1/dsdt.asl | 6 - 2 files changed, 250 deletions(-) diff --git a/src/mainboard/pcengines/apu1/acpi/ide.asl b/src/mainboard/pcengines/apu1/acpi/ide.asl deleted file mode 100644 index 46973e2..0000000 --- a/src/mainboard/pcengines/apu1/acpi/ide.asl +++ /dev/null @@ -1,244 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0, Serialized) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, Serialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF, 0, Serialized) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl index d550c86..523b445 100644 --- a/src/mainboard/pcengines/apu1/dsdt.asl +++ b/src/mainboard/pcengines/apu1/dsdt.asl @@ -48,12 +48,6 @@ DefinitionBlock ( /* Describe the AMD Fusion Controller Hub Southbridge */ #include <southbridge/amd/cimx/sb800/acpi/fch.asl> - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - } } /* End Scope(_SB) */

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coreboot-gerrit June 2015