coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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1226 discussions

Patch merged into coreboot/master: buildgcc: Add list of valid platform to the help text.
by gerrit＠coreboot.org 22 Jun '15

22 Jun '15

the following patch was just integrated into master: commit d1da74ff9d61f42432eb78e76a11903afcf68b7b Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jun 21 12:06:28 2015 -0600 buildgcc: Add list of valid platform to the help text. Change-Id: Ic48a08d1067c850555cf04ad29e65e9bdb7c4243 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10619 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10619 for details. -gerrit

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Patch merged into coreboot/master: Remove incorrect Kconfig expressions
by gerrit＠coreboot.org 22 Jun '15

22 Jun '15

the following patch was just integrated into master: commit 7403e059ec8cf1407b5f79c5665f7be99d195d77 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 5 21:01:59 2015 -0600 Remove incorrect Kconfig expressions The symbols used in these expressions were not correct and would never evaluate as true. Change-Id: Ia20177f41505473b14bc7b8e4b6fb16de36cc295 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10437 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10437 for details. -gerrit

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New patch to review for coreboot: acpi: bring back ability to link DSDT into ramstage
by Patrick Georgi 22 Jun '15

22 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10637 -gerrit commit 76d63478c1c0bf7d73767c7cb637c5256eb88649 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jun 22 21:10:34 2015 +0200 acpi: bring back ability to link DSDT into ramstage Bring back the ability to link in the DSDT. This is to help Chrome OS to switch over to a new upstream quickly (because some of the custom built mechanisms are a pain with tons of files). This is supposed to be temporary (famous last words), but I'd rather fix the lack of CBFS awareness in CrOS bit for good in the time I usually spend on keeping upstream and CrOS branches close. Change-Id: I7fa5540bbf5c568c4adca56a09c83b6c7e358ad5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/Makefile.inc | 17 +++++++++++++++++ src/arch/x86/boot/acpi.c | 7 +++++++ 3 files changed, 28 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 1e35846..88b2592 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -134,3 +134,7 @@ config HPET_ADDRESS config ID_SECTION_OFFSET hex default 0x80 + +config COMPILE_IN_DSDT + bool "compile in DSDT and use that over DSDT in CBFS" + default n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 4c00162..68c5ac4 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -245,6 +245,23 @@ endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) +ifeq ($(CONFIG_COMPILE_IN_DSDT),y) +ramstage-srcs += $(obj)/dsdt.aml + +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) +target-objcopy=-O elf32-i386 -B i386 +endif +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_64),y) +target-objcopy=-O elf64-x86_64 -B x86_64 +endif + +define ramstage-objs_aml_template +$(call src-to-obj,ramstage,$(1).aml): $(1).aml + @printf " OBJCOPY $$(subst $$(obj)/,,$$(@))\n" + cd $$(dir $$@) && $$(OBJCOPY_ramstage) -I binary $$(target-objcopy) $$(notdir $$<) $$(notdir $$@) +endef +endif + ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) ifeq ($(CONFIG_GENERATE_MP_TABLE),y) ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/mptable.c),) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 208411e..cf33e40 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -757,9 +757,16 @@ unsigned long write_acpi_tables(unsigned long start) if (fw) return fw; +#if CONFIG_COMPILE_IN_DSDT + extern char _binary_dsdt_aml_start; + extern char _binary_dsdt_aml_end; + dsdt_file = (acpi_header_t *)&_binary_dsdt_aml_start; + dsdt_size = (size_t)(&_binary_dsdt_aml_end - &_binary_dsdt_aml_start); +#else dsdt_file = cbfs_boot_map_with_leak( CONFIG_CBFS_PREFIX "/dsdt.aml", CBFS_TYPE_RAW, &dsdt_size); +#endif if (!dsdt_file) { printk(BIOS_ERR, "No DSDT file, skipping ACPI tables\n"); return current;

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New patch to review for coreboot: ddr3: add missing newline
by Patrick Rudolph 22 Jun '15

22 Jun '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10636 -gerrit commit 98d2b0efe57a63e64bda027edf177d4f3976c0de Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Jun 22 19:46:34 2015 +0200 ddr3: add missing newline Add missing newline to SPD CRC verification error message. Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H. Change-Id: Id1a0a2329507975c3f66ab884f6e26d99003318e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/dram/ddr3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index c10741b..e1bb873 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -133,7 +133,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) spd_crc = (spd[127] << 8) + spd[126]; /* Verify the CRC is correct */ if (crc != spd_crc) { - printram("ERROR: SPD CRC failed!!!"); + printram("ERROR: SPD CRC failed!!!\n"); ret = SPD_STATUS_CRC_ERROR; };

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Patch set updated for coreboot: ddr3: Fix SPD CRC calculation
by Patrick Rudolph 22 Jun '15

22 Jun '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10629 -gerrit commit 172821bb83387ea0e9b59526098b9bc5439600ec Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Jun 22 19:32:53 2015 +0200 ddr3: Fix SPD CRC calculation Use the correct SPD size for crc calculation. sizeof(*spd) returns 4 while sizeof(spd_raw_data) returns the expected value of 256. Fixes erroneous printing of "ERROR: SPD CRC failed!!!" in raminit log. Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H. Change-Id: Iba305c69debd64fa921e08e00ec0a3531c80f56f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/dram/ddr3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 8170ae1..c10741b 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -128,7 +128,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3; dimm->dimm_type = spd[3] & 0xf; - crc = spd_ddr3_calc_crc(spd, sizeof(*spd)); + crc = spd_ddr3_calc_crc(spd, sizeof(spd_raw_data)); /* Compare with the CRC in the SPD */ spd_crc = (spd[127] << 8) + spd[126]; /* Verify the CRC is correct */

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New patch to review for coreboot: veyron_mickey: Apply differences between Brain and Mickey
by Patrick Georgi 22 Jun '15

22 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10630 -gerrit commit 8e6a2b5238be1fb3a0de0b491397e687b845f6f7 Author: huang lin <hl(a)rock-chips.com> Date: Thu Jun 4 16:41:27 2015 +0800 veyron_mickey: Apply differences between Brain and Mickey Mickey: - Does not have power key - Does not have an audio codec(all audio goes thru HDMI) - VCC18_LCD moved to VLDO8 and needs to be turned on (was connected to VSWOUT2 earlier) BUG=none BRANCH=none TEST=Boot from mickey board, and hdmi work normal Change-Id: I88cdc41ce8bb96a6b17aeb7f24b1c5619471b24e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6c966edfa29df1049c469442dc3ad8bf8b4197b1 Original-Change-Id: I3d98203185f52ed751a5d3045a0ee8f9b4dfbc71 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/274876 --- src/mainboard/google/veyron_mickey/Kconfig | 8 -------- src/mainboard/google/veyron_mickey/chromeos.c | 10 --------- src/mainboard/google/veyron_mickey/devicetree.cb | 1 + src/mainboard/google/veyron_mickey/mainboard.c | 26 ++++++++++++++++-------- 4 files changed, 19 insertions(+), 26 deletions(-) diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index 2337e5b..d316b6a 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -65,14 +65,6 @@ config CONSOLE_SERIAL_UART_ADDRESS depends on DRIVERS_UART default 0xFF690000 -# FIXME(dhendrix): This is a gross hack intended to get us past -# display init which currently hangs the machine. It will be removed -# once we've re-factored the display init code to properly handle -# various types of displays. -config SKIP_DISPLAY_INIT_HACK - int - default 1 - config PMIC_BUS int default 0 diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index 7eed42e..2222c0e 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -26,13 +26,11 @@ #include "board.h" #define GPIO_WP GPIO(7, A, 6) -#define GPIO_POWER GPIO(0, A, 5) #define GPIO_RECOVERY GPIO(0, B, 1) void setup_chromeos_gpios(void) { gpio_input(GPIO_WP); - gpio_input(GPIO_POWER); gpio_input_pullup(GPIO_RECOVERY); } @@ -56,14 +54,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) GPIO_MAX_NAME_LENGTH); count++; - /* Power Button: GPIO active low */ - gpios->gpios[count].port = GPIO_POWER.raw; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - /* Developer: GPIO active high */ gpios->gpios[count].port = -1; gpios->gpios[count].polarity = ACTIVE_HIGH; diff --git a/src/mainboard/google/veyron_mickey/devicetree.cb b/src/mainboard/google/veyron_mickey/devicetree.cb index 4c2ea8f..6d0555a 100644 --- a/src/mainboard/google/veyron_mickey/devicetree.cb +++ b/src/mainboard/google/veyron_mickey/devicetree.cb @@ -22,4 +22,5 @@ chip soc/rockchip/rk3288 device cpu_cluster 0 on end register "vop_id" = "1" register "framebuffer_bits_per_pixel" = "16" + register "vop_mode" = "1" end diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index a5c40c23..17e4d4b 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -55,16 +55,11 @@ static void configure_emmc(void) gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */ } -static void configure_codec(void) +static void configure_i2s(void) { - write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */ - i2c_init(2, 400*KHz); /* CODEC I2C */ - write32(&rk3288_grf->iomux_i2s, IOMUX_I2S); write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK); - rk808_configure_ldo(6, 1800); /* VCC18_CODEC */ - /* AUDIO IO domain 1.8V voltage selection */ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6)); rkclk_configure_i2s(12288000); @@ -77,19 +72,29 @@ static void configure_vop(void) /* lcdc(vop) iodomain select 1.8V */ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0)); - rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */ + rk808_configure_ldo(8, 1800); /* VCC18_LCD (HDMI_AVDD_1V8) */ rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */ rk808_configure_switch(1, 1); /* VCC33_LCD */ } +static void configure_hdmi(void) +{ + /* HDMI I2C */ + write32(&rk3288_grf->iomux_i2c5sda, IOMUX_HDMI_EDP_I2C_SDA); + write32(&rk3288_grf->iomux_i2c5scl, IOMUX_HDMI_EDP_I2C_SCL); + + gpio_output(GPIO(7, B, 3), 1); /* POWER_HDMI_ON */ +} + static void mainboard_init(device_t dev) { gpio_output(GPIO_RESET, 0); configure_usb(); configure_emmc(); - configure_codec(); + configure_i2s(); configure_vop(); + configure_hdmi(); elog_init(); elog_add_watchdog_reset(); @@ -115,3 +120,8 @@ void lb_board(struct lb_header *header) dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = _dma_coherent_size; } + +void mainboard_power_on_backlight(void) +{ + return; +}

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New patch to review for coreboot: ddr3: Fix SPD CRC calculation
by Patrick Rudolph 22 Jun '15

22 Jun '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10629 -gerrit commit 7400cd88379a158ede0581c181290dcdd5548a7e Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Jun 22 19:32:53 2015 +0200 ddr3: Fix SPD CRC calculation Use the correct SPD size for crc calculation. sizeof(*spd) returns 4 while sizeof(spd_raw_data) returns the expected value of 256. Change-Id: Iba305c69debd64fa921e08e00ec0a3531c80f56f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/dram/ddr3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 8170ae1..c10741b 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -128,7 +128,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3; dimm->dimm_type = spd[3] & 0xf; - crc = spd_ddr3_calc_crc(spd, sizeof(*spd)); + crc = spd_ddr3_calc_crc(spd, sizeof(spd_raw_data)); /* Compare with the CRC in the SPD */ spd_crc = (spd[127] << 8) + spd[126]; /* Verify the CRC is correct */

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New patch to review for coreboot: veyron_danger: Fix #include guard
by Patrick Georgi 22 Jun '15

22 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10628 -gerrit commit 8f7d7b773fb25974080d797d9fa7a30e8d451914 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jun 3 17:20:54 2015 -0700 veyron_danger: Fix #include guard Cosmetic change only. BUG=none BRANCH=none TEST=it compiles Change-Id: Ibe86f624606e365457e03c50c005400d4b335536 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7dfc7002fbf5c100ae65458b33f5aa007dc8d60b Original-Change-Id: Ibc03b028a7918d90cfab9614e800f6df463d86db Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280851 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_danger/board.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/veyron_danger/board.h b/src/mainboard/google/veyron_danger/board.h index aa51f79..8f62078 100644 --- a/src/mainboard/google/veyron_danger/board.h +++ b/src/mainboard/google/veyron_danger/board.h @@ -17,8 +17,8 @@ * Foundation, Inc. */ -#ifndef __MAINBOARD_GOOGLE_VEYRON_BRAIN_BOARD_H -#define __MAINBOARD_GOOGLE_VEYRON_BRAIN_BOARD_H +#ifndef __MAINBOARD_GOOGLE_VEYRON_DANGER_BOARD_H +#define __MAINBOARD_GOOGLE_VEYRON_DANGER_BOARD_H #include <boardid.h> #include <gpio.h> @@ -29,4 +29,4 @@ void setup_chromeos_gpios(void); -#endif /* __MAINBOARD_GOOGLE_VEYRON_BRAIN_BOARD_H */ +#endif /* __MAINBOARD_GOOGLE_VEYRON_DANGER_BOARD_H */

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New patch to review for coreboot: chromeos: vpd: properly null terminate values
by Patrick Georgi 22 Jun '15

22 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10627 -gerrit commit 47781ddd92f882eb36c44438aeb963f649daf124 Author: Stephen Barber <smbarber(a)chromium.org> Date: Fri Jun 19 12:56:34 2015 -0700 chromeos: vpd: properly null terminate values VPD strings are not null terminated, so we can't use strcpy on them in cros_vpd_gets. BUG=none BRANCH=none TEST=add serial_number followed by cam_calib_data to VPD on smaug; make sure that smaug boots and serial number matches exactly (no garbage) Change-Id: Id72885517b3d0b1934ba329c1ef0d89a67bd2bb4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 56bbe6688b11043360a046a250d1ea93db4d9f0e Original-Change-Id: I811dfc2f0830a91410eb69961a6565080ff78267 Original-Signed-off-by: Stephen Barber <smbarber(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280836 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> --- src/vendorcode/google/chromeos/cros_vpd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c index fed1d82..f9aec88 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.c +++ b/src/vendorcode/google/chromeos/cros_vpd.c @@ -132,7 +132,8 @@ char *cros_vpd_gets(const char *key, char *buffer, int size) return NULL; if (size > (string_size + 1)) { - strcpy(buffer, string_address); + memcpy(buffer, string_address, string_size); + buffer[string_size] = '\0'; } else { memcpy(buffer, string_address, size - 1); buffer[size - 1] = '\0';

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New patch to review for coreboot: libpayload udc: add interface to add string descriptors
by Patrick Georgi 22 Jun '15

22 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10626 -gerrit commit 415537fa31dfba34c25c0dcd7ff4b269847c1987 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Thu Jun 18 00:15:00 2015 +0200 libpayload udc: add interface to add string descriptors They're ASCII only, with only one language at a time, but they should be good enough to report device names and serial numbers. BUG=none BRANCH=none TEST=with depthcharge CL, check dmesg on the host device Change-Id: If888e05b2f372f7f0f43fadb108ca7ef4ed3b7c1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f0bc4242057d3edc4f4796ebeed2d98d89d60a1d Original-Change-Id: Ibe42f1b49f412e5482cebb7ebe20f6034352fd12 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/278300 Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/drivers/udc/chipidea.c | 1 + payloads/libpayload/drivers/udc/udc.c | 68 ++++++++++++++++++++++++++++++ payloads/libpayload/include/udc/udc.h | 21 +++++++++ 3 files changed, 90 insertions(+) diff --git a/payloads/libpayload/drivers/udc/chipidea.c b/payloads/libpayload/drivers/udc/chipidea.c index 8299a08..16a42e4 100644 --- a/payloads/libpayload/drivers/udc/chipidea.c +++ b/payloads/libpayload/drivers/udc/chipidea.c @@ -489,6 +489,7 @@ struct usbdev_ctrl *chipidea_init(device_descriptor_t *dd) ctrl->poll = chipidea_poll; ctrl->add_gadget = udc_add_gadget; + ctrl->add_strings = udc_add_strings; ctrl->enqueue_packet = chipidea_enqueue_packet; ctrl->shutdown = chipidea_shutdown; ctrl->set_address = chipidea_set_address; diff --git a/payloads/libpayload/drivers/udc/udc.c b/payloads/libpayload/drivers/udc/udc.c index d0683ff..01aa4b1 100644 --- a/payloads/libpayload/drivers/udc/udc.c +++ b/payloads/libpayload/drivers/udc/udc.c @@ -47,6 +47,18 @@ #define min(a, b) (((a) < (b)) ? (a) : (b)) +static unsigned short strings_lang_id = 0; +static unsigned char strings_count = 0; +static const char **strings; + +void udc_add_strings(unsigned short lang_id, unsigned char count, + const char **str) +{ + strings_lang_id = lang_id; + strings_count = count; + strings = str; +} + /* determine if an additional zero length packet is necessary for * a transfer */ static unsigned int zlp(struct usbdev_ctrl *this, const int epnum, @@ -303,6 +315,62 @@ static int setup_ep0(struct usbdev_ctrl *this, dev_req_t *dr) } else if ((dr->bmRequestType == 0x80) && (dr->bRequest == GET_DESCRIPTOR) && + ((dr->wValue & 0xff00) == 0x0300)) { + int id = (dr->wValue & 0xff); + if (id == 0) { + if (strings_lang_id == 0) + return 0; + + uint8_t *data = dma_malloc(4); + data[0] = 0x04; // length + data[1] = 0x03; // string descriptor + data[2] = strings_lang_id & 0xff; + data[3] = strings_lang_id >> 8; + /* data phase IN */ + this->enqueue_packet(this, 0, 1, + data, + min(data[0], dr->wLength), + zlp(this, 0, data[0], dr->wLength), + 1); + + /* status phase OUT */ + this->enqueue_packet(this, 0, 0, NULL, 0, 0, 0); + } else { + if (strings_lang_id == 0) + return 0; + + int lang = dr->wIndex; + if (lang != strings_lang_id) + return 0; + + if (id > strings_count) + return 0; + + int s_len = strlen(strings[id]); + int d_len = s_len * 2; + + uint8_t *data = dma_malloc(d_len + 2); + memset(data, 0, d_len); + data[0] = d_len + 2; // length + data[1] = 0x03; // string descriptor + int i; + for (i = 0; i < s_len; i++) + data[i * 2 + 2] = strings[id][i]; + + /* data phase IN */ + this->enqueue_packet(this, 0, 1, + data, + min(d_len + 2, dr->wLength), + zlp(this, 0, d_len + 2, dr->wLength), + 1); + + /* status phase OUT */ + this->enqueue_packet(this, 0, 0, NULL, 0, 0, 0); + } + return 1; + } else + if ((dr->bmRequestType == 0x80) && + (dr->bRequest == GET_DESCRIPTOR) && ((dr->wValue & 0xff00) == 0x0100)) { device_descriptor_t *dd = dma_malloc(sizeof(*dd)); memcpy(dd, &this->device_descriptor, sizeof(*dd)); diff --git a/payloads/libpayload/include/udc/udc.h b/payloads/libpayload/include/udc/udc.h index 7987c51..99cbb1b 100644 --- a/payloads/libpayload/include/udc/udc.h +++ b/payloads/libpayload/include/udc/udc.h @@ -103,6 +103,22 @@ struct usbdev_ctrl { struct usbdev_configuration *config); /** + * Add a set of strings to use for string descriptors. + * + * 's' must point to an array of strings of which the first + * element is unused, with at most 255 elements. + * + * 'm' is the size of 'strings' (ie. the index of the last entry). + * + * 'l' is the USB language code, of which some are defined below, + * eg. LANG_EN_US. + * + * For now, only one language is ever exposed: Calling add_strings overwrites + * older configuration. + */ + void (*add_strings)(unsigned short l, unsigned char m, const char **s); + + /** * Add packet to process by the controller. * zlp: zero length packet, if such a termination is necessary * autofree: free data after use @@ -136,8 +152,13 @@ struct usbdev_ctrl { void (*free_data)(void *); }; +#define LANG_DE_DE 0x0407 +#define LANG_EN_US 0x0409 + void udc_add_gadget(struct usbdev_ctrl *this, struct usbdev_configuration *config); +void udc_add_strings(unsigned short id, unsigned char count, + const char *strings[]); void udc_handle_setup(struct usbdev_ctrl *this, int ep, dev_req_t *dr); #endif

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coreboot-gerrit June 2015