the following patch was just integrated into master:
commit a412d399e951860a1b7913d568d390bf5ce47a5a
Author: Martin Roth <gaumless(a)gmail.com>
Date: Sat Jun 20 16:45:30 2015 -0600
Remove obsolete EARLY_CONSOLE usage
The EARLY_CONSOLE Kconfig symbol was removed in
commit 48713a1b - console: Drop EARLY_CONSOLE option
The arm64 and mips directories don't even have early_console.c
to include.
Change-Id: Idc60ffb2bac2b180f4fdd0adf5c411e1f692a846
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Reviewed-on: http://review.coreboot.org/10615
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/10615 for details.
-gerrit
the following patch was just integrated into master:
commit 64ae446dbca1fbd25395aa4f857caec746613c98
Author: Martin Roth <gaumless(a)gmail.com>
Date: Sat Jun 20 16:32:24 2015 -0600
superio/fintek/Kconfig: add newline at end of file.
Kconfig sometimes fails to parse the last line of a file if there's
no newline at the end. Add one to be safe.
Change-Id: Ia9973a89b12596e1f2a2741ad2e255e886495331
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Reviewed-on: http://review.coreboot.org/10614
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/10614 for details.
-gerrit
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10621
-gerrit
commit 70830bd9bd13d767821041b9a2e832cf2f73a9cf
Author: Martin Roth <gaumless(a)gmail.com>
Date: Sun Jun 21 13:05:03 2015 -0600
crossgcc/Makefile: clean more, add distclean target
Update the clean target to remove the intermediate files. These should
get removed automatically, but if the build stops in the middle, or if
the -t command is used for buildgcc, they can be left in the directory.
Add a distclean target that removes the downloaded tarballs as well as
everything else.
Change-Id: I6ea19e7a499b0c313c1d2eff7e36386204ec834e
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
---
util/crossgcc/Makefile | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile
index d0ab28a..2104a89 100644
--- a/util/crossgcc/Makefile
+++ b/util/crossgcc/Makefile
@@ -44,5 +44,13 @@ build-riscv-without-gdb:
clean:
rm -rf xgcc
+ rm -rf build-*
+ rm -rf binutils-* gcc-* gmp-* libelf-* mpc-* mpfr-*
+ rm -rf llvm-* clang-tools-* cfe-* compiler-rt-*
+ rm -rf acpica-*
+ rm -rf gdb-*
-.PHONY: all build clean
+distclean: clean
+ rm -rf tarballs
+
+.PHONY: all build clean distclean
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10619
-gerrit
commit a5adb35d172acdf0b7d92852fb90ba86d125d2b4
Author: Martin Roth <gaumless(a)gmail.com>
Date: Sun Jun 21 12:06:28 2015 -0600
buildgcc: Add list of valid platform to the help text.
Change-Id: Ic48a08d1067c850555cf04ad29e65e9bdb7c4243
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
---
util/crossgcc/buildgcc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index ddb6c4c..b78b141 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -305,6 +305,8 @@ myhelp()
printf " [-p|--platform <platform>] target platform to build cross compiler for\n"
printf " (defaults to $TARGETARCH)\n"
printf " [-S|--scripting] build scripting support for GDB\n\n"
+ printf "Platforms for GCC & GDB:\n"
+ printf " x86_64 i386-elf i386-mingw32 mipsel-elf riscv-elf arm aarch64\n\n"
}
myversion()
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10619
-gerrit
commit de535c8c00f6dcd9a2fdbecb67f73d4064732312
Author: Martin Roth <gaumless(a)gmail.com>
Date: Sun Jun 21 12:06:28 2015 -0600
crossgcc: Add list of valid platform to the help text.
Change-Id: Ic48a08d1067c850555cf04ad29e65e9bdb7c4243
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
---
util/crossgcc/buildgcc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index ddb6c4c..b78b141 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -305,6 +305,8 @@ myhelp()
printf " [-p|--platform <platform>] target platform to build cross compiler for\n"
printf " (defaults to $TARGETARCH)\n"
printf " [-S|--scripting] build scripting support for GDB\n\n"
+ printf "Platforms for GCC & GDB:\n"
+ printf " x86_64 i386-elf i386-mingw32 mipsel-elf riscv-elf arm aarch64\n\n"
}
myversion()
Tobias Diedrich (ranma+coreboot(a)tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10617
-gerrit
commit b352a4efb3e822d5403d7af8cd6bd2ca3d4a68ac
Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>
Date: Sun Jun 21 18:15:40 2015 +0200
amd/fam10: Add k10temp ACPI thermal zone mixin.
This ACPI thermal zone is applicable to AMD family 10 to 14 (and some
15) CPUs.
It should not be used on boards for which errata 319 (The thermal sensor
of Socket F/AM2+ processors may be unreliable) is applicable. AM3 and
later should be fine.
Derived from src/northbridge/amd/amdk8/thermal_mixin.asl
Change-Id: Id036cbf4cd717c3320a720edc452945df2b5e072
Signed-off-by: <ranma+coreboot(a)tdiedrich.de>
---
src/northbridge/amd/amdfam10/thermal_mixin.asl | 89 ++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/src/northbridge/amd/amdfam10/thermal_mixin.asl b/src/northbridge/amd/amdfam10/thermal_mixin.asl
new file mode 100644
index 0000000..3bd7e40
--- /dev/null
+++ b/src/northbridge/amd/amdfam10/thermal_mixin.asl
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/*
+ * Include this file into a mainboard DSDT inside the PCI device
+ * "Northbridge Miscellaneous Control (Northbridge function 3)" and it
+ * will expose the temperature sensor of the processor as a thermal
+ * zone.
+ *
+ * Families 10 through 14 and some family 15 CPUs are supported.
+ *
+ * If, for example, the NB Misc. Control device is on 0:18.3, include
+ * the following:
+ *
+ * Scope (\_SB.PCI0) {
+ * Device (K10M) {
+ * Name (_ADR, 0x00180003)
+ * #include <northbridge/amd/amdfam10/thermal_mixin.asl>
+ * }
+ * }
+ *
+ * Do not include this if the board is affected by erratum 319 as the
+ * thermal sensor of Socket F/AM2+ processors may be unreliable.
+ * (Erratum 319 affects AM2+ boards, AM3 and later should be fine)
+ */
+
+#ifndef K10TEMP_HOT_OFFSET
+# define K10TEMP_HOT_OFFSET 100
+#endif
+
+#define K10TEMP_KELVIN_OFFSET 2732
+#define K10TEMP_TLIMIT_OFFSET 520
+
+OperationRegion (TCFG, PCI_Config, 0x64, 0x4)
+Field (TCFG, ByteAcc, NoLock, Preserve) {
+ HTCE, 1, /* Hardware thermal control enable */
+ , 15,
+ TLMT, 7, /* (LimitTmp - 52) / 0.5 */
+ , 9,
+}
+
+OperationRegion (TCTL, PCI_Config, 0xa4, 0x4)
+Field (TCTL, ByteAcc, NoLock, Preserve) {
+ , 21,
+ TNOW, 11, /* CurTmp / 0.125 */
+}
+
+ThermalZone (TZ00) {
+ Name (_HID, EisaId ("PNP0C11"))
+ Name (_STR, Unicode ("AMD CPU Core Thermal Sensor"))
+
+ Method (_STA) {
+ If (LEqual (HTCE, One)) {
+ Return (0x0F)
+ }
+ Return (Zero)
+ }
+
+ Method (_TMP) { /* Current temp in tenths degree Kelvin. */
+ Multiply (TNOW, 10, Local0)
+ ShiftRight (Local0, 3, Local0)
+ Return (Add (Local0, K10TEMP_KELVIN_OFFSET))
+ }
+
+ Method (_CRT) { /* Critical temp in tenths degree Kelvin. */
+ Multiply (TLMT, 10, Local0)
+ ShiftRight (Local0, 1, Local0)
+ Add (Local0, K10TEMP_TLIMIT_OFFSET, Local0)
+ Return (Add (Local0, K10TEMP_KELVIN_OFFSET))
+ }
+
+ Method (_HOT) { /* Hot temp in tenths degree Kelvin. */
+ Return (Subtract (_CRT, K10TEMP_HOT_OFFSET))
+ }
+}
the following patch was just integrated into master:
commit e1523ecaa1da2ee77aad1b08889a07f626c5e8ed
Author: Martin Roth <gaumless(a)gmail.com>
Date: Fri Jun 19 22:30:43 2015 -0600
Reorder arch & vendorcode in Kconfig
Because Kconfig uses the first valid default that it comes across, the
'source' commands to load sub-Kconfigs should be ordered from the
most specific (mainboards) to less specific (chipsets) to least specific
(architectures). This allows the mainboards to override chipsets and
architecture Kconfig files.
Because the architecture files were getting loaded ahead of the chipset
and cpu Kconfigs, the preferred defaults values for things such as
NUM_IPI_STARTS or RISCV_BOOTBLOCK_CUSTOM could not be set.
Change-Id: Ic327452833f012ec06dabb5b5ef661aba3aff464
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Reviewed-on: http://review.coreboot.org/10609
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie(a)google.com>
See http://review.coreboot.org/10609 for details.
-gerrit