coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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1226 discussions

Patch set updated for coreboot: oprom: Fix for 64bit
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10591 -gerrit commit f6016bdbee212189156e4d2efc70c940e715ca13 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 22:01:07 2015 -0700 oprom: Fix for 64bit Change-Id: If4c1ab5ae33a64be3e7b14150d410edd291ee4ed Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/device/oprom/realmode/x86.c | 2 +- src/device/pci_rom.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 485d1a4..14bcbc0 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -188,7 +188,7 @@ static void setup_realmode_idt(void) for (i = 0; i < 256; i++) { idts[i].cs = 0; idts[i].offset = 0x1000 + (i * __idt_handler_size); - write_idt_stub((void *)((u32 )idts[i].offset), i); + write_idt_stub((void *)((uintptr_t)idts[i].offset), i); } /* Many option ROMs use the hard coded interrupt entry points in the diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 26cd6cf..80b2a51 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -57,7 +57,7 @@ struct rom_header *pci_rom_probe(struct device *dev) printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", dev_path(dev), rom_header); } else { - u32 rom_address; + uintptr_t rom_address; rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);

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Patch set updated for coreboot: x86: Make ACPI 64bit clean
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10578 -gerrit commit edf5feabd0536649b817b462f8de2ebcc4339065 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:11:19 2015 -0700 x86: Make ACPI 64bit clean Change-Id: I29eaba74185711df055cf56c23ef2bdae0c7b43e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/boot/acpi.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 4090a1d..208411e 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -65,11 +65,11 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table) acpi_xsdt_t *xsdt = NULL; /* The RSDT is mandatory... */ - rsdt = (acpi_rsdt_t *)rsdp->rsdt_address; + rsdt = (acpi_rsdt_t *)(uintptr_t)rsdp->rsdt_address; /* ...while the XSDT is not. */ if (rsdp->xsdt_address) - xsdt = (acpi_xsdt_t *)((u32)rsdp->xsdt_address); + xsdt = (acpi_xsdt_t *)((uintptr_t)rsdp->xsdt_address); /* This should always be MAX_ACPI_TABLES. */ entries_num = ARRAY_SIZE(rsdt->entry); @@ -86,7 +86,7 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table) } /* Add table to the RSDT. */ - rsdt->entry[i] = (u32)table; + rsdt->entry[i] = (uintptr_t)table; /* Fix RSDT length or the kernel will assume invalid entries. */ rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i + 1)); @@ -101,7 +101,7 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table) */ if (xsdt) { /* Add table to the XSDT. */ - xsdt->entry[i] = (u64)(u32)table; + xsdt->entry[i] = (u64)(uintptr_t)table; /* Fix XSDT length. */ xsdt->header.length = sizeof(acpi_header_t) + @@ -299,7 +299,7 @@ static void acpi_create_tcpa(acpi_tcpa_t *tcpa) tcpa->platform_class = 0; tcpa->laml = tcpa_log_len; - tcpa->lasa = (u32) lasa; + tcpa->lasa = (uintptr_t) lasa; /* Calculate checksum. */ header->checksum = acpi_checksum((void *)tcpa, header->length); @@ -588,7 +588,7 @@ static void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, memcpy(rsdp->oem_id, oem_id, 6); rsdp->length = sizeof(acpi_rsdp_t); - rsdp->rsdt_address = (u32)rsdt; + rsdp->rsdt_address = (uintptr_t)rsdt; /* * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2. @@ -600,7 +600,7 @@ static void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, if (xsdt == NULL) { rsdp->revision = 0; } else { - rsdp->xsdt_address = (u64)(u32)xsdt; + rsdp->xsdt_address = (u64)(uintptr_t)xsdt; rsdp->revision = 2; }

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Patch set updated for coreboot: cpu: port amd/agesa to 64bit
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10579 -gerrit commit a30efad7aea0de7044e69a39428c4c13a967fe7f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:14:01 2015 -0700 cpu: port amd/agesa to 64bit Change-Id: I8644b04f4b57db5fc95ec155d3f78d53c63c9831 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/cpu/amd/agesa/Makefile.inc | 4 + src/cpu/amd/agesa/cache_as_ram64.inc | 159 +++++++++++++++++++++++++++++++++++ src/cpu/amd/agesa/s3_resume.c | 7 ++ 3 files changed, 170 insertions(+) diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 153b2db..485d107 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -27,7 +27,11 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb romstage-y += s3_resume.c ramstage-y += s3_mtrr.c +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc +else +cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram64.inc +endif romstage-y += heapmanager.c ramstage-y += heapmanager.c diff --git a/src/cpu/amd/agesa/cache_as_ram64.inc b/src/cpu/amd/agesa/cache_as_ram64.inc new file mode 100644 index 0000000..de3a9bc --- /dev/null +++ b/src/cpu/amd/agesa/cache_as_ram64.inc @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/****************************************************************************** + * AMD Generic Encapsulated Software Architecture + * + * $Workfile:: cache_as_ram.inc + * + * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier + * + ****************************************************************************** + */ + +#include "gcccar.inc" +#include <cpu/x86/cache.h> + +/* + * XMM map: + * xmm0: BIST + * xmm1: backup ebx -- cpu_init_detected + */ + +.code32 +.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out + +cache_as_ram_setup: + + post_code(0xa0) + + /* enable SSE2 128bit instructions */ + /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ + + movl %cr4, %eax + orl $(3<<9), %eax + movl %eax, %cr4 + + /* Get the cpu_init_detected */ + mov $1, %eax + cpuid + shr $24, %ebx + + /* Save the BIST result */ + cvtsi2sd %ebp, %xmm0 + + /* for normal part %ebx already contain cpu_init_detected from fallback call */ + + /* Save the cpu_init_detected */ + cvtsi2sd %ebx, %xmm1 + + post_code(0xa1) + // AMD_ENABLE_STACK + + post_code(0xa1) + + /* switch to 64 bit long mode */ + .intel_syntax noprefix + + mov ecx, esi + add ecx, 0 # core number + xor eax, eax + lea edi, [ecx+0x1000+0x23] + mov dword ptr [ecx+0], edi + mov dword ptr [ecx+4], eax + + lea edi, [ecx+0x1000] + mov dword ptr [edi+0x00], 0x000000e3 + mov dword ptr [edi+0x04], eax + mov dword ptr [edi+0x08], 0x400000e3 + mov dword ptr [edi+0x0c], eax + mov dword ptr [edi+0x10], 0x800000e3 + mov dword ptr [edi+0x14], eax + mov dword ptr [edi+0x18], 0xc00000e3 + mov dword ptr [edi+0x1c], eax + + # load rom based identity mapped page tables + mov eax, ecx + mov cr3,eax + + # enable PAE + mov eax, cr4 + bts eax, 5 + mov cr4, eax + + # enable long mode + mov ecx, 0xC0000080 + rdmsr + bts eax, 8 + wrmsr + + # enable paging + mov eax, cr0 + bts eax, 31 + mov cr0, eax + + # use call far to switch to 64-bit code segment + jmp 0x18,.+7 + + /* Pass the BIST result */ + cvtsd2si esi, xmm1 + + /* Pass the cpu_init_detected */ + cvtsd2si edi, xmm0 + + /* align the stack */ + and esp, 0xFFFFFFF0 + + .code64 + call cache_as_ram_main + .code32 + + .att_syntax prefix + + /* Should never see this postcode */ + post_code(0xaf) +stop: + jmp stop + +disable_cache_as_ram: + /* Save return stack */ + movd 0(%esp), %xmm1 + movd %esp, %xmm0 + + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + AMD_DISABLE_STACK + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff, %eax + movl %eax, %cr0 + xorl %eax, %eax + + /* Restore the return stack */ + wbinvd + movd %xmm0, %esp + movd %xmm1, (%esp) + ret + +cache_as_ram_setup_out: +.code64 diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 5e07d7a..98671f4 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -56,10 +56,17 @@ static void move_stack_high_mem(void) memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); /* TODO: We only switch stack on BSP. */ +#ifdef __x86_64__ + __asm__ + volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g" + (high_stack - BSP_STACK_BASE_ADDR) + :); +#else __asm__ volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" (high_stack - BSP_STACK_BASE_ADDR) :); +#endif } static void set_resume_cache(void)

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Patch set updated for coreboot: x86: make PCI MMIO CFG functions 64bit proof
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10577 -gerrit commit 86b9f8e35562040404543c434202f96d91a3df12 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jun 17 16:12:17 2015 -0700 x86: make PCI MMIO CFG functions 64bit proof Change-Id: Ife94f5324971f4fa03e9139f458b985f6fed9d87 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/arch/x86/include/arch/pci_mmio_cfg.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index fb582dd..eec9d97 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -29,7 +29,7 @@ static inline __attribute__ ((always_inline)) u8 pcie_read_config8(pci_devfn_t dev, unsigned int where) { void *addr; - addr = (void *)(DEFAULT_PCIEXBAR | dev | where); + addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); return read8(addr); } @@ -37,7 +37,7 @@ static inline __attribute__ ((always_inline)) u16 pcie_read_config16(pci_devfn_t dev, unsigned int where) { void *addr; - addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~1)); + addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); return read16(addr); } @@ -45,7 +45,7 @@ static inline __attribute__ ((always_inline)) u32 pcie_read_config32(pci_devfn_t dev, unsigned int where) { void *addr; - addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~3)); + addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); return read32(addr); } @@ -53,7 +53,7 @@ static inline __attribute__ ((always_inline)) void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value) { void *addr; - addr = (void *)(DEFAULT_PCIEXBAR | dev | where); + addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); write8(addr, value); } @@ -61,7 +61,7 @@ static inline __attribute__ ((always_inline)) void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value) { void *addr; - addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~1)); + addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); write16(addr, value); } @@ -69,7 +69,7 @@ static inline __attribute__ ((always_inline)) void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value) { void *addr; - addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~3)); + addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); write32(addr, value); }

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Patch set updated for coreboot: SB800: Port to 64bit
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10582 -gerrit commit 42a30f9e2f46363009b8942a4315960f56884fad Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:17:38 2015 -0700 SB800: Port to 64bit Change-Id: I944fb254e9470c80b13c9eef9d6b1177a56e615f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/southbridge/amd/cimx/sb800/fadt.c | 25 +++++++++++++++++++------ src/southbridge/amd/cimx/sb800/gpio_oem.h | 6 +++--- src/southbridge/amd/cimx/sb800/late.c | 8 ++++---- src/southbridge/amd/cimx/sb800/spi.c | 2 +- 4 files changed, 27 insertions(+), 14 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 70173b6..d8fdd6f 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -63,8 +63,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; + if ((uintptr_t)facs > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n"); + else + fadt->firmware_ctrl = (uintptr_t)facs; + + if ((uintptr_t)dsdt > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n"); + else + fadt->dsdt = (uintptr_t)dsdt; + fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 – ACPI SCI */ @@ -153,10 +161,15 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; + + fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; +#ifdef __x86_64__ + fadt->x_firmware_ctl_h = ((uintptr_t)facs) >> 32; +#endif + fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; +#ifdef __x86_64__ + fadt->x_dsdt_h = ((uintptr_t)dsdt) >> 32; +#endif fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/southbridge/amd/cimx/sb800/gpio_oem.h b/src/southbridge/amd/cimx/sb800/gpio_oem.h index a9f59e3..e2c81fc 100644 --- a/src/southbridge/amd/cimx/sb800/gpio_oem.h +++ b/src/southbridge/amd/cimx/sb800/gpio_oem.h @@ -11,9 +11,9 @@ #define SB_GPIO_REG28 28 /* FCH GPIO access helpers */ -#define FCH_IOMUX(gpio_nr) (*(u8*)(ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr))) -#define FCH_PMIO(reg_nr) (*(u8*)(ACPI_MMIO_BASE+PMIO_BASE+(reg_nr))) -#define FCH_GPIO(gpio_nr) (*(volatile u8*)(ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr))) +#define FCH_IOMUX(gpio_nr) (*(u8*)((uintptr_t)ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr))) +#define FCH_PMIO(reg_nr) (*(u8*)((uintptr_t)ACPI_MMIO_BASE+PMIO_BASE+(reg_nr))) +#define FCH_GPIO(gpio_nr) (*(volatile u8*)((uintptr_t)ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr))) static inline u8 fch_gpio_state(unsigned int gpio_nr) { diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 0ada673..01900fe 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -108,15 +108,15 @@ static void ahci_raid_init(struct device *dev) bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); - caps = *(volatile u32 *)(bar5 + HOST_CAP); + caps = *(volatile u32 *)((uintptr_t)bar5 + HOST_CAP); caps = (caps & 0x1F) + 1; - ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); + ports= *(volatile u32 *)((uintptr_t)bar5 + HOST_PORTS_IMPL); printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); /* make sure ahci is enabled */ - val = *(volatile u32 *)(bar5 + HOST_CTL); + val = *(volatile u32 *)((uintptr_t)bar5 + HOST_CTL); if (!(val & HOST_CTL_AHCI_EN)) { - *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; + *(volatile u32 *)((uintptr_t)bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; } dev->command |= PCI_COMMAND_MASTER; diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 1ce7fcd..694a3b7 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -35,7 +35,7 @@ static int bus_claimed = 0; #define AMD_SB_SPI_TX_LEN 8 -static u32 spibar; +static uintptr_t spibar; static void reset_internal_fifo_pointer(void) {

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Patch set updated for coreboot: Port Fam14 northbridge code to 64bit
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10583 -gerrit commit c80b1b11f300269fa74cca0ca5606fbdeb5bb6ed Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:18:09 2015 -0700 Port Fam14 northbridge code to 64bit Change-Id: I694b739a29e9d82d153d9fb3b729dc250bd4901e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/northbridge/amd/agesa/family14/northbridge.c | 6 +++--- src/northbridge/amd/agesa/oem_s3.c | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index fcc0d87..691fdf6 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -529,7 +529,7 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); + printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev); unsigned long mmio_basek; u32 pci_tolm; @@ -741,11 +741,11 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 0, (void *)((uintptr_t)addr + 2), *(UINT16 *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 1, (void *)((uintptr_t)addr + 2), *(UINT16 *)addr - 2); return (unsigned long)current; } diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index dfc1ebc..2897e39 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -39,7 +39,7 @@ typedef enum { #error "Please increase the value of S3_DATA_SIZE" #endif -static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) +static void get_s3nv_data(S3_DATA_TYPE S3DataType, uintptr_t *pos, uintptr_t *len) { /* FIXME: Find file from CBFS. */ u32 s3_data = CONFIG_S3_DATA_POS; @@ -65,7 +65,7 @@ static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams) { AMD_S3_PARAMS *dataBlock = &ResumeParams->S3DataBlock; - u32 pos, size; + uintptr_t pos, size; get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); @@ -120,7 +120,7 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) AMD_S3_PARAMS *dataBlock = &S3SaveParams->S3DataBlock; u8 MTRRStorage[S3_DATA_MTRR_SIZE]; u32 MTRRStorageSize = 0; - u32 pos, size; + uintptr_t pos, size; if (HIGH_ROMSTAGE_STACK_SIZE) cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE); @@ -151,7 +151,7 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) const void *OemS3Saved_MTRR_Storage(void) { - u32 pos, size; + uintptr_t pos, size; get_s3nv_data(S3DataTypeMTRR, &pos, &size); if (!size) return NULL;

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Patch set updated for coreboot: cpu: x86 port to 64bit
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10580 -gerrit commit 9d8b4a0d3bcddbfc00398d1b035d5bd78bdd3a45 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:15:27 2015 -0700 cpu: x86 port to 64bit Change-Id: Ib1c6732d3a338f6d898fadc19e5af59032343451 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/cpu/x86/32bit/entry32.inc | 4 ++++ src/cpu/x86/lapic/lapic_cpu_init.c | 8 ++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index b016f8e..5c3072e 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -27,6 +27,10 @@ gdtptr: .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + /* selgdt 0x18, flat code segment (64-bit) */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 + gdt_end: diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 0e2550f..0e314fd 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -58,13 +58,17 @@ int lowmem_backup_size; static inline void setup_secondary_gdt(void) { u16 *gdt_limit; +#ifdef __x86_64__ + u64 *gdt_base; +#else u32 *gdt_base; +#endif gdt_limit = (void *)&_secondary_gdt_addr; gdt_base = (void *)&gdt_limit[1]; - *gdt_limit = (u32)&gdt_end - (u32)&gdt - 1; - *gdt_base = (u32)&gdt; + *gdt_limit = (uintptr_t)&gdt_end - (uintptr_t)&gdt - 1; + *gdt_base = (uintptr_t)&gdt; } static void copy_secondary_start_to_lowest_1M(void)

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Patch set updated for coreboot: vendorcode: Port AMD Agesa for Fam14 to 64bit
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10581 -gerrit commit ac495e71861ccfca936bd4ba7d126d52b80f7d77 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:16:40 2015 -0700 vendorcode: Port AMD Agesa for Fam14 to 64bit Change-Id: Ic6b3c3382a6d3fdc6d716ea899db598910b4fe3e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 46 +++++++++++------------ src/vendorcode/amd/agesa/f14/Makefile.inc | 6 +++ src/vendorcode/amd/agesa/f14/gcccar.inc | 4 ++ 3 files changed, 33 insertions(+), 23 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 7d90f8b..9ae45c3 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -27,11 +27,11 @@ */ #if defined (__GNUC__) - +#include <stdint.h> /* I/O intrin functions. */ -static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port) +static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port) { - unsigned char value; + uint8_t value; __asm__ __volatile__ ( "in %1, %0" @@ -42,9 +42,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned return value; } -static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port) +static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port) { - unsigned short value; + uint16_t value; __asm__ __volatile__ ( "in %1, %0" @@ -55,9 +55,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne return value; } -static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port) +static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port) { - unsigned long value; + uint32_t value; __asm__ __volatile__ ( "in %1, %0" @@ -68,7 +68,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne } -static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data) +static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data) { __asm__ __volatile__ ( "out %0, %1" @@ -77,7 +77,7 @@ static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short P ); } -static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data) +static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data) { __asm__ __volatile__ ( "out %0, %1" @@ -86,7 +86,7 @@ static __inline__ __attribute__((always_inline)) void __outword(unsigned short P ); } -static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data) +static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data) { __asm__ __volatile__ ( "out %0, %1" @@ -95,7 +95,7 @@ static __inline__ __attribute__((always_inline)) void __outdword(unsigned short ); } -static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; insb" @@ -104,7 +104,7 @@ static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned sh ); } -static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; insw" @@ -113,7 +113,7 @@ static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned sh ); } -static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; insl" @@ -122,7 +122,7 @@ static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned s ); } -static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; outsb" @@ -131,7 +131,7 @@ static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned s ); } -static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; outsw" @@ -140,7 +140,7 @@ static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned s ); } -static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) +static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( "rep ; outsl" @@ -525,7 +525,7 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source) } static __inline__ __attribute__((always_inline)) void -__writefsbyte(const unsigned long Offset, const unsigned char Data) +__writefsbyte(const unsigned long Offset, const uint8_t Data) { __asm__ ("movb %[Data], %%fs:%a[Offset]" : @@ -533,7 +533,7 @@ __writefsbyte(const unsigned long Offset, const unsigned char Data) } static __inline__ __attribute__((always_inline)) void -__writefsword(const unsigned long Offset, const unsigned short Data) +__writefsword(const unsigned long Offset, const uint16_t Data) { __asm__ ("movw %[Data], %%fs:%a[Offset]" : @@ -541,14 +541,14 @@ __writefsword(const unsigned long Offset, const unsigned short Data) } static __inline__ __attribute__((always_inline)) void -__writefsdword(const unsigned long Offset, const unsigned long Data) +__writefsdword(const unsigned long Offset, const uint32_t Data) { __asm__ ("movl %[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "ir" (Data)); } -static __inline__ __attribute__((always_inline)) unsigned char +static __inline__ __attribute__((always_inline)) uint8_t __readfsbyte(const unsigned long Offset) { unsigned char value; @@ -558,7 +558,7 @@ __readfsbyte(const unsigned long Offset) return value; } -static __inline__ __attribute__((always_inline)) unsigned short +static __inline__ __attribute__((always_inline)) uint16_t __readfsword(const unsigned long Offset) { unsigned short value; @@ -568,11 +568,11 @@ __readfsword(const unsigned long Offset) return value; } -static __inline__ __attribute__((always_inline)) unsigned long +static __inline__ __attribute__((always_inline)) uint32_t __readfsdword(unsigned long Offset) { unsigned long value; - __asm__ ("movl %%fs:%a[Offset], %[value]" + __asm__ ("mov %%fs:%a[Offset], %[value]" : [value] "=r" (value) : [Offset] "ir" (Offset)); return value; diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index 00e2443..ba6a30e 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -64,15 +64,21 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing +CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### classes-y += libagesa +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call create_class_compiler,libagesa,x86_32)) +else +$(eval $(call create_class_compiler,libagesa,x86_64)) +endif libagesa-y = Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index f0a1901..9b1d893 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -42,7 +42,11 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +#ifdef __x86_64__ CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ +#else +CORE1_STACK_SIZE = 0x2000 /* 4KB for each AP cores */ +#endif APIC_BASE_ADDRESS = 0x0000001B APIC_BSC = 8 /* Boot Strap Core */

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Patch set updated for coreboot: cpu/amd: Fix cbtypes.h to match UINTN convention
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10601 -gerrit commit 7fff22864b0355db048b467b5a25fe045315a899 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jun 19 16:42:58 2015 -0700 cpu/amd: Fix cbtypes.h to match UINTN convention UINTN maps to uintptr_t in UEFI land. Do the same here. Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/include/cpu/amd/common/cbtypes.h | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/include/cpu/amd/common/cbtypes.h b/src/include/cpu/amd/common/cbtypes.h index 346f1a3..6a47e00 100644 --- a/src/include/cpu/amd/common/cbtypes.h +++ b/src/include/cpu/amd/common/cbtypes.h @@ -20,16 +20,20 @@ #ifndef _CBTYPES_H_ #define _CBTYPES_H_ -typedef signed long long __int64; +/* Map coreboot stdint types to AGESA types. */ + +#include <stdint.h> + +typedef int64_t __int64; typedef void VOID; -typedef unsigned int UINTN; -typedef signed char CHAR8; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef signed int INT32; -typedef unsigned long long UINT64; -typedef unsigned char BOOLEAN; +typedef uintptr_t UINTN; +typedef int8_t CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef int32_t INT32; +typedef uint64_t UINT64; +typedef uint8_t BOOLEAN; #define DMSG_SB_TRACE 0x02 #define TRACE(Arguments)

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Patch set updated for coreboot: lippert/frontrunner-af: 64bit fixes
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10600 -gerrit commit a75fbf137c1757a1fdd1085f5185053558197b52 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jun 19 15:55:49 2015 -0700 lippert/frontrunner-af: 64bit fixes Change-Id: Ia764798c8b58497e2b453bd000dd06816c28f98f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/lippert/frontrunner-af/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 5a4ee09..692e2a6 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -126,7 +126,7 @@ static void init(struct device *dev) } /* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */ - spi_base = (u8*)(pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0xA0) & 0xFFFFFFE0); + spi_base = (u8*)((uintptr_t)pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0xA0) & 0xFFFFFFE0); spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register /* Notify the SMC we're alive and kicking, or after a while it will

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coreboot-gerrit June 2015