coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: SeaBIOS: Store the .config and revision in CBFS
by Martin Roth 19 Jun '15

19 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10607 -gerrit commit 00e016d2884f77b5e1c7777644918b57925123a0 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 20:50:59 2015 -0600 SeaBIOS: Store the .config and revision in CBFS Add a Kconfig option to store the SeaBIOS .config and version.c files into CBFS if using a SeaBIOS payload. This defaults to disabled if using SEABIOS_STABLE, because the coreboot version specifies everything needed to rebuild that. For SeaBIOS master, the version changes, and for User-managed builds, both the config and version are needed. Change-Id: I0c1b4da8f6179b9cee06cecfa76bc631b43196e0 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile.inc | 7 +++++++ src/Kconfig | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index b5acdd0..a1874d7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -629,6 +629,13 @@ ifeq ($(CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD),y) $(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) endif endif +ifeq ($(CONFIG_SEABIOS_INCLUDE_CONFIG_FILE),y) + @printf " CONFIG payloads/external/SeaBIOS/seabios/.config\n" + if [ -f payloads/external/SeaBIOS/seabios/.config ]; then \ + $(CBFSTOOL) $@.tmp add -f payloads/external/SeaBIOS/seabios/.config -n seabios_config -t raw ; fi + @printf " REVISION payloads/external/SeaBIOS/seabios/out/version.c\n" + if [ -f payloads/external/SeaBIOS/seabios/out/version.c ]; then $(CBFSTOOL) $@.tmp add -f payloads/external/SeaBIOS/seabios/out/version.c -n seabios_revision -t raw; fi +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print diff --git a/src/Kconfig b/src/Kconfig index d4e0012..1c07988 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -771,6 +771,15 @@ config SEABIOS_VGA_COREBOOT After initializing the GPU, the information about it can be passed to the payload. Provide an option rom that implements this legacy VGA BIOS compatibility requirement. +config SEABIOS_INCLUDE_CONFIG_FILE + bool "Include SeaBIOS .config and version.c in CBFS" if PAYLOAD_SEABIOS + depends on !SEABIOS_STABLE + default INCLUDE_CONFIG_FILE + help + Similar to storing the coreboot .config and build.h files in CBFS, + this stores the SeaBIOS .config and version.c files into CBFS so it's + easier to see what version and options were used to create the image. + choice prompt "GRUB2 version" default GRUB2_MASTER

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New patch to review for coreboot: SeaBIOS: Clean up build command line.
by Martin Roth 19 Jun '15

19 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10606 -gerrit commit 6abae6a9d15701377c585b8dbface18c1327e8fd Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 20:22:05 2015 -0600 SeaBIOS: Clean up build command line. - Move IASL up with the other tools. - Remove OUT= which is no longer used in the payloads/external/SeaBIOS Makefile. Change-Id: I211ddcf3496b533151936fa5cbfa7a92986ec28f Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/arch/x86/Makefile.inc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 239563a..1538efe 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -316,7 +316,7 @@ seabios: LD=$(word 1,$(LD_x86_32)) LDFLAGS="$(patsubst $(word 1,$(LD_x86_32))%,,$(LD_x86_32))" \ OBJDUMP="$(OBJDUMP_x86_32)" \ OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \ - AS="$(AS_x86_32)" \ + AS="$(AS_x86_32)" IASL="$(IASL)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ CONFIG_SEABIOS_USER_MANAGED=$(CONFIG_SEABIOS_USER_MANAGED) \ @@ -324,8 +324,7 @@ seabios: CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ - CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) \ - OUT=$(abspath $(obj)) IASL="$(IASL)" + CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) filo: $(MAKE) -C payloads/external/FILO -f Makefile.inc \

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New patch to review for coreboot: SeaBIOS: Rename Makefile.inc to Makefile
by Martin Roth 19 Jun '15

19 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10605 -gerrit commit b553c16bab7cd23983e607d7db30f85eea94577a Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 20:20:27 2015 -0600 SeaBIOS: Rename Makefile.inc to Makefile The payloads/external/SeaBIOS/Makefile.inc is not actually included in the rest of the coreboot Makefile tree, it's called out explicitly when doing the build. Because of this, the standard CONFIG_ variables need to be passed to it on the command line instead of just being available. Since it's named .inc, it would be expected that similar to other Makefile.inc files, these would just be available for use. Change-Id: I64de18f9e0d88d188705b53921e9e12c2f37f71d Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- payloads/external/SeaBIOS/Makefile | 81 ++++++++++++++++++++++++++++++++++ payloads/external/SeaBIOS/Makefile.inc | 81 ---------------------------------- src/arch/x86/Makefile.inc | 2 +- 3 files changed, 82 insertions(+), 82 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile new file mode 100644 index 0000000..7cd2b03 --- /dev/null +++ b/payloads/external/SeaBIOS/Makefile @@ -0,0 +1,81 @@ +TAG-$(CONFIG_SEABIOS_MASTER)=origin/master +TAG-$(CONFIG_SEABIOS_STABLE)=e51488c5f8800a52ac5c8da7a31b85cca5cc95d2 + +unexport KCONFIG_AUTOHEADER +unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES + +all: build + +fetch: seabios + cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ + then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi + +checkout: fetch + echo " Checking out SeaBIOS revision $(TAG-y)" + cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + +config: checkout + echo " CONFIG SeaBIOS $(TAG-y)" + echo "CONFIG_COREBOOT=y" > seabios/.config +ifeq ($(CONFIG_CONSOLE_SERIAL),y) + echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config + echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config +else + echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config +endif +ifneq ($(CONFIG_SEABIOS_MALLOC_UPPERMEMORY),y) + echo "# CONFIG_MALLOC_UPPERMEMORY is not set" >> seabios/.config +endif +ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) + echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config +endif +ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) + echo "CONFIG_VGA_COREBOOT=y" >> seabios/.config + echo "CONFIG_BUILD_VGABIOS=y" >> seabios/.config +endif + # This shows how to force a previously set .config option *off* + #echo "# CONFIG_SMBIOS is not set" >> seabios/.config + $(MAKE) -C seabios olddefconfig OUT=out/ + +ifeq ($(CONFIG_SEABIOS_USER_MANAGED),) + +seabios: + echo " Cloning SeaBIOS from Git" + git clone http://review.coreboot.org/p/seabios.git seabios + +build: config + echo " MAKE SeaBIOS $(TAG-y)" + $(MAKE) -C seabios OUT=out/ + +else # User-managed SeaBIOS configuration + +seabios: + @printf "\nError: No local version of SeaBIOS exists in:\n" + @printf " $$(pwd)/seabios\n" + @printf " Please select a different version of SeaBIOS in Kconfig\n" + @printf " or put a copy of SeaBIOS in that location.\n\n" + false # halt the build. + +seabios/.config: + @printf "\nError: SeaBIOS .config does not exist. Run the SeaBIOS 'make menuconfig'.\n\n" + false # halt the build. + +seabios/out/bios.bin.elf: seabios/.config + echo " MAKE SeaBIOS" + $(MAKE) -C seabios OUT=out/ + +build: seabios seabios/out/bios.bin.elf + +endif # User-managed SeaBIOS configuration + +clean: + test -d seabios && $(MAKE) -C seabios clean OUT=out/ || exit 0 + +distclean: + rm -rf seabios + +.PHONY: checkout config build clean distclean clone fetch diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc deleted file mode 100644 index 7cd2b03..0000000 --- a/payloads/external/SeaBIOS/Makefile.inc +++ /dev/null @@ -1,81 +0,0 @@ -TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=e51488c5f8800a52ac5c8da7a31b85cca5cc95d2 - -unexport KCONFIG_AUTOHEADER -unexport KCONFIG_AUTOCONFIG -unexport KCONFIG_DEPENDENCIES -unexport KCONFIG_SPLITCONFIG -unexport KCONFIG_TRISTATE -unexport KCONFIG_NEGATIVES - -all: build - -fetch: seabios - cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ - then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi - -checkout: fetch - echo " Checking out SeaBIOS revision $(TAG-y)" - cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) - -config: checkout - echo " CONFIG SeaBIOS $(TAG-y)" - echo "CONFIG_COREBOOT=y" > seabios/.config -ifeq ($(CONFIG_CONSOLE_SERIAL),y) - echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config - echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config -else - echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config -endif -ifneq ($(CONFIG_SEABIOS_MALLOC_UPPERMEMORY),y) - echo "# CONFIG_MALLOC_UPPERMEMORY is not set" >> seabios/.config -endif -ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) - echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config -endif -ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) - echo "CONFIG_VGA_COREBOOT=y" >> seabios/.config - echo "CONFIG_BUILD_VGABIOS=y" >> seabios/.config -endif - # This shows how to force a previously set .config option *off* - #echo "# CONFIG_SMBIOS is not set" >> seabios/.config - $(MAKE) -C seabios olddefconfig OUT=out/ - -ifeq ($(CONFIG_SEABIOS_USER_MANAGED),) - -seabios: - echo " Cloning SeaBIOS from Git" - git clone http://review.coreboot.org/p/seabios.git seabios - -build: config - echo " MAKE SeaBIOS $(TAG-y)" - $(MAKE) -C seabios OUT=out/ - -else # User-managed SeaBIOS configuration - -seabios: - @printf "\nError: No local version of SeaBIOS exists in:\n" - @printf " $$(pwd)/seabios\n" - @printf " Please select a different version of SeaBIOS in Kconfig\n" - @printf " or put a copy of SeaBIOS in that location.\n\n" - false # halt the build. - -seabios/.config: - @printf "\nError: SeaBIOS .config does not exist. Run the SeaBIOS 'make menuconfig'.\n\n" - false # halt the build. - -seabios/out/bios.bin.elf: seabios/.config - echo " MAKE SeaBIOS" - $(MAKE) -C seabios OUT=out/ - -build: seabios seabios/out/bios.bin.elf - -endif # User-managed SeaBIOS configuration - -clean: - test -d seabios && $(MAKE) -C seabios clean OUT=out/ || exit 0 - -distclean: - rm -rf seabios - -.PHONY: checkout config build clean distclean clone fetch diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cd5d2b3..239563a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -310,7 +310,7 @@ endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 ################################################################################ seabios: - $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ + $(MAKE) -C payloads/external/SeaBIOS -f Makefile \ HOSTCC="$(HOSTCC)" \ CC=$(word 1,$(CC_x86_32)) CFLAGS="$(patsubst $(word 1,$(CC_x86_32))%,,$(CC_x86_32))" \ LD=$(word 1,$(LD_x86_32)) LDFLAGS="$(patsubst $(word 1,$(LD_x86_32))%,,$(LD_x86_32))" \

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New patch to review for coreboot: SeaBIOS: Allow an expert local-managed build
by Martin Roth 19 Jun '15

19 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10604 -gerrit commit 6463ea4d815c4430c661dd1c86ad015587c083d9 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 20:11:07 2015 -0600 SeaBIOS: Allow an expert local-managed build This tries to address many of the issues I have with the current coreboot-managed SeaBIOS builds: 1) SeaBIOS is re-built on every build, even when nothing changed. If you set SeaBIOS as a payload, and run two makes in a row, the only thing that gets built the second time is SeaBIOS. 2) SeaBIOS is checked out again on every build, so if something in the seabios directory is modified, the coreboot build fails. If the user is building on a system that doesn't have git installed, the build fails. 3) The SeaBIOS configuration is updated on every build, so even if I wanted to customize my SeaBIOS configuration, it would get overwritten on the next build. This change addresses each of these issues. 1) SeaBIOS only gets rebuilt if seabios/out/bios.bin.elf is missing. 2) This doesn't ever check-out SeaBIOS, and doesn't use git. It throws an error and fails if the seabios directory is missing. 3) This doesn't modify the SeaBIOS .config. It throws an error if there is no seabios/.config file. In an attempt to cut down on issues and complaints about the option, it's set it to an 'EXPERT' level config option, so most people won't even ever see it. Similar to the PAYLOAD_ELF or PAYLOAD_LINUX options, this is not reproducable, so it probably shouldn't be used when building for board-status. Change-Id: I85ccc193cbf7bc0675af1ce6cbd6276dfdb6de0d Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 31 +++++++++++++++++++++++++++---- src/Kconfig | 16 ++++++++++++---- src/arch/x86/Makefile.inc | 1 + 3 files changed, 40 insertions(+), 8 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 4d2367e..7cd2b03 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -10,10 +10,6 @@ unexport KCONFIG_NEGATIVES all: build -seabios: - echo " Cloning SeaBIOS from Git" - git clone http://review.coreboot.org/p/seabios.git seabios - fetch: seabios cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi @@ -45,10 +41,37 @@ endif #echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ +ifeq ($(CONFIG_SEABIOS_USER_MANAGED),) + +seabios: + echo " Cloning SeaBIOS from Git" + git clone http://review.coreboot.org/p/seabios.git seabios + build: config echo " MAKE SeaBIOS $(TAG-y)" $(MAKE) -C seabios OUT=out/ +else # User-managed SeaBIOS configuration + +seabios: + @printf "\nError: No local version of SeaBIOS exists in:\n" + @printf " $$(pwd)/seabios\n" + @printf " Please select a different version of SeaBIOS in Kconfig\n" + @printf " or put a copy of SeaBIOS in that location.\n\n" + false # halt the build. + +seabios/.config: + @printf "\nError: SeaBIOS .config does not exist. Run the SeaBIOS 'make menuconfig'.\n\n" + false # halt the build. + +seabios/out/bios.bin.elf: seabios/.config + echo " MAKE SeaBIOS" + $(MAKE) -C seabios OUT=out/ + +build: seabios seabios/out/bios.bin.elf + +endif # User-managed SeaBIOS configuration + clean: test -d seabios && $(MAKE) -C seabios clean OUT=out/ || exit 0 diff --git a/src/Kconfig b/src/Kconfig index b7d2e67..d4e0012 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -715,11 +715,19 @@ config SEABIOS_MASTER bool "master" help Newest SeaBIOS version +config SEABIOS_USER_MANAGED + bool "User-managed local version" if EXPERT + help + Use the SeaBIOS version in payloads/external/Seabios/seabios + This option will not update the seabios directory with git. + It will only rebuild SeaBIOS if there is no bios.bin.elf + already built. The user will need to set up their own SeaBIOS + .config. endchoice config SEABIOS_PS2_TIMEOUT - prompt "PS/2 keyboard controller initialization timeout (milliseconds)" if PAYLOAD_SEABIOS + prompt "PS/2 keyboard controller initialization timeout (milliseconds)" if PAYLOAD_SEABIOS && !SEABIOS_USER_MANAGED default 0 depends on EXPERT int @@ -729,7 +737,7 @@ config SEABIOS_PS2_TIMEOUT keyboard controller to become ready before giving up. config SEABIOS_THREAD_OPTIONROMS - prompt "Hardware init during option ROM execution" if PAYLOAD_SEABIOS + prompt "Hardware init during option ROM execution" if PAYLOAD_SEABIOS && !SEABIOS_USER_MANAGED default n bool help @@ -742,7 +750,7 @@ config SEABIOS_THREAD_OPTIONROMS config SEABIOS_MALLOC_UPPERMEMORY bool default y - depends on PAYLOAD_SEABIOS + depends on PAYLOAD_SEABIOS && !SEABIOS_USER_MANAGED help Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal "low memory" allocations. If this is not selected, the memory is @@ -753,7 +761,7 @@ config SEABIOS_MALLOC_UPPERMEMORY set to 'N' by the chipset Kconfig. config SEABIOS_VGA_COREBOOT - prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS + prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS && !SEABIOS_USER_MANAGED default n depends on !VGA_BIOS && (MAINBOARD_DO_NATIVE_VGA_INIT || MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG) bool diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 4c00162..cd5d2b3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -319,6 +319,7 @@ seabios: AS="$(AS_x86_32)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ + CONFIG_SEABIOS_USER_MANAGED=$(CONFIG_SEABIOS_USER_MANAGED) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \

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Patch merged into coreboot/master: 3rdparty/blobs: Move submodule marker forward
by gerrit＠coreboot.org 19 Jun '15

19 Jun '15

the following patch was just integrated into master: commit dbe6ba465e298afc4acdf769844c9d515846a843 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Jun 19 18:25:58 2015 -0600 3rdparty/blobs: Move submodule marker forward Pick up the latest from blobs. 34b0926 AMD Merlin Falcon: remove build warnings e581a5c AMD pi: replace LocateModule with agesawrapper_locate_module c5ddfb6 AMD PI: remove unuseful code Change-Id: I2b9d2b61cb00aa651b90dc76368d215077e27cad Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/10603 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10603 for details. -gerrit

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New patch to review for coreboot: 3rdparty/blobs: Move submodule marker forward
by Marc Jones 19 Jun '15

19 Jun '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10603 -gerrit commit 32b352055ea9e10fdfd63e69cd800492e6f97cfc Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Jun 19 18:25:58 2015 -0600 3rdparty/blobs: Move submodule marker forward Pick up the latest from blobs. 34b0926 AMD Merlin Falcon: remove build warnings e581a5c AMD pi: replace LocateModule with agesawrapper_locate_module c5ddfb6 AMD PI: remove unuseful code Change-Id: I2b9d2b61cb00aa651b90dc76368d215077e27cad Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- 3rdparty/blobs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 14739c7..34b0926 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 14739c76936455b18a759dd2789fd4d13b16da67 +Subproject commit 34b09265063c19ea5d61bd5a2f057b47b5aa2232

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Patch set updated for coreboot: x86: Port x86 over to compile cleanly with x86-64
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10586 -gerrit commit 271302eb84b568094a2cf081aaa2eef43a25b8b6 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:23:48 2015 -0700 x86: Port x86 over to compile cleanly with x86-64 Change-Id: I26f1bbf027435be593f11bce4780111dcaf7cb86 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/arch/x86/Makefile.inc | 4 + src/arch/x86/boot/boot.c | 68 ++++++++++++-- src/arch/x86/boot/gdt.c | 8 +- src/arch/x86/boot/mpspec.c | 5 +- src/arch/x86/boot/wakeup.S | 5 + src/arch/x86/include/arch/cpu.h | 8 +- src/arch/x86/include/arch/rom_segs.h | 1 + src/arch/x86/include/arch/stages.h | 4 + src/arch/x86/lib/c_start.S | 171 +++++++++++++++++++++++++++-------- src/arch/x86/lib/cpu.c | 4 + src/arch/x86/lib/cpu_common.c | 9 ++ src/arch/x86/lib/ebda.c | 4 +- src/arch/x86/lib/exception.c | 6 +- src/arch/x86/lib/pci_ops_mmconf.c | 2 +- 14 files changed, 243 insertions(+), 56 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 4c00162..7e10acb 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -125,7 +125,11 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOC $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(LD_bootblock) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld +else + $(LD_bootblock) -m elf_x86_64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld +endif endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index d86a6c3..8600471 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -39,17 +39,64 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) /* Jump to kernel */ __asm__ __volatile__( " cld \n\t" +#ifdef __x86_64__ + /* switch back to 32-bit mode */ + " push %4\n\t" + " push %3\n\t" + " push %2\n\t" + " push %1\n\t" + " push %0\n\t" + + ".intel_syntax noprefix\n\t" + /* use iret to switch to 32-bit code segment */ + " xor rax,rax\n\t" + " mov ax, ss\n\t" + " push rax\n\t" + " mov rax, rsp\n\t" + " add rax, 8\n\t" + " push rax\n\t" + " pushfq\n\t" + " push 0x10\n\t" + " lea rax,[rip+3]\n\t" + " push rax\n\t" + " iretq\n\t" + ".code32\n\t" + /* disable paging */ + " mov eax, cr0\n\t" + " btc eax, 31\n\t" + " mov cr0, eax\n\t" + /* disable long mode */ + " mov ecx, 0xC0000080\n\t" + " rdmsr\n\t" + " btc eax, 8\n\t" + " wrmsr\n\t" + + " pop eax\n\t" + " add esp, 4\n\t" + " pop ebx\n\t" + " add esp, 4\n\t" + " pop ecx\n\t" + + " add esp, 4\n\t" + " pop edx\n\t" + " add esp, 4\n\t" + " pop esi\n\t" + " add esp, 4\n\t" + + ".att_syntax prefix\n\t" +#endif + /* Save the callee save registers... */ " pushl %%esi\n\t" " pushl %%edi\n\t" " pushl %%ebx\n\t" /* Save the parameters I was passed */ - " pushl $0\n\t" /* 20 adjust */ - " pushl %0\n\t" /* 16 lb_start */ - " pushl %1\n\t" /* 12 buffer */ - " pushl %2\n\t" /* 8 lb_size */ - " pushl %3\n\t" /* 4 entry */ - " pushl %4\n\t" /* 0 elf_boot_notes */ + " pushl $0\n\t" /* 20 adjust */ + " pushl %%eax\n\t" /* 16 lb_start */ + " pushl %%ebx\n\t" /* 12 buffer */ + " pushl %%ecx\n\t" /* 8 lb_size */ + " pushl %%edx\n\t" /* 4 entry */ + " pushl %%esi\n\t" /* 0 elf_boot_notes */ /* Compute the adjustment */ " xorl %%eax, %%eax\n\t" " subl 16(%%esp), %%eax\n\t" @@ -115,7 +162,9 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) " popl %%ebx\n\t" " popl %%edi\n\t" " popl %%esi\n\t" - +#ifdef __x86_64__ + ".code64\n\t" +#endif :: "ri" (lb_start), "ri" (buffer), "ri" (lb_size), "ri" (entry), @@ -140,7 +189,12 @@ void arch_prog_run(struct prog *prog) if (ENV_RAMSTAGE) try_payload(prog); __asm__ volatile ( +#ifdef __x86_64__ + "jmp *%%rdi\n" +#else "jmp *%%edi\n" +#endif + :: "D"(prog_entry(prog)) ); } diff --git a/src/arch/x86/boot/gdt.c b/src/arch/x86/boot/gdt.c index 44156ea..a21fab2 100644 --- a/src/arch/x86/boot/gdt.c +++ b/src/arch/x86/boot/gdt.c @@ -26,7 +26,11 @@ /* i386 lgdt argument */ struct gdtarg { u16 limit; +#ifdef __x86_64__ + u64 base; +#else u32 base; +#endif } __attribute__((packed)); /* Copy GDT to new location and reload it. @@ -35,7 +39,7 @@ struct gdtarg { static void move_gdt(int is_recovery) { void *newgdt; - u16 num_gdt_bytes = (u32)&gdt_end - (u32)&gdt; + u16 num_gdt_bytes = (uintptr_t)&gdt_end - (uintptr_t)&gdt; struct gdtarg gdtarg; newgdt = cbmem_find(CBMEM_ID_GDT); @@ -49,7 +53,7 @@ static void move_gdt(int is_recovery) memcpy((void*)newgdt, &gdt, num_gdt_bytes); } - gdtarg.base = (u32)newgdt; + gdtarg.base = (uintptr_t)newgdt; gdtarg.limit = num_gdt_bytes - 1; __asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg)); diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index 4474d7c..1a0ac31 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -73,7 +73,7 @@ static unsigned char smp_compute_checksum(void *v, int len) return checksum; } -static void *smp_write_floating_table_physaddr(u32 addr, u32 mpf_physptr, unsigned int virtualwire) +static void *smp_write_floating_table_physaddr(uintptr_t addr, uintptr_t mpf_physptr, unsigned int virtualwire) { struct intel_mp_floating *mf; void *v; @@ -591,6 +591,7 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) mptable_lintsrc(mc, isa_bus); tmp = mptable_finalize(mc); - printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)tmp - (unsigned int)v); + printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)((uintptr_t)tmp - + (uintptr_t)v)); return (unsigned long)tmp; } diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S index a614b55..38d6ea4 100644 --- a/src/arch/x86/boot/wakeup.S +++ b/src/arch/x86/boot/wakeup.S @@ -24,7 +24,12 @@ /* CR0 bits */ #define PE (1 << 0) +#ifdef __x86_64__ + .code64 +#else .code32 +#endif + .globl __wakeup __wakeup: /* First prepare the jmp to the resume vector */ diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 851b58d..5c371d9 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -179,8 +179,14 @@ struct cpu_info { static inline struct cpu_info *cpu_info(void) { struct cpu_info *ci; - __asm__("andl %%esp,%0; " + __asm__( +#ifdef __x86_64__ + "and %%rsp,%0; " + "or %2, %0 " +#else + "andl %%esp,%0; " "orl %2, %0 " +#endif :"=r" (ci) : "0" (~(CONFIG_STACK_SIZE - 1)), "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) diff --git a/src/arch/x86/include/arch/rom_segs.h b/src/arch/x86/include/arch/rom_segs.h index 8c00eb3..3b3711b 100644 --- a/src/arch/x86/include/arch/rom_segs.h +++ b/src/arch/x86/include/arch/rom_segs.h @@ -3,5 +3,6 @@ #define ROM_CODE_SEG 0x08 #define ROM_DATA_SEG 0x10 +#define ROM_CODE_SEG64 0x18 #endif /* ROM_SEGS_H */ diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 80df8e2..dfdb592 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -27,7 +27,11 @@ void asmlinkage copy_and_run(void); static inline void stage_exit(void *entry) { __asm__ volatile ( +#ifdef __x86_64__ + "jmp *%%rdi\n" +#else "jmp *%%edi\n" +#endif :: "D"(entry) ); } diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index dbed123..582966b 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -17,20 +17,30 @@ thread_stacks: #endif .section ".text._start", "ax", @progbits +#ifdef __x86_64__ + .code64 +#else .code32 +#endif .globl _start .globl __rmodule_entry __rmodule_entry: _start: cli lgdt %cs:gdtaddr +#ifndef __x86_64__ ljmp $0x10, $1f +#endif 1: movl $0x18, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss movl %eax, %fs movl %eax, %gs +#ifdef __x86_64__ + mov $0x48, %ecx + call SetCodeSelector +#endif post_code(POST_ENTRY_C_START) /* post 13 */ @@ -54,11 +64,11 @@ _start: #if CONFIG_COOP_MULTITASKING /* Push the thread pointer. */ - pushl $0 + push $0 #endif /* Push the cpu index and struct cpu */ - pushl $0 - pushl $0 + push $0 + push $0 /* Initialize the Interrupt Descriptor table */ leal _idt, %edi @@ -76,7 +86,11 @@ _start: jne 1b /* Load the Interrupt descriptor table */ +#ifndef __x86_64__ lidt idtarg +#else + // FIXME port table to x64 - lidt idtarg +#endif /* * Now we are finished. Memory is up, data is copied and @@ -97,122 +111,150 @@ _start: jmp .Lhlt vec0: - pushl $0 /* error code */ - pushl $0 /* vector */ + push $0 /* error code */ + push $0 /* vector */ jmp int_hand vec1: - pushl $0 /* error code */ - pushl $1 /* vector */ + push $0 /* error code */ + push $1 /* vector */ jmp int_hand vec2: - pushl $0 /* error code */ - pushl $2 /* vector */ + push $0 /* error code */ + push $2 /* vector */ jmp int_hand vec3: - pushl $0 /* error code */ - pushl $3 /* vector */ + push $0 /* error code */ + push $3 /* vector */ jmp int_hand vec4: - pushl $0 /* error code */ - pushl $4 /* vector */ + push $0 /* error code */ + push $4 /* vector */ jmp int_hand vec5: - pushl $0 /* error code */ - pushl $5 /* vector */ + push $0 /* error code */ + push $5 /* vector */ jmp int_hand vec6: - pushl $0 /* error code */ - pushl $6 /* vector */ + push $0 /* error code */ + push $6 /* vector */ jmp int_hand vec7: - pushl $0 /* error code */ - pushl $7 /* vector */ + push $0 /* error code */ + push $7 /* vector */ jmp int_hand vec8: /* error code */ - pushl $8 /* vector */ + push $8 /* vector */ jmp int_hand .word 0x9090 vec9: - pushl $0 /* error code */ - pushl $9 /* vector */ + push $0 /* error code */ + push $9 /* vector */ jmp int_hand vec10: /* error code */ - pushl $10 /* vector */ + push $10 /* vector */ jmp int_hand .word 0x9090 vec11: /* error code */ - pushl $11 /* vector */ + push $11 /* vector */ jmp int_hand .word 0x9090 vec12: /* error code */ - pushl $12 /* vector */ + push $12 /* vector */ jmp int_hand .word 0x9090 vec13: /* error code */ - pushl $13 /* vector */ + push $13 /* vector */ jmp int_hand .word 0x9090 vec14: /* error code */ - pushl $14 /* vector */ + push $14 /* vector */ jmp int_hand .word 0x9090 vec15: - pushl $0 /* error code */ - pushl $15 /* vector */ + push $0 /* error code */ + push $15 /* vector */ jmp int_hand vec16: - pushl $0 /* error code */ - pushl $16 /* vector */ + push $0 /* error code */ + push $16 /* vector */ jmp int_hand vec17: /* error code */ - pushl $17 /* vector */ + push $17 /* vector */ jmp int_hand .word 0x9090 vec18: - pushl $0 /* error code */ - pushl $18 /* vector */ + push $0 /* error code */ + push $18 /* vector */ jmp int_hand vec19: - pushl $0 /* error code */ - pushl $19 /* vector */ + push $0 /* error code */ + push $19 /* vector */ jmp int_hand int_hand: - /* At this point on the stack there is: + /* At this point, on x86-32, on the stack there is: * 0(%esp) vector * 4(%esp) error code * 8(%esp) eip * 12(%esp) cs * 16(%esp) eflags */ +#ifdef __x86_64__ + push %rdi + push %rsi + push %rbp + /* Original stack pointer */ + lea 32(%rsp), %rbp + push %rbp + push %rbx + push %rdx + push %rcx + push %rax + + push %rsp /* Pointer to structure on the stack */ + call x86_exception + pop %rax /* Drop the pointer */ + + pop %rax + pop %rcx + pop %rdx + pop %rbx + pop %rbp /* Ignore saved %rsp value */ + pop %rbp + pop %rsi + pop %rdi + + add $8, %rsp /* pop of the vector and error code */ +#else pushl %edi pushl %esi pushl %ebp + /* Original stack pointer */ leal 32(%esp), %ebp pushl %ebp @@ -235,6 +277,7 @@ int_hand: popl %edi addl $8, %esp /* pop of the vector and error code */ +#endif iret @@ -242,21 +285,33 @@ int_hand: .globl gdb_stub_breakpoint gdb_stub_breakpoint: +#ifdef __x86_64__ + pop %rax /* Return address */ + pushfl + push %cs + push %rax /* Return address */ + push $0 /* No error code */ + push $32 /* vector 32 is user defined */ +#else popl %eax /* Return address */ pushfl pushl %cs pushl %eax /* Return address */ pushl $0 /* No error code */ pushl $32 /* vector 32 is user defined */ +#endif jmp int_hand - #endif .globl gdt, gdt_end, idtarg gdtaddr: .word gdt_end - gdt - 1 +#ifdef __x86_64__ + .quad gdt +#else .long gdt /* we know the offset */ +#endif .data @@ -287,7 +342,11 @@ gdt: /* selgdt 0x18, flat data segment */ .word 0xffff, 0x0000 +#ifdef __x86_64__ + .byte 0x00, 0x92, 0xcf, 0x00 +#else .byte 0x00, 0x93, 0xcf, 0x00 +#endif /* selgdt 0x20, unused */ .word 0x0000, 0x0000 /* dummy */ @@ -312,6 +371,12 @@ gdt: /* selgdt 0x40, flat code segment 16 bit */ .word 0xffff, 0x0000 .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ + +#ifdef __x86_64__ + /* selgdt 0x48, flat x64 code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 +#endif gdt_end: idtarg: @@ -322,5 +387,35 @@ _idt: .fill 20, 8, 0 # idt is uninitialized _idt_end: +#ifdef __x86_64__ +SetCodeSelector: +.intel_syntax noprefix + + # save rsp because iret will align it to a 16 byte boundary + mov rdx, rsp + + # use iret to jump to a 64-bit offset in a new code segment + # iret will pop cs:rip, flags, then ss:rsp + mov ax, ss # need to push ss.. + push rax # push ss instuction not valid in x64 mode, so use ax + push rsp + pushfq + push rcx # cx is code segment selector from caller + mov rax, offset setCodeSelectorLongJump + push rax + + # the iret will continue at next instruction, with the new cs value loaded + iretq + +setCodeSelectorLongJump: + # restore rsp, it might not have been 16-byte aligned on entry + mov rsp, rdx + ret +.att_syntax prefix + + .previous +.code64 +#else .previous .code32 +#endif diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index db72695..3eb7b94 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -10,6 +10,7 @@ #include <device/device.h> #include <smp/spinlock.h> +#ifndef __x86_64__ /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -78,6 +79,7 @@ static int deep_magic_nexgen_probe(void) : "=a" (ret) : : "cx", "dx" ); return ret; } +#endif /* List of cpu vendor strings along with their normalized * id values. @@ -131,6 +133,7 @@ static void identify_cpu(struct device *cpu) vendor_name[0] = '\0'; /* Unset */ +#ifndef __x86_64__ /* Find the id and vendor_name */ if (!cpu_have_cpuid()) { /* Its a 486 if we can modify the AC flag */ @@ -148,6 +151,7 @@ static void identify_cpu(struct device *cpu) memcpy(vendor_name, "NexGenDriven", 13); } } +#endif if (cpu_have_cpuid()) { int cpuid_level; struct cpuid_result result; diff --git a/src/arch/x86/lib/cpu_common.c b/src/arch/x86/lib/cpu_common.c index 6c5561d..af0ab2a 100644 --- a/src/arch/x86/lib/cpu_common.c +++ b/src/arch/x86/lib/cpu_common.c @@ -10,6 +10,7 @@ #include <device/device.h> #include <smp/spinlock.h> +#ifndef __x86_64__ /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -37,6 +38,14 @@ int cpu_have_cpuid(void) return flag_is_changeable_p(X86_EFLAGS_ID); } +#else + +int cpu_have_cpuid(void) +{ + return 1; +} +#endif + int cpu_cpuid_extended_level(void) { return cpuid_eax(0x80000000); diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c index 6089578..47dfbdb 100644 --- a/src/arch/x86/lib/ebda.c +++ b/src/arch/x86/lib/ebda.c @@ -40,8 +40,8 @@ void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) write16(X86_EBDA_SEGMENT, ebda_segment); /* Set up EBDA */ - memset((void *)(ebda_segment << 4), 0, ebda_size); - write16((void*)(ebda_segment << 4), (ebda_size >> 10)); + memset((void *)((uintptr_t)ebda_segment << 4), 0, ebda_size); + write16((void*)((uintptr_t)ebda_segment << 4), (ebda_size >> 10)); } void setup_default_ebda(void) diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c index f64b2e7..65181e2 100644 --- a/src/arch/x86/lib/exception.c +++ b/src/arch/x86/lib/exception.c @@ -494,16 +494,16 @@ void x86_exception(struct eregs *info) info->error_code, info->eflags, info->eax, info->ebx, info->ecx, info->edx, info->edi, info->esi, info->ebp, info->esp); - u8 *code = (u8*)((u32)info->eip - (MDUMP_SIZE >>1)); + u8 *code = (u8*)((uintptr_t)info->eip - (MDUMP_SIZE >>1)); /* Align to 8-byte boundary please, and print eight bytes per row. * This is done to make DRAM burst timing/reordering errors more * evident from the looking at the dump */ - code = (u8*)((u32)code & ~0x7); + code = (u8*)((uintptr_t)code & ~0x7); int i; for(i = 0; i < MDUMP_SIZE; i++) { if( (i & 0x07) == 0 ) - printk(BIOS_EMERG, "\n%.8x:\t", (int)code + i ); + printk(BIOS_EMERG, "\n%p:\t", code + i); printk(BIOS_EMERG, "%.2x ", code[i]); } die(""); diff --git a/src/arch/x86/lib/pci_ops_mmconf.c b/src/arch/x86/lib/pci_ops_mmconf.c index 4853f6b..e4fa128 100644 --- a/src/arch/x86/lib/pci_ops_mmconf.c +++ b/src/arch/x86/lib/pci_ops_mmconf.c @@ -10,7 +10,7 @@ */ #define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK) \ - ((void *)((CONFIG_MMCONF_BASE_ADDRESS |\ + ((void *)(((uintptr_t)CONFIG_MMCONF_BASE_ADDRESS |\ (((SEGBUS) & 0xFFF) << 20) |\ (((DEVFN) & 0xFF) << 12) |\ ((WHERE) & 0xFFF)) & ~MASK))

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Patch set updated for coreboot: device: Use x86 specific code on x86-64
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10584 -gerrit commit e1e1d124059e0279332d0b0f502429c94cb91500 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:19:14 2015 -0700 device: Use x86 specific code on x86-64 Change-Id: I4763ce32bb0b0e301401daaeb89440524fcc682e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/device/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 3918115..1e19a7c 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -10,6 +10,7 @@ ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c +ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-$(CONFIG_PCI) += pci_early.c ramstage-y += smbus_ops.c

1 0

Patch set updated for coreboot: prog_loader: Play nice with gc-sections
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10585 -gerrit commit 0f0d3214a5f4e98b65ea988d386ec5cc11dcc5dd Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:19:50 2015 -0700 prog_loader: Play nice with gc-sections This is the wrong fix I'm sure, but it got me a bit further Change-Id: I75518149b53c24eda4b985b0fef856447e196dec Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/lib/prog_loaders.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ec5eeb8..7c00aba 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -121,6 +121,8 @@ fail: die("Ramstage was not loaded!\n"); } +#ifdef __RAMSTAGE__ // gc-sections should take care of this + static struct prog global_payload = PROG_INIT(ASSET_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); @@ -170,3 +172,5 @@ void payload_run(void) prog_run(payload); } + +#endif

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Patch set updated for coreboot: x86: Move architecture selection from linker script to Makefile.inc
by Stefan Reinauer 19 Jun '15

19 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10590 -gerrit commit 22bac4291f2fe5717e1dbd71ae9c8dfc9a7b99a9 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 21:59:34 2015 -0700 x86: Move architecture selection from linker script to Makefile.inc Change-Id: I5efd3cb3e6970b5740f740507244a1ab823e0bb6 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/Makefile.inc | 14 ++++++++++---- src/arch/x86/init/failover.ld | 4 ---- src/arch/x86/init/romstage.ld | 4 ---- 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7e10acb..f4c5dda 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -126,9 +126,9 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOC $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) - $(LD_bootblock) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld + $(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld else - $(LD_bootblock) -m elf_x86_64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld + $(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld endif @@ -201,9 +201,15 @@ romstage-srcs += $(objgenerated)/crt0.S romstage-libs ?= +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +romstage-oformat=elf32-i386 +else +romstage-oformat=elf64-x86-64 +endif + $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld + $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat) $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders && \ $(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \ echo "Forbidden global variables in romstage:"; \ @@ -212,7 +218,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null. $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld + $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) $(objgenerated)/romstage_null.ld: $(obj)/config.h $$(filter %.ld,$$(romstage-srcs)) @printf " GEN $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/init/failover.ld b/src/arch/x86/init/failover.ld index 5e4efa9..d7aa47e 100644 --- a/src/arch/x86/init/failover.ld +++ b/src/arch/x86/init/failover.ld @@ -18,10 +18,6 @@ * Foundation, Inc. */ -/* We use ELF as output format. So that we can debug the code in some form. */ -OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") -OUTPUT_ARCH(i386) - MEMORY { rom : ORIGIN = 0xffff0000, LENGTH = 64K } diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 74e665f..7b9cb6a 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -18,10 +18,6 @@ * Foundation, Inc. */ -/* We use ELF as output format. So that we can debug the code in some form. */ -OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") -OUTPUT_ARCH(i386) - TARGET(binary) SECTIONS {

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coreboot-gerrit June 2015