coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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1226 discussions

New patch to review for coreboot: AMD/Hudson Makefile: Fill the ROMSIG with 0xFF instead of 0
by Zheng Bao 24 Jun '15

24 Jun '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10651 -gerrit commit 770f7664a013c2db9c753ea902e50a0e20b258b8 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Jun 17 18:51:42 2015 -0400 AMD/Hudson Makefile: Fill the ROMSIG with 0xFF instead of 0 Besides the first five DWORDs are used in ROMSIG, the offset 0x40 & 0x41 are used to save SPI settings. They should only be 0xFF for being written. Other parts in ROMSIG are also changed to 0xFF for potential requirement. Change-Id: I61ea8295d5ee8ffbbd0cfcf9e4bece770d70e1f2 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index ccca421..235ce1e 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -116,7 +116,7 @@ $(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ $(obj)/config.h echo " Hudson FW $@" - dd if=/dev/zero of=$@ count=$(ROMSIG_SIZE) ibs=1 status=noxfer 2>/dev/null; \ + printf %d $(ROMSIG_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@; \ for fwm in 1437226410 \ $(HUDSON_IMC_POSITION) \ $(HUDSON_GEC_POSITION) \

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Patch merged into coreboot/master: pcengines/apu1: Remove unused ide.asl
by gerrit＠coreboot.org 24 Jun '15

24 Jun '15

the following patch was just integrated into master: commit 1f7f4d49a192d5d516be4a72f45416febcc0d489 Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Date: Sun Jun 21 21:02:59 2015 +0200 pcengines/apu1: Remove unused ide.asl The APU1 board has no IDE port, remove ide.asl. Change-Id: I76b926969748de79ac1281ed50b37e9ade1a6771 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Reviewed-on: http://review.coreboot.org/10622 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/10622 for details. -gerrit

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Patch merged into coreboot/master: Remove address from GPLv2 headers
by gerrit＠coreboot.org 24 Jun '15

24 Jun '15

the following patch was just integrated into master: commit ba71ca3315726d112507242781c306749faeb44c Author: Patrick Georgi <pgeorgi(a)google.com> Date: Thu Mar 26 15:17:45 2015 +0100 Remove address from GPLv2 headers Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: Icf83d5e2a3daea385af3572e9eac6b2431652c28 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10640 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/10640 for details. -gerrit

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Patch set updated for coreboot: smbios: Calculate SMBIOS Max Struct size
by Ben Frisch 24 Jun '15

24 Jun '15

Ben Frisch (bfrisch(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10163 -gerrit commit d2561d45b6bcce19f07fd00190234da90eb2d7c7 Author: Ben Frisch <bfrisch(a)gmail.com> Date: Sat May 9 19:52:18 2015 -0500 smbios: Calculate SMBIOS Max Struct size The SMBIOS Specification 2.3 and up defines Maximum Structure Size as the "Size of the largest SMBIOS structure, in bytes, and encompasses the structure’s formatted area and text strings." The hardcoded size is too small to accurately represent the maximum SMBIOS structure sizes. While the field is not used by Linux it is used by some RTOS implementations, eg. VxWorks. TEST=Booted Linux and ran github.com/bfrisch/dmidecode which verified the maximum structure size on Minnowboard Max. Change-Id: I98087975c53a02857742dea283f4e303485b2ffe Signed-off-by: Ben Frisch <bfrisch(a)gmail.com> --- src/arch/x86/boot/smbios.c | 28 +++++++++++++++------------- src/include/smbios.h | 2 ++ 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 1dbe32d..2f7cc5a 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -533,7 +533,9 @@ unsigned long smbios_write_tables(unsigned long current) { struct smbios_entry *se; unsigned long tables; - int len, handle = 0; + int len = 0; + int max_struct_size = 0; + int handle = 0; current = ALIGN(current, 16); printk(BIOS_DEBUG, "%s: %08lx\n", __func__, current); @@ -543,28 +545,28 @@ unsigned long smbios_write_tables(unsigned long current) current = ALIGN(current, 16); tables = current; - len = smbios_write_type0(&current, handle++); - len += smbios_write_type1(&current, handle++); - len += smbios_write_type2(&current, handle++); - len += smbios_write_type3(&current, handle++); - len += smbios_write_type4(&current, handle++); - len += smbios_write_type11(&current, &handle); + update_max(len, max_struct_size, smbios_write_type0(&current, handle++)); + update_max(len, max_struct_size, smbios_write_type1(&current, handle++)); + update_max(len, max_struct_size, smbios_write_type2(&current, handle++)); + update_max(len, max_struct_size, smbios_write_type3(&current, handle++)); + update_max(len, max_struct_size, smbios_write_type4(&current, handle++)); + update_max(len, max_struct_size, smbios_write_type11(&current, &handle)); #if CONFIG_ELOG - len += elog_smbios_write_type15(&current, handle++); + update_max(len, max_struct_size, smbios_write_type15(&current, &handle)); #endif - len += smbios_write_type17(&current, &handle); - len += smbios_write_type32(&current, handle++); + update_max(len, max_struct_size, smbios_write_type17(&current, &handle)); + update_max(len, max_struct_size, smbios_write_type32(&current, handle++)); - len += smbios_walk_device_tree(all_devices, &handle, &current); + update_max(len, max_struct_size, smbios_walk_device_tree(all_devices, &handle, &current)); - len += smbios_write_type127(&current, handle++); + update_max(len, max_struct_size, smbios_write_type127(&current, handle++)); memset(se, 0, sizeof(struct smbios_entry)); memcpy(se->anchor, "_SM_", 4); se->length = sizeof(struct smbios_entry); se->major_version = 2; se->minor_version = 7; - se->max_struct_size = 24; + se->max_struct_size = max_struct_size; se->struct_count = handle; memcpy(se->intermediate_anchor_string, "_DMI_", 5); diff --git a/src/include/smbios.h b/src/include/smbios.h index 66d2b2f..b37f131 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -44,6 +44,8 @@ u8 smbios_mainboard_enclosure_type(void); const char *smbios_mainboard_family(void); #endif +#define update_max(len, max_len, stmt) do { int tmp = stmt; max_len = MAX(max_len, tmp); len += tmp; } while(0) + #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) #define BIOS_CHARACTERISTICS_PNP (1 << 9)

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Patch merged into coreboot/master: crossgcc/Makefile: Allow making toolchains using multiple cores
by gerrit＠coreboot.org 24 Jun '15

24 Jun '15

the following patch was just integrated into master: commit 3950966e327c8420e6dffa2efcd9181bd7bc3527 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jun 21 12:38:42 2015 -0600 crossgcc/Makefile: Allow making toolchains using multiple cores I looked for a way to pass the 'make crossgcc -j8' on to buildgcc, but didn't find a way to get that value directly. MAKEFLAGS turns -j8 into a jobserver variable. Instead, this patch allows the number of CPUs to be set on the command line through a variable instead. Example: 'make crossgcc BUILDJOBS=8' Change-Id: I37608cdb4549226cb7ff8c3ff6d9f4773acf6b0b Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10620 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10620 for details. -gerrit

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Patch set updated for coreboot: crossgcc/Makefile: Allow making toolchains using multiple cores
by Martin Roth 24 Jun '15

24 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10620 -gerrit commit ccff7506aaed37531a100fb6bd34bd67e2b183be Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jun 21 12:38:42 2015 -0600 crossgcc/Makefile: Allow making toolchains using multiple cores I looked for a way to pass the 'make crossgcc -j8' on to buildgcc, but didn't find a way to get that value directly. MAKEFLAGS turns -j8 into a jobserver variable. Instead, this patch allows the number of CPUs to be set on the command line through a variable instead. Example: 'make crossgcc BUILDJOBS=8' Change-Id: I37608cdb4549226cb7ff8c3ff6d9f4773acf6b0b Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- util/crossgcc/Makefile | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index d0ab28a..4b731d3 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -1,46 +1,46 @@ all: build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv build-i386: - bash ./buildgcc -G -p i386-elf + bash ./buildgcc -G -p i386-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) build-x64: - bash ./buildgcc -G -p x86_64-elf + bash ./buildgcc -G -p x86_64-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) build-armv7a: - bash ./buildgcc -G -p armv7a-eabi + bash ./buildgcc -G -p armv7a-eabi $(if $(BUILDJOBS),-j $(BUILDJOBS)) build-aarch64: - bash ./buildgcc -G -p aarch64-elf + bash ./buildgcc -G -p aarch64-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) build-mips: - bash ./buildgcc -G -p mipsel-elf + bash ./buildgcc -G -p mipsel-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) build-riscv: - bash ./buildgcc -G -p riscv-elf + bash ./buildgcc -G -p riscv-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) .PHONY: build-i386-without-gdb build-i386-without-gdb: - bash ./buildgcc -p i386-elf + bash ./buildgcc -p i386-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) .PHONY: build-x64-without-gdb build-x64-without-gdb: - bash ./buildgcc -p x86_64-elf + bash ./buildgcc -p x86_64-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) .PHONY: build-armv7a-without-gdb build-armv7a-without-gdb: - bash ./buildgcc -p armv7a-eabi + bash ./buildgcc -p armv7a-eabi $(if $(BUILDJOBS),-j $(BUILDJOBS)) .PHONY: build-aarch64-without-gdb build-aarch64-without-gdb: - bash ./buildgcc -p aarch64-elf + bash ./buildgcc -p aarch64-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) .PHONY: build-mips-without-gdb build-mips-without-gdb: - bash ./buildgcc -p mipsel-elf + bash ./buildgcc -p mipsel-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) .PHONY: build-riscv-without-gdb build-riscv-without-gdb: - bash ./buildgcc -p riscv-elf + bash ./buildgcc -p riscv-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) clean: rm -rf xgcc

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Patch merged into coreboot/master: crossgcc/Makefile: clean more, add distclean target
by gerrit＠coreboot.org 24 Jun '15

24 Jun '15

the following patch was just integrated into master: commit 32c965170512a62659f54fe46d53117a847f97f3 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jun 21 13:05:03 2015 -0600 crossgcc/Makefile: clean more, add distclean target Update the clean target to remove the intermediate files. These should get removed automatically, but if the build stops in the middle, or if the -t command is used for buildgcc, they can be left in the directory. Add a distclean target that removes the downloaded tarballs as well as everything else. Change-Id: I6ea19e7a499b0c313c1d2eff7e36386204ec834e Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10621 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10621 for details. -gerrit

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Patch merged into coreboot/master: Kconfig: Get rid of obsolete symbols
by gerrit＠coreboot.org 24 Jun '15

24 Jun '15

the following patch was just integrated into master: commit c4dd3e02121f113483acb983899f8cdea3998e19 Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 20 16:40:28 2015 -0600 Kconfig: Get rid of obsolete symbols CAR_MIGRATION was removed in commit: cbf5bdfe - CBMEM: Always select CAR_MIGRATION ALT_CBFS_LOAD_PAYLOAD was removed in commit: cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD MARK_GRAPHICS_MEM_WRCOMB was removed in commit: 30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB. EXTERNAL_MRC_BLOB was removed in commit: 0aede118 - Drop unused EXTERNAL_MRC_BLOB CACHE_ROM is only in Google's codebase. LID_SWITCH is only in Google's codebase. DEFAULT_POST_DEVICE_LPC is only in Sage's codebase. ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used. HUDSON_NOT_LEGACY_FREE never existed as far as I can tell. MAINBOARD_DO_EDID never existed as far as I can tell. Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10616 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10616 for details. -gerrit

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Patch set updated for coreboot: Kconfig: Get rid of obsolete symbols
by Martin Roth 24 Jun '15

24 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10616 -gerrit commit 52388eef5d09a29c7d6aade4677659491df2bf39 Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 20 16:40:28 2015 -0600 Kconfig: Get rid of obsolete symbols CAR_MIGRATION was removed in commit: cbf5bdfe - CBMEM: Always select CAR_MIGRATION ALT_CBFS_LOAD_PAYLOAD was removed in commit: cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD MARK_GRAPHICS_MEM_WRCOMB was removed in commit: 30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB. EXTERNAL_MRC_BLOB was removed in commit: 0aede118 - Drop unused EXTERNAL_MRC_BLOB CACHE_ROM is only in Google's codebase. LID_SWITCH is only in Google's codebase. DEFAULT_POST_DEVICE_LPC is only in Sage's codebase. ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used. HUDSON_NOT_LEGACY_FREE never existed as far as I can tell. MAINBOARD_DO_EDID never existed as far as I can tell. Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/mainboard/apple/macbook21/Kconfig | 1 - src/mainboard/asus/f2a85-m_le/Kconfig | 1 - src/mainboard/google/auron/Kconfig | 4 ---- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/jecht/Kconfig | 1 - src/mainboard/google/panther/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/samus/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/mohonpeak/Kconfig | 1 - src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 3 --- src/soc/intel/fsp_baytrail/Kconfig | 1 - 15 files changed, 20 deletions(-) diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 7ad3f93..e653c08 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select VGA - select MAINBOARD_DO_EDID select INTEL_EDID config MAINBOARD_DIR diff --git a/src/mainboard/asus/f2a85-m_le/Kconfig b/src/mainboard/asus/f2a85-m_le/Kconfig index 3172760..9476b0c 100644 --- a/src/mainboard/asus/f2a85-m_le/Kconfig +++ b/src/mainboard/asus/f2a85-m_le/Kconfig @@ -33,7 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select GFXUMA select HUDSON_DISABLE_IMC - select HUDSON_NOT_LEGACY_FREE choice prompt "DDR3 memory voltage" diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 779e6b3..740afe1 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -14,12 +14,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB - select CACHE_ROM - select MARK_GRAPHICS_MEM_WRCOMB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 - select LID_SWITCH select CHROMEOS_VBNV_CMOS config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 74e1edd..17ec406 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index 5b97259..1234044 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_INT15 diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index fbf61de..ad54b16 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 37a8548..6fb6c5f 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select INTEL_INT15 select PHYSICAL_REC_SWITCH select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 2c1560a..8c7d630 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_DP diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index 06317e9..68d622d 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index cfbce5e..a2dd3d0 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select EXTERNAL_MRC_BLOB select INTEL_DP select INTEL_DDI select INTEL_INT15 diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 2aaa766..f487e2b 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select MMCONF_SUPPORT select POST_IO - select DEFAULT_POST_DEVICE_LPC select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT config MAINBOARD_DIR diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5060e45..cbf4a1f 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS - select CAR_MIGRATION select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index aa191b3..a7bc046 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS - select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 1ef386b..c9600ea 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -11,15 +11,12 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select ALT_CBFS_LOAD_PAYLOAD select ALWAYS_LOAD_OPROM select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_BIN select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM - select CACHE_ROM - select CAR_MIGRATION select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_MONOTONIC_TIMER diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 371ad52..1ad5891 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -47,7 +47,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS - select ROMSTAGE_RTC_INIT config SOC_INTEL_FSP_BAYTRAIL_MD bool

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New patch to review for coreboot: Intel FSP 1.1: Move Kconfig comment inside 'if' block
by Martin Roth 24 Jun '15

24 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10650 -gerrit commit ef26a9051b9fabcff14555f0cea33fe94b1eb78d Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jun 23 21:58:32 2015 -0600 Intel FSP 1.1: Move Kconfig comment inside 'if' block - Move the 'Intel FSP' Kconfig comment inside the 'if' block so that it doesn't show up on platforms that aren't using it. - Update the comment to reflect that this is version 1.1 of the FSP interface. Change-Id: I7182c5b07332c4f95620f7374526ab1de0484d01 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/intel/fsp1_1/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index f722e65..91f325d 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -17,8 +17,6 @@ ## Foundation, Inc. ## -comment "Intel FSP" - config PLATFORM_USES_FSP1_1 bool help @@ -26,6 +24,8 @@ config PLATFORM_USES_FSP1_1 if PLATFORM_USES_FSP1_1 +comment "Intel FSP 1.1" + config DCACHE_RAM_BASE hex default 0xfef00000

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coreboot-gerrit June 2015