coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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1226 discussions

Patch merged into coreboot/master: amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0
by gerrit＠coreboot.org 25 Jun '15

25 Jun '15

the following patch was just integrated into master: commit 3ad1f1ca5fb35d698359c88baaa57939a258639a Author: zbao <fishbaozi(a)gmail.com> Date: Wed Jun 17 20:03:29 2015 -0400 amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0 Besides the first five DWORDs, the offsets 0x40 & 0x41 are used to save SPI settings. They should only be 0xFF for being written. Other parts in ROMSIG are also changed to 0xFF for potential requirement. Change-Id: I61ea8295d5ee8ffbbd0cfcf9e4bece770d70e1f2 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/10651 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10651 for details. -gerrit

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New patch to review for coreboot: SeaBIOS: Change clean to just 'rm -rf seabios/out'
by Martin Roth 25 Jun '15

25 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10655 -gerrit commit 0b47087b67d00c725cd210b59ae0df83ce05ed53 Author: Martin Roth <gaumless(a)gmail.com> Date: Wed Jun 24 19:43:17 2015 -0600 SeaBIOS: Change clean to just 'rm -rf seabios/out' When running 'make clean' if the seabios directory is present, we get warnings about not having IASL installed or that the C compiler can't be executed. It fails to actually run the clean because we're not correctly passing in the toolchain. Just do what the SeaBIOS clean does directly and delete the 'out' directory without actually calling the SeaBIOS clean. Here were the previous warnings: % make clean Unable to execute the C compiler (). Please install a working compiler and retry. Makefile:104: *** "Please upgrade the build environment". Stop. or % make clean The SeaBIOS project requires the 'iasl' package be installed. Many Linux distributions have this package. Try: sudo yum install iasl Or: sudo apt-get install iasl Please install iasl and retry. Makefile:106: *** "Please upgrade the build environment". Stop. Change-Id: Ice41376bc242f1f622d849e7628f8a9b6ef47404 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 087b723..7fb63d4 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -53,7 +53,7 @@ build: config $(MAKE) -C seabios OUT=out/ clean: - test -d seabios && $(MAKE) -C seabios clean OUT=out/ || exit 0 + test -d seabios/out && rm -rf seabios/out || exit 0 distclean: rm -rf seabios

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New patch to review for coreboot: soc/intel/common/Kconfig: Fix warning & whitespace
by Martin Roth 25 Jun '15

25 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10654 -gerrit commit 4dcb1e1769f8fd81b9f4391da33a64e615d8c673 Author: Martin Roth <gaumless(a)gmail.com> Date: Wed Jun 24 19:04:16 2015 -0600 soc/intel/common/Kconfig: Fix warning & whitespace Because of a missing close quote, we have the warning: src/soc/intel/common/Kconfig:52:warning:multi-line strings not supported This was added in commit 0946ec37 -Intel Common SOC:Add romstage support The whitespace issue - using spaces instead of a leading tab was added in the same commit. Change-Id: I429c66afb5a7e10ca0e0ef619ac46722c63fb376 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/soc/intel/common/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 7b88d55..75e585d 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -40,7 +40,7 @@ config CHIPSET_RESERVED_MEM_BYTES hex "Size in bytes of chipset reserved memory area" default 0 help - If insufficient documentation is available to determine the size of + If insufficient documentation is available to determine the size of the chipset reserved memory area by walking the chipset registers, the CHIPSET_RESERVED_MEM_BYTES may be used as a workaround to account for the missing pieces of memory. The value specified in bytes is: @@ -49,7 +49,7 @@ config CHIPSET_RESERVED_MEM_BYTES by reading chipset registers) config DISPLAY_MTRRS - bool "MTRRs: Display the MTRR settings + bool "MTRRs: Display the MTRR settings" default n config DISPLAY_SMM_MEMORY_MAP

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Patch merged into coreboot/master: Intel FSP 1.1: Move Kconfig comment inside 'if' block
by gerrit＠coreboot.org 25 Jun '15

25 Jun '15

the following patch was just integrated into master: commit 128043edeea673f87c8a5d6dbcaf9f728d6c0869 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jun 23 21:58:32 2015 -0600 Intel FSP 1.1: Move Kconfig comment inside 'if' block - Move the 'Intel FSP' Kconfig comment inside the 'if' block so that it doesn't show up on platforms that aren't using it. - Update the comment to reflect that this is version 1.1 of the FSP interface. Change-Id: I7182c5b07332c4f95620f7374526ab1de0484d01 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10650 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> See http://review.coreboot.org/10650 for details. -gerrit

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New patch to review for coreboot: soc/intel/common: Restrict common romstage/ramstage code to FSP
by Leroy P Leahy 24 Jun '15

24 Jun '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10653 -gerrit commit ec43ed773711cf83816770bbc0455b1109d8b56f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jun 24 11:17:54 2015 -0700 soc/intel/common: Restrict common romstage/ramstage code to FSP Restrict the use of the common romstage/ramstage code to FSP 1.1 BRANCH=none BUG=None TEST=Build and run on cyan/sklrvp Change-Id: Ifbdb6b4c201560a97617e83d69bf9974f9411994 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/common/Kconfig | 4 ++++ src/soc/intel/common/romstage.c | 30 ++++++++---------------------- src/soc/intel/common/romstage.h | 6 ------ 3 files changed, 12 insertions(+), 28 deletions(-) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 7b88d55..2e930f4 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -73,18 +73,22 @@ config SOC_INTEL_COMMON_FSP_RAM_INIT config SOC_INTEL_COMMON_FSP_ROMSTAGE bool default n + depends on PLATFORM_USES_FSP1_1 config SOC_INTEL_COMMON_RESET bool default n + depends on PLATFORM_USES_FSP1_1 config SOC_INTEL_COMMON_STACK bool default n + depends on PLATFORM_USES_FSP1_1 config SOC_INTEL_COMMON_STAGE_CACHE bool default n + depends on PLATFORM_USES_FSP1_1 config ROMSTAGE_RAM_STACK_SIZE hex "Size of the romstage RAM stack in bytes" diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c index 4f449ed..919de83 100644 --- a/src/soc/intel/common/romstage.c +++ b/src/soc/intel/common/romstage.c @@ -85,10 +85,8 @@ asmlinkage void *romstage_main(unsigned int bist, "No Memory Support")); /* Display FSP banner */ - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { - printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); - print_fsp_info(params.chipset_context); - } + printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); + print_fsp_info(params.chipset_context); /* Get power state */ params.power_state = fill_power_state(); @@ -109,10 +107,8 @@ asmlinkage void *romstage_main(unsigned int bist, top_of_stack = setup_stack_and_mtrrs(); - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { - printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); - timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); - } + printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); + timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); return top_of_stack; } @@ -197,12 +193,10 @@ void romstage_common(struct romstage_params *params) asmlinkage void romstage_after_car(void *chipset_context) { - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { - timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END); - printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n"); - soc_after_temp_ram_exit(); - soc_display_mtrrs(); - } + timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END); + printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n"); + soc_after_temp_ram_exit(); + soc_display_mtrrs(); timestamp_add_now(TS_END_ROMSTAGE); @@ -253,7 +247,6 @@ __attribute__((weak)) void mainboard_romstage_entry( } /* Save the DIMM information for SMBIOS table 17 */ -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) __attribute__((weak)) void mainboard_save_dimm_info( struct romstage_params *params) { @@ -348,13 +341,6 @@ __attribute__((weak)) void mainboard_save_dimm_info( mem_info->dimm_cnt = index; printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -#else /* CONFIG_PLATFORM_USES_FSP1_1 */ -__attribute__((weak)) void mainboard_save_dimm_info( - struct romstage_params *params) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} -#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ /* Get the memory configuration data */ __attribute__((weak)) int mrc_cache_get_current( diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h index 81f32bc..c677095 100644 --- a/src/soc/intel/common/romstage.h +++ b/src/soc/intel/common/romstage.h @@ -23,9 +23,7 @@ #include <stdint.h> #include <arch/cpu.h> -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp_util.h> -#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ #include <soc/intel/common/util.h> #include <soc/pei_data.h> #include <soc/pm.h> /* chip_power_state */ @@ -73,10 +71,8 @@ struct romstage_params { */ void mainboard_check_ec_image(struct romstage_params *params); -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params); -#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ void mainboard_pre_console_init(struct romstage_params *params); void mainboard_romstage_entry(struct romstage_params *params); void mainboard_save_dimm_info(struct romstage_params *params); @@ -91,11 +87,9 @@ void *setup_stack_and_mtrrs(void); void set_max_freq(void); void soc_after_ram_init(struct romstage_params *params); void soc_after_temp_ram_exit(void); -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new); void soc_memory_init_params(MEMORY_INIT_UPD *params); -#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ void soc_pre_console_init(struct romstage_params *params); void soc_pre_ram_init(struct romstage_params *params); void soc_romstage_init(struct romstage_params *params);

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Patch set updated for coreboot: mainboard/intel/strago: Intel Braswell RVP support
by Leroy P Leahy 24 Jun '15

24 Jun '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10052 -gerrit commit 307711b94a70745b1819f747d7afcf32746c1e01 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri May 1 10:34:54 2015 -0700 mainboard/intel/strago: Intel Braswell RVP support Initial files to support the Intel RVP for Braswell BRANCH=none BUG=None TEST=Build and run on strago Change-Id: I5cb2efe3d8adf919165c62b25e08c544b316a05a Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/strago/Kconfig | 71 +++++ src/mainboard/intel/strago/Kconfig.name | 2 + src/mainboard/intel/strago/Makefile.inc | 35 +++ src/mainboard/intel/strago/acpi/chromeos.asl | 37 +++ src/mainboard/intel/strago/acpi/dptf.asl | 93 +++++++ src/mainboard/intel/strago/acpi/ec.asl | 25 ++ src/mainboard/intel/strago/acpi/mainboard.asl | 286 +++++++++++++++++++++ src/mainboard/intel/strago/acpi/superio.asl | 34 +++ src/mainboard/intel/strago/acpi_tables.c | 66 +++++ src/mainboard/intel/strago/boardid.c | 35 +++ src/mainboard/intel/strago/chromeos.c | 132 ++++++++++ src/mainboard/intel/strago/cmos.layout | 140 ++++++++++ src/mainboard/intel/strago/com_init.c | 57 ++++ src/mainboard/intel/strago/devicetree.cb | 142 ++++++++++ src/mainboard/intel/strago/dsdt.asl | 57 ++++ src/mainboard/intel/strago/ec.c | 59 +++++ src/mainboard/intel/strago/ec.h | 69 +++++ src/mainboard/intel/strago/fadt.c | 51 ++++ src/mainboard/intel/strago/gpio.c | 273 ++++++++++++++++++++ src/mainboard/intel/strago/gpio.h | 24 ++ src/mainboard/intel/strago/gpio_dvt.c | 273 ++++++++++++++++++++ src/mainboard/intel/strago/irqroute.c | 23 ++ src/mainboard/intel/strago/irqroute.h | 64 +++++ src/mainboard/intel/strago/mainboard.c | 44 ++++ src/mainboard/intel/strago/onboard.h | 94 +++++++ src/mainboard/intel/strago/ramstage.c | 26 ++ src/mainboard/intel/strago/romstage.c | 47 ++++ src/mainboard/intel/strago/smihandler.c | 166 ++++++++++++ src/mainboard/intel/strago/spd/Makefile.inc | 42 +++ .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 +++ ...nix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 32 +++ .../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 32 +++ src/mainboard/intel/strago/spd/spd.c | 120 +++++++++ src/mainboard/intel/strago/w25q64.c | 75 ++++++ 34 files changed, 2758 insertions(+) diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig new file mode 100755 index 0000000..67d4f76 --- /dev/null +++ b/src/mainboard/intel/strago/Kconfig @@ -0,0 +1,71 @@ +if BOARD_INTEL_STRAGO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ALWAYS_LOAD_OPROM + select BOARD_ROMSIZE_KB_8192 + select CHROMEOS + select CHROMEOS_VBNV_CMOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_MEC + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP + select EC_SOFTWARE_SYNC + select ENABLE_BUILTIN_COM1 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select LID_SWITCH + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM + select SOC_INTEL_BRASWELL + select VBOOT_DYNAMIC_WORK_BUFFER + select VIRTUAL_DEV_SWITCH + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory configuration data. + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory SPD data. + +config DYNAMIC_VNN_SUPPORT + bool "Enables support for Dynamic VNN" + default n + +config MAINBOARD_DIR + string + default intel/strago + +config MAINBOARD_PART_NUMBER + string + default "Strago" + +config MAINBOARD_VENDOR + string + default "Intel" + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config VBOOT_REFCODE_INDEX + hex + default 0x3 + +if !CONFIG_GOP_SUPPORT +config VGA_BIOS_FILE + string + default "3rdparty/blobs/mainboard/intel/strago/vgabios_c0.bin" if C0_DISP_SUPPORT + default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" if !C0_DISP_SUPPORT +config VGA_BIOS_ID + string + default "8086,22b1" if C0_DISP_SUPPORT + default "8086,22b0" if !C0_DISP_SUPPORT +endif + +endif # BOARD_INTEL_STRAGO diff --git a/src/mainboard/intel/strago/Kconfig.name b/src/mainboard/intel/strago/Kconfig.name new file mode 100644 index 0000000..aae2379 --- /dev/null +++ b/src/mainboard/intel/strago/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_STRAGO + bool "Strago" diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc new file mode 100755 index 0000000..db5189b --- /dev/null +++ b/src/mainboard/intel/strago/Makefile.inc @@ -0,0 +1,35 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += spd + +romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c + +ramstage-y += boardid.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio_dvt.c +ramstage-y += irqroute.c +ramstage-y += ramstage.c +ramstage-y += w25q64.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/intel/strago/acpi/chromeos.asl b/src/mainboard/intel/strago/acpi/chromeos.asl new file mode 100644 index 0000000..7db294d --- /dev/null +++ b/src/mainboard/intel/strago/acpi/chromeos.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Fields are in the following order. + * - Type: recovery = 1 developer mode = 2 write protect = 3 + * - Active Level - if -1 not a valid gpio + * - GPIO number encoding - if -1 not a valid gpio + * - Chipset Name + * + * Note: We need to encode gpios within the 4 separate banks + * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded + * as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. + */ + +Name(OIPG, Package() { + /* No physical recovery button */ + Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, + Package () { 0x0003, 1, 0x10016, "Braswell" }, +}) diff --git a/src/mainboard/intel/strago/acpi/dptf.asl b/src/mainboard/intel/strago/acpi/dptf.asl new file mode 100755 index 0000000..4b85449 --- /dev/null +++ b/src/mainboard/intel/strago/acpi/dptf.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 6200, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <acpi/dptf/dptf.asl> diff --git a/src/mainboard/intel/strago/acpi/ec.asl b/src/mainboard/intel/strago/acpi/ec.asl new file mode 100755 index 0000000..baa0d56 --- /dev/null +++ b/src/mainboard/intel/strago/acpi/ec.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include "ec.h" + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl new file mode 100755 index 0000000..f99781f --- /dev/null +++ b/src/mainboard/intel/strago/acpi/mainboard.asl @@ -0,0 +1,286 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "onboard.h" + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} +Scope (\_SB.I2C1) +{ + Device (ATSB) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen Bootloader") + Name (_UID, 4) + Name (ISTP, 0) /* TouchScreen */ + + Method(_CRS, 0x0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + I2cSerialBus( + 0x26, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C1", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { BOARD_TOUCH_GPIO_INDEX } + }) + Name (BUF1, ResourceTemplate () + { + I2cSerialBus( + 0x26, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C1", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { BOARD_DVT_TOUCH_GPIO_INDEX } + }) + If (LEqual (\BDID, BOARD_DVT)) { + Return (BUF1) + } Else { + Return (BUF0) + } + } + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } + + Device (ATSA) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x4b, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C1", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { BOARD_TOUCH_GPIO_INDEX } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.I2C2) +{ + /* Realtek Audio Codec */ + Device (RTEK) /* Audio Codec driver I2C */ + { + Name (_ADR, 0) + Name (_HID, AUDIO_CODEC_HID) + Name (_CID, AUDIO_CODEC_CID) + Name (_DDN, AUDIO_CODEC_DDN) + Name (_UID, 1) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX } + } ) + Return (SBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.I2C5) +{ + Device (ALSI) + { + /* + * TODO(dlaurie): Need official HID. + * + * The current HID is created from the Intersil PNP + * Vendor ID "LSD" and a shortened device identifier. + */ + Name (_HID, EisaId ("LSD2918")) + Name (_DDN, "Intersil 29018 Ambient Light Sensor") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x44, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C5", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_ALS_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.I2C6) +{ + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x15, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C6", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX } + }) +} + +Scope (\_SB.GPNC) +{ + Method (_AEI, 0, NotSerialized) // _AEI: ACPI Event Interrupts + { + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { BOARD_SCI_GPIO_INDEX } + }) + Return (RBUF) + } + + Method (_E0F, 0, NotSerialized) // _Exx: Edge-Triggered GPE + { + } +} diff --git a/src/mainboard/intel/strago/acpi/superio.asl b/src/mainboard/intel/strago/acpi/superio.asl new file mode 100755 index 0000000..2db1013 --- /dev/null +++ b/src/mainboard/intel/strago/acpi/superio.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include "ec.h" +#include "onboard.h" + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Override default IRQ settings */ +#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow){\ + BOARD_I8042_IRQ} + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c new file mode 100755 index 0000000..a88abed --- /dev/null +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <string.h> +#include <types.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* Enable DPTF */ + gnvs->dpte = 1; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/intel/strago/boardid.c b/src/mainboard/intel/strago/boardid.c new file mode 100644 index 0000000..9b0aa73 --- /dev/null +++ b/src/mainboard/intel/strago/boardid.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <boardid.h> +#include <stdlib.h> +#include "ec/google/chromeec/ec.h" + +uint8_t board_id(void) +{ + static int id = -1; + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (id < 0) + id = google_chromeec_get_board_version(); +#endif + return id; +} + diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c new file mode 100755 index 0000000..67e289c --- /dev/null +++ b/src/mainboard/intel/strago/chromeos.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#endif +#include <soc/gpio.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ +#define WP_STATUS_PAD 36 + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +static int get_lid_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u8 ec_switches; + + mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1, + &ec_switches, NULL); + + return !!(ec_switches & EC_SWITCH_LID_OPEN); +#else + /* Default to force open. */ + return 1; +#endif +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", + get_write_protect_state()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", + recovery_mode_enabled()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); +} +#endif /* ENV_RAMSTAGE */ + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u8 ec_switches; + u32 ec_events; + + mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1, + &ec_switches, NULL); + + /* If a switch is set, we don't need to look at events. */ + if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) + return 1; + + /* Else check if the EC has posted the keyboard recovery event. */ + ec_events = google_chromeec_get_events_b(); + + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +#else + return 0; +#endif +} + +int clear_recovery_mode_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + const uint32_t kb_rec_mask = + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY); + /* Unconditionally clear the EC recovery request. */ + return google_chromeec_clear_events_b(kb_rec_mask); +#else + return 0; +#endif +} + +int get_write_protect_state(void) +{ + /* + * The vboot loader queries this function in romstage. The GPIOs have + * not been set up yet as that configuration is done in ramstage. The + * hardware defaults to an input but there is a 20K pulldown. Externally + * there is a 10K pullup. Disable the internal pull in romstage so that + * there isn't any ambiguity in the reading. + */ +#if ENV_ROMSTAGE + ssus_disable_internal_pull(WP_STATUS_PAD); +#endif + + /* WP is enabled when the pin is reading high. */ + return ssus_get_gpio(WP_STATUS_PAD); +} diff --git a/src/mainboard/intel/strago/cmos.layout b/src/mainboard/intel/strago/cmos.layout new file mode 100644 index 0000000..18bf4ce --- /dev/null +++ b/src/mainboard/intel/strago/cmos.layout @@ -0,0 +1,140 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c new file mode 100755 index 0000000..d34c2df --- /dev/null +++ b/src/mainboard/intel/strago/com_init.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/gpio.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +/* + * return family number and internal pad number in that community + * by pad number and which community it is in. + */ + + + + /* family number in high byte and inner pad number in lowest byte */ + +void mainboard_pre_console_init(struct romstage_params *params) +{ + uint32_t reg; + uint32_t *pad_config_reg; + + /* Enable the UART hardware for COM1. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* + * Set up the pads to select the UART function + * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Setting Mode 2 for UART0_RXD + * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Setting Mode 2 for UART0_TXD + */ + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, + M2)); + + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, + M2)); +} diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb new file mode 100755 index 0000000..8b4ef21 --- /dev/null +++ b/src/mainboard/intel/strago/devicetree.cb @@ -0,0 +1,142 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_ACPI_MODE" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "1" + register "PcdEnableAzalia" = "1" + register "PcdEnableSata" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "1" + register "PcdEnableDma1" = "1" + register "PcdEnableI2C0" = "1" + register "PcdEnableI2C1" = "1" + register "PcdEnableI2C2" = "1" + register "PcdEnableI2C3" = "1" + register "PcdEnableI2C4" = "1" + register "PcdEnableI2C5" = "1" + register "PcdEnableI2C6" = "1" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "SVID_CONFIG3" + register "PcdEmmcMode" = "PCH_ACPI_MODE" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "0" # Disable SATA + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "3" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "1" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # Enable devices in ACPI mode + register "lpss_acpi_mode" = "1" + register "emmc_acpi_mode" = "1" + register "sd_acpi_mode" = "1" + register "lpe_acpi_mode" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + # EDS Table 24-4, Figure 24-5 + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 on end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 on end # 8086 22dc - ? + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 11.0 off end # 8086 0F15 - SDIO Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 13.0 off end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 on end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 on end # 8086 22c3 - I2C Port 3 + device pci 18.4 on end # 8086 22c4 - I2C Port 4 + device pci 18.5 on end # 8086 22c5 - I2C Port 5 + device pci 18.6 on end # 8086 22c6 - I2C Port 6 + device pci 18.7 on end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine + device pci 1b.0 on end # 8086 0F04 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.1 off end # 8086 0F08 - PWM 1 + device pci 1e.2 off end # 8086 0F09 - PWM 2 + device pci 1e.3 on end # 8086 228a - HSUART 1 + device pci 1e.4 on end # 8086 228c - HSUART 2 + device pci 1e.5 on end # 8086 228e - SPI 1 + device pci 1e.6 on end # 8086 2290 - SPI 2 + device pci 1e.7 on end # 8086 22ac - SPI 3 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Bridge + device pci 1f.3 off end # 8086 0F12 - SMBus 0 + end +end diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl new file mode 100755 index 0000000..d888651 --- /dev/null +++ b/src/mainboard/intel/strago/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, /* DSDT revision: ACPI v5.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <acpi/platform.asl> + + /* global NVS and variables */ + #include <acpi/globalnvs.asl> + + #include <acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <acpi/southcluster.asl> + #include <acpi/dptf/cpu.asl> + } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c new file mode 100755 index 0000000..89d289b --- /dev/null +++ b/src/mainboard/intel/strago/ec.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" +#include <vendorcode/google/chromeos/chromeos.h> +#include <types.h> + +void mainboard_ec_init(void) +{ + printk(BIOS_DEBUG, "mainboard_ec_init\n"); + post_code(0xf0); + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Restore SCI event mask on resume. */ + if (acpi_slp_type == 3) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + /* + * Set SCI mask.OS may not generate the SMI event to + * set this on S3 resume + */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); +#endif + post_code(0xf1); +} diff --git a/src/mainboard/intel/strago/ec.h b/src/mainboard/intel/strago/ec.h new file mode 100755 index 0000000..7e70d48 --- /dev/null +++ b/src/mainboard/intel/strago/ec.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +/* GPIO_S0_000 is EC_SCI#, but it is bit 16 in GPE_STS */ +#define EC_SCI_GPI 16 +/* GPIO_S5_07 is EC_SMI#, but it is bit 19 in GPE_STS and ALT_GPIO_SMI. */ +#define EC_SMI_GPI 19 + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/intel/strago/fadt.c b/src/mainboard/intel/strago/fadt.c new file mode 100755 index 0000000..45a680a --- /dev/null +++ b/src/mainboard/intel/strago/fadt.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/acpi.h> +#include <string.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c new file mode 100755 index 0000000..a4f60b2 --- /dev/null +++ b/src/mainboard/intel/strago/gpio.c @@ -0,0 +1,273 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" +#include <soc/gpio.h> +#include <stdlib.h> +#include "gpio.h" + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + Native_M1, /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* SPI1_CS1_B 66 */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + /* GPIO_ALERT 77 */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + GPIO_NC, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPIO_NC, /* 82 spkr asummed gpio number */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN,/* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + GPIO_NC, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + GPIO_NC, /* 03 FST_SPI_D3 */ + GPIO_NC, /* GPO FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + Native_M2, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + Native_M2, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + GPIO_NC, /* 30 MF_HDA_CLK */ + GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ + GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + GPIO_NC, /* 33 MF_HDA_SDO */ + GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 34 MF_HDA_DOCKRSTB */ + GPIO_NC, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ + GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ + GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ + GPIO_OUT_HIGH, /* 75 SATA_GP0 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 76 GPI SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 80 SATA_GP3 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ + Native_M1, /* 92 GP_SSP_2_CLK */ + NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + Native_M1, /* 94 GP_SSP_2_RXD */ + GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + Native_M1, /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + Native_M5, /* 00 GPIO_DFX0 */ + Native_M5, /* 01 GPIO_DFX3 */ + Native_M1, /* 02 GPIO_DFX7 */ + Native_M5, /* 03 GPIO_DFX1 */ + Native_M1, /* 04 GPIO_DFX5 */ + Native_M1, /* 05 GPIO_DFX4 */ + GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), + /* 06 GPIO_DFX8 */ + Native_M5, /* 07 GPIO_DFX2 */ + Native_M8, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, + /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPIO_NC, /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + Native_M2, /* 45 GP_CAMERASB05 */ + Native_M2, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + Native_M2, /* 48 GP_CAMERASB00 */ + Native_M2, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + Native_M2, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + Native_M2, /* 53 GP_CAMERASB01 */ + Native_M2, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + Native_M2, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + Native_M1, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_NC, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return get_override_gpios(&gpio_config); +} + +__attribute__((weak)) struct soc_gpio_config *get_override_gpios( + struct soc_gpio_config *config) +{ + return config; +} diff --git a/src/mainboard/intel/strago/gpio.h b/src/mainboard/intel/strago/gpio.h new file mode 100644 index 0000000..618524f --- /dev/null +++ b/src/mainboard/intel/strago/gpio.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#ifndef _BOARD_GPIO_H_ +#define _BOARD_GPIO_H_ + +struct soc_gpio_config *get_override_gpios(struct soc_gpio_config *config); +#endif diff --git a/src/mainboard/intel/strago/gpio_dvt.c b/src/mainboard/intel/strago/gpio_dvt.c new file mode 100755 index 0000000..17e7934 --- /dev/null +++ b/src/mainboard/intel/strago/gpio_dvt.c @@ -0,0 +1,273 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "irqroute.h" +#include <soc/gpio.h> +#include <stdlib.h> +#include <boardid.h> +#include "onboard.h" +#include "gpio.h" + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + Native_M1, /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* SPI1_CS1_B 66 */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + /* GPIO_ALERT 77 */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + GPIO_NC, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPIO_NC, /* 82 spkr asummed gpio number */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN,/* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + GPIO_NC, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + GPIO_NC, /* 03 FST_SPI_D3 */ + GPIO_NC, /* GPO FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + Native_M2, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + Native_M2, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + GPIO_NC, /* 30 MF_HDA_CLK */ + GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ + GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + GPIO_NC, /* 33 MF_HDA_SDO */ + GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 34 MF_HDA_DOCKRSTB */ + GPIO_NC, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ + GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ + GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ + GPIO_OUT_HIGH, /* 75 SATA_GP0 */ + GPIO_NC, + /* 76 GPI SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 80 SATA_GP3 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ + Native_M1, /* 92 GP_SSP_2_CLK */ + NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + Native_M1, /* 94 GP_SSP_2_RXD */ + GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + Native_M1, /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + Native_M5, /* 00 GPIO_DFX0 */ + Native_M5, /* 01 GPIO_DFX3 */ + Native_M1, /* 02 GPIO_DFX7 */ + Native_M5, /* 03 GPIO_DFX1 */ + Native_M1, /* 04 GPIO_DFX5 */ + Native_M1, /* 05 GPIO_DFX4 */ + GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), + /* 06 GPIO_DFX8 */ + Native_M5, /* 07 GPIO_DFX2 */ + Native_M8, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPI(trig_edge_high, L2, P_20K_H, non_maskable, en_edge_rx_data, NA , NA), + /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, + /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPIO_NC, /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + Native_M2, /* 45 GP_CAMERASB05 */ + Native_M2, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + Native_M2, /* 48 GP_CAMERASB00 */ + Native_M2, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + Native_M2, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + Native_M2, /* 53 GP_CAMERASB01 */ + Native_M2, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + Native_M2, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + Native_M1, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_NC, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *get_override_gpios(struct soc_gpio_config *config) +{ + if (board_id() == BOARD_DVT) + return &gpio_config; + + return config; +} diff --git a/src/mainboard/intel/strago/irqroute.c b/src/mainboard/intel/strago/irqroute.c new file mode 100644 index 0000000..83207d9 --- /dev/null +++ b/src/mainboard/intel/strago/irqroute.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/intel/strago/irqroute.h b/src/mainboard/intel/strago/irqroute.h new file mode 100644 index 0000000..5353d42 --- /dev/null +++ b/src/mainboard/intel/strago/irqroute.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) + +/* CORE bank DIRQs - up to 16 supported */ +#define TPAD_IRQ_OFFSET 0 +#define TOUCH_IRQ_OFFSET 1 +#define I8042_IRQ_OFFSET 2 +#define ALS_IRQ_OFFSET 3 +/* Corresponding SCORE GPIO pins */ +#define TPAD_IRQ_GPIO 55 +#define TOUCH_IRQ_GPIO 72 +#define I8042_IRQ_GPIO 101 +#define ALS_IRQ_GPIO 70 + +/* SUS bank DIRQs - up to 16 supported */ +#define CODEC_IRQ_OFFSET 0 +/* Corresponding SUS GPIO pins */ +#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c new file mode 100755 index 0000000..b109574 --- /dev/null +++ b/src/mainboard/intel/strago/mainboard.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootstate.h> +#include <device/device.h> +#include <soc/gpio.h> +#include "ec.h" + +static void mainboard_init(device_t dev) +{ + mainboard_ec_init(); +} + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h new file mode 100755 index 0000000..9d4b8b6 --- /dev/null +++ b/src/mainboard/intel/strago/onboard.h @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include "irqroute.h" + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +/* + * gpio based irq for kbd, 17th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 18 + */ +#define BOARD_I8042_IRQ 182 + +/* + * gpio based irq for trackpad, 18th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 19 + */ +#define BOARD_TRACKPAD_IRQ 231 + +/* + * gpio based irq for touchscreen, 76th index in SW Bank + * MAX_DIRECT_IRQ + 77 + */ +#define BOARD_TOUCHSCREEN_IRQ 191 + +/* Audio: Gpio index in SW bank */ +#define JACK_DETECT_GPIO_INDEX 95 +/* SCI: Gpio index in N bank */ +#define BOARD_SCI_GPIO_INDEX 15 +/* Trackpad: Gpio index in N bank */ +#define BOARD_TRACKPAD_GPIO_INDEX 18 +/* Touch: Gpio index in SW bank */ +#define BOARD_TOUCH_GPIO_INDEX 76 +/* Touch: Gpio index in SW bank */ +#define BOARD_DVT_TOUCH_GPIO_INDEX 19 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ + +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +/* + * gpio based irq for codec irq, 77th index in GPSE Bank + * MAX_DIRECT_IRQ+GPSW_SIZE+GPNC_SIZE +GPEC_SIZE + 78 + */ +#define BOARD_CODEC_IRQ 390 + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "10EC5650" +#define AUDIO_CODEC_CID "10EC5650" +#define AUDIO_CODEC_DDN "RTEK Codec Controller " +#define AUDIO_CODEC_I2C_ADDR 0x1A + +#define BOARD_DVT 0x03 + +#endif diff --git a/src/mainboard/intel/strago/ramstage.c b/src/mainboard/intel/strago/ramstage.c new file mode 100644 index 0000000..283ea42 --- /dev/null +++ b/src/mainboard/intel/strago/ramstage.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + if (IS_ENABLED(CONFIG_DYNAMIC_VNN_SUPPORT)) + params->ChvSvidConfig = SVID_CONFIG1; +} diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c new file mode 100755 index 0000000..22e26b5 --- /dev/null +++ b/src/mainboard/intel/strago/romstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <string.h> + +/* All FSP specific code goes in this block */ +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data *ps = rp->pei_data; + + mainboard_fill_spd_data(ps); + + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); +} + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + /* Update SPD data */ + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c new file mode 100755 index 0000000..5af0421 --- /dev/null +++ b/src/mainboard/intel/strago/smihandler.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#include <elog.h> +#include <soc/nvs.h> +#include <soc/pm.h> + +/* The wake gpio is SUS_GPIO[0]. */ +#define WAKE_GPIO_EN SUS_GPIO_EN0 + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +static uint8_t mainboard_smi_ec(void) +{ + uint8_t cmd = google_chromeec_get_event(); + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt; + +#if IS_ENABLED(CONFIG_ELOG_GSMI) + /* Log this event */ + if (cmd) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); +#endif + + switch (cmd) { + case EC_HOST_EVENT_LID_CLOSED: + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + + /* Go to S5 */ + pm1_cnt = inl(pmbase + PM1_CNT); + pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); + outl(pm1_cnt, pmbase + PM1_CNT); + break; + } + + return cmd; +} +#endif + +/* + * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that + * this includes the enable bits in the lower 16 bits. + */ +void mainboard_smi_gpi(uint32_t alt_gpio_smi) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (alt_gpio_smi & (1 << EC_SMI_GPI)) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0) + ; + } +#endif +} + +void mainboard_smi_sleep(uint8_t slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (smm_get_gnvs()->s3u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s3u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); +#endif + /* Enable wake pin in GPE block. */ + enable_gpe(WAKE_GPIO_EN); + break; + case 5: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (smm_get_gnvs()->s5u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s5u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); +#endif + break; + } + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Disable SCI and SMI events */ + google_chromeec_set_smi_mask(0); + google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + while (google_chromeec_get_event() != 0) + ; +#endif +} + +int mainboard_smi_apmc(uint8_t apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); +#endif + break; + case APM_CNT_ACPI_DISABLE: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); +#endif + break; + } + return 0; +} diff --git a/src/mainboard/intel/strago/spd/Makefile.inc b/src/mainboard/intel/strago/spd/Makefile.inc new file mode 100755 index 0000000..4b4bff6 --- /dev/null +++ b/src/mainboard/intel/strago/spd/Makefile.inc @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab diff --git a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex new file mode 100755 index 0000000..ff4fd29 --- /dev/null +++ b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex @@ -0,0 +1,32 @@ +92 12 0b 03 04 19 02 02 +03 52 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +20 08 3c 3c 01 40 83 01 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ad 01 +00 00 00 00 00 00 ff ab +48 4d 54 34 32 35 53 36 +41 46 52 36 41 2d 50 42 +20 20 4e 30 80 ad 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex new file mode 100755 index 0000000..fdd1a43 --- /dev/null +++ b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex @@ -0,0 +1,32 @@ +92 13 0B 03 04 19 02 02 +03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 +00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 +43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF diff --git a/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex new file mode 100755 index 0000000..e0b0ac5 --- /dev/null +++ b/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex @@ -0,0 +1,32 @@ +92 12 0B 03 04 19 02 02 +03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 +88 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 +34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/strago/spd/spd.c b/src/mainboard/intel/strago/spd/spd.c new file mode 100755 index 0000000..9951708 --- /dev/null +++ b/src/mainboard/intel/strago/spd/spd.c @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <soc/gpio.h> +#include <soc/romstage.h> +#include <string.h> + +#define SPD_SIZE 256 +#define SATA_GP3_PAD_CFG0 0x5828 +#define I2C3_SCL_PAD_CFG0 0x5438 +#define MF_PLT_CLK1_PAD_CFG0 0x4410 +#define I2C3_SDA_PAD_CFG0 0x5420 + +/* + * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b0010- 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + */ +static const uint32_t dual_channel_config = (1 << 0); + +static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +{ + int ram_id = 0; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1; + ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0) + << 2; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3; + + /* + * There are only 2 SPDs supported on Cyan Board: + * Samsung 4G:0000 & Hynix 2G:0011 + */ + + /* + * RAMID0 on the first boot does not read the correct value,so checking + * bit 1 is enough as WA + */ + if (ram_id > 0) + ram_id = 3; + printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); + + if (ram_id >= total_spds) + return NULL; + + /* Single channel configs */ + if (dual_channel_config & (1 << ram_id)) + *dual = 1; + + return &spd_file_content[SPD_SIZE * ram_id]; +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *ps) +{ + char *spd_file; + size_t spd_file_len; + void *spd_content; + int dual_channel = 0; + + /* Find the SPD data in CBFS. */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < SPD_SIZE) + die("Missing SPD data."); + + /* + * Both channels are always present in SPD data. Always use matched + * DIMMs so use the same SPD data for each DIMM. + */ + spd_content = get_spd_pointer(spd_file, + spd_file_len / SPD_SIZE, + &dual_channel); + if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) { + printk(BIOS_DEBUG, "SPD Data:\n"); + hexdump(spd_content, SPD_SIZE); + printk(BIOS_DEBUG, "\n"); + } + + /* + * Set SPD and memory configuration: + * Memory type: 0=DimmInstalled, + * 1=SolderDownMemory, + * 2=DimmDisabled + */ + if (spd_content != NULL) { + ps->spd_data_ch0 = spd_content; + ps->spd_ch0_config = 1; + if (dual_channel) { + ps->spd_data_ch1 = spd_content; + ps->spd_ch1_config = 1; + } else { + ps->spd_ch1_config = 2; + } + } +} diff --git a/src/mainboard/intel/strago/w25q64.c b/src/mainboard/intel/strago/w25q64.c new file mode 100755 index 0000000..4399d88 --- /dev/null +++ b/src/mainboard/intel/strago/w25q64.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/spi.h> +#include <string.h> + +/* + * SPI lockdown configuration W25Q64FW. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config = { + .preop = SPI_OPPREFIX, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_config(struct spi_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + + return 0; +}

1 0

Patch set updated for coreboot: Braswell: Add Braswell SOC support
by Leroy P Leahy 24 Jun '15

24 Jun '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10051 -gerrit commit bd96a908012c224f4c4dad2d197227d6ffdc9504 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Apr 20 15:20:28 2015 -0700 Braswell: Add Braswell SOC support Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/braswell/Kconfig | 169 ++-- src/soc/intel/braswell/Makefile.inc | 100 +-- src/soc/intel/braswell/acpi.c | 204 +++-- src/soc/intel/braswell/acpi/cpu.asl | 50 +- src/soc/intel/braswell/acpi/device_nvs.asl | 110 +-- src/soc/intel/braswell/acpi/dptf/cpu.asl | 86 ++- src/soc/intel/braswell/acpi/dptf/dptf.asl | 11 +- src/soc/intel/braswell/acpi/dptf/thermal.asl | 12 +- src/soc/intel/braswell/acpi/dptf/wifi.asl | 16 + src/soc/intel/braswell/acpi/dptf/wwan.asl | 16 + src/soc/intel/braswell/acpi/globalnvs.asl | 66 +- src/soc/intel/braswell/acpi/gpio.asl | 69 +- src/soc/intel/braswell/acpi/irqlinks.asl | 145 ++-- src/soc/intel/braswell/acpi/irqroute.asl | 6 +- src/soc/intel/braswell/acpi/lpc.asl | 42 +- src/soc/intel/braswell/acpi/lpe.asl | 6 +- src/soc/intel/braswell/acpi/lpss.asl | 24 +- src/soc/intel/braswell/acpi/pcie.asl | 109 --- src/soc/intel/braswell/acpi/platform.asl | 18 +- src/soc/intel/braswell/acpi/scc.asl | 12 +- src/soc/intel/braswell/acpi/sleepstates.asl | 2 +- src/soc/intel/braswell/acpi/southcluster.asl | 78 +- src/soc/intel/braswell/bootblock/Makefile.inc | 2 +- src/soc/intel/braswell/bootblock/bootblock.c | 9 +- src/soc/intel/braswell/bootblock/timestamp.inc | 7 +- src/soc/intel/braswell/chip.c | 280 ++++++- src/soc/intel/braswell/chip.h | 146 ++-- src/soc/intel/braswell/cpu.c | 116 ++- src/soc/intel/braswell/dptf.c | 52 -- src/soc/intel/braswell/ehci.c | 181 ----- src/soc/intel/braswell/elog.c | 49 +- src/soc/intel/braswell/emmc.c | 29 +- src/soc/intel/braswell/gfx.c | 350 +-------- src/soc/intel/braswell/gpio.c | 423 +++++----- src/soc/intel/braswell/gpio_support.c | 87 +++ src/soc/intel/braswell/hda.c | 77 +- src/soc/intel/braswell/include/soc/acpi.h | 17 +- .../intel/braswell/include/soc/chipset_fsp_util.h | 41 + src/soc/intel/braswell/include/soc/device_nvs.h | 8 +- src/soc/intel/braswell/include/soc/efi_wrapper.h | 52 -- src/soc/intel/braswell/include/soc/ehci.h | 24 +- src/soc/intel/braswell/include/soc/gfx.h | 62 +- src/soc/intel/braswell/include/soc/gpio.h | 851 ++++++++++++--------- src/soc/intel/braswell/include/soc/hda.h | 45 ++ src/soc/intel/braswell/include/soc/iomap.h | 20 +- src/soc/intel/braswell/include/soc/iosf.h | 266 ++----- src/soc/intel/braswell/include/soc/irq.h | 158 ++-- src/soc/intel/braswell/include/soc/lpc.h | 9 +- src/soc/intel/braswell/include/soc/mrc_wrapper.h | 107 --- src/soc/intel/braswell/include/soc/msr.h | 19 +- src/soc/intel/braswell/include/soc/nvs.h | 19 +- src/soc/intel/braswell/include/soc/pattrs.h | 24 +- src/soc/intel/braswell/include/soc/pci_devs.h | 87 ++- src/soc/intel/braswell/include/soc/pcie.h | 10 +- src/soc/intel/braswell/include/soc/pei_data.h | 62 ++ src/soc/intel/braswell/include/soc/pei_wrapper.h | 30 + src/soc/intel/braswell/include/soc/pm.h | 267 +++++++ src/soc/intel/braswell/include/soc/pmc.h | 303 -------- src/soc/intel/braswell/include/soc/ramstage.h | 26 +- src/soc/intel/braswell/include/soc/reset.h | 36 - src/soc/intel/braswell/include/soc/romstage.h | 38 +- src/soc/intel/braswell/include/soc/sata.h | 135 +++- src/soc/intel/braswell/include/soc/smm.h | 22 +- src/soc/intel/braswell/include/soc/spi.h | 7 +- src/soc/intel/braswell/include/soc/xhci.h | 15 +- src/soc/intel/braswell/iosf.c | 261 ++----- src/soc/intel/braswell/lpe.c | 44 +- src/soc/intel/braswell/lpss.c | 45 +- src/soc/intel/braswell/memmap.c | 60 +- src/soc/intel/braswell/microcode/Makefile.inc | 14 +- src/soc/intel/braswell/microcode/microcode_blob.c | 21 +- src/soc/intel/braswell/northcluster.c | 89 ++- src/soc/intel/braswell/pcie.c | 141 ++-- src/soc/intel/braswell/perf_power.c | 292 ------- src/soc/intel/braswell/placeholders.c | 3 - src/soc/intel/braswell/pmutil.c | 28 +- src/soc/intel/braswell/ramstage.c | 88 ++- src/soc/intel/braswell/refcode.c | 148 ---- src/soc/intel/braswell/reset.c | 47 -- src/soc/intel/braswell/romstage/Makefile.inc | 9 +- src/soc/intel/braswell/romstage/cache_as_ram.inc | 284 ------- src/soc/intel/braswell/romstage/early_spi.c | 19 +- src/soc/intel/braswell/romstage/gfx.c | 50 -- src/soc/intel/braswell/romstage/pmc.c | 51 +- src/soc/intel/braswell/romstage/raminit.c | 185 ----- src/soc/intel/braswell/romstage/romstage.c | 318 +++----- src/soc/intel/braswell/romstage/uart.c | 38 - src/soc/intel/braswell/sata.c | 188 +---- src/soc/intel/braswell/scc.c | 82 +- src/soc/intel/braswell/sd.c | 14 +- src/soc/intel/braswell/smihandler.c | 227 +++--- src/soc/intel/braswell/smm.c | 24 +- src/soc/intel/braswell/southcluster.c | 361 ++++----- src/soc/intel/braswell/spi.c | 129 ++-- src/soc/intel/braswell/spi_loading.c | 154 ++++ src/soc/intel/braswell/stage_cache.c | 35 - src/soc/intel/braswell/tsc_freq.c | 54 +- src/soc/intel/braswell/xhci.c | 259 ------- 98 files changed, 4005 insertions(+), 5676 deletions(-) diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index d4200c7..dac38ce 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -1,31 +1,45 @@ config SOC_INTEL_BRASWELL bool help - Bay Trail M/D part support. + Braswell M/D part support. if SOC_INTEL_BRASWELL config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_ROM + select CAR_MIGRATION select COLLECT_TIMESTAMPS + select CPU_MICROCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED - select SUPPORT_CPU_UCODE_IN_CBFS + select DYNAMIC_CBMEM + select ENABLE_MRC_CACHE + select HAS_PRECBMEM_TIMESTAMP_REGION + select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES - select RELOCATABLE_RAMSTAGE select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK + select PLATFORM_USES_FSP1_1 select REG_SCRIPT + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_FSP_RAM_INIT + select SOC_INTEL_COMMON_FSP_ROMSTAGE + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_STACK + select SOC_INTEL_COMMON_STAGE_CACHE + select SMM_MODULES select SMM_TSEG select SMP select SPI_FLASH @@ -35,14 +49,14 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC - select SOC_INTEL_COMMON + select USE_GENERIC_FSP_CAR_INC config BOOTBLOCK_CPU_INIT string - default "soc/intel/baytrail/bootblock/bootblock.c" + default "soc/intel/braswell/bootblock/bootblock.c" config MMCONF_BASE_ADDRESS - hex + hex "PCIe CFG Base Address" default 0xe0000000 config MAX_CPUS @@ -61,39 +75,8 @@ config SMM_RESERVED_SIZE hex default 0x100000 -config HAVE_MRC - bool "Add a Memory Reference Code binary" - default y - help - Select this option to add a blob containing - memory reference code. - Note: Without this binary coreboot will not work - -if HAVE_MRC - -config MRC_FILE - string "Intel memory refeference code path and filename" - default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin" - help - The path and filename of the file to use as System Agent - binary. Note that this points to the sandybridge binary file - which is will not work, but it serves its purpose to do builds. - -config MRC_BIN_ADDRESS - hex - default 0xfffa0000 - -config MRC_RMT - bool "Enable MRC RMT training + debug prints" - default n - -endif # HAVE_MRC - # Cache As RAM region layout: # -# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE -# | MRC usage | -# | | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE # | Stack |\ # | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE @@ -104,48 +87,63 @@ endif # HAVE_MRC # | CAR Globals | # +-------------+ DCACHE_RAM_BASE # -# Note that the MRC binary is linked to assume the region marked as "MRC usage" -# starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then -# a new MRC binary needs to be produced with the updated start and size -# information. config DCACHE_RAM_BASE - hex - default 0xfe000000 + hex "Temporary RAM Base Address" + default 0xfef00000 config DCACHE_RAM_SIZE - hex - default 0x8000 + hex "Temporary RAM Size" + default 0x4000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2. -config DCACHE_RAM_MRC_VAR_SIZE - hex - default 0x8000 - help - The amount of cache-as-ram region required by the reference code. - config DCACHE_RAM_ROMSTAGE_STACK_SIZE hex default 0x800 help The amount of anticipated stack usage from the data cache - during pre-RAM ROM stage execution. + during pre-ram rom stage execution. config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n depends on RELOCATABLE_RAMSTAGE help - The baytrail romstage code caches the loaded ramstage program + The haswell romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs. +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default 0x100000 + help + The firmware image has to store a lot more than just coreboot, + including: + - a firmware descriptor + - Intel Management Engine firmware + - MRC cache information + This option allows to limit the size of the CBFS portion in the + firmware image. + +config LOCK_MANAGEMENT_ENGINE + bool "Lock Management Engine section" + default n + help + The Intel Management Engine supports preventing write accesses + from the host to the Management Engine section in the firmware + descriptor. If the ME section is locked, it can only be overwritten + with an external SPI flash programmer. You will want this if you + want to increase security of your ROM image once you are sure + that the ME firmware is no longer going to change. + + If unsure, say N. + config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n @@ -154,22 +152,6 @@ config ENABLE_BUILTIN_COM1 configure the pads and enable it. This serial port can be used for the debug console. -config HAVE_ME_BIN - bool "Add Intel Management Engine firmware" - default y - help - The Intel processor in the selected system requires a special firmware - for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty repository. If - not and if you don't have the firmware elsewhere, you can still - build coreboot without it. In this case however, you'll have to make - sure that you don't overwrite your ME firmware on your flash ROM. - -config ME_BIN_PATH - string "Path to management engine firmware" - depends on HAVE_ME_BIN - default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" - config HAVE_IFD_BIN bool default y @@ -191,6 +173,26 @@ config BUILD_WITH_FAKE_IFD [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html +config HAVE_ME_BIN + bool "Add Intel Management Engine firmware" + default y + help + The Intel processor in the selected system requires a special firmware + for an integrated controller called Management Engine (ME). The ME + firmware might be provided in coreboot's 3rdparty/blobs repository. If + not and if you don't have the firmware elsewhere, you can still + build coreboot without it. In this case however, you'll have to make + sure that you don't overwrite your ME firmware on your flash ROM. + +config IED_REGION_SIZE + hex + default 0x400000 + +config IFD_BIN_PATH + string "Path to intel firmware descriptor" + depends on !BUILD_WITH_FAKE_IFD + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" + config IFD_BIOS_SECTION depends on BUILD_WITH_FAKE_IFD string @@ -206,26 +208,9 @@ config IFD_PLATFORM_SECTION string default "" -config IFD_BIN_PATH - string "Path to intel firmware descriptor" - depends on !BUILD_WITH_FAKE_IFD - default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" - -config HAVE_REFCODE_BLOB - depends on ARCH_X86 - bool "An external reference code blob should be put into cbfs." - default n - help - The reference code blob will be placed into cbfs. - -if HAVE_REFCODE_BLOB - -config REFCODE_BLOB_FILE - string "Path and filename to reference code blob." - default "refcode.elf" - help - The path and filename to the file to be added to cbfs. - -endif # HAVE_REFCODE_BLOB +config ME_BIN_PATH + string "Path to management engine firmware" + depends on HAVE_ME_BIN + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" endif diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 0806bbb..540ac84 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage +subdirs-y += ../common subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm @@ -10,56 +11,63 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -ramstage-y += memmap.c +romstage-y += gpio_support.c +romstage-y += iosf.c romstage-y += memmap.c -ramstage-y += tsc_freq.c romstage-y += tsc_freq.c -smm-y += tsc_freq.c -ramstage-y += spi.c -smm-y += spi.c + +ramstage-y += acpi.c ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += emmc.c +ramstage-y += gpio.c +ifeq ($(CONFIG_GOP_SUPPORT),n) ramstage-y += gfx.c +endif +ramstage-y += hda.c ramstage-y += iosf.c -romstage-y += iosf.c -smm-y += iosf.c +ramstage-y += lpe.c +ramstage-y += lpss.c +ramstage-y += memmap.c ramstage-y += northcluster.c -ramstage-y += ramstage.c -ramstage-y += gpio.c -romstage-y += reset.c -ramstage-y += reset.c -ramstage-y += cpu.c +ramstage-y += pcie.c ramstage-y += pmutil.c -smm-y += pmutil.c -smm-y += smihandler.c -ramstage-y += smm.c -ramstage-y += ehci.c -ramstage-y += xhci.c -ramstage-y += southcluster.c -ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c +ramstage-y += ramstage.c ramstage-y += sata.c -ramstage-y += acpi.c -ramstage-y += lpe.c ramstage-y += scc.c -ramstage-y += emmc.c -ramstage-y += lpss.c -ramstage-y += pcie.c ramstage-y += sd.c -ramstage-y += dptf.c -ramstage-y += perf_power.c -ramstage-y += stage_cache.c -romstage-y += stage_cache.c -ramstage-$(CONFIG_ELOG) += elog.c -ramstage-y += hda.c +ramstage-y += smm.c +ramstage-y += southcluster.c +ramstage-y += spi.c +ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c +ramstage-y += tsc_freq.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c -CPPFLAGS_common += -Isrc/soc/intel/baytrail/include +smm-y += pmutil.c +smm-y += smihandler.c +smm-y += spi.c +smm-y += tsc_freq.c + +CPPFLAGS_common += -I$(src)/arch/x86/include/ +CPPFLAGS_common += -I$(src)/soc/intel/braswell/ +CPPFLAGS_common += -I$(src)/soc/intel/braswell/include + +CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR) + +CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1 +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1 +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4 +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32 +CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH) # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS -INTERMEDIATE:=baytrail_add_me +INTERMEDIATE := pch_add_me ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) IFD_BIN_PATH := $(objgenerated)/ifdfake.bin @@ -70,7 +78,7 @@ else IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) endif -baytrail_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) +pch_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) printf "\n** WARNING **\n" printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" @@ -80,28 +88,30 @@ ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) endif printf " DD Adding Intel Firmware Descriptor\n" + printf "CONFIG_IFD_BIN_PATH: $(CONFIG_IFD_BIN_PATH)\n" + printf "IFD_BIN_PATH: $(IFD_BIN_PATH)\n" dd if=$(IFD_BIN_PATH) \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 + printf "CONFIG_HAVE_ME_BIN: $(CONFIG_HAVE_ME_BIN)\n" ifeq ($(CONFIG_HAVE_ME_BIN),y) printf " IFDTOOL me.bin -> coreboot.pre\n" + printf "CONFIG_ME_BIN_PATH: $(CONFIG_ME_BIN_PATH)\n" $(objutil)/ifdtool/ifdtool \ -i ME:$(CONFIG_ME_BIN_PATH) \ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif -# If an MRC file is an ELF file determine the entry address and first loadable -# section offset in the file. Subtract the offset from the entry address to -# determine the final location. -mrcelfoffset = $(shell $(READELF_x86_32) -S -W $(CONFIG_MRC_FILE) | sed -e 's/\[ /[0/' | awk '$$3 ~ /PROGBITS/ { print "0x"$$5; exit }' ) -mrcelfentry = $(shell $(READELF_x86_32) -h -W $(CONFIG_MRC_FILE) | grep 'Entry point address' | awk '{print $$NF }') - -# Add memory reference code blob. -cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin -mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) -mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS)) -mrc.bin-type := mrc +ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) + printf " IFDTOOL Locking Management Engine\n" + $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +else + printf " IFDTOOL Unlocking Management Engine\n" + $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +endif -PHONY += baytrail_add_me +PHONY += pch_add_me endif diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 8357705..e008f07 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,27 +21,30 @@ #include <arch/acpi.h> #include <arch/acpigen.h> +#include <arch/cpu.h> #include <arch/io.h> #include <arch/smp/mpspec.h> +#include <cbfs.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/x86/smm.h> -#include <console/console.h> -#include <types.h> -#include <string.h> -#include <arch/cpu.h> +#include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/x86/tsc.h> -#include <cpu/intel/turbo.h> - +#include <device/pci.h> +#include <device/pci_ids.h> +#include <ec/google/chromeec/ec.h> +#include <fsp_gop.h> #include <soc/acpi.h> +#include <soc/gfx.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/msr.h> #include <soc/pattrs.h> -#include <soc/pmc.h> - -#include <ec/google/chromeec/ec.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <string.h> +#include <types.h> #include <vendorcode/google/chromeos/gnvs.h> #define MWAIT_RES(state, sub_state) \ @@ -89,15 +93,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); -#if CONFIG_CONSOLE_CBMEM +#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_vboot(&(gnvs->chromeos)); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif @@ -137,7 +141,7 @@ static int acpi_sci_irq(void) return sci_irq; } -void acpi_create_intel_hpet(acpi_hpet_t * hpet) +void acpi_create_intel_hpet(acpi_hpet_t *hpet) { acpi_header_t *header = &(hpet->header); acpi_addr_t *addr = &(hpet->addr); @@ -284,7 +288,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } -static acpi_tstate_t baytrail_tss_table[] = { +static acpi_tstate_t soc_tss_table[] = { { 100, 1000, 0, 0x00, 0 }, { 88, 875, 0, 0x1e, 0 }, { 75, 750, 0, 0x1c, 0 }, @@ -295,24 +299,20 @@ static acpi_tstate_t baytrail_tss_table[] = { { 13, 125, 0, 0x12, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set NVS controlled T-state limit */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* Write TSS table for MSR access */ - len += acpigen_write_TSS_package( - ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); - - return len; + acpigen_write_TSS_package( + ARRAY_SIZE(soc_tss_table), soc_tss_table); } static int calculate_power(int tdp, int p1_ratio, int ratio) @@ -336,9 +336,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; } -static int generate_P_state_entries(int core, int cores_per_package) +static void generate_P_state_entries(int core, int cores_per_package) { - int len, len_pss; int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; int coord_type, power_max, power_unit, num_entries; int ratio, power, clock, clock_max; @@ -366,16 +365,16 @@ static int generate_P_state_entries(int core, int cores_per_package) power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; /* Write _PCT indicating use of FFixedHW */ - len = acpigen_write_empty_PCT(); + acpigen_write_empty_PCT(); /* Write _PPC with NVS specified limit on supported P-state */ - len += acpigen_write_PPC_NVS(); + acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, 1, coord_type); + acpigen_write_PSD_package(core, 1, coord_type); /* Add P-state entries in _PSS table */ - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS"); /* Determine ratio points */ ratio_step = 1; @@ -388,36 +387,36 @@ static int generate_P_state_entries(int core, int cores_per_package) /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ - len_pss = acpigen_write_package(num_entries + 2); + acpigen_write_package(num_entries + 2); ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; control_status = (ratio_turbo << 8) | vid_turbo; /* Add entry for Turbo ratio */ - len_pss += acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control*/ - control_status); /*status*/ + acpigen_write_PSS_package( + clock_max + 1, /* MHz */ + power_max, /* mW */ + 10, /* lat1 */ + 10, /* lat2 */ + control_status, /* control */ + control_status); /* status */ } else { /* _PSS package count without Turbo */ - len_pss = acpigen_write_package(num_entries + 1); + acpigen_write_package(num_entries + 1); ratio_turbo = ratio_max; vid_turbo = vid_max; } /* First regular entry is max non-turbo ratio */ control_status = (ratio_max << 8) | vid_max; - len_pss += acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control */ - control_status); /*status*/ + acpigen_write_PSS_package( + clock_max, /* MHz */ + power_max, /* mW */ + 10, /* lat1 */ + 10, /* lat2 */ + control_status, /* control */ + control_status); /* status */ /* Set up ratio and vid ranges for VID calculation */ ratio_range_2 = (ratio_turbo - ratio_min) * 2; @@ -439,52 +438,48 @@ static int generate_P_state_entries(int core, int cores_per_package) clock = (ratio * pattrs->bclk_khz) / 1000; control_status = (ratio << 8) | (vid & 0xff); - len_pss += acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control*/ - control_status); /*status*/ + acpigen_write_PSS_package( + clock, /* MHz */ + power, /* mW */ + 10, /* lat1 */ + 10, /* lat2 */ + control_status, /* control */ + control_status); /* status */ } /* Fix package length */ - len_pss--; - acpigen_patch_len(len_pss); - - return len + len_pss; + acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { - int len_pr, core; + int core; int pcontrol_blk = get_pmbase(), plen = 6; const struct pattrs *pattrs = pattrs_get(); - for (core=0; core<pattrs->num_cpus; core++) { + for (core = 0; core < pattrs->num_cpus; core++) { if (core > 0) { pcontrol_blk = 0; plen = 0; } /* Generate processor \_PR.CPUx */ - len_pr = acpigen_write_processor( + acpigen_write_processor( core, pcontrol_blk, plen); /* Generate P-state tables */ - len_pr += generate_P_state_entries( + generate_P_state_entries( core, pattrs->num_cpus); /* Generate C-state tables */ - len_pr += acpigen_write_CST_package( + acpigen_write_CST_package( cstate_map, ARRAY_SIZE(cstate_map)); /* Generate T-state tables */ - len_pr += generate_T_state_entries( + generate_T_state_entries( core, pattrs->num_cpus); - len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } @@ -505,7 +500,80 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, - sci_flags); + sci_flags); return current; } + +#if CONFIG_GOP_SUPPORT +/* Reading VBT table from flash */ +static void get_fsp_vbt(igd_opregion_t *opregion) +{ + const optionrom_vbt_t *vbt; + uint32_t vbt_len; + + vbt = fsp_get_vbt(&vbt_len); + if (!vbt) + die("vbt data not found"); + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < + sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : + sizeof(opregion->vbt.gvd1)); +} + +/* Initialize IGD OpRegion, called from ACPI code */ +int init_igd_opregion(igd_opregion_t *opregion) +{ + device_t igd; + u16 reg16; + + memset(opregion, 0, sizeof(igd_opregion_t)); + + /* FIXME if IGD is disabled, we should exit here. */ + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(IGD_OPREGION_SIGNATURE)); + + /* 8kb */ + opregion->header.size = sizeof(igd_opregion_t) / 1024; + opregion->header.version = IGD_OPREGION_VERSION; + + /* FIXME We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* TODO Initialize Mailbox 1 */ + + /* TODO Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + get_fsp_vbt(opregion); + + /* + * TODO This needs to happen in S3 resume, too. + * Maybe it should move to the finalize handler + */ + igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC)); + + pci_write_config32(igd, ASLS, (u32)opregion); + reg16 = pci_read_config16(igd, SWSCI); + reg16 &= ~(1 << 0); + reg16 |= (1 << 15); + pci_write_config16(igd, SWSCI, reg16); + + return 0; +} +#endif diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl index 85b2014..d487974 100644 --- a/src/soc/intel/braswell/acpi/cpu.asl +++ b/src/soc/intel/braswell/acpi/cpu.asl @@ -18,22 +18,34 @@ * Foundation, Inc. */ +/* CPU */ +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + /* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) +External (\_PR.CPU0, DeviceObj) +External (\_PR.CPU1, DeviceObj) +External (\_PR.CPU2, DeviceObj) +External (\_PR.CPU3, DeviceObj) + /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST + Notify (\_PR.CPU0, 0x81) /* _CST */ + Notify (\_PR.CPU1, 0x81) /* _CST */ } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST + Notify (\_PR.CPU2, 0x81) /* _CST */ + Notify (\_PR.CPU3, 0x81) /* _CST */ } } @@ -41,12 +53,12 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC + Notify (\_PR.CPU0, 0x80) /* _PPC */ + Notify (\_PR.CPU1, 0x80) /* _PPC */ } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC + Notify (\_PR.CPU2, 0x80) /* _PPC */ + Notify (\_PR.CPU3, 0x80) /* _PPC */ } } @@ -54,12 +66,12 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC + Notify (\_PR.CPU0, 0x82) /* _TPC */ + Notify (\_PR.CPU1, 0x82) /* _TPC */ } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC + Notify (\_PR.CPU2, 0x82) /* _TPC */ + Notify (\_PR.CPU3, 0x82) /* _TPC */ } } @@ -67,10 +79,10 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) + Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CP00, \_PR.CP01}) + Return (Package() {\_PR.CPU0, \_PR.CPU1}) } Else { - Return (Package() {\_PR.CP00}) + Return (Package() {\_PR.CPU0}) } } diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl index 1bb7d95..19e4368 100644 --- a/src/soc/intel/braswell/acpi/device_nvs.asl +++ b/src/soc/intel/braswell/acpi/device_nvs.asl @@ -20,67 +20,67 @@ /* Device Enabled in ACPI Mode */ -S0EN, 8, // SDMA Enable -S1EN, 8, // I2C1 Enable -S2EN, 8, // I2C2 Enable -S3EN, 8, // I2C3 Enable -S4EN, 8, // I2C4 Enable -S5EN, 8, // I2C5 Enable -S6EN, 8, // I2C6 Enable -S7EN, 8, // I2C7 Enable -S8EN, 8, // SDMA2 Enable -S9EN, 8, // SPI Enable -SAEN, 8, // PWM1 Enable -SBEN, 8, // PWM2 Enable -SCEN, 8, // UART2 Enable -SDEN, 8, // UART2 Enable -C0EN, 8, // MMC Enable -C1EN, 8, // SDIO Enable -C2EN, 8, // SD Card Enable -LPEN, 8, // LPE Enable +S0EN, 8, /* SDMA Enable */ +S1EN, 8, /* I2C1 Enable */ +S2EN, 8, /* I2C2 Enable */ +S3EN, 8, /* I2C3 Enable */ +S4EN, 8, /* I2C4 Enable */ +S5EN, 8, /* I2C5 Enable */ +S6EN, 8, /* I2C6 Enable */ +S7EN, 8, /* I2C7 Enable */ +S8EN, 8, /* SDMA2 Enable */ +S9EN, 8, /* SPI Enable */ +SAEN, 8, /* PWM1 Enable */ +SBEN, 8, /* PWM2 Enable */ +SCEN, 8, /* UART2 Enable */ +SDEN, 8, /* UART2 Enable */ +C0EN, 8, /* MMC Enable */ +C1EN, 8, /* SDIO Enable */ +C2EN, 8, /* SD Card Enable */ +LPEN, 8, /* LPE Enable */ /* BAR 0 */ -S0B0, 32, // SDMA BAR0 -S1B0, 32, // I2C1 BAR0 -S2B0, 32, // I2C2 BAR0 -S3B0, 32, // I2C3 BAR0 -S4B0, 32, // I2C4 BAR0 -S5B0, 32, // I2C5 BAR0 -S6B0, 32, // I2C6 BAR0 -S7B0, 32, // I2C7 BAR0 -S8B0, 32, // SDMA2 BAR0 -S9B0, 32, // SPI BAR0 -SAB0, 32, // PWM1 BAR0 -SBB0, 32, // PWM2 BAR0 -SCB0, 32, // UART1 BAR0 -SDB0, 32, // UART2 BAR0 -C0B0, 32, // MMC BAR0 -C1B0, 32, // SDIO BAR0 -C2B0, 32, // SD Card BAR0 -LPB0, 32, // LPE BAR0 +S0B0, 32, /* SDMA BAR0 */ +S1B0, 32, /* I2C1 BAR0 */ +S2B0, 32, /* I2C2 BAR0 */ +S3B0, 32, /* I2C3 BAR0 */ +S4B0, 32, /* I2C4 BAR0 */ +S5B0, 32, /* I2C5 BAR0 */ +S6B0, 32, /* I2C6 BAR0 */ +S7B0, 32, /* I2C7 BAR0 */ +S8B0, 32, /* SDMA2 BAR0 */ +S9B0, 32, /* SPI BAR0 */ +SAB0, 32, /* PWM1 BAR0 */ +SBB0, 32, /* PWM2 BAR0 */ +SCB0, 32, /* UART1 BAR0 */ +SDB0, 32, /* UART2 BAR0 */ +C0B0, 32, /* MMC BAR0 */ +C1B0, 32, /* SDIO BAR0 */ +C2B0, 32, /* SD Card BAR0 */ +LPB0, 32, /* LPE BAR0 */ /* BAR 1 */ -S0B1, 32, // SDMA BAR1 -S1B1, 32, // I2C1 BAR1 -S2B1, 32, // I2C2 BAR1 -S3B1, 32, // I2C3 BAR1 -S4B1, 32, // I2C4 BAR1 -S5B1, 32, // I2C5 BAR1 -S6B1, 32, // I2C6 BAR1 -S7B1, 32, // I2C7 BAR1 -S8B1, 32, // SDMA2 BAR1 -S9B1, 32, // SPI BAR1 -SAB1, 32, // PWM1 BAR1 -SBB1, 32, // PWM2 BAR1 -SCB1, 32, // UART1 BAR1 -SDB1, 32, // UART2 BAR1 -C0B1, 32, // MMC BAR1 -C1B1, 32, // SDIO BAR1 -C2B1, 32, // SD Card BAR1 -LPB1, 32, // LPE BAR1 +S0B1, 32, /* SDMA BAR1 */ +S1B1, 32, /* I2C1 BAR1 */ +S2B1, 32, /* I2C2 BAR1 */ +S3B1, 32, /* I2C3 BAR1 */ +S4B1, 32, /* I2C4 BAR1 */ +S5B1, 32, /* I2C5 BAR1 */ +S6B1, 32, /* I2C6 BAR1 */ +S7B1, 32, /* I2C7 BAR1 */ +S8B1, 32, /* SDMA2 BAR1 */ +S9B1, 32, /* SPI BAR1 */ +SAB1, 32, /* PWM1 BAR1 */ +SBB1, 32, /* PWM2 BAR1 */ +SCB1, 32, /* UART1 BAR1 */ +SDB1, 32, /* UART2 BAR1 */ +C0B1, 32, /* MMC BAR1 */ +C1B1, 32, /* SDIO BAR1 */ +C2B1, 32, /* SD Card BAR1 */ +LPB1, 32, /* LPE BAR1 */ /* Extra */ -LPFW, 32, // LPE BAR2 Firmware +LPFW, 32, /* LPE BAR2 Firmware */ diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl index 58c1c7b..9b1930b 100644 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -1,13 +1,13 @@ -External (\_PR.CP00._TSS, MethodObj) -External (\_PR.CP00._TPC, MethodObj) -External (\_PR.CP00._PTC, PkgObj) -External (\_PR.CP00._TSD, PkgObj) -External (\_PR.CP00._PSS, MethodObj) - -Device (TCPU) +External (\_PR.CPU0._TSS, MethodObj) +External (\_PR.CPU0._TPC, MethodObj) +External (\_PR.CPU0._PTC, PkgObj) +External (\_PR.CPU0._TSD, PkgObj) +External (\_PR.CPU0._PSS, MethodObj) +External (\_SB.DPTF.CTOK, MethodObj) + +Device (B0DB) { - Name (_HID, EISAID ("INT3401")) - Name (_UID, 0) + Name (_ADR, 0x000B0000) /* Bus 0, Device B, Function 0 */ Method (_STA) { @@ -24,8 +24,8 @@ Device (TCPU) Method (_TSS) { - If (CondRefOf (\_PR.CP00._TSS)) { - Return (\_PR.CP00._TSS) + If (CondRefOf (\_PR.CPU0._TSS)) { + Return (\_PR.CPU0._TSS) } Else { Return (Package () { @@ -36,8 +36,8 @@ Device (TCPU) Method (_TPC) { - If (CondRefOf (\_PR.CP00._TPC)) { - Return (\_PR.CP00._TPC) + If (CondRefOf (\_PR.CPU0._TPC)) { + Return (\_PR.CPU0._TPC) } Else { Return (0) } @@ -45,8 +45,8 @@ Device (TCPU) Method (_PTC) { - If (CondRefOf (\_PR.CP00._PTC)) { - Return (\_PR.CP00._PTC) + If (CondRefOf (\_PR.CPU0._PTC)) { + Return (\_PR.CPU0._PTC) } Else { Return (Package () { @@ -58,8 +58,8 @@ Device (TCPU) Method (_TSD) { - If (CondRefOf (\_PR.CP00._TSD)) { - Return (\_PR.CP00._TSD) + If (CondRefOf (\_PR.CPU0._TSD)) { + Return (\_PR.CPU0._TSD) } Else { Return (Package () { @@ -70,8 +70,8 @@ Device (TCPU) Method (_TDL) { - If (CondRefOf (\_PR.CP00._TSS)) { - Store (SizeOf (\_PR.CP00._TSS ()), Local0) + If (CondRefOf (\_PR.CPU0._TSS)) { + Store (SizeOf (\_PR.CPU0._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -98,8 +98,8 @@ Device (TCPU) Method (_PSS) { - If (CondRefOf (\_PR.CP00._PSS)) { - Return (\_PR.CP00._PSS) + If (CondRefOf (\_PR.CPU0._PSS)) { + Return (\_PR.CPU0._PSS) } Else { Return (Package () { @@ -113,8 +113,8 @@ Device (TCPU) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CP00._PSS)) { - Store (SizeOf (\_PR.CP00._PSS ()), Local0) + } ElseIf (CondRefOf (\_PR.CPU0._PSS)) { + Store (SizeOf (\_PR.CPU0._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -127,18 +127,52 @@ Device (TCPU) { Return (\_SB.MPPC) } - #ifdef DPTF_CPU_CRITICAL Method (_CRT) { - Return (^^CTOK (DPTF_CPU_CRITICAL)) + Return (\_SB.DPTF.CTOK(DPTF_CPU_CRITICAL)) } #endif #ifdef DPTF_CPU_PASSIVE Method (_PSV) { - Return (^^CTOK (DPTF_CPU_PASSIVE)) + Return (\_SB.DPTF.CTOK(DPTF_CPU_PASSIVE)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4)) } #endif } diff --git a/src/soc/intel/braswell/acpi/dptf/dptf.asl b/src/soc/intel/braswell/acpi/dptf/dptf.asl index 9ebfb8c..f8d8347 100644 --- a/src/soc/intel/braswell/acpi/dptf/dptf.asl +++ b/src/soc/intel/braswell/acpi/dptf/dptf.asl @@ -1,3 +1,4 @@ + Device (DPTF) { Name (_HID, EISAID ("INT3400")) @@ -24,7 +25,8 @@ Device (DPTF) } } - /* Arg0: Buffer containing UUID + /* + * Arg0: Buffer containing UUID * Arg1: Integer containing Revision ID of buffer format * Arg2: Integer containing count of entries in Arg3 * Arg3: Buffer containing list of DWORD capabilities @@ -65,9 +67,6 @@ Device (DPTF) Return (Local0) } - /* Include CPU Participant */ - #include "cpu.asl" - /* Include Thermal Participants */ #include "thermal.asl" @@ -75,4 +74,8 @@ Device (DPTF) /* Include Charger Participant */ #include "charger.asl" #endif + + /* Include Network Participants */ + #include "wifi.asl" + #include "wwan.asl" } diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl index 7113215..b123fb6 100644 --- a/src/soc/intel/braswell/acpi/dptf/thermal.asl +++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl @@ -60,12 +60,12 @@ Device (TSR0) Method (_PSV) { - Return (^^CTOK (DPTF_TSR0_PASSIVE)) + Return (CTOK (DPTF_TSR0_PASSIVE)) } Method (_CRT) { - Return (^^CTOK (DPTF_TSR0_CRITICAL)) + Return (CTOK (DPTF_TSR0_CRITICAL)) } Name (PATC, 2) @@ -116,12 +116,12 @@ Device (TSR1) Method (_PSV) { - Return (^^CTOK (DPTF_TSR1_PASSIVE)) + Return (CTOK (DPTF_TSR1_PASSIVE)) } Method (_CRT) { - Return (^^CTOK (DPTF_TSR1_CRITICAL)) + Return (CTOK (DPTF_TSR1_CRITICAL)) } Name (PATC, 2) @@ -172,12 +172,12 @@ Device (TSR2) Method (_PSV) { - Return (^^CTOK (DPTF_TSR2_PASSIVE)) + Return (CTOK (DPTF_TSR2_PASSIVE)) } Method (_CRT) { - Return (^^CTOK (DPTF_TSR2_CRITICAL)) + Return (CTOK (DPTF_TSR2_CRITICAL)) } Name (PATC, 2) diff --git a/src/soc/intel/braswell/acpi/dptf/wifi.asl b/src/soc/intel/braswell/acpi/dptf/wifi.asl new file mode 100644 index 0000000..28da69a --- /dev/null +++ b/src/soc/intel/braswell/acpi/dptf/wifi.asl @@ -0,0 +1,16 @@ +Device (WIFI) +{ + Name (_HID, "INT3408") + Name (_UID, 0) + Name (PTYP, 0x07) + Name (_STR, Unicode("WIFI wireless device")) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} diff --git a/src/soc/intel/braswell/acpi/dptf/wwan.asl b/src/soc/intel/braswell/acpi/dptf/wwan.asl new file mode 100644 index 0000000..f205b8a --- /dev/null +++ b/src/soc/intel/braswell/acpi/dptf/wwan.asl @@ -0,0 +1,16 @@ +Device (WWAN) +{ + Name (_HID, "INT3408") + Name (_UID, 0) + Name (PTYP, 0xF) + Name (_STR, Unicode("Wireless Wide Area Network")) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 36eb98f..fe131f9 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -20,9 +20,10 @@ /* Global Variables */ -Name(\PICM, 0) // IOAPIC/8259 +Name(\PICM, 0) /* IOAPIC/8259 */ -/* Global ACPI memory region. This region is used for passing information +/* + * Global ACPI memory region. This region is used for passing information * between coreboot (aka "the system bios"), ACPI, and the SMI handler. * Since we don't know where this will end up in memory at ACPI compile time, * we have to fix it up in coreboot's ACPI creation phase. @@ -34,48 +35,49 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ Offset (0x00), - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - PCNT, 8, // 0x11 - Processor count - TPMP, 8, // 0x12 - TPM Present and Enabled - TLVL, 8, // 0x13 - Throttle Level - PPCM, 8, // 0x14 - Maximum P-state usable by OS - PM1I, 32, // 0x15 - System Wake Source - PM1 Index + OSYS, 16, /* 0x00 - Operating System */ + SMIF, 8, /* 0x02 - SMI function */ + PRM0, 8, /* 0x03 - SMI function parameter */ + PRM1, 8, /* 0x04 - SMI function parameter */ + SCIF, 8, /* 0x05 - SCI function */ + PRM2, 8, /* 0x06 - SCI function parameter */ + PRM3, 8, /* 0x07 - SCI function parameter */ + LCKF, 8, /* 0x08 - Global Lock function for EC */ + PRM4, 8, /* 0x09 - Lock function parameter */ + PRM5, 8, /* 0x0a - Lock function parameter */ + P80D, 32, /* 0x0b - Debug port (IO 0x80) value */ + LIDS, 8, /* 0x0f - LID state (open = 1) */ + PWRS, 8, /* 0x10 - Power State (AC = 1) */ + PCNT, 8, /* 0x11 - Processor count */ + TPMP, 8, /* 0x12 - TPM Present and Enabled */ + TLVL, 8, /* 0x13 - Throttle Level */ + PPCM, 8, /* 0x14 - Maximum P-state usable by OS */ + PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */ + BDID, 8, /* 0x19 - Board ID */ /* Device Config */ Offset (0x20), - S5U0, 8, // 0x20 - Enable USB0 in S5 - S5U1, 8, // 0x21 - Enable USB1 in S5 - S3U0, 8, // 0x22 - Enable USB0 in S3 - S3U1, 8, // 0x23 - Enable USB1 in S3 - TACT, 8, // 0x24 - Thermal Active trip point - TPSV, 8, // 0x25 - Thermal Passive trip point - TCRT, 8, // 0x26 - Thermal Critical trip point - DPTE, 8, // 0x27 - Enable DPTF + S5U0, 8, /* 0x20 - Enable USB0 in S5 */ + S5U1, 8, /* 0x21 - Enable USB1 in S5 */ + S3U0, 8, /* 0x22 - Enable USB0 in S3 */ + S3U1, 8, /* 0x23 - Enable USB1 in S3 */ + TACT, 8, /* 0x24 - Thermal Active trip point */ + TPSV, 8, /* 0x25 - Thermal Passive trip point */ + TCRT, 8, /* 0x26 - Thermal Critical trip point */ + DPTE, 8, /* 0x27 - Enable DPTF */ /* Base addresses */ Offset (0x30), - CMEM, 32, // 0x30 - CBMEM TOC - TOLM, 32, // 0x34 - Top of Low Memory - CBMC, 32, // 0x38 - coreboot mem console pointer + CMEM, 32, /* 0x30 - CBMEM TOC */ + TOLM, 32, /* 0x34 - Top of Low Memory */ + CBMC, 32, /* 0x38 - coreboot mem console pointer */ /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> Offset (0x1000), - #include <soc/intel/baytrail/acpi/device_nvs.asl> + #include <soc/intel/braswell/acpi/device_nvs.asl> } /* Set flag to enable USB charging in S3 */ diff --git a/src/soc/intel/braswell/acpi/gpio.asl b/src/soc/intel/braswell/acpi/gpio.asl index abe5890..4f1114f 100644 --- a/src/soc/intel/braswell/acpi/gpio.asl +++ b/src/soc/intel/braswell/acpi/gpio.asl @@ -21,26 +21,26 @@ #include <soc/iomap.h> #include <soc/irq.h> -/* SouthCluster GPIO */ -Device (GPSC) +/* GPIO SouthWest Community */ +Device (GPSW) { - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") Name (_UID, 1) Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Memory32Fixed (ReadWrite, 0, 0x8000, RMEM) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) { - GPIO_SC_IRQ + GPIO_SW_IRQ } }) Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) + Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPSOUTHWEST, RBAS) Return (^RBUF) } @@ -50,26 +50,26 @@ Device (GPSC) } } -/* NorthCluster GPIO */ +/* GPIO North Community */ Device (GPNC) { - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") Name (_UID, 2) Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Memory32Fixed (ReadWrite, 0, 0x8000, RMEM) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) { - GPIO_NC_IRQ + GPIO_N_IRQ } }) Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) + Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPNORTH, RBAS) Return (^RBUF) } @@ -79,26 +79,55 @@ Device (GPNC) } } -/* SUS GPIO */ -Device (GPSS) +/* GPIO East Community */ +Device (GPEC) { - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") Name (_UID, 3) Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Memory32Fixed (ReadWrite, 0, 0x8000, RMEM) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) { - GPIO_SUS_IRQ + GPIO_E_IRQ } }) Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) + Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPEAST, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + Return (0xF) + } +} + +/* GPIO SouthEast Community */ +Device (GPSE) +{ + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") + Name (_UID, 4) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x8000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) + { + GPIO_SE_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPSOUTHEAST, RBAS) Return (^RBUF) } diff --git a/src/soc/intel/braswell/acpi/irqlinks.asl b/src/soc/intel/braswell/acpi/irqlinks.asl index acc03f0..cb45e13 100644 --- a/src/soc/intel/braswell/acpi/irqlinks.asl +++ b/src/soc/intel/braswell/acpi/irqlinks.asl @@ -23,20 +23,20 @@ Device (LNKA) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 1) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTA) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLA, ResourceTemplate() @@ -45,28 +45,28 @@ Device (LNKA) }) CreateWordField(RTLA, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTA + /* Set the bit from PRTA */ ShiftLeft(1, And(PRTA, 0x0f), IRQ0) Return (RTLA) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTA) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTA, 0x80)) { @@ -82,20 +82,20 @@ Device (LNKB) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 2) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTB) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLB, ResourceTemplate() @@ -104,28 +104,28 @@ Device (LNKB) }) CreateWordField(RTLB, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTB + /* Set the bit from PRTB */ ShiftLeft(1, And(PRTB, 0x0f), IRQ0) Return (RTLB) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTB) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTB, 0x80)) { @@ -141,20 +141,20 @@ Device (LNKC) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 3) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTC) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLC, ResourceTemplate() @@ -163,28 +163,28 @@ Device (LNKC) }) CreateWordField(RTLC, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTC + /* Set the bit from PRTC */ ShiftLeft(1, And(PRTC, 0x0f), IRQ0) Return (RTLC) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTC) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTC, 0x80)) { @@ -200,20 +200,20 @@ Device (LNKD) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 4) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTD) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLD, ResourceTemplate() @@ -222,28 +222,28 @@ Device (LNKD) }) CreateWordField(RTLD, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTD + /* Set the bit from PRTD */ ShiftLeft(1, And(PRTD, 0x0f), IRQ0) Return (RTLD) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTD) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTD, 0x80)) { @@ -259,20 +259,20 @@ Device (LNKE) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 5) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTE) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLE, ResourceTemplate() @@ -281,28 +281,28 @@ Device (LNKE) }) CreateWordField(RTLE, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTE + /* Set the bit from PRTE */ ShiftLeft(1, And(PRTE, 0x0f), IRQ0) Return (RTLE) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTE) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTE, 0x80)) { @@ -318,20 +318,20 @@ Device (LNKF) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 6) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTF) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLF, ResourceTemplate() @@ -340,28 +340,28 @@ Device (LNKF) }) CreateWordField(RTLF, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTF + /* Set the bit from PRTF */ ShiftLeft(1, And(PRTF, 0x0f), IRQ0) Return (RTLF) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTF) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTF, 0x80)) { @@ -377,20 +377,20 @@ Device (LNKG) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 7) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTG) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLG, ResourceTemplate() @@ -399,28 +399,28 @@ Device (LNKG) }) CreateWordField(RTLG, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTG + /* Set the bit from PRTG */ ShiftLeft(1, And(PRTG, 0x0f), IRQ0) Return (RTLG) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTG) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTG, 0x80)) { @@ -436,20 +436,20 @@ Device (LNKH) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 8) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTH) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLH, ResourceTemplate() @@ -458,28 +458,28 @@ Device (LNKH) }) CreateWordField(RTLH, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTH + /* Set the bit from PRTH */ ShiftLeft(1, And(PRTH, 0x0f), IRQ0) Return (RTLH) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTH) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTH, 0x80)) { @@ -489,3 +489,4 @@ Device (LNKH) } } } + diff --git a/src/soc/intel/braswell/acpi/irqroute.asl b/src/soc/intel/braswell/acpi/irqroute.asl index 3a0abe4..32c12ba 100644 --- a/src/soc/intel/braswell/acpi/irqroute.asl +++ b/src/soc/intel/braswell/acpi/irqroute.asl @@ -18,19 +18,19 @@ * Foundation, Inc. */ -// PCI Interrupt Routing +/* PCI Interrupt Routing */ Method(_PRT) { If (PICM) { Return (Package() { #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> + #include <soc/intel/braswell/acpi/irq_helper.h> PCI_DEV_PIRQ_ROUTES }) } Else { Return (Package() { #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> + #include <soc/intel/braswell/acpi/irq_helper.h> PCI_DEV_PIRQ_ROUTES }) } diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 8d48ed4..7fa48df 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -19,7 +19,7 @@ * Foundation, Inc. */ -// Intel LPC Bus Device - 0:1f.0 +/* Intel LPC Bus Device - 0:1f.0 */ Device (LPCB) { @@ -29,7 +29,7 @@ Device (LPCB) #include "acpi/ec.asl" - Device (DMAC) // DMA Controller + Device (DMAC) /* DMA Controller */ { Name(_HID, EISAID("PNP0200")) Name(_CRS, ResourceTemplate() @@ -42,7 +42,7 @@ Device (LPCB) }) } - Device (FWH) // Firmware Hub + Device (FWH) /* Firmware Hub */ { Name (_HID, EISAID("INT0800")) Name (_CRS, ResourceTemplate() @@ -56,9 +56,9 @@ Device (LPCB) Name (_HID, EISAID("PNP0103")) Name (_CID, 0x010CD041) - Method (_STA, 0) // Device Status + Method (_STA, 0) /* Device Status */ { - Return (0xf) // Enable and show device + Return (0xf) /* Enable and show device */ } Name(_CRS, ResourceTemplate() @@ -67,7 +67,7 @@ Device (LPCB) }) } - Device(PIC) // 8259 Interrupt Controller + Device(PIC) /* 8259 Interrupt Controller */ { Name(_HID,EISAID("PNP0000")) Name(_CRS, ResourceTemplate() @@ -93,20 +93,20 @@ Device (LPCB) }) } - Device(LDRC) // LPC device: Resource consumption + Device(LDRC) /* LPC device: Resource consumption */ { Name (_HID, EISAID("PNP0C02")) Name (_UID, 2) Name (RBUF, ResourceTemplate() { - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + IO (Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */ + IO (Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */ + IO (Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */ + IO (Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */ + IO (Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */ + IO (Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */ + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */ }) Method (_CRS, 0, NotSerialized) @@ -115,18 +115,20 @@ Device (LPCB) } } - Device (RTC) // Real Time Clock + Device (RTC) /* Real Time Clock */ { Name (_HID, EISAID("PNP0B00")) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } +/* + * Disable as Windows doesn't like it, and systems don't seem to use it. + * IRQNoFlags() { 8 } + */ }) } - Device (TIMR) // Intel 8254 timer + Device (TIMR) /* Intel 8254 timer */ { Name(_HID, EISAID("PNP0100")) Name(_CRS, ResourceTemplate() @@ -137,11 +139,11 @@ Device (LPCB) }) } - // Include mainboard's superio.asl file. + /* Include mainboard's superio.asl file. */ #include "acpi/superio.asl" #ifdef ENABLE_TPM - Device (TPM) // Trusted Platform Module + Device (TPM) /* Trusted Platform Module */ { Name(_HID, EISAID("IFX0102")) Name(_CID, 0x310cd041) diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl index 57fa465..001e63d 100644 --- a/src/soc/intel/braswell/acpi/lpe.asl +++ b/src/soc/intel/braswell/acpi/lpe.asl @@ -20,10 +20,10 @@ Device (LPEA) { - Name (_HID, "80860F28") - Name (_CID, "80860F28") + Name (_HID, "808622A8") + Name (_CID, "808622A8") Name (_UID, 1) - Name (_DDN, "Low Power Audio Controller") + Name (_DDN, "Intel(R) Low Power Audio Controller - 808622A8") Name (_PR0, Package () { PLPE }) Name (RBUF, ResourceTemplate() diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl index 2591aa1..ed1ba99 100644 --- a/src/soc/intel/braswell/acpi/lpss.asl +++ b/src/soc/intel/braswell/acpi/lpss.asl @@ -84,7 +84,7 @@ Device (SDM2) Device (I2C1) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 1) Name (_DDN, "I2C Controller #1") @@ -143,7 +143,7 @@ Device (I2C1) Device (I2C2) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 2) Name (_DDN, "I2C Controller #2") @@ -202,7 +202,7 @@ Device (I2C2) Device (I2C3) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 3) Name (_DDN, "I2C Controller #3") @@ -261,7 +261,7 @@ Device (I2C3) Device (I2C4) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 4) Name (_DDN, "I2C Controller #4") @@ -320,7 +320,7 @@ Device (I2C4) Device (I2C5) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 5) Name (_DDN, "I2C Controller #5") @@ -379,7 +379,7 @@ Device (I2C5) Device (I2C6) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 6) Name (_DDN, "I2C Controller #6") @@ -438,7 +438,7 @@ Device (I2C6) Device (I2C7) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 7) Name (_DDN, "I2C Controller #7") @@ -497,7 +497,7 @@ Device (I2C7) Device (SPI1) { - Name (_HID, "80860F0E") + Name (_HID, "8086228E") Name (_UID, 1) Name (_DDN, "SPI Controller #2") @@ -550,7 +550,7 @@ Device (SPI1) Device (PWM1) { - Name (_HID, "80860F09") + Name (_HID, "80862288") Name (_UID, 1) Name (_DDN, "PWM Controller #1") @@ -578,7 +578,7 @@ Device (PWM1) Device (PWM2) { - Name (_HID, "80860F09") + Name (_HID, "80862288") Name (_UID, 2) Name (_DDN, "PWM Controller #2") @@ -606,7 +606,7 @@ Device (PWM2) Device (UAR1) { - Name (_HID, "80860F0A") + Name (_HID, "8086228A") Name (_UID, 1) Name (_DDN, "HS-UART Controller #1") @@ -659,7 +659,7 @@ Device (UAR1) Device (UAR2) { - Name (_HID, "80860F0A") + Name (_HID, "8086228A") Name (_UID, 2) Name (_DDN, "HS-UART Controller #2") diff --git a/src/soc/intel/braswell/acpi/pcie.asl b/src/soc/intel/braswell/acpi/pcie.asl deleted file mode 100644 index c3f70cc..0000000 --- a/src/soc/intel/braswell/acpi/pcie.asl +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Intel SOC PCIe support */ - -Device (RP01) -{ - Name (_ADR, 0x001c0000) - - Method (_PRT) - { - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D) - }) - } Else { - Return (Package() { - #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D) - }) - } - } -} - -Device (RP02) -{ - Name (_ADR, 0x001c0001) - - Method (_PRT) - { - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A) - }) - } Else { - Return (Package() { - #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A) - }) - } - } -} - -Device (RP03) -{ - Name (_ADR, 0x001c0002) - - Method (_PRT) - { - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B) - }) - } Else { - Return (Package() { - #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B) - }) - } - } -} - -Device (RP04) -{ - Name (_ADR, 0x001c0003) - - Method (_PRT) - { - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C) - }) - } Else { - Return (Package() { - #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C) - }) - } - } -} diff --git a/src/soc/intel/braswell/acpi/platform.asl b/src/soc/intel/braswell/acpi/platform.asl index 6c27ec3..33be9ee 100644 --- a/src/soc/intel/braswell/acpi/platform.asl +++ b/src/soc/intel/braswell/acpi/platform.asl @@ -23,8 +23,8 @@ OperationRegion (APMP, SystemIO, 0xb2, 2) Field (APMP, ByteAcc, NoLock, Preserve) { - APMC, 8, // APM command - APMS, 8 // APM status + APMC, 8, /* APM command */ + APMS, 8 /* APM status */ } /* Port 80 POST */ @@ -38,12 +38,13 @@ Field (POST, ByteAcc, Lock, Preserve) /* SMI I/O Trap */ Method(TRAP, 1, Serialized) { - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ } -/* The _PIC method is called by the OS to choose between interrupt +/* + * The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. * * _PIC is called with a parameter of 0 for i8259 configuration and @@ -52,11 +53,12 @@ Method(TRAP, 1, Serialized) Method(_PIC, 1) { - // Remember the OS' IRQ routing choice. + /* Remember the OS' IRQ routing choice. */ Store(Arg0, PICM) } -/* The _PTS method (Prepare To Sleep) is called before the OS is +/* + * The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl index 3bf3f39f..3034d25 100644 --- a/src/soc/intel/braswell/acpi/scc.asl +++ b/src/soc/intel/braswell/acpi/scc.asl @@ -135,18 +135,18 @@ Device (SDIO) Device (SDCD) { - Name (_HID, "80860F16") + Name (_HID, "INT33BB") Name (_CID, "PNP0D40") Name (_UID, 3) Name (_DDN, "SD Card Controller") Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - SCC_SD_IRQ - } + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , , ) + {SCC_SD_IRQ} /* SD Card IRQ */ + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 10000, "\\_SB.GPSE", 0, ResourceConsumer, , ) + {SDCARD_CD} /* SE81 */ }) Method (_CRS) diff --git a/src/soc/intel/braswell/acpi/sleepstates.asl b/src/soc/intel/braswell/acpi/sleepstates.asl index fef196e..8da76b9 100644 --- a/src/soc/intel/braswell/acpi/sleepstates.asl +++ b/src/soc/intel/braswell/acpi/sleepstates.asl @@ -19,7 +19,7 @@ */ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) Name(\_S3, Package(){0x5,0x5,0x0,0x0}) Name(\_S4, Package(){0x6,0x6,0x0,0x0}) Name(\_S5, Package(){0x7,0x7,0x0,0x0}) + diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index a985f15..25e0bd8 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -23,16 +23,16 @@ Scope(\) { - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. + /* IO-Trap at 0x800. This is the ACPI->SMI communication interface. */ OperationRegion(IO_T, SystemIO, 0x800, 0x10) Field(IO_T, ByteAcc, NoLock, Preserve) { Offset(0x8), - TRP0, 8 // IO-Trap at 0x808 + TRP0, 8 /* IO-Trap at 0x808 */ } - // Intel Legacy Block + /* Intel Legacy Block */ OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) Field (ILBS, AnyAcc, NoLock, Preserve) { @@ -48,8 +48,8 @@ Scope(\) } } -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI +Name(_HID,EISAID("PNP0A08")) /* PCIe */ +Name(_CID,EISAID("PNP0A03")) /* PCI */ Name(_ADR, 0) Name(_BBN, 0) @@ -58,126 +58,125 @@ Method (_CRS, 0, Serialized) { Name (MCRS, ResourceTemplate() { - // Bus Numbers + /* Bus Numbers */ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - // IO Region 0 + /* IO Region 0 */ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - // PCI Config Space + /* PCI Config Space */ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - // IO Region 1 + /* IO Region 1 */ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - // VGA memory (0xa0000-0xbffff) + /* VGA memory (0xa0000-0xbffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, 0x00020000,,, ASEG) - // OPROM reserved (0xc0000-0xc3fff) + /* OPROM reserved (0xc0000-0xc3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, 0x00004000,,, OPR0) - // OPROM reserved (0xc4000-0xc7fff) + /* OPROM reserved (0xc4000-0xc7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, 0x00004000,,, OPR1) - // OPROM reserved (0xc8000-0xcbfff) + /* OPROM reserved (0xc8000-0xcbfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, 0x00004000,,, OPR2) - // OPROM reserved (0xcc000-0xcffff) + /* OPROM reserved (0xcc000-0xcffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, 0x00004000,,, OPR3) - // OPROM reserved (0xd0000-0xd3fff) + /* OPROM reserved (0xd0000-0xd3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, 0x00004000,,, OPR4) - // OPROM reserved (0xd4000-0xd7fff) + /* OPROM reserved (0xd4000-0xd7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, 0x00004000,,, OPR5) - // OPROM reserved (0xd8000-0xdbfff) + /* OPROM reserved (0xd8000-0xdbfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, 0x00004000,,, OPR6) - // OPROM reserved (0xdc000-0xdffff) + /* OPROM reserved (0xdc000-0xdffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, 0x00004000,,, OPR7) - // BIOS Extension (0xe0000-0xe3fff) + /* BIOS Extension (0xe0000-0xe3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, 0x00004000,,, ESG0) - // BIOS Extension (0xe4000-0xe7fff) + /* BIOS Extension (0xe4000-0xe7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, 0x00004000,,, ESG1) - // BIOS Extension (0xe8000-0xebfff) + /* BIOS Extension (0xe8000-0xebfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, 0x00004000,,, ESG2) - // BIOS Extension (0xec000-0xeffff) + /* BIOS Extension (0xec000-0xeffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000ec000, 0x000effff, 0x00000000, 0x00004000,,, ESG3) - // System BIOS (0xf0000-0xfffff) + /* System BIOS (0xf0000-0xfffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + /* PCI Memory Region (Top of memory-0xfeafffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PMEM) + 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000, + 0x00100000,,, PMEM) - // TPM Area (0xfed40000-0xfed44fff) + /* TPM Area (0xfed40000-0xfed44fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, 0x00005000,,, TPMR) }) - // Update PCI resource area + /* Update PCI resource area */ CreateDwordField(MCRS, PMEM._MIN, PMIN) CreateDwordField(MCRS, PMEM._MAX, PMAX) CreateDwordField(MCRS, PMEM._LEN, PLEN) - // TOLM is BMBOUND accessible from IOSF so is saved in NVS + /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ Store (\TOLM, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) Add (Subtract (PMAX, PMIN), 1, PLEN) Return (MCRS) @@ -200,7 +199,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) }) - // Current Resource Settings + /* Current Resource Settings */ Method (_CRS, 0, Serialized) { Return(PDRS) @@ -245,29 +244,26 @@ Device (IOSF) } } -// LPC Bridge 0:1f.0 +/* LPC Bridge 0:1f.0 */ #include "lpc.asl" -// USB XHCI 0:14.0 +/* USB XHCI 0:14.0 */ #include "xhci.asl" -// IRQ routing for each PCI device +/* IRQ routing for each PCI device */ #include "irqroute.asl" -// PCI Express Ports 0:1c.x -#include "pcie.asl" - Scope (\_SB) { - // GPIO Devices + /* GPIO Devices */ #include "gpio.asl" - // LPSS Devices + /* LPSS Devices */ #include "lpss.asl" - // SCC Devices + /* SCC Devices */ #include "scc.asl" - // LPE Device + /* LPE Device */ #include "lpe.asl" } diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc index 3a40251..17d1ee8 100644 --- a/src/soc/intel/braswell/bootblock/Makefile.inc +++ b/src/soc/intel/braswell/bootblock/Makefile.inc @@ -1 +1 @@ -chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc +chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 6d31add..f98f694 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -54,10 +55,12 @@ static void setup_mmconfig(void) { uint32_t reg; - /* Set up the MMCONF range. The register lives in the BUNIT. The + /* + * Set up the MMCONF range. The register lives in the BUNIT. The * IO variant of the config access needs to be used initially to * properly configure as the IOSF access registers live in PCI - * config space. */ + * config space. + */ reg = 0; /* Clear the extended register. */ pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); diff --git a/src/soc/intel/braswell/bootblock/timestamp.inc b/src/soc/intel/braswell/bootblock/timestamp.inc index 3db5c35..e504132 100644 --- a/src/soc/intel/braswell/bootblock/timestamp.inc +++ b/src/soc/intel/braswell/bootblock/timestamp.inc @@ -1,6 +1,8 @@ -/* Store the initial timestamp for booting in mmx registers. This works +/* + * Store the initial timestamp for booting in mmx registers. This works * because the bootblock isn't being compiled with MMX support so mm0 and - * mm1 will be preserved into romstage. */ + * mm1 will be preserved into romstage. + */ .code32 .global stash_timestamp @@ -16,3 +18,4 @@ stash_timestamp: /* Restore the BIST value to %eax */ movl %ebp, %eax + diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index ecacd5f..c986507 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,17 +18,18 @@ * Foundation, Inc. */ +#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <arch/pci_ops.h> - +#include <fsp_util.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include "chip.h" static void pci_domain_set_resources(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); assign_resources(dev->link_list); } @@ -40,17 +42,35 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; +static void cpu_bus_noop(device_t dev) { } + static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = baytrail_init_cpus, - .scan_bus = NULL, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = soc_init_cpus }; static void enable_dev(device_t dev) { + printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n", + __FILE__, __func__, + dev_name(dev), dev->path.type); + printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n", + pci_read_config16(dev, PCI_VENDOR_ID), + pci_read_config16(dev, PCI_DEVICE_ID)); + printk(BIOS_SPEW, "class: 0x%02x %s\n" + "subclass: 0x%02x %s\n" + "prog: 0x%02x\n" + "revision: 0x%02x\n", + pci_read_config16(dev, PCI_CLASS_DEVICE) >> 8, + get_pci_class_name(dev), + pci_read_config16(dev, PCI_CLASS_DEVICE) & 0xff, + get_pci_subclass_name(dev), + pci_read_config8(dev, PCI_CLASS_PROG), + pci_read_config8(dev, PCI_REVISION_ID)); + /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; @@ -65,20 +85,258 @@ static void enable_dev(device_t dev) } } +void soc_silicon_init_params(SILICON_INIT_UPD *params) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct soc_intel_braswell_config *config = dev->chip_info; + + /* Set the parameters for SiliconInit */ + printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n"); + params->PcdSdcardMode = config->PcdSdcardMode; + params->PcdEnableHsuart0 = config->PcdEnableHsuart0; + params->PcdEnableHsuart1 = config->PcdEnableHsuart1; + params->PcdEnableAzalia = config->PcdEnableAzalia; + params->AzaliaConfigPtr = config->AzaliaConfigPtr; + params->PcdEnableSata = config->PcdEnableSata; + params->PcdEnableXhci = config->PcdEnableXhci; + params->PcdEnableLpe = config->PcdEnableLpe; + params->PcdEnableDma0 = config->PcdEnableDma0; + params->PcdEnableDma1 = config->PcdEnableDma1; + params->PcdEnableI2C0 = config->PcdEnableI2C0; + params->PcdEnableI2C1 = config->PcdEnableI2C1; + params->PcdEnableI2C2 = config->PcdEnableI2C2; + params->PcdEnableI2C3 = config->PcdEnableI2C3; + params->PcdEnableI2C4 = config->PcdEnableI2C4; + params->PcdEnableI2C5 = config->PcdEnableI2C5; + params->PcdEnableI2C6 = config->PcdEnableI2C6; + params->PcdGraphicsConfigPtr = config->PcdGraphicsConfigPtr; + params->PunitPwrConfigDisable = config->PunitPwrConfigDisable; + params->ChvSvidConfig = config->ChvSvidConfig; + params->DptfDisable = config->DptfDisable; + params->PcdEmmcMode = config->PcdEmmcMode; + params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc; + params->PcdDispClkSsc = config->PcdDispClkSsc; + params->PcdSataClkSsc = config->PcdSataClkSsc; + params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet; + params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; + params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn; + params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf; + params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet; + params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet; + params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn; + params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf; + params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet; + params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet; + params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn; + params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf; + params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet; + params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet; + params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn; + params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf; + params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet; + params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet; + params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn; + params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf; + params->Usb3Lane0Ow2tapgen2deemph3p5 = + config->Usb3Lane0Ow2tapgen2deemph3p5; + params->Usb3Lane1Ow2tapgen2deemph3p5 = + config->Usb3Lane1Ow2tapgen2deemph3p5; + params->Usb3Lane2Ow2tapgen2deemph3p5 = + config->Usb3Lane2Ow2tapgen2deemph3p5; + params->Usb3Lane3Ow2tapgen2deemph3p5 = + config->Usb3Lane3Ow2tapgen2deemph3p5; + params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed; + params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort; + params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort; + params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed; + params->PcdPchSsicEnable = config->PcdPchSsicEnable; + params->PcdLogoPtr = config->PcdLogoPtr; + params->PcdLogoSize = config->PcdLogoSize; + params->PcdRtcLock = config->PcdRtcLock; + params->PMIC_I2CBus = config->PMIC_I2CBus; + params->ISPEnable = config->ISPEnable; + params->ISPPciDevConfig = config->ISPPciDevConfig; +} + +void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, + SILICON_INIT_UPD *new) +{ + /* Display the parameters for SiliconInit */ + printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); + soc_display_upd_value("PcdSdcardMode", 1, old->PcdSdcardMode, + new->PcdSdcardMode); + soc_display_upd_value("PcdEnableHsuart0", 1, old->PcdEnableHsuart0, + new->PcdEnableHsuart0); + soc_display_upd_value("PcdEnableHsuart1", 1, old->PcdEnableHsuart1, + new->PcdEnableHsuart1); + soc_display_upd_value("PcdEnableAzalia", 1, old->PcdEnableAzalia, + new->PcdEnableAzalia); + soc_display_upd_value("AzaliaVerbTablePtr", 4, + (uint32_t)old->AzaliaVerbTablePtr, + (uint32_t)new->AzaliaVerbTablePtr); + soc_display_upd_value("AzaliaConfigPtr", 4, old->AzaliaConfigPtr, + new->AzaliaConfigPtr); + soc_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata, + new->PcdEnableSata); + soc_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci, + new->PcdEnableXhci); + soc_display_upd_value("PcdEnableLpe", 1, old->PcdEnableLpe, + new->PcdEnableLpe); + soc_display_upd_value("PcdEnableDma0", 1, old->PcdEnableDma0, + new->PcdEnableDma0); + soc_display_upd_value("PcdEnableDma1", 1, old->PcdEnableDma1, + new->PcdEnableDma1); + soc_display_upd_value("PcdEnableI2C0", 1, old->PcdEnableI2C0, + new->PcdEnableI2C0); + soc_display_upd_value("PcdEnableI2C1", 1, old->PcdEnableI2C1, + new->PcdEnableI2C1); + soc_display_upd_value("PcdEnableI2C2", 1, old->PcdEnableI2C2, + new->PcdEnableI2C2); + soc_display_upd_value("PcdEnableI2C3", 1, old->PcdEnableI2C3, + new->PcdEnableI2C3); + soc_display_upd_value("PcdEnableI2C4", 1, old->PcdEnableI2C4, + new->PcdEnableI2C4); + soc_display_upd_value("PcdEnableI2C5", 1, old->PcdEnableI2C5, + new->PcdEnableI2C5); + soc_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6, + new->PcdEnableI2C6); + soc_display_upd_value("PcdGraphicsConfigPtr", 4, + old->PcdGraphicsConfigPtr, new->PcdGraphicsConfigPtr); + soc_display_upd_value("GpioFamilyInitTablePtr", 4, + (uint32_t)old->GpioFamilyInitTablePtr, + (uint32_t)new->GpioFamilyInitTablePtr); + soc_display_upd_value("GpioPadInitTablePtr", 4, + (uint32_t)old->GpioPadInitTablePtr, + (uint32_t)new->GpioPadInitTablePtr); + soc_display_upd_value("PunitPwrConfigDisable", 1, + old->PunitPwrConfigDisable, + new->PunitPwrConfigDisable); + soc_display_upd_value("ChvSvidConfig", 1, old->ChvSvidConfig, + new->ChvSvidConfig); + soc_display_upd_value("DptfDisable", 1, old->DptfDisable, + new->DptfDisable); + soc_display_upd_value("PcdEmmcMode", 1, old->PcdEmmcMode, + new->PcdEmmcMode); + soc_display_upd_value("PcdUsb3ClkSsc", 1, old->PcdUsb3ClkSsc, + new->PcdUsb3ClkSsc); + soc_display_upd_value("PcdDispClkSsc", 1, old->PcdDispClkSsc, + new->PcdDispClkSsc); + soc_display_upd_value("PcdSataClkSsc", 1, old->PcdSataClkSsc, + new->PcdSataClkSsc); + soc_display_upd_value("Usb2Port0PerPortPeTxiSet", 1, + old->Usb2Port0PerPortPeTxiSet, + new->Usb2Port0PerPortPeTxiSet); + soc_display_upd_value("Usb2Port0PerPortTxiSet", 1, + old->Usb2Port0PerPortTxiSet, + new->Usb2Port0PerPortTxiSet); + soc_display_upd_value("Usb2Port0IUsbTxEmphasisEn", 1, + old->Usb2Port0IUsbTxEmphasisEn, + new->Usb2Port0IUsbTxEmphasisEn); + soc_display_upd_value("Usb2Port0PerPortTxPeHalf", 1, + old->Usb2Port0PerPortTxPeHalf, + new->Usb2Port0PerPortTxPeHalf); + soc_display_upd_value("Usb2Port1PerPortPeTxiSet", 1, + old->Usb2Port1PerPortPeTxiSet, + new->Usb2Port1PerPortPeTxiSet); + soc_display_upd_value("Usb2Port1PerPortTxiSet", 1, + old->Usb2Port1PerPortTxiSet, + new->Usb2Port1PerPortTxiSet); + soc_display_upd_value("Usb2Port1IUsbTxEmphasisEn", 1, + old->Usb2Port1IUsbTxEmphasisEn, + new->Usb2Port1IUsbTxEmphasisEn); + soc_display_upd_value("Usb2Port1PerPortTxPeHalf", 1, + old->Usb2Port1PerPortTxPeHalf, + new->Usb2Port1PerPortTxPeHalf); + soc_display_upd_value("Usb2Port2PerPortPeTxiSet", 1, + old->Usb2Port2PerPortPeTxiSet, + new->Usb2Port2PerPortPeTxiSet); + soc_display_upd_value("Usb2Port2PerPortTxiSet", 1, + old->Usb2Port2PerPortTxiSet, + new->Usb2Port2PerPortTxiSet); + soc_display_upd_value("Usb2Port2IUsbTxEmphasisEn", 1, + old->Usb2Port2IUsbTxEmphasisEn, + new->Usb2Port2IUsbTxEmphasisEn); + soc_display_upd_value("Usb2Port2PerPortTxPeHalf", 1, + old->Usb2Port2PerPortTxPeHalf, + new->Usb2Port2PerPortTxPeHalf); + soc_display_upd_value("Usb2Port3PerPortPeTxiSet", 1, + old->Usb2Port3PerPortPeTxiSet, + new->Usb2Port3PerPortPeTxiSet); + soc_display_upd_value("Usb2Port3PerPortTxiSet", 1, + old->Usb2Port3PerPortTxiSet, + new->Usb2Port3PerPortTxiSet); + soc_display_upd_value("Usb2Port3IUsbTxEmphasisEn", 1, + old->Usb2Port3IUsbTxEmphasisEn, + new->Usb2Port3IUsbTxEmphasisEn); + soc_display_upd_value("Usb2Port3PerPortTxPeHalf", 1, + old->Usb2Port3PerPortTxPeHalf, + new->Usb2Port3PerPortTxPeHalf); + soc_display_upd_value("Usb2Port4PerPortPeTxiSet", 1, + old->Usb2Port4PerPortPeTxiSet, + new->Usb2Port4PerPortPeTxiSet); + soc_display_upd_value("Usb2Port4PerPortTxiSet", 1, + old->Usb2Port4PerPortTxiSet, + new->Usb2Port4PerPortTxiSet); + soc_display_upd_value("Usb2Port4IUsbTxEmphasisEn", 1, + old->Usb2Port4IUsbTxEmphasisEn, + new->Usb2Port4IUsbTxEmphasisEn); + soc_display_upd_value("Usb2Port4PerPortTxPeHalf", 1, + old->Usb2Port4PerPortTxPeHalf, + new->Usb2Port4PerPortTxPeHalf); + soc_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1, + old->Usb3Lane0Ow2tapgen2deemph3p5, + new->Usb3Lane0Ow2tapgen2deemph3p5); + soc_display_upd_value("Usb3Lane1Ow2tapgen2deemph3p5", 1, + old->Usb3Lane1Ow2tapgen2deemph3p5, + new->Usb3Lane1Ow2tapgen2deemph3p5); + soc_display_upd_value("Usb3Lane2Ow2tapgen2deemph3p5", 1, + old->Usb3Lane2Ow2tapgen2deemph3p5, + new->Usb3Lane2Ow2tapgen2deemph3p5); + soc_display_upd_value("Usb3Lane3Ow2tapgen2deemph3p5", 1, + old->Usb3Lane3Ow2tapgen2deemph3p5, + new->Usb3Lane3Ow2tapgen2deemph3p5); + soc_display_upd_value("PcdSataInterfaceSpeed", 1, + old->PcdSataInterfaceSpeed, + new->PcdSataInterfaceSpeed); + soc_display_upd_value("PcdPchUsbSsicPort", 1, + old->PcdPchUsbSsicPort, new->PcdPchUsbSsicPort); + soc_display_upd_value("PcdPchUsbHsicPort", 1, + old->PcdPchUsbHsicPort, new->PcdPchUsbHsicPort); + soc_display_upd_value("PcdPcieRootPortSpeed", 1, + old->PcdPcieRootPortSpeed, new->PcdPcieRootPortSpeed); + soc_display_upd_value("PcdPchSsicEnable", 1, old->PcdPchSsicEnable, + new->PcdPchSsicEnable); + soc_display_upd_value("PcdLogoPtr", 4, old->PcdLogoPtr, + new->PcdLogoPtr); + soc_display_upd_value("PcdLogoSize", 4, old->PcdLogoSize, + new->PcdLogoSize); + soc_display_upd_value("PcdRtcLock", 1, old->PcdRtcLock, + new->PcdRtcLock); + soc_display_upd_value("PMIC_I2CBus", 1, + old->PMIC_I2CBus, new->PMIC_I2CBus); + soc_display_upd_value("ISPEnable", 1, + old->ISPEnable, new->ISPEnable); + soc_display_upd_value("ISPPciDevConfig", 1, + old->ISPPciDevConfig, new->ISPPciDevConfig); +} + /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ static void soc_init(void *chip_info) { - baytrail_init_pre_device(chip_info); + printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__); + soc_init_pre_device(chip_info); } -struct chip_operations soc_intel_baytrail_ops = { - CHIP_NAME("Intel BayTrail SoC") +struct chip_operations soc_intel_braswell_ops = { + CHIP_NAME("Intel Braswell SoC") .enable_dev = enable_dev, .init = soc_init, }; static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { + printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", + __FILE__, __func__, dev_name(dev), vendor, device); if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_read_config32(dev, PCI_VENDOR_ID)); diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index ffcf54c..fde508c 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,46 +18,28 @@ * Foundation, Inc. */ -/* The devicetree parser expects chip.h to reside directly in the path - * specified by the devicetree. */ +/* + * The devicetree parser expects chip.h to reside directly in the path + * specified by the devicetree. + */ -#ifndef _BAYTRAIL_CHIP_H_ -#define _BAYTRAIL_CHIP_H_ +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ #include <stdint.h> +#include <fsp_util.h> +#include <soc/pci_devs.h> + +#define SVID_CONFIG1 1 +#define SVID_CONFIG3 3 -struct soc_intel_baytrail_config { +struct soc_intel_braswell_config { uint8_t enable_xdp_tap; - uint8_t sata_port_map; - uint8_t sata_ahci; - uint8_t ide_legacy_combined; uint8_t clkreq_enable; - /* VR low power settings -- enable PS2 mode for gfx and core */ - int vnn_ps2_enable; - int vcc_ps2_enable; - /* Disable SLP_X stretching after SUS power well loss. */ int disable_slp_x_stretch_sus_fail; - /* USB Port Disable mask */ - uint16_t usb2_port_disable_mask; - uint16_t usb3_port_disable_mask; - - /* USB routing */ - int usb_route_to_xhci; - - /* USB PHY settings specific to the board */ - uint32_t usb2_per_port_lane0; - uint32_t usb2_per_port_rcomp_hs_pullup0; - uint32_t usb2_per_port_lane1; - uint32_t usb2_per_port_rcomp_hs_pullup1; - uint32_t usb2_per_port_lane2; - uint32_t usb2_per_port_rcomp_hs_pullup2; - uint32_t usb2_per_port_lane3; - uint32_t usb2_per_port_rcomp_hs_pullup3; - uint32_t usb2_comp_bg; - /* LPE Audio Clock configuration. */ int lpe_codec_clk_freq; /* 19 or 25 are valid. */ int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ @@ -67,29 +50,94 @@ struct soc_intel_baytrail_config { /* Enable devices in ACPI mode */ int lpss_acpi_mode; - int scc_acpi_mode; + int emmc_acpi_mode; + int sd_acpi_mode; int lpe_acpi_mode; /* Allow PCIe devices to wake system from suspend. */ int pcie_wake_enable; - int gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */ - uint16_t gpu_pipea_power_on_delay; - uint16_t gpu_pipea_light_on_delay; - uint16_t gpu_pipea_power_off_delay; - uint16_t gpu_pipea_light_off_delay; - uint16_t gpu_pipea_power_cycle_delay; - int gpu_pipea_pwm_freq_hz; - - int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */ - uint16_t gpu_pipeb_power_on_delay; - uint16_t gpu_pipeb_light_on_delay; - uint16_t gpu_pipeb_power_off_delay; - uint16_t gpu_pipeb_light_off_delay; - uint16_t gpu_pipeb_power_cycle_delay; - int gpu_pipeb_pwm_freq_hz; - int disable_ddr_2x_refresh_rate; + /* + * The following fields come from fsp_vpd.h .aka. VpdHeader.h. + * These are configuration values that are passed to FSP during + * MemoryInit. + */ + UINT16 PcdMrcInitTsegSize; + UINT16 PcdMrcInitMmioSize; + UINT8 PcdMrcInitSpdAddr1; + UINT8 PcdMrcInitSpdAddr2; + UINT8 PcdIgdDvmt50PreAlloc; + UINT8 PcdApertureSize; + UINT8 PcdGttSize; + UINT8 PcdLegacySegDecode; + + /* + * The following fields come from fsp_vpd.h .aka. VpdHeader.h. + * These are configuration values that are passed to FSP during + * SiliconInit. + */ + UINT8 PcdSdcardMode; + UINT8 PcdEnableHsuart0; + UINT8 PcdEnableHsuart1; + UINT8 PcdEnableAzalia; + UINT32 AzaliaConfigPtr; + UINT8 PcdEnableSata; + UINT8 PcdEnableXhci; + UINT8 PcdEnableLpe; + UINT8 PcdEnableDma0; + UINT8 PcdEnableDma1; + UINT8 PcdEnableI2C0; + UINT8 PcdEnableI2C1; + UINT8 PcdEnableI2C2; + UINT8 PcdEnableI2C3; + UINT8 PcdEnableI2C4; + UINT8 PcdEnableI2C5; + UINT8 PcdEnableI2C6; + UINT32 PcdGraphicsConfigPtr; + UINT8 PunitPwrConfigDisable; + UINT8 ChvSvidConfig; + UINT8 DptfDisable; + UINT8 PcdEmmcMode; + UINT8 PcdUsb3ClkSsc; + UINT8 PcdDispClkSsc; + UINT8 PcdSataClkSsc; + UINT8 Usb2Port0PerPortPeTxiSet; + UINT8 Usb2Port0PerPortTxiSet; + UINT8 Usb2Port0IUsbTxEmphasisEn; + UINT8 Usb2Port0PerPortTxPeHalf; + UINT8 Usb2Port1PerPortPeTxiSet; + UINT8 Usb2Port1PerPortTxiSet; + UINT8 Usb2Port1IUsbTxEmphasisEn; + UINT8 Usb2Port1PerPortTxPeHalf; + UINT8 Usb2Port2PerPortPeTxiSet; + UINT8 Usb2Port2PerPortTxiSet; + UINT8 Usb2Port2IUsbTxEmphasisEn; + UINT8 Usb2Port2PerPortTxPeHalf; + UINT8 Usb2Port3PerPortPeTxiSet; + UINT8 Usb2Port3PerPortTxiSet; + UINT8 Usb2Port3IUsbTxEmphasisEn; + UINT8 Usb2Port3PerPortTxPeHalf; + UINT8 Usb2Port4PerPortPeTxiSet; + UINT8 Usb2Port4PerPortTxiSet; + UINT8 Usb2Port4IUsbTxEmphasisEn; + UINT8 Usb2Port4PerPortTxPeHalf; + UINT8 Usb3Lane0Ow2tapgen2deemph3p5; + UINT8 Usb3Lane1Ow2tapgen2deemph3p5; + UINT8 Usb3Lane2Ow2tapgen2deemph3p5; + UINT8 Usb3Lane3Ow2tapgen2deemph3p5; + UINT8 PcdSataInterfaceSpeed; + UINT8 PcdPchUsbSsicPort; + UINT8 PcdPchUsbHsicPort; + UINT8 PcdPcieRootPortSpeed; + UINT8 PcdPchSsicEnable; + UINT32 PcdLogoPtr; + UINT32 PcdLogoSize; + UINT8 PcdRtcLock; + UINT8 PMIC_I2CBus; + UINT8 ISPEnable; + UINT8 ISPPciDevConfig; }; -extern struct chip_operations soc_intel_baytrail_ops; -#endif /* _BAYTRAIL_CHIP_H_ */ +extern struct chip_operations soc_intel_braswell_ops; + +#endif /* _SOC_CHIP_H_ */ diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 6b84c59..3abec6b 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,7 +18,6 @@ * Foundation, Inc. */ -#include <stdlib.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/intel/microcode.h> @@ -28,64 +28,42 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -#include <reg_script.h> - -#include <soc/iosf.h> +#include <soc/intel/common/memmap.h> #include <soc/msr.h> #include <soc/pattrs.h> #include <soc/ramstage.h> #include <soc/smm.h> +#include <stdlib.h> static void smm_relocate(void *unused); static void enable_smis(void *unused); +static void pre_smm_relocation(void *unused); static struct mp_flight_record mp_steps[] = { + MP_FR_BLOCK_APS(pre_smm_relocation, NULL, pre_smm_relocation, NULL), MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL), MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), /* Wait for APs to finish initialization before proceeding. */ MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), }; -/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ +/* The APIC id space is sparse. Each id is separated by 2. */ static int adjust_apic_id(int index, int apic_id) { return 2 * index; } -/* Package level MSRs */ -const struct reg_script package_msr_script[] = { - /* Set Package TDP to ~7W */ - REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa), - REG_MSR_RMW(MSR_PP1_POWER_LIMIT, ~(0x7f << 17), 0), - REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702), - REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b), - REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0), - REG_MSR_WRITE(MSR_CPU_THERM_CFG1, 0x00000305), - REG_MSR_WRITE(MSR_CPU_THERM_CFG2, 0x0405500d), - REG_MSR_WRITE(MSR_CPU_THERM_SENS_CFG, 0x27), - REG_SCRIPT_END -}; -/* Core level MSRs */ -const struct reg_script core_msr_script[] = { - /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), - REG_MSR_RMW(MSR_POWER_MISC, - ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), - /* Disable C1E */ - REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), - REG_MSR_OR(MSR_POWER_MISC, 0x44), - REG_SCRIPT_END -}; - -void baytrail_init_cpus(device_t dev) +void soc_init_cpus(device_t dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); struct mp_params mp_params; - uint32_t bsmrwac; void *default_smm_area; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + /* Set up MTRRs based on physical address size. */ x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(pattrs->address_bits, 2); @@ -100,52 +78,22 @@ void baytrail_init_cpus(device_t dev) default_smm_area = backup_default_smm_area(); - /* - * Configure the BUNIT to allow dirty cache line evictions in non-SMM - * mode for the lines that were dirtied while in SMM mode. Otherwise - * the writes would be silently dropped. - */ - bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; - iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); - - /* Set package MSRs */ - reg_script_run(package_msr_script); - - /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */ enable_turbo(); - if (mp_init(cpu_bus, &mp_params)) { + if (mp_init(cpu_bus, &mp_params)) printk(BIOS_ERR, "MP initialization failure.\n"); - } restore_default_smm_area(default_smm_area); } -static void baytrail_core_init(device_t cpu) -{ - printk(BIOS_DEBUG, "Init BayTrail core.\n"); - - /* On bay trail the turbo disable bit is actually scoped at building - * block level -- not package. For non-bsp cores that are within a - * building block enable turbo. The cores within the BSP's building - * block will just see it already enabled and move on. */ - if (lapicid()) - enable_turbo(); - - /* Set core MSRs */ - reg_script_run(core_msr_script); - - /* Set this core to max frequency ratio */ - set_max_freq(); -} static struct device_operations cpu_dev_ops = { - .init = baytrail_core_init, + .init = NULL, }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x30673 }, - { X86_VENDOR_INTEL, 0x30678 }, + { X86_VENDOR_INTEL, 0x406C3 }, + { X86_VENDOR_INTEL, 0x406C2 }, { 0, 0 }, }; @@ -202,9 +150,11 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) smrr.hi = 0; wrmsr(SMRRphysMask_MSR, smrr); - /* The relocated handler runs with all CPUs concurrently. Therefore + /* + * The relocated handler runs with all CPUs concurrently. Therefore * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ + * size * CPU num. + */ smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + runtime->smbase); smm_state->smbase = relo_attrs.smbase - cpu * runtime->save_state_size; printk(BIOS_DEBUG, "New SMBASE 0x%08x\n", smm_state->smbase); @@ -232,8 +182,10 @@ static int install_relocation_handler(int num_cpus) static int install_permanent_handler(int num_cpus) { - /* There are num_cpus concurrent stacks and num_cpus concurrent save - * state areas. Lastly, set the stack size to the save state size. */ + /* + * There are num_cpus concurrent stacks and num_cpus concurrent save + * state areas. Lastly, set the stack size to the save state size. + */ int save_state_size = sizeof(em64t100_smm_state_save_area_t); struct smm_loader_params smm_params = { .per_cpu_stack_size = save_state_size, @@ -241,11 +193,15 @@ static int install_permanent_handler(int num_cpus) .per_cpu_save_state_size = save_state_size, .num_concurrent_save_states = num_cpus, }; - const int tseg_size = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; + void *smm_base; + size_t smm_size; + int tseg_size; printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", relo_attrs.smbase); + smm_region(&smm_base, &smm_size); + tseg_size = smm_size - CONFIG_SMM_RESERVED_SIZE; if (smm_load_module((void *)relo_attrs.smbase, tseg_size, &smm_params)) return -1; @@ -259,11 +215,14 @@ static int smm_load_handlers(void) /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); const struct pattrs *pattrs = pattrs_get(); + void *smm_base; + size_t smm_size; /* Initialize global tracking state. */ - relo_attrs.smbase = (uint32_t)smm_region_start(); + smm_region(&smm_base, &smm_size); + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; - relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; + relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRRphysMaskValid; /* Install handlers. */ @@ -283,6 +242,17 @@ static int smm_load_handlers(void) return 0; } +static void pre_smm_relocation(void *unused) +{ + const struct pattrs *pattrs = pattrs_get(); + msr_t msr_value; + + /* Need to make sure that all cores have microcode loaded. */ + msr_value = rdmsr(MSR_IA32_BIOS_SIGN_ID); + if (msr_value.hi == 0) + intel_microcode_load_unlocked(pattrs->microcode_patch); +} + static void smm_relocate(void *unused) { const struct pattrs *pattrs = pattrs_get(); diff --git a/src/soc/intel/braswell/dptf.c b/src/soc/intel/braswell/dptf.c deleted file mode 100644 index 79a000d..0000000 --- a/src/soc/intel/braswell/dptf.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <bootstate.h> -#include <console/console.h> -#include <reg_script.h> -#include <soc/iosf.h> - -static const struct reg_script dptf_init_settings[] = { - /* SocThermInit */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTMC, 0x00030708), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 0x00000000), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029), - /* ratio 11 = 1466mhz for mid and entry celeron */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000B00), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002), - REG_SCRIPT_END, -}; - -static void dptf_init(void *unused) -{ - printk(BIOS_DEBUG, "Applying SOC Thermal settings for DPTF.\n"); - reg_script_run(dptf_init_settings); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL); diff --git a/src/soc/intel/braswell/ehci.c b/src/soc/intel/braswell/ehci.c deleted file mode 100644 index fce1ba7..0000000 --- a/src/soc/intel/braswell/ehci.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/acpi.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <reg_script.h> - -#include <soc/iomap.h> -#include <soc/iosf.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> -#include <soc/ramstage.h> -#include <soc/ehci.h> - -#include "chip.h" - -static const struct reg_script ehci_init_script[] = { - /* Enable S0 PLL shutdown - * D29:F0:7A[12,10,7,6,4,3,2,1]=11111111b */ - REG_PCI_OR16(0x7a, 0x14de), - /* Enable SB local clock gating - * D29:F0:7C[14,3,2]=111b (14 set in clock gating step) */ - REG_PCI_OR32(0x7c, 0x0000000c), - REG_PCI_OR32(0x8c, 0x00000001), - /* Enable dynamic clock gating 0x4001=0xCE */ - REG_IOSF_RMW(IOSF_PORT_USBPHY, 0x4001, 0xFFFFFF00, 0xCE), - /* Magic RCBA register set sequence */ - /* RCBA + 0x200=0x1 */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x200, 0x00000001), - /* RCBA + 0x204=0x2 */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x204, 0x00000002), - /* RCBA + 0x208=0x0 */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x208, 0x00000000), - /* RCBA + 0x240[4,3,2,1,0]=00000b */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x240, ~0x0000001f, 0), - /* RCBA + 0x318[9,8,6,5,4,3,2,1,0]=000000111b */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x318, ~0x00000378, 0x00000007), - /* RCBA + 0x31c[3,2,1,0]=0011b */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x31c, ~0x0000000c, 0x00000003), - REG_SCRIPT_END -}; - -static const struct reg_script ehci_clock_gating_script[] = { - /* Enable SB local clock gating */ - REG_PCI_OR32(0x7c, 0x00004000), - /* RCBA + 0x284=0xbe (step B0+) */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x284, 0x000000be), - REG_SCRIPT_END -}; - -static const struct reg_script ehci_disable_script[] = { - /* Clear Run/Stop Bit */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0), - /* Wait for HC Halted */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, USB2STS, - USB2STS_HCHALT, USB2STS_HCHALT, 10000), - /* Disable Interrupts */ - REG_PCI_OR32(EHCI_CMD_STS, INTRDIS), - /* Disable Asynchronous and Periodic Scheduler */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, - ~(USB2CMD_ASE | USB2CMD_PSE), 0), - /* Disable port wake */ - REG_PCI_RMW32(EHCI_SBRN_FLA_PWC, ~(PORTWKIMP | PORTWKCAPMASK), 0), - /* Set Function Disable bit in RCBA */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + RCBA_FUNC_DIS, RCBA_EHCI_DIS), - REG_SCRIPT_END -}; - -static const struct reg_script ehci_hc_reset[] = { - REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), - REG_SCRIPT_END -}; - -static void usb2_phy_init(device_t dev) -{ - struct soc_intel_baytrail_config *config = dev->chip_info; - u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ? - 0x4700 : config->usb2_comp_bg); - struct reg_script usb2_phy_script[] = { - /* USB3PHYInit() */ - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, - usb2_comp_bg), - /* Per port phy settings, set in devicetree.cb */ - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0, - config->usb2_per_port_lane0), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, - USBPHY_PER_PORT_RCOMP_HS_PULLUP0, - config->usb2_per_port_rcomp_hs_pullup0), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE1, - config->usb2_per_port_lane1), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, - USBPHY_PER_PORT_RCOMP_HS_PULLUP1, - config->usb2_per_port_rcomp_hs_pullup1), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE2, - config->usb2_per_port_lane2), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, - USBPHY_PER_PORT_RCOMP_HS_PULLUP2, - config->usb2_per_port_rcomp_hs_pullup2), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE3, - config->usb2_per_port_lane3), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, - USBPHY_PER_PORT_RCOMP_HS_PULLUP3, - config->usb2_per_port_rcomp_hs_pullup3), - REG_SCRIPT_END - }; - reg_script_run(usb2_phy_script); -} - -static void ehci_init(device_t dev) -{ - struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script ehci_hc_init[] = { - /* Controller init */ - REG_SCRIPT_NEXT(ehci_init_script), - /* Enable clock gating */ - REG_SCRIPT_NEXT(ehci_clock_gating_script), - /* - * Disable ports if requested - */ - /* Open per-port disable control override */ - REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), - REG_PCI_WRITE8(EHCI_USB2PDO, config->usb2_port_disable_mask), - /* Close per-port disable control override */ - REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), - REG_SCRIPT_END - }; - - /* Don't reset controller in S3 resume path */ - if (!acpi_is_wakeup_s3()) - reg_script_run_on_dev(dev, ehci_hc_reset); - - /* Disable controller if ports are routed to XHCI */ - if (config->usb_route_to_xhci) { - /* Disable controller */ - reg_script_run_on_dev(dev, ehci_disable_script); - - /* Hide device with southcluster function */ - dev->enabled = 0; - southcluster_enable_dev(dev); - } else { - /* Initialize EHCI controller */ - reg_script_run_on_dev(dev, ehci_hc_init); - } - - /* Setup USB2 PHY based on board config */ - usb2_phy_init(dev); -} - -static struct device_operations ehci_device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ehci_init, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver baytrail_ehci __pci_driver = { - .ops = &ehci_device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = EHCI_DEVID -}; diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index 4fa92f7..1626d0f 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -20,15 +21,15 @@ #include <arch/io.h> #include <arch/acpi.h> -#include <stdint.h> -#include <console/console.h> #include <cbmem.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> #include <elog.h> #include <soc/iomap.h> -#include <soc/pmc.h> +#include <soc/pm.h> +#include <stdint.h> static void log_power_and_resets(const struct chipset_power_state *ps) { @@ -37,29 +38,23 @@ static void log_power_and_resets(const struct chipset_power_state *ps) elog_add_event(ELOG_TYPE_PWROK_FAIL); } - if (ps->gen_pmcon1 & SUS_PWR_FLR) { + if (ps->gen_pmcon1 & SUS_PWR_FLR) elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); - } - if (ps->gen_pmcon1 & RPS) { + if (ps->gen_pmcon1 & RPS) elog_add_event(ELOG_TYPE_RTC_RESET); - } - if (ps->tco_sts & SECOND_TO_STS) { + if (ps->tco_sts & SECOND_TO_STS) elog_add_event(ELOG_TYPE_TCO_RESET); - } - if (ps->pm1_sts & PRBTNOR_STS) { + if (ps->pm1_sts & PRBTNOR_STS) elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); - } - if (ps->gen_pmcon1 & SRS) { + if (ps->gen_pmcon1 & SRS) elog_add_event(ELOG_TYPE_RESET_BUTTON); - } - if (ps->gen_pmcon1 & GEN_RST_STS) { + if (ps->gen_pmcon1 & GEN_RST_STS) elog_add_event(ELOG_TYPE_SYSTEM_RESET); - } } static void log_wake_events(const struct chipset_power_state *ps) @@ -74,33 +69,27 @@ static void log_wake_events(const struct chipset_power_state *ps) /* Mask off disabled events. */ gpe0_sts = ps->gpe0_sts & ps->gpe0_en; - if (ps->pm1_sts & WAK_STS) { + if (ps->pm1_sts & WAK_STS) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? 3 : 5); - } + acpi_slp_type == 3 ? 3 : 5); - if (ps->pm1_sts & PWRBTN_STS) { + if (ps->pm1_sts & PWRBTN_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); - } - if (ps->pm1_sts & RTC_STS) { + if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - } - if (gpe0_sts & PME_B0_EN) { + if (gpe0_sts & PME_B0_EN) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); - } - if (gpe0_sts & pcie_wake_mask) { + if (gpe0_sts & pcie_wake_mask) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); - } gpio_mask = SUS_GPIO_STS0; i = 0; while (gpio_mask) { - if (gpio_mask & gpe0_sts) { + if (gpio_mask & gpe0_sts) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); - } gpio_mask <<= 1; i++; } @@ -111,8 +100,8 @@ void southcluster_log_state(void) struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); if (ps == NULL) { - printk(BIOS_DEBUG, "Not logging power state information. " - "Power state not found in cbmem.\n"); + printk(BIOS_DEBUG, + "Not logging power state information. Power state not found in cbmem.\n"); return; } diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 3c65de3..7420205 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,46 +33,34 @@ #include "chip.h" static const struct reg_script emmc_ops[] = { - /* Enable 2ms card stable feature. */ - REG_PCI_OR32(0xa8, (1 << 24)), - /* Enable HS200 */ - REG_PCI_WRITE32(0xa0, 0x446cc801), - REG_PCI_WRITE32(0xa4, 0x80000807), - /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */ - REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)), - /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */ - REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)), - /* Set slew for HS200 */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c), - /* Max timeout */ - REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e), REG_SCRIPT_END, }; static void emmc_init(device_t dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); printk(BIOS_DEBUG, "eMMC init\n"); reg_script_run_on_dev(dev, emmc_ops); - if (config->scc_acpi_mode) + if (config->emmc_acpi_mode) { + printk(BIOS_DEBUG, "Enabling ACPI mode\n"); scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); + } } -static struct device_operations device_ops = { +static struct device_operations emmc_device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = emmc_init, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; static const struct pci_driver southcluster __pci_driver = { - .ops = &device_ops, + .ops = &emmc_device_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = MMC_DEVID, }; diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index bf38d2e..703746d 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,250 +18,28 @@ * Foundation, Inc. */ +#include "chip.h" #include <arch/io.h> #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <reg_script.h> -#include <stdlib.h> - #include <soc/gfx.h> -#include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include "chip.h" - -#define GFX_TIMEOUT 100000 /* 100ms */ - -/* - * Lock Power Context Base Register to point to a 24KB block - * of memory in GSM. Power context save data is stored here. - */ -static void gfx_lock_pcbase(device_t dev) -{ - struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); - const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256, - 288,320,352,384,416,448,480,512 }; - u32 pcsize = 24 << 10; /* 24KB */ - u32 wopcmsz = 0x100000; /* PAVP offset */ - u32 gms, gmsize, pcbase; - - gms = pci_read_config32(dev, GGC) & GGC_GSM_SIZE_MASK; - gms >>= 3; - if (gms > ARRAY_SIZE(gms_size_map)) - return; - gmsize = gms_size_map[gms]; - - /* PcBase = BDSM + GMS Size - WOPCMSZ - PowerContextSize */ - pcbase = pci_read_config32(dev, GSM_BASE) & 0xfff00000; - pcbase += (gmsize-1) * wopcmsz - pcsize; - pcbase |= 1; /* Lock */ - - write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase); -} - -static const struct reg_script gfx_init_script[] = { - /* Allow-Wake render/media wells */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT), - /* Render Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000, - GFX_TIMEOUT), - /* Media Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000, - GFX_TIMEOUT), - /* Workaround - X0:261954/A0:261955 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1), - - /* - * PowerMeter Weights - */ - - /* SET1 */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA800, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA804, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA808, 0x0000ff0A), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA80C, 0x1D000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA810, 0xAC004900), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA814, 0x000F0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA818, 0x5A000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA81C, 0x2600001F), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA820, 0x00090000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA824, 0x2000ff00), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA828, 0xff090016), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA82C, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA830, 0x00000100), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA834, 0x00A00F51), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA838, 0x000B0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA83C, 0xcb7D3307), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA840, 0x003C0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA844, 0xFFFF0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA848, 0x00220000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA84c, 0x43000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA850, 0x00000800), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA854, 0x00000F00), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA858, 0x00000021), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA85c, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA860, 0x00190000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA80, 0x00FF00FF), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA84, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x1300A4, 0x00000000), - /* SET2 */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA900, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA904, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA908, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa90c, 0x1D000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa910, 0xAC005000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa914, 0x000F0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa918, 0x5A000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa91c, 0x2600001F), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa920, 0x00090000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa924, 0x2000ff00), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa928, 0xff090016), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa92c, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa930, 0x00000100), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa934, 0x00A00F51), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa938, 0x000B0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA93C, 0xcb7D3307), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA940, 0x003C0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA944, 0xFFFF0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA948, 0x00220000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA94C, 0x43000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA950, 0x00000800), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA954, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA960, 0x00000000), - /* SET3 */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa3c, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa54, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa60, 0x00000000), - /* Enable PowerMeter Counters */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA248, 0x00000058), - - /* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */ - /* SDP Profile 4 == 0x11940, others 0xcf08 */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08), - - /* GfxPause */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388), - - /* Dynamic EU Control Settings */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa080, 0x00000004), - - /* Lock ECO Bit Settings */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x80000000), - - /* DOP Clock Gating */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x00000001), - - /* MBCunit will send the VCR (Fuse) writes as NP-W */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x907c, 0xfffeffff, 0x00010000), - - /* - * RC6 Settings - */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA090, 0x00000000), - /* RC1e - RC6/6p - RC6pp Wake Rate Limits */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA09C, 0x00280000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0A8, 0x0001E848), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0AC, 0x00000019), - /* RC Sleep / RCx Thresholds */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B0, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B8, 0x00000557), - - /* - * Turbo Settings - */ - - /* Render/Video/Blitter Idle Max Count */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x2054, 0x0000000A), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000A), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000A), - /* RP Down Timeout */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA010, 0x000F4240), - - /* - * Turbo Control Settings - */ - - /* RP Up/Down Threshold */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA02C, 0x0000E8E8), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA030, 0x0003BD08), - /* RP Up/Down EI */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA068, 0x000101D0), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA06C, 0x00055730), - - /* RP Idle Hysteresis */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a), - - /* HW RC6 Control Settings */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x11000000), - - /* RP Control */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000592), - - /* Enable PM Interrupts */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x44024, 0x03000000), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa168, 0x0000007e), - - /* Aggressive Clock Gating */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0), - - /* Enable Gfx Turbo. */ - REG_IOSF_RMW(IOSF_PORT_PMC, SB_BIOS_CONFIG, - ~SB_BIOS_CONFIG_GFX_TURBO_DIS, 0), - REG_SCRIPT_END -}; - static const struct reg_script gpu_pre_vbios_script[] = { /* Make sure GFX is bus master with MMIO access */ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), - /* Display */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, - GFX_TIMEOUT), - /* Tx/Rx Lanes */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0, - GFX_TIMEOUT), - /* Common Lane */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0, - GFX_TIMEOUT), - /* Ungating Tx only */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0, - GFX_TIMEOUT), - /* Ungating Common Lane only */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0, - GFX_TIMEOUT), - /* Ungating Display */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, - GFX_TIMEOUT), REG_SCRIPT_END }; static const struct reg_script gfx_post_vbios_script[] = { - /* Deassert Render Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), - /* Deassert Media Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), /* Set Lock bits */ - REG_PCI_RMW32(GGC, 0xffffffff, 1), - REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), - REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), + REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK), + REG_PCI_RMW32(GSM_BASE, 0xffffffff, GSM_BDSM_LOCK), + REG_PCI_RMW32(GTT_BASE, 0xffffffff, GTT_BGSM_LOCK), REG_SCRIPT_END }; @@ -271,111 +50,28 @@ static inline void gfx_run_script(device_t dev, const struct reg_script *ops) static void gfx_pre_vbios_init(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); } -static void gfx_pm_init(device_t dev) -{ - printk(BIOS_INFO, "GFX: Power Management Init\n"); - gfx_run_script(dev, gfx_init_script); - - /* Lock power context base */ - gfx_lock_pcbase(dev); -} - static void gfx_post_vbios_init(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); } -static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz) -{ - int divider; - struct resource *res; - - res = find_resource(dev, PCI_BASE_ADDRESS_0); - - if (res == NULL) - return; - - /* Default to 200 Hz if nothing is set. */ - if (req_hz == 0) - req_hz = 200; - - /* Base clock is 25MHz */ - divider = 25 * 1000 * 1000 / (16 * req_hz); - - /* Do not set duty cycle (lower 16 bits). Just set the divider. */ - write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16); -} - -static void gfx_panel_setup(device_t dev) -{ - struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script gfx_pipea_init[] = { - /* CONTROL */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), - PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), - /* POWER ON */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS), - (config->gpu_pipea_port_select << 30 | - config->gpu_pipea_power_on_delay << 16 | - config->gpu_pipea_light_on_delay)), - /* POWER OFF */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS), - (config->gpu_pipea_power_off_delay << 16 | - config->gpu_pipea_light_off_delay)), - /* DIVISOR */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR), - ~0x1f, config->gpu_pipea_power_cycle_delay), - REG_SCRIPT_END - }; - struct reg_script gfx_pipeb_init[] = { - /* CONTROL */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), - PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), - /* POWER ON */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS), - (config->gpu_pipeb_port_select << 30 | - config->gpu_pipeb_power_on_delay << 16 | - config->gpu_pipeb_light_on_delay)), - /* POWER OFF */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS), - (config->gpu_pipeb_power_off_delay << 16 | - config->gpu_pipeb_light_off_delay)), - /* DIVISOR */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR), - ~0x1f, config->gpu_pipeb_power_cycle_delay), - REG_SCRIPT_END - }; - - if (config->gpu_pipea_port_select) { - printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); - reg_script_run_on_dev(dev, gfx_pipea_init); - set_backlight_pwm(dev, PIPEA_REG(BACKLIGHT_CTL), - config->gpu_pipea_pwm_freq_hz); - } - - if (config->gpu_pipeb_port_select) { - printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); - reg_script_run_on_dev(dev, gfx_pipeb_init); - set_backlight_pwm(dev, PIPEB_REG(BACKLIGHT_CTL), - config->gpu_pipeb_pwm_freq_hz); - } -} - static void gfx_init(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); - /* Power Management Init */ - gfx_pm_init(dev); - - gfx_panel_setup(dev); - /* Run VBIOS */ pci_dev_init(dev); @@ -383,8 +79,28 @@ static void gfx_init(device_t dev) gfx_post_vbios_init(dev); } +static void gfx_read_resources(device_t dev) +{ + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + + pci_dev_read_resources(dev); + +#if IS_ENABLED(CONFIG_MARK_GRAPHICS_MEM_WRCOMB) + struct resource *res; + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "GFX: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +#endif +} + static struct device_operations gfx_device_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gfx_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gfx_init, diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c old mode 100644 new mode 100755 index 0c32917..637a4da --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,228 +18,298 @@ * Foundation, Inc. */ -#include <device/pci.h> + #include <console/console.h> +#include <device/pci.h> #include <soc/gpio.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/smm.h> -/* GPIO-to-Pad LUTs */ -static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = - { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ - 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ - 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ - 2, 5, 9 }; /* [24:26] */ - -static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = - { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ - 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */ - 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */ - 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */ - 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */ - 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */ - 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */ - 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */ - 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */ - 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */ - 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */ - 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */ - 106, 87, 91, 104, 97, 100 }; /* [96:101] */ - -static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = - { 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */ - 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */ - 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */ - 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */ - 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */ - 52, 53, 59, 40 }; /* [40:43] */ - -/* GPIO bank descriptions */ -static const struct gpio_bank gpncore_bank = { - .gpio_count = GPNCORE_COUNT, - .gpio_to_pad = gpncore_gpio_to_pad, - .legacy_base = GP_LEGACY_BASE_NONE, - .pad_base = GPNCORE_PAD_BASE, - .has_wake_en = 0, - .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START, - .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END, + +#define GPIO_DEBUG + +/* gpio map to pad number LUTs */ + +static const u8 gpncommunity_gpio_to_pad[GP_NORTH_COUNT] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, + 26, 27, 30, 31, 32, 33, 34, 35, 36, 37, + 38, 39, 40, 41, 45, 46, 47, 48, 49, 50, + 51, 52, 53, 54, 55, 56, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72 }; + +static const u8 gpsecommunity_gpio_to_pad[GP_SOUTHEAST_COUNT] = { + 0, 1, 2, 3, 4, 5, 6, 7, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, + 30, 31, 32, 33, 34, 35, 45, 46, 47, 48, + 49, 50, 51, 52, 60, 61, 62, 63, 64, 65, + 66, 67, 68, 69, 75, 76, 77, 78, 79, 80, + 81, 82, 83, 84, 85 }; + + +static const u8 gpswcommunity_gpio_to_pad[GP_SOUTHWEST_COUNT] = { + 0, 1, 2, 3, 4, 5, 6, 7, 15, 16, + 17, 18, 19, 20, 21, 22, 30, 31, 32, 33, + 34, 35, 36, 37, 45, 46, 47, 48, 49, 50, + 51, 52, 60, 61, 62, 63, 64, 65, 66, 67, + 75, 76, 77, 78, 79, 80, 81, 82, 90, 91, + 92, 93, 94, 95, 96, 97 }; + +static const u8 gpecommunity_gpio_to_pad[GP_EAST_COUNT] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 15, 16, 17, 18, 19, 20, 21, 22, + 23, 24, 25, 26 }; + +/* GPIO Community descriptions */ +static const struct gpio_bank gpnorth_community = { + .gpio_count = GP_NORTH_COUNT, + .gpio_to_pad = gpncommunity_gpio_to_pad , + .pad_base = COMMUNITY_GPNORTH_BASE , + .has_gpe_en = GPE_CAPABLE , + .has_wake_en = 1, }; -static const struct gpio_bank gpscore_bank = { - .gpio_count = GPSCORE_COUNT, - .gpio_to_pad = gpscore_gpio_to_pad, - .legacy_base = GPSCORE_LEGACY_BASE, - .pad_base = GPSCORE_PAD_BASE, - .has_wake_en = 0, - .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START, - .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END, +static const struct gpio_bank gpsoutheast_community = { + .gpio_count = GP_SOUTHEAST_COUNT, + .gpio_to_pad = gpsecommunity_gpio_to_pad, + .pad_base = COMMUNITY_GPSOUTHEAST_BASE, + .has_gpe_en = GPE_CAPABLE_NONE, + .has_wake_en = 1, }; -static const struct gpio_bank gpssus_bank = { - .gpio_count = GPSSUS_COUNT, - .gpio_to_pad = gpssus_gpio_to_pad, - .legacy_base = GPSSUS_LEGACY_BASE, - .pad_base = GPSSUS_PAD_BASE, +static const struct gpio_bank gpsouthwest_community = { + .gpio_count = GP_SOUTHWEST_COUNT, + .gpio_to_pad = gpswcommunity_gpio_to_pad, + .pad_base = COMMUNITY_GPSOUTHWEST_BASE, + .has_gpe_en = GPE_CAPABLE, .has_wake_en = 1, - .gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START, - .gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END, }; +static const struct gpio_bank gpeast_community = { + .gpio_count = GP_EAST_COUNT, + .gpio_to_pad = gpecommunity_gpio_to_pad, + .pad_base = COMMUNITY_GPEAST_BASE, + .has_gpe_en = GPE_CAPABLE_NONE, + .has_wake_en = 1, +}; + +static void setup_gpio_route(const struct soc_gpio_map *sw_gpios, + const struct soc_gpio_map *n_gpios) +{ + const struct soc_gpio_map *n_config; + const struct soc_gpio_map *sw_config; + uint32_t route_reg = 0; + uint32_t int_selection = 0; + uint32_t alt_gpio_smi = 0; + uint32_t gpe0a_en = 0; + int gpio = 0; + int north_done = 0; + int south_done = 0; + + for (sw_config = sw_gpios, n_config = n_gpios; + (!north_done || !south_done); sw_config++, n_config++, gpio++) { + + /* when north config is done */ + if ((gpio > GP_NORTH_COUNT) || + (n_config->pad_conf0 == GPIO_LIST_END)) + north_done = 1; + + /* when sw is done */ + if ((gpio > GP_SOUTHWEST_COUNT) || + (sw_config->pad_conf0 == GPIO_LIST_END)) + south_done = 1; + + /* route north gpios */ + if (!north_done) { + /* Int select from 8 to 15 */ + int_selection = ((n_config->pad_conf0 >> 28) & 0xf); + if (n_config->gpe == SMI) { + /* + * Set the corresponding bits (01) as + * per the interrupt line + */ + route_reg |= (1 << ((int_selection - 8) * 2)); + /* reset the higher bit */ + route_reg &= + ~(1 << ((int_selection - 8) * 2 + 1)); + alt_gpio_smi |= (1 << (int_selection + 8)); + } else if (n_config->gpe == SCI) { + /* + * Set the corresponding bits as per the + * interrupt line + */ + route_reg |= + (1 << (((int_selection - 8) * 2) + 1)); + /* reset the bit */ + route_reg &= ~(1 << ((int_selection - 8) * 2)); + gpe0a_en |= (1 << (int_selection + 8)); + } + } + + /* route southwest gpios */ + if (!south_done) { + /* Int select from 8 to 15 */ + int_selection = ((sw_config->pad_conf0 >> 28) & 0xf); + if (sw_config->gpe == SMI) { + /* + * Set the corresponding bits (10) as + * per the interrupt line + */ + route_reg |= (1 << (int_selection * 2)); + route_reg &= ~(1 << (int_selection * 2 + 1)); + alt_gpio_smi |= (1 << (int_selection + 16)); + } else if (sw_config->gpe == SCI) { + /* + * Set the corresponding bits as + * per the interrupt line + */ + route_reg |= (1 << ((int_selection * 2) + 1)); + /* reset the bit */ + route_reg &= ~(1 << (int_selection * 2)); + gpe0a_en |= (1 << (int_selection + 16)); + } + } + } + + /* enable gpe bits in GPE0A_EN_REG */ + outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0A_EN_REG); + +#ifdef GPIO_DEBUG + printk(BIOS_DEBUG, "gpio_rout = %x alt_gpio_smi = %x gpe0a_en = %x\n", + route_reg, alt_gpio_smi, gpe0a_en); +#endif + /* Save as an smm param */ + southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); +} + + static void setup_gpios(const struct soc_gpio_map *gpios, - const struct gpio_bank *bank) + const struct gpio_bank *community) { const struct soc_gpio_map *config; int gpio = 0; - u32 reg, pad_conf0; - u8 set, bit; - - u32 use_sel[4] = {0}; - u32 io_sel[4] = {0}; - u32 gp_lvl[4] = {0}; - u32 tpe[4] = {0}; - u32 tne[4] = {0}; - u32 wake_en[4] = {0}; + u32 reg, family, internal_pad_num; + u32 mmio_addr, int_selection; + u32 gpio_wake0 = 0; + u32 gpio_wake1 = 0; + u32 gpio_int_mask = 0; if (!gpios) return; - for (config = gpios; config->pad_conf0 != GPIO_LIST_END; config++, gpio++) { - if (gpio > bank->gpio_count) + if (gpio > community->gpio_count) break; - set = gpio >> 5; - bit = gpio % 32; - - if (bank->legacy_base != GP_LEGACY_BASE_NONE) { - /* Legacy IO configuration */ - use_sel[set] |= config->use_sel << bit; - io_sel[set] |= config->io_sel << bit; - gp_lvl[set] |= config->gp_lvl << bit; - tpe[set] |= config->tpe << bit; - tne[set] |= config->tne << bit; - - /* Some banks do not have wake_en ability */ - if (bank->has_wake_en) - wake_en[set] |= config->wake_en << bit; - } - /* Pad configuration registers */ - reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio]; - - /* Add correct func to GPIO pad config */ - pad_conf0 = config->pad_conf0; - if (config->is_gpio) - { - if (gpio >= bank->gpio_f1_range_start && - gpio <= bank->gpio_f1_range_end) - pad_conf0 |= PAD_FUNC1; - else - pad_conf0 |= PAD_FUNC0; - } - + family = community->gpio_to_pad[gpio] / MAX_FAMILY_PAD_GPIO_NO; + internal_pad_num = community->gpio_to_pad[gpio] % + MAX_FAMILY_PAD_GPIO_NO; + + /* + * Calculate the MMIO Address for specific GPIO pin + * control register pointed by index. + * REG = (IOBASE + COMMUNITY_BASE + (0X04400)) + + * (0X400*FAMILY_NUM) + (8 * PAD_NUM) + */ + mmio_addr = FAMILY_PAD_REGS_OFF + + (FAMILY_PAD_REGS_SIZE * family) + + (GPIO_REGS_SIZE * internal_pad_num); + + reg = community->pad_base + mmio_addr; + + /* get int selection value */ + int_selection = ((config->pad_conf0 >> 28) & 0xf); + + /* get int mask register value */ + gpio_int_mask |= (config->int_mask << int_selection); + + /* + * wake capable programming + * some communities have 2 wake regs + */ + if (gpio > 31) + gpio_wake1 |= config->wake_mask << (gpio % 32); + else + gpio_wake0 |= config->wake_mask << gpio; + + if (!config->skip_config) { #ifdef GPIO_DEBUG - printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n", - reg, pad_conf0, config->pad_conf1, config->pad_val); + printk(BIOS_DEBUG, + "Write Pad: Base(%x) - conf0 = %x conf1= %x gpio #- %d pad # = %d\n", + reg, config->pad_conf0, config->pad_conf1, + community->gpio_to_pad[gpio], gpio); #endif - - write32((u32 *)(reg + PAD_CONF0_REG), pad_conf0); - write32((u32 *)(reg + PAD_CONF1_REG), config->pad_conf1); - write32((u32 *)(reg + PAD_VAL_REG), config->pad_val); + /* + * write pad configurations to conf0 and conf1 register + */ + write32((void *)(reg + PAD_CONF0_REG), + config->pad_conf0); + write32((void *)(reg + PAD_CONF1_REG), + config->pad_conf1); + } } - if (bank->legacy_base != GP_LEGACY_BASE_NONE) - for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) { - reg = bank->legacy_base + 0x20 * set; - #ifdef GPIO_DEBUG - printk(BIOS_DEBUG, - "Write GPIO: Reg(%x) - %x %x %x %x %x\n", - reg, use_sel[set], io_sel[set], gp_lvl[set], - tpe[set], tne[set]); + printk(BIOS_DEBUG, + "gpio_wake_mask0 = %x gpio_wake_mask1 = %x gpio_int_mask = %x\n", + gpio_wake0, gpio_wake1, gpio_int_mask); #endif - outl(use_sel[set], reg + LEGACY_USE_SEL_REG); - outl(io_sel[set], reg + LEGACY_IO_SEL_REG); - outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG); - outl(tpe[set], reg + LEGACY_TPE_REG); - outl(tne[set], reg + LEGACY_TNE_REG); + /* Wake */ + write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0), + gpio_wake0); - /* TS registers are WOC */ - outl(0, reg + LEGACY_TS_REG); + /* wake mask config for communities with 2 regs */ + if (community->gpio_count > 32) + write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1), + gpio_wake1); - if (bank->has_wake_en) - outl(wake_en[set], reg + LEGACY_WAKE_EN_REG); - } -} + /* Interrupt */ + write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), + gpio_int_mask); -static void setup_gpio_route(const struct soc_gpio_map *sus, - const struct soc_gpio_map *core) -{ - uint32_t route_reg = 0; - int i; - - for (i = 0; i < 8; i++) { - /* SMI takes precedence and wake_en implies SCI. */ - if (sus[i].smi) { - route_reg |= ROUTE_SMI << (2 * i); - } else if (sus[i].sci) { - route_reg |= ROUTE_SCI << (2 * i); - } - - if (core[i].smi) { - route_reg |= ROUTE_SMI << (2 * (i + 8)); - } else if (core[i].sci) { - route_reg |= ROUTE_SCI << (2 * (i + 8)); - } - } - southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); } -static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], - const struct gpio_bank *bank) -{ - u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET); - u32 val; - int i; - - /* Write all four DIRQ registers */ - for (i=0; i<4; ++i) { - val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 | - dirq[i * 4 + 1] << 8 | dirq[i * 4]; - write32(reg + i, val); -#ifdef GPIO_DEBUG - printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n", - reg + i, val); -#endif - } -} void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) { + if (config) { - setup_gpios(config->ncore, &gpncore_bank); - setup_gpios(config->score, &gpscore_bank); - setup_gpios(config->ssus, &gpssus_bank); - setup_gpio_route(config->ssus, config->score); - - if (config->core_dirq) - setup_dirqs(*config->core_dirq, &gpscore_bank); - if (config->sus_dirq) - setup_dirqs(*config->sus_dirq, &gpssus_bank); + + /* + * Write the default value 0xffffff to the SW + * write_access_policy_interrupt_reg to allow the SW interrupt + * mask register to be set + */ + write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108), + 0xffffffff); + + printk(BIOS_DEBUG, "north\n"); + setup_gpios(config->north, &gpnorth_community); + + printk(BIOS_DEBUG, "southwest\n"); + setup_gpios(config->southwest, &gpsouthwest_community); + + printk(BIOS_DEBUG, "southeast\n"); + setup_gpios(config->southeast, &gpsoutheast_community); + + printk(BIOS_DEBUG, "east\n"); + setup_gpios(config->east, &gpeast_community); + + printk(BIOS_DEBUG, "Routing SW and N gpios\n"); + setup_gpio_route(config->southwest, config->north); } - /* Set on die termination feature with pull up value and + /* + * Set on die termination feature with pull up value and * drive the pad high for TAP_TDO and TAP_TMS */ - if (!enable_xdp_tap) { + if (!enable_xdp_tap) printk(BIOS_DEBUG, "Tri-state TDO and TMS\n"); - write32((u32 *)(GPSSUS_PAD_BASE + 0x2fc), 0xc); - write32((u32 *)(GPSSUS_PAD_BASE + 0x2cc), 0xc); - } } -struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void) +__attribute__((weak)) struct soc_gpio_config *mainboard_get_gpios(void) { printk(BIOS_DEBUG, "Default/empty GPIO config\n"); return NULL; diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c new file mode 100644 index 0000000..7be1914 --- /dev/null +++ b/src/soc/intel/braswell/gpio_support.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <soc/gpio.h> + +/* + * Return family number and internal pad number in that community by pad number + * and which community it is in. + */ +uint16_t gpio_family_number(uint8_t community, uint8_t pad) +{ + /* + * Refer to BSW BIOS Writers Guide, Table "Family Number". + * BSW has 4 GPIO communities. Each community has up to 7 families and + * each family contains a range of Pad numbers. The number in the array + * is the maximum no. of that range. + * For example: East community, family 0, Pad 0~11. + */ + static const uint8_t community_base[GPIO_COMMUNITY_COUNT] + [GPIO_FAMILIES_MAX_PER_COMM + 1] = { + {0, 8, 16, 24, 32, 40, 48, 56}, /* Southwest */ + {0, 9, 22, 34, 46, 59, 59, 59}, /* North */ + {0, 12, 24, 24, 24, 24, 24, 24}, /* East */ + {0, 8, 20, 26, 34, 44, 55, 55} /* Southeast */ + }; + const uint8_t *base; + uint8_t i; + + /* Validate the pad number */ + if (pad > community_base[community][7]) + die("Pad number is out of range!"); + + /* Locate the family number for the pad */ + base = &community_base[community][0]; + for (i = 0; i < 7; i++) { + if ((pad >= base[0]) && (pad < base[1])) + break; + base++; + } + + /* Family number in high byte and inner pad number in lowest byte */ + return (i << 8) + pad - *base; +} + +/* + * Return pad configuration register offset by pad number and which community + * it is in. + */ +uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad) +{ + uint16_t fpad; + uint32_t *pad_config_reg; + + /* Get the GPIO family number */ + fpad = gpio_family_number(community, pad); + + /* + * Refer to BSW BIOS Writers Guide, Table "Per Pad Memory Space + * Registers Addresses" for the Pad configuration register calculation. + */ + pad_config_reg = (uint32_t *)(COMMUNITY_BASE(community) + 0x4400 + + (0x400 * (fpad >> 8)) + (8 * (fpad & 0xff))); + + return pad_config_reg; +} + +int get_gpio(int community_base, int pad0_offset) +{ + return (read32((void *)(community_base + pad0_offset))) & PAD_RX_BIT; +} diff --git a/src/soc/intel/braswell/hda.c b/src/soc/intel/braswell/hda.c index f20386f..31593fd 100644 --- a/src/soc/intel/braswell/hda.c +++ b/src/soc/intel/braswell/hda.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,88 +25,16 @@ #include <device/pci_ids.h> #include <reg_script.h> -#include <soc/intel/common/hda_verb.h> +#include <soc/hda.h> #include <soc/iomap.h> -#include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -static const struct reg_script init_ops[] = { - /* Enable no snoop traffic. */ - REG_PCI_OR16(0x78, 1 << 11), - /* Configure HDMI codec connection. */ - REG_PCI_OR32(0xc4, 1 << 1), - REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00), - /* Configure internal settings. */ - REG_PCI_OR32(0xc0, 0x7 << 21), - REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)), - REG_PCI_WRITE32(0xc8, 0x82a30000), - REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0), - /* Disable docking. */ - REG_PCI_RMW8(0x4d, ~(1 << 7), 0), - REG_SCRIPT_END, -}; - -static const uint32_t hdmi_codec_verb_table[] = { - /* coreboot specific header */ - 0x80862882, /* vid did for hdmi codec */ - 0x00000000, /* subsystem id */ - 0x00000003, /* number of jacks */ - - /* pin widget 5 - port B */ - 0x20471c10, - 0x20471d00, - 0x20471e56, - 0x20471f18, - - /* pin widget 6 - port C */ - 0x20571c20, - 0x20571d00, - 0x20571e56, - 0x20571f18, - - /* pin widget 7 - port D */ - 0x20671c30, - 0x20671d00, - 0x20671e56, - 0x20671f58, -}; - -static void hda_init(device_t dev) -{ - struct resource *res; - int codec_mask; - int i; - u8 *base; - - reg_script_run_on_dev(dev, init_ops); - - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res == NULL) - return; - - base = res2mmio(res, 0, 0); - codec_mask = hda_codec_detect(base); - - printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask); - if (!codec_mask) - return; - - for (i = 3; i >= 0; i--) { - if (!((1 << i) & codec_mask)) - continue; - hda_codec_init(base, i, sizeof(hdmi_codec_verb_table), - hdmi_codec_verb_table); - } -} - static const struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = hda_init, + .init = NULL, .enable = NULL, .scan_bus = NULL, .ops_pci = &soc_pci_ops, diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index fb88d12..7f0d5d8 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -17,15 +18,21 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_ACPI_H_ -#define _BAYTRAIL_ACPI_H_ +#ifndef _SOC_ACPI_H_ +#define _SOC_ACPI_H_ #include <arch/acpi.h> #include <soc/nvs.h> -void acpi_create_intel_hpet(acpi_hpet_t * hpet); +#if CONFIG_GOP_SUPPORT +#include <soc/intel/common/gma.h> +int init_igd_opregion(igd_opregion_t *igd_opregion); +#endif + +void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); -#endif /* _BAYTRAIL_ACPI_H_ */ +#endif /* _SOC_ACPI_H_ */ + diff --git a/src/soc/intel/braswell/include/soc/chipset_fsp_util.h b/src/soc/intel/braswell/include/soc/chipset_fsp_util.h new file mode 100644 index 0000000..c269a61 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/chipset_fsp_util.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef CHIPSET_FSP_UTIL_H +#define CHIPSET_FSP_UTIL_H + +/* + * Include the FSP binary interface files + * + * These files include the necessary UEFI constants and data structures + * that are used to interface to the FSP binary. + */ + +#include <uefi_types.h> /* UEFI data types */ +#include <IntelFspPkg/Include/FspApi.h> /* FSP API definitions */ +#include <IntelFspPkg/Include/FspInfoHeader.h> /* FSP binary layout */ +#include <MdePkg/Include/Pi/PiBootMode.h> /* UEFI boot mode definitions */ +#include <MdePkg/Include/Pi/PiFirmwareFile.h> /* UEFI file definitions */ +#include <MdePkg/Include/Pi/PiFirmwareVolume.h> /* UEFI file system defs */ +#include <MdePkg/Include/Uefi/UefiMultiPhase.h> /* UEFI memory types */ +#include <MdePkg/Include/Pi/PiHob.h> /* Hand off block definitions */ +#include <MdePkg/Include/Library/HobLib.h> /* HOB routine declarations */ +#include <FspUpdVpd.h> /* Vital/updatable product data definitions */ + +#endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h index 719c0f3..18aaf7a 100644 --- a/src/soc/intel/braswell/include/soc/device_nvs.h +++ b/src/soc/intel/braswell/include/soc/device_nvs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_DEVICE_NVS_H_ -#define _BAYTRAIL_DEVICE_NVS_H_ +#ifndef _SOC_DEVICE_NVS_H_ +#define _SOC_DEVICE_NVS_H_ #include <stdint.h> @@ -62,7 +63,6 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ - u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ } __attribute__((packed)) device_nvs_t; -#endif +#endif /* _SOC_DEVICE_NVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/efi_wrapper.h b/src/soc/intel/braswell/include/soc/efi_wrapper.h deleted file mode 100644 index 3304d03..0000000 --- a/src/soc/intel/braswell/include/soc/efi_wrapper.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * PEI EFI entry point - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __EFI_WRAPPER_H__ -#define __EFI_WRAPPER_H__ - -#define EFI_WRAPPER_VER 2 - -/* Provide generic x86 calling conventions. */ -#define ABI_X86 __attribute((regparm(0))) - -/* Errors returned by the EFI wrapper. */ -enum efi_wrapper_error { - INVALID_VER = -1, -}; - -struct efi_wrapper_params { - /* Mainboard Inputs */ - int version; - - void ABI_X86 (*console_out)(unsigned char byte); - - unsigned int tsc_ticks_per_microsecond; -} __attribute__((packed)); - -typedef int ABI_X86 (*efi_wrapper_entry_t)(struct efi_wrapper_params *); -#endif diff --git a/src/soc/intel/braswell/include/soc/ehci.h b/src/soc/intel/braswell/include/soc/ehci.h index 444e8ce..22337bf 100644 --- a/src/soc/intel/braswell/include/soc/ehci.h +++ b/src/soc/intel/braswell/include/soc/ehci.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,28 +18,11 @@ * Foundation, Inc. */ -#ifndef BAYTRAIL_EHCI_H -#define BAYTRAIL_EHCI_H +#ifndef _SOC_EHCI_H_ +#define _SOC_EHCI_H_ /* EHCI PCI Registers */ #define EHCI_CMD_STS 0x04 # define INTRDIS (1 << 10) -#define EHCI_SBRN_FLA_PWC 0x60 -# define PORTWKIMP (1 << 16) -# define PORTWKCAPMASK (0x3ff << 17) -#define EHCI_USB2PDO 0x64 -/* EHCI Memory Registers */ -#define USB2CMD 0x20 -# define USB2CMD_ASE (1 << 5) -# define USB2CMD_PSE (1 << 4) -# define USB2CMD_HCRESET (1 << 1) -# define USB2CMD_RS (1 << 0) -#define USB2STS 0x24 -# define USB2STS_HCHALT (1 << 12) - -/* RCBA EHCI Registers */ -#define RCBA_FUNC_DIS 0x220 -# define RCBA_EHCI_DIS (1 << 0) - -#endif /* BAYTRAIL_EHCI_H */ +#endif /* _SOC_EHCI_H_ */ diff --git a/src/soc/intel/braswell/include/soc/gfx.h b/src/soc/intel/braswell/include/soc/gfx.h index 3b66870..743a89a 100644 --- a/src/soc/intel/braswell/include/soc/gfx.h +++ b/src/soc/intel/braswell/include/soc/gfx.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,27 +18,48 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_GFX_H_ -#define _BAYTRAIL_GFX_H_ +#ifndef _SOC_GFX_H_ +#define _SOC_GFX_H_ /* * PCI config registers. */ #define GGC 0x50 -# define GGC_VGA_DISABLE (1 << 1) -# define GGC_GTT_SIZE_MASK (3 << 8) +# define GGC_VAMEN (1 << 14) /* Enable acceleration mode */ +# define GGC_GTT_SIZE_MASK (3 << 8) /* GTT graphics memory size */ # define GGC_GTT_SIZE_0MB (0 << 8) -# define GGC_GTT_SIZE_1MB (1 << 8) -# define GGC_GTT_SIZE_2MB (2 << 8) -# define GGC_GSM_SIZE_MASK (0x1f << 3) +# define GGC_GTT_SIZE_2MB (1 << 8) +# define GGC_GTT_SIZE_4MB (2 << 8) +# define GGC_GTT_SIZE_8MB (3 << 8) +# define GGC_GSM_SIZE_MASK (0x1f << 3) /* Main memory use */ # define GGC_GSM_SIZE_0MB (0 << 3) # define GGC_GSM_SIZE_32MB (1 << 3) # define GGC_GSM_SIZE_64MB (2 << 3) +# define GCC_GSM_SIZE_96MB (3 << 3) # define GGC_GSM_SIZE_128MB (4 << 3) +# define GGC_GSM_SIZE_160MB (5 << 3) +# define GGC_GSM_SIZE_192MB (6 << 3) +# define GGC_GSM_SIZE_224MB (7 << 3) +# define GGC_GSM_SIZE_256MB (8 << 3) +# define GGC_GSM_SIZE_288MB (9 << 3) +# define GGC_GSM_SIZE_320MB (0x0a << 3) +# define GGC_GSM_SIZE_352MB (0x0b << 3) +# define GGC_GSM_SIZE_384MB (0x0c << 3) +# define GGC_GSM_SIZE_416MB (0x0d << 3) +# define GGC_GSM_SIZE_448MB (0x0e << 3) +# define GGC_GSM_SIZE_480MB (0x0f << 3) +# define GGC_GSM_SIZE_512MB (0x10 << 3) +# define GGC_VGA_DISABLE (1 << 1) /* VGA Disable */ +# define GGC_GGCLCK (1 << 0) /* Prevent register writes */ #define GSM_BASE 0x5c +# define GSM_BDSM 0xfff00000 /* Base of stolen memory */ +# define GSM_BDSM_LOCK (1 << 0) /* Prevent register writes */ + #define GTT_BASE 0x70 +# define GTT_BGSM 0xfff00000 /* Base of stolen memory */ +# define GTT_BGSM_LOCK (1 << 0) /* Prevent register writes */ #define MSAC 0x62 #define APERTURE_SIZE_MASK (3 << 1) @@ -45,20 +67,32 @@ #define APERTURE_SIZE_256MB (1 << 1) #define APERTURE_SIZE_512MB (3 << 1) -#define VLV_DISPLAY_BASE 0x180000 -#define PIPEA_REG(reg) (VLV_DISPLAY_BASE + (reg)) -#define PIPEB_REG(reg) (VLV_DISPLAY_BASE + 0x100 + (reg)) +#define SWSCI 0xe8 /* SWSCI enable */ +#define ASLS 0xfc /* OpRegion Base */ /* Panel control registers */ #define HOTPLUG_CTRL 0x61110 #define PP_CONTROL 0x61204 -#define PP_CONTROL_UNLOCK 0xabcd0000 -#define PP_CONTROL_EDP_FORCE_VDD (1 << 3) +# define PP_CONTROL_WRITE_PROTECT_KEY 0xffff0000 /* Enable display port VDD */ +# define PP_CONTROL_UNLOCK 0xabcd0000 +# define PP_CONTROL_EDP_FORCE_VDD (1 << 3) /* Enable display port VDD */ +# define PP_CONTROL_BACKLIGHT_ENABLE (1 << 2) +# define PP_CONTROL_POWER_DOWN_ON_RESET (1 << 1) +# define PP_CONTROL_POWER_STATE_TARGET (1 << 0) /* Power up/down (1/0) */ + #define PP_ON_DELAYS 0x61208 #define PP_OFF_DELAYS 0x6120c #define PP_DIVISOR 0x61210 #define BACKLIGHT_CTL2 0x61250 -#define BACKLIGHT_ENABLE (1 << 31) +# define BACKLIGHT_PWM_ENABLE (1 << 31) +# define BACKLIGHT_POLARITY (1 << 28) /* Active low/high (1/0) */ +# define BACKLIGHT_PHASE_IN_INT_STATUS (1 << 26) +# define BACKLIGHT_PHASE_IN_ENABLE (1 << 25) +# define BACKLIGHT_PHASE_IN_INT_ENABLE (1 << 24) +# define BACKLIGHT_PHASE_IN_TIME_BASE 0x00ff0000 +# define BACKLIGHT_PHASE_IN_COUNT 0x0000ff00 +# define BACKLIGHT_PHASE_IN_INCREMENT 0x000000ff + #define BACKLIGHT_CTL 0x61254 -#endif /* _BAYTRAIL_GFX_H_ */ +#endif /* _SOC_GFX_H_ */ diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index fb0b5d2..20a4d51 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,299 +18,332 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_GPIO_H_ -#define _BAYTRAIL_GPIO_H_ +#ifndef _SOC_GPIO_H_ +#define _SOC_GPIO_H_ #include <stdint.h> #include <arch/io.h> #include <soc/iomap.h> -/* #define GPIO_DEBUG */ +#define COMMUNITY_SIZE 0x20000 -/* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ -#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) -#define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) -#define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) +#define COMMUNITY_GPSOUTHWEST_BASE \ +(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPSOUTHWEST) -/* DIRQ registers start at pad base + 0x980 */ -#define PAD_BASE_DIRQ_OFFSET 0x980 +#define COMMUNITY_GPNORTH_BASE \ +(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPNORTH) -/* Pad register offset */ -#define PAD_CONF0_REG 0x0 -#define PAD_CONF1_REG 0x4 -#define PAD_VAL_REG 0x8 - -/* Legacy IO register base */ -#define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00) -#define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80) -/* Some banks have no legacy GPIO interface */ -#define GP_LEGACY_BASE_NONE 0xFFFF - -#define LEGACY_USE_SEL_REG 0x00 -#define LEGACY_IO_SEL_REG 0x04 -#define LEGACY_GP_LVL_REG 0x08 -#define LEGACY_TPE_REG 0x0C -#define LEGACY_TNE_REG 0x10 -#define LEGACY_TS_REG 0x14 -#define LEGACY_WAKE_EN_REG 0x18 - -/* Number of GPIOs in each bank */ -#define GPNCORE_COUNT 27 -#define GPSCORE_COUNT 102 -#define GPSSUS_COUNT 44 - -/* GPIO legacy IO register settings */ -#define GPIO_USE_MMIO 0 -#define GPIO_USE_LEGACY 1 - -#define GPIO_DIR_OUTPUT 0 -#define GPIO_DIR_INPUT 1 - -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 - -#define GPIO_PEDGE_DISABLE 0 -#define GPIO_PEDGE_ENABLE 1 - -#define GPIO_NEDGE_DISABLE 0 -#define GPIO_NEDGE_ENABLE 1 +#define COMMUNITY_GPEAST_BASE \ +(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPEAST) -/* config0[29] - Disable second mask */ -#define PAD_MASK2_DISABLE (1 << 29) +#define COMMUNITY_GPSOUTHEAST_BASE \ +(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPSOUTHEAST) -/* config0[27] - Direct Irq En */ -#define PAD_IRQ_EN (1 << 27) +#define GPIO_COMMUNITY_COUNT 4 +#define GPIO_FAMILIES_MAX_PER_COMM 7 +#define GP_SOUTHWEST 0 +#define GP_NORTH 1 +#define GP_EAST 2 +#define GP_SOUTHEAST 3 -/* config0[26] - gd_tne */ -#define PAD_TNE_IRQ (1 << 26) +#define COMMUNITY_BASE(community) \ +(IO_BASE_ADDRESS + community * 0x8000) -/* config0[25] - gd_tpe */ -#define PAD_TPE_IRQ (1 << 25) +#define GP_READ_ACCESS_POLICY_BASE(community) \ +(COMMUNITY_BASE(community) + 0x000) -/* config0[24] - Gd Level */ -#define PAD_LEVEL_IRQ (1 << 24) -#define PAD_EDGE_IRQ (0 << 24) +#define GP_WRITE_ACCESS_POLICY_BASE(community) \ +(COMMUNITY_BASE(community) + 0x100) -/* config0[17] - Slow clkgate / glitch filter */ -#define PAD_SLOWGF_ENABLE (1 << 17) +#define GP_WAKE_STATUS_REG_BASE(community) \ +(COMMUNITY_BASE(community) + 0x200) -/* config0[16] - Fast clkgate / glitch filter */ -#define PAD_FASTGF_ENABLE (1 << 16) +#define GP_WAKE_MASK_REG_BASE(community) \ +(COMMUNITY_BASE(community) + 0x280) -/* config0[15] - Hysteresis enable (inverted) */ -#define PAD_HYST_DISABLE (1 << 15) -#define PAD_HYST_ENABLE (0 << 15) +#define GP_INT_STATUS_REG_BASE(community) \ +(COMMUNITY_BASE(community) + 0x300) -/* config0[14:13] - Hysteresis control */ -#define PAD_HYST_CTRL_DEFAULT (2 << 13) +#define GP_INT_MASK_REG_BASE(community) \ +(COMMUNITY_BASE(community) + 0x380) -/* config0[11] - Bypass Flop */ -#define PAD_FLOP_BYPASS (1 << 11) -#define PAD_FLOP_ENABLE (0 << 11) +#define GP_FAMILY_RCOMP_CTRL(community, family) \ +(COMMUNITY_BASE(community) + 0x1080 + 0x80 * family) -/* config0[10:9] - Pull str */ -#define PAD_PU_2K (0 << 9) -#define PAD_PU_10K (1 << 9) -#define PAD_PU_20K (2 << 9) -#define PAD_PU_40K (3 << 9) +#define GP_FAMILY_RCOMP_OFFSET(community, family) \ +(COMMUNITY_BASE(community) + 0x1084 + 0x80 * family) -/* config0[8:7] - Pull assign */ -#define PAD_PULL_DISABLE (0 << 7) -#define PAD_PULL_UP (1 << 7) -#define PAD_PULL_DOWN (2 << 7) +#define GP_FAMILY_RCOMP_OVERRIDE(community, family) \ +(COMMUNITY_BASE(community) + 0x1088 + 0x80 * family) -/* config0[2:0] - Func. pin mux */ -#define PAD_FUNC0 0x0 -#define PAD_FUNC1 0x1 -#define PAD_FUNC2 0x2 -#define PAD_FUNC3 0x3 -#define PAD_FUNC4 0x4 -#define PAD_FUNC5 0x5 -#define PAD_FUNC6 0x6 +#define GP_FAMILY_RCOMP_VALUE(community, family) \ +(COMMUNITY_BASE(community) + 0x108C + 0x80 * family) -/* pad config0 power-on values - We will not often want to change these */ -#define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \ - PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \ - PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS) +#define GP_FAMILY_CONF_COMP(community, family) \ +(COMMUNITY_BASE(community) + 0x1090 + 0x80 * family) -/* pad config1 reg power-on values - Shouldn't need to change this */ -#define PAD_CONFIG1_DEFAULT 0x8000 +#define GP_FAMILY_CONF_REG(community, family) \ +(COMMUNITY_BASE(community) + 0x1094 + 0x80 * family) -/* pad_val[2] - Iinenb - active low */ -#define PAD_VAL_INPUT_DISABLE (1 << 2) -#define PAD_VAL_INPUT_ENABLE (0 << 2) -/* pad_val[1] - Ioutenb - active low */ -#define PAD_VAL_OUTPUT_DISABLE (1 << 1) -#define PAD_VAL_OUTPUT_ENABLE (0 << 1) +/* Value written into pad control reg 0 */ +#define PAD_CONTROL_REG0_TRISTATE (PAD_CONFIG0_DEFAULT|PAD_GPIOFG_HI_Z) -/* Input / Output state should usually be mutually exclusive */ -#define PAD_VAL_INPUT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) -#define PAD_VAL_OUTPUT (PAD_VAL_OUTPUT_ENABLE | PAD_VAL_INPUT_DISABLE) +/* Calculate the MMIO Address for specific GPIO pin + * control register pointed by index. + */ +#define FAMILY_NUMBER(gpio_pad) (gpio_pad / MAX_FAMILY_PAD_GPIO_NO) +#define INTERNAL_PAD_NUM(gpio_pad) (gpio_pad % MAX_FAMILY_PAD_GPIO_NO) +#define GPIO_OFFSET(gpio_pad) (FAMILY_PAD_REGS_OFF \ + + (FAMILY_PAD_REGS_SIZE * FAMILY_NUMBER(gpio_pad) \ + + (GPIO_REGS_SIZE * INTERNAL_PAD_NUM(gpio_pad)))) + +/* Gpio to Pad mapping */ +#define SDMMC1_CMD_MMIO_OFFSET GPIO_OFFSET(23) +#define SDMMC1_D0_MMIO_OFFSET GPIO_OFFSET(17) +#define SDMMC1_D1_MMIO_OFFSET GPIO_OFFSET(24) +#define SDMMC1_D2_MMIO_OFFSET GPIO_OFFSET(20) +#define SDMMC1_D3_MMIO_OFFSET GPIO_OFFSET(26) +#define MMC1_D4_SD_WE_MMIO_OFFSET GPIO_OFFSET(67) +#define MMC1_D5_MMIO_OFFSET GPIO_OFFSET(65) +#define MMC1_D6_MMIO_OFFSET GPIO_OFFSET(63) +#define MMC1_D7_MMIO_OFFSET GPIO_OFFSET(68) +#define HV_DDI2_DDC_SDA_MMIO_OFFSET GPIO_OFFSET(62) +#define HV_DDI2_DDC_SCL_MMIO_OFFSET GPIO_OFFSET(67) + +/* GPIO Security registers offset */ +#define GPIO_READ_ACCESS_POLICY_REG 0x0000 +#define GPIO_WRITE_ACCESS_POLICY_REG 0x0100 +#define GPIO_WAKE_STATUS_REG 0x0200 +#define GPIO_WAKE_MASK_REG0 0x0280 +#define GPIO_WAKE_MASK_REG1 0x0284 +#define GPIO_INTERRUPT_STATUS 0x0300 +#define GPIO_INTERRUPT_MASK 0x0380 +#define GPE0A_STS_REG 0x20 +#define GPE0A_EN_REG 0x28 +#define ALT_GPIO_SMI_REG 0x38 +#define GPIO_ROUT_REG 0x58 -/* pad_val[0] - Value */ -#define PAD_VAL_HIGH (1 << 0) -#define PAD_VAL_LOW (0 << 0) +/* Pad register offset */ +#define PAD_CONF0_REG 0x0 +#define PAD_CONF1_REG 0x4 +#define PAD_VAL_REG 0x8 -/* pad_val reg power-on default varies by pad, and apparently can cause issues - * if not set correctly, even if the pin isn't configured as GPIO. */ -#define PAD_VAL_DEFAULT PAD_VAL_INPUT +/* Some banks have no legacy GPIO interface */ +#define GP_LEGACY_BASE_NONE 0xFFFF -/* Configure GPIOs as MMIO by default */ -#define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } +/* Number of GPIOs in each bank */ +#define GPNCORE_COUNT 27 +#define GPSCORE_COUNT 102 +#define GPSSUS_COUNT 44 + +#define GP_SOUTHWEST_COUNT 56 +#define GP_NORTH_COUNT 59 +#define GP_EAST_COUNT 24 +#define GP_SOUTHEAST_COUNT 55 + +/* General */ +#define GPIO_REGS_SIZE 8 +#define NA 0 +#define LOW 0 +#define HIGH 1 +#define MASK_WAKE 0 +#define UNMASK_WAKE 1 +#define GPE_CAPABLE 1 +#define GPE_CAPABLE_NONE 0 + +#define MAX_FAMILY_PAD_GPIO_NO 15 +#define FAMILY_PAD_REGS_OFF 0x4400 +#define FAMILY_PAD_REGS_SIZE 0x400 + +/* config0[31:28] - Interrupt Selection Interrupt Select */ +#define PAD_INT_SEL(int_s) (int_s << 28) + +/* config0[27:26] - Glitch Filter Config */ +#define PAD_GFCFG(glitch_cfg) (glitch_cfg << 26) +#define PAD_GFCFG_DISABLE (0 << 26) +#define PAD_ENABLE_EDGE_DETECTION (1 << 26) /* EDGE DETECTION ONLY */ +#define PAD_ENABLE_RX_DETECTION (2 << 26) /* RX DETECTION ONLY */ +#define PAD_ENABLE_EDGE_RX_DETECTION (3 << 26) /* RX & EDGE DETECTION */ + +/* config0[25:24] - RX/TX Enable Config */ +#define PAD_FUNC_CTRL(tx_rx_enable) (tx_rx_enable << 24) +#define PAD_FUNC_CTRL_RX_TX_ENABLE (0 << 24) +#define PAD_FUNC_CTRL_TX_ENABLE_RX_DISABLE (1 << 24) +#define PAD_FUNC_CTRL_TX_ENABLE_RX_ENABLE (2 << 24) +#define PAD_TX_RX_ENABLE (3 << 24) + +/* config0[23:20] - Termination */ +#define PAD_PULL(TERM) (TERM << 20) +#define PAD_PULL_DISABLE (0 << 20) +#define PAD_PULL_DOWN_20K (1 << 20) +#define PAD_PULL_DOWN_5K (2 << 20) +#define PAD_PULL_DOWN_1K (4 << 20) +#define PAD_PULL_UP_20K (9 << 20) +#define PAD_PULL_UP_5K (10 << 20) +#define PAD_PULL_UP_1K (12 << 20) + +/* config0[19:16] - PAD Mode */ +#define PAD_MODE_SELECTION(MODE_SEL) (MODE_SEL<<16) + +#define SET_PAD_MODE_SELECTION(pad_config, mode) \ + ((pad_config & 0xfff0ffff) | PAD_MODE_SELECTION(mode)) + +/* config0[15] - GPIO Enable */ +#define PAD_GPIO_DISABLE (0 << 15) +#define PAD_GPIO_ENABLE (1 << 15) + +/* config0[14:11] - Reserver2 */ + +/* config0[10:8] - GPIO Config */ +#define PAD_GPIO_CFG(gpio_cfg) (gpio_cfg << 8) +#define PAD_GPIOFG_GPIO (0 << 8) +#define PAD_GPIOFG_GPO (1 << 8) +#define PAD_GPIOFG_GPI (2 << 8) +#define PAD_GPIOFG_HI_Z (3 << 8) + +/* config0[7] - Gpio Light Mode Bar */ +/* config0[6:2] - Reserved1 */ +/* config0[1] - GPIO TX State */ +#define PAD_DEFAULT_TX(STATE) (STATE<<1) +/* config0[0] - GPIO RX State */ +#define PAD_RX_BIT 1 + +/* Pad Control Register 1 configuration */ +#define PAD_DISABLE_INT (0 << 0) +#define PAD_TRIG_EDGE_LOW (1 << 0) +#define PAD_TRIG_EDGE_HIGH (2 << 0) +#define PAD_TRIG_EDGE_BOTH (3 << 0) +#define PAD_TRIG_EDGE_LEVEL (4 << 0) + +/* Pad config0 power-on values */ +#define PAD_CONFIG0_DEFAULT 0x00010300 +#define PAD_CONFIG0_DEFAULT0 0x00910300 +#define PAD_CONFIG0_DEFAULT1 0x00110300 +#define PAD_CONFIG0_GPI_DEFAULT 0x00010200 + +/* Pad config1 reg power-on values */ +#define PAD_CONFIG1_DEFAULT0 0x05C00000 +#define PAD_CONFIG1_CSEN 0x0DC00000 +#define PAD_CONFIG1_DEFAULT1 0x05C00020 + +#define GPIO_INPUT_NO_PULL \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_GPIO_ENABLE \ + | PAD_CONFIG0_GPI_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } #define GPIO_INPUT_PU_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PD_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PD_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_NOPU \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_LEGACY_NOPU \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .is_gpio = 1 } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ_LEVELHIGH_NO_PULL \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ_LEVELLOW_PU_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_LEVEL_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ_EDGELOW_PU_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ_EDGEHIGH_PD_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_EDGE_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ_EDGELOW_PD_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ_EDGEBOTH_PU_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ| PAD_TNE_IRQ | PAD_EDGE_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -#define GPIO_OUT_LOW \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_LOW, \ - .is_gpio = 1 } - -#define GPIO_OUT_HIGH \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_HIGH, \ - .is_gpio = 1 } - -/* Define no-pull / PU / PD configs for each functional config option */ -#define GPIO_FUNC(_func, _pudir, _str) \ - { .use_sel = GPIO_USE_MMIO, \ - .pad_conf0 = PAD_FUNC##_func | PAD_##_pudir | PAD_PU_##_str | \ - PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -/* Default functional configs -- no PU */ -#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 20K) -#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 20K) -#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 20K) -#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 20K) -#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 20K) -#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 20K) -#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 20K) - -/* ACPI GPIO routing. Assume everything is externally pulled and negative edge - * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */ -#define GPIO_ACPI_SCI \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .sci = 1, \ - .wake_en = 1, } -#define GPIO_ACPI_WAKE \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .wake_en = 1, } -#define GPIO_ACPI_SMI \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .smi = 1} + { .pad_conf0 = PAD_PULL_UP_20K | PAD_GPIO_ENABLE \ + | PAD_CONFIG0_GPI_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +#define GPIO_INPUT_PU_5K \ + { .pad_conf0 = PAD_PULL_UP_5K | PAD_GPIO_ENABLE \ + | PAD_CONFIG0_GPI_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +#define GPI(int_type, int_sel, term, int_msk, glitch_cfg, wake_msk, gpe_val) { \ + .pad_conf0 = PAD_INT_SEL(int_sel) | PAD_GFCFG(glitch_cfg) \ + | PAD_PULL(term) | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI, \ + .pad_conf1 = int_type << 0 | PAD_CONFIG1_DEFAULT0, \ + .wake_mask = wake_msk, \ + .int_mask = int_msk, \ + .gpe = gpe_val } + +#define GPO_FUNC(term, tx_state) {\ + .pad_conf0 = PAD_GPIO_ENABLE | PAD_GPIOFG_GPO | PAD_PULL(term) \ + | tx_state << 1, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +#define NATIVE_FUNC(mode, term, inv_rx_tx) {\ + .pad_conf0 = PAD_GPIO_DISABLE | PAD_GPIOFG_HI_Z \ + | PAD_MODE_SELECTION(mode) | PAD_PULL(term),\ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 | inv_rx_tx << 4 } + +#define NATIVE_FUNC_TX_RX(tx_rx_enable, mode, term, inv_rx_tx) {\ + .pad_conf0 = PAD_FUNC_CTRL(tx_rx_enable) | PAD_GPIO_DISABLE \ + | PAD_GPIOFG_GPIO | PAD_MODE_SELECTION(mode) \ + | PAD_PULL(term),\ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 | inv_rx_tx << 4 } + +#define NATIVE_FUNC_CSEN(mode, term, inv_rx_tx) {\ + .pad_conf0 = PAD_GPIO_DISABLE | PAD_GPIOFG_HI_Z \ + | PAD_MODE_SELECTION(mode) | PAD_PULL(term),\ + .pad_conf1 = PAD_CONFIG1_CSEN | inv_rx_tx << 4 } + +#define NATIVE_INT(mode, int_sel) {\ + .pad_conf0 = PAD_INT_SEL(int_sel) | PAD_GPIO_DISABLE \ + | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +#define SPEAKER \ +{ .pad_conf0 = PAD_CONFIG0_DEFAULT0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +#define SPARE_PIN\ + { .pad_conf0 = 0x00110300,\ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +/* SCI , SMI, Wake */ +#define GPIO_SCI(int_sel) \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\ + | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \ + | PAD_INT_SEL(int_sel), \ + .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \ + .gpe = SCI, \ + .int_mask = 1 } + +#define GPIO_WAKE(int_sel) \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\ + | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \ + | PAD_INT_SEL(int_sel), \ + .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \ + .int_mask = 1 ,\ + .wake_mask = 1 } + +#define GPIO_SMI(int_sel) \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\ + | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \ + | PAD_INT_SEL(int_sel), \ + .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \ + .int_mask = 1,\ + .gpe = SMI } + +#define GPIO_SKIP { .skip_config = 1 } + +/* Common GPIO settings */ +#define NATIVE_DEFAULT(mode) NATIVE_FUNC(mode, 0, 0) /* no pull */ +#define NATIVE_PU20K(mode) NATIVE_FUNC(mode, 9, 0) /* PH 20k */ +#define NATIVE_PU5K(mode) NATIVE_FUNC(mode, 10, 0) /* PH 5k */ +#define NATIVE_PU5K_INVTX(mode) NATIVE_FUNC(mode, 10, inv_tx_enable) /* PH 5k */ +#define NATIVE_PU1K(mode) NATIVE_FUNC(mode, 12, 0) /* PH 1k */ +#define NATIVE_PU1K_CSEN_INVTX(mode) \ + NATIVE_FUNC_CSEN(mode, 12, inv_tx_enable) /* PH 1k */ +#define NATIVE_PU1K_INVTX(mode) NATIVE_FUNC(mode, 12, inv_tx_enable) /* PH 1k */ +#define NATIVE_PD20K(mode) NATIVE_FUNC(mode, 1, 0) /* PD 20k */ +#define NATIVE_PD5K(mode) NATIVE_FUNC(mode, 2, 0) /* PD 5k */ +#define NATIVE_PD1K(mode) NATIVE_FUNC(mode, 4, 0) /* PD 1k */ +#define NATIVE_PD1K_CSEN_INVTX(mode) NATIVE_FUNC_CSEN(mode, 4, inv_tx_enable) + /* no pull */ +#define NATIVE_TX_RX_EN NATIVE_FUNC_TX_RX(3, 1, 0, inv_tx_enable) +#define NATIVE_TX_RX_M1 NATIVE_FUNC_TX_RX(0, 1, 0, 0) /* no pull */ +#define NATIVE_TX_RX_M3 NATIVE_FUNC_TX_RX(0, 3, 0, 0) /* no pull */ +#define NATIVE_PU1K_M1 NATIVE_PU1K(1) /* PU1k M1 */ + +/* Default native functions */ +#define Native_M0 NATIVE_DEFAULT(0) +#define Native_M1 NATIVE_DEFAULT(1) +#define Native_M2 NATIVE_DEFAULT(2) +#define Native_M3 NATIVE_DEFAULT(3) +#define Native_M4 NATIVE_DEFAULT(4) +#define Native_M5 NATIVE_DEFAULT(5) +#define Native_M6 NATIVE_DEFAULT(6) +#define Native_M7 NATIVE_DEFAULT(7) +#define Native_M8 NATIVE_DEFAULT(8) + +#define GPIO_OUT_LOW GPO_FUNC(0, 0) /* gpo low */ +#define GPIO_OUT_HIGH GPO_FUNC(0, 1) /* gpo high */ +#define GPIO_NC GPIO_INPUT_PU_20K /* not connect */ /* End marker */ #define GPIO_LIST_END 0xffffffff @@ -317,143 +351,226 @@ #define GPIO_END \ { .pad_conf0 = GPIO_LIST_END } -/* Common default GPIO settings */ -#define GPIO_INPUT GPIO_INPUT_NOPU -#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU -#define GPIO_INPUT_PU GPIO_INPUT_PU_20K -#define GPIO_INPUT_PD GPIO_INPUT_PD_20K -#define GPIO_NC GPIO_OUT_HIGH -#define GPIO_DEFAULT GPIO_FUNC0 - /* 16 DirectIRQs per supported bank */ -#define GPIO_MAX_DIRQS 16 - -/* Most pins are GPIO function 0. Some banks have a range of pins with GPIO - * function 1. Indicate first / last GPIOs with function 1. */ -#define GPIO_NONE 255 -/* All NCORE GPIOs are function 0 */ -#define GPNCORE_GPIO_F1_RANGE_START GPIO_NONE -#define GPNCORE_GPIO_F1_RANGE_END GPIO_NONE -/* SCORE GPIO [92:93] are function 1 */ -#define GPSCORE_GPIO_F1_RANGE_START 92 -#define GPSCORE_GPIO_F1_RANGE_END 93 -/* SSUS GPIO [11:21] are function 1 */ -#define GPSSUS_GPIO_F1_RANGE_START 11 -#define GPSSUS_GPIO_F1_RANGE_END 21 +#define GPIO_MAX_DIRQS 16 + +#define GPIO_NONE 255 + +/* Functions / defines for changing GPIOs in romstage */ +/* SCORE Pad definitions. */ +#define UART_RXD_PAD 82 +#define UART_TXD_PAD 83 +#define PCU_SMB_CLK_PAD 88 +#define PCU_SMB_DATA_PAD 90 +#define SOC_DDI1_VDDEN_PAD 16 +#define UART1_RXD_PAD 9 +#define UART1_TXD_PAD 13 +#define DDI2_DDC_SCL 48 +#define DDI2_DDC_SDA 53 struct soc_gpio_map { u32 pad_conf0; u32 pad_conf1; u32 pad_val; - u32 use_sel : 1; - u32 io_sel : 1; - u32 gp_lvl : 1; - u32 tpe : 1; - u32 tne : 1; - u32 wake_en : 1; - u32 smi : 1; - u32 is_gpio : 1; - u32 sci : 1; + u32 gpe; + u32 int_mask:1; + u32 wake_mask:1; + u32 is_gpio:1; + u32 skip_config:1; } __attribute__ ((packed)); struct soc_gpio_config { - const struct soc_gpio_map *ncore; - const struct soc_gpio_map *score; - const struct soc_gpio_map *ssus; - const u8 (*core_dirq)[GPIO_MAX_DIRQS]; - const u8 (*sus_dirq)[GPIO_MAX_DIRQS]; + const struct soc_gpio_map *north; + const struct soc_gpio_map *southeast; + const struct soc_gpio_map *southwest; + const struct soc_gpio_map *east; }; -/* Description of GPIO 'bank' ex. {ncore, score. ssus} */ +/* Description of a GPIO 'community' */ struct gpio_bank { const int gpio_count; - const u8* gpio_to_pad; + const u8 *gpio_to_pad; const int legacy_base; const unsigned long pad_base; - const u8 has_wake_en :1; - const u8 gpio_f1_range_start; - const u8 gpio_f1_range_end; + const u8 has_gpe_en:1; + const u8 has_wake_en:1; }; -void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap); -/* This function is weak and can be overridden by a mainboard function. */ -struct soc_gpio_config* mainboard_get_gpios(void); +typedef enum { + NATIVE = 0xff, + GPIO = 0, /* Native, no need to set PAD_VALUE */ + GPO = 1, /* GPI, input only in PAD_VALUE */ + GPI = 2, /* GPO, output only in PAD_VALUE */ + HI_Z = 3, + NA_GPO = 0, +} gpio_en_t; + +typedef enum { + LO = 0, + HI = 1, +} gpo_d4_t; + +typedef enum { + F0 = 0, + F1 = 1, + F2 = 2, + F3 = 3 +} gpio_func_num_t; + +typedef enum { + _CAP = 1, + _NOT_CAP = 0 +} int_capable_t; + +typedef enum { + P_NONE = 0, /* Pull None */ + P_20K_L = 1, /* Pull Down 20K */ + P_5K_L = 2, /* Pull Down 5K */ + P_1K_L = 4, /* Pull Down 1K */ + P_20K_H = 9, /* Pull Up 20K */ + P_5K_H = 10, /* Pull Up 5K */ + P_1K_H = 12 /* Pull Up 1K */ +} pull_type_t; + +typedef enum { + DISABLE = 0, /* Disable */ + ENABLE = 1, /* Enable */ +} park_mode_enb_t; + +typedef enum { + VOLT_3_3 = 0, /* Working on 3.3 Volts */ + VOLT_1_8 = 1, /* Working on 1.8 Volts */ +} voltage_t; + +typedef enum { + DISABLE_HS = 0, /* Disable high speed mode */ + ENABLE_HS = 1, /* Enable high speed mode */ +} hs_mode_t; + +typedef enum { + PULL_UP = 0, /* On Die Termination Up */ + PULL_DOWN = 1, /* On Die Termination Down */ +} odt_up_dn_t; + +typedef enum { + DISABLE_OD = 0, /* On Die Termination Disable */ + ENABLE_OD = 1, /* On Die Termination Enable */ +} odt_en_t; + +typedef enum { + ONE_BIT = 1, + TWO_BIT = 3, + THREE_BIT = 7, + FOUR_BIT = 15, + FIVE_BIT = 31, + SIX_BIT = 63, + SEVEN_BIT = 127, + EIGHT_BIT = 255 +} bit_t; + +typedef enum { + M0 = 0, + M1, + M2, + M3, + M4, + M5, + M6, + M7, + M8, + M9, + M10, + M11, + M12, + M13, +} mode_list_t; + +typedef enum { + L0 = 0, + L1 = 1, + L2 = 2, + L3 = 3, + L4 = 4, + L5 = 5, + L6 = 6, + L7 = 7, + L8 = 8, + L9 = 9, + L10 = 10, + L11 = 11, + L12 = 12, + L13 = 13, + L14 = 14, + L15 = 15, +} int_select_t; + +typedef enum { + INT_DIS = 0, + trig_edge_low = 1, + trig_edge_high = 2, + trig_edge_both = 3, + trig_level = 4, +} int_type_t; + +typedef enum { + glitch_disable = 0, + en_edge_detect, + en_rx_data, + en_edge_rx_data, +} glitch_cfg; + +typedef enum { + maskable = 0, + non_maskable, +} mask_t; + +typedef enum { + GPE = 0, + SMI, + SCI, +} gpe_config_t; -/* Functions / defines for changing GPIOs in romstage */ -/* SCORE Pad definitions. */ -#define UART_RXD_PAD 82 -#define UART_TXD_PAD 83 -#define PCU_SMB_CLK_PAD 88 -#define PCU_SMB_DATA_PAD 90 -#define SOC_DDI1_VDDEN_PAD 16 - -static inline u32 *ncore_pconf0(int pad_num) -{ - return (u32 *)(GPNCORE_PAD_BASE + pad_num * 16); -} - -static inline void ncore_select_func(int pad, int func) -{ - uint32_t reg; - u32 *pconf0_addr = ncore_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~0x7; - reg |= func & 0x7; - write32(pconf0_addr, reg); -} - -static inline u32 *score_pconf0(int pad_num) -{ - return (u32 *)(GPSCORE_PAD_BASE + pad_num * 16); -} - -static inline u32 *ssus_pconf0(int pad_num) -{ - return (u32 *)(GPSSUS_PAD_BASE + pad_num * 16); -} +/* + * InvertRxTx 7:4 + * 0 - No Inversion + * 1 - Inversion + * [0] RX Enable + * [1] TX Enable + * [2] RX Data + * [3] TX Data + */ +typedef enum { + no_inversion = 0, + inv_rx_enable = 0x1, + inv_tx_enable = 0x2, + inv_rx_tx_enable = 0x3, + inv_rx_data = 0x4, + inv_tx_data = 0x8, +} invert_rx_tx_t; -static inline void score_select_func(int pad, int func) -{ - uint32_t reg; - uint32_t *pconf0_addr = score_pconf0(pad); +#define PAD_VAL_HIGH (1 << 0) - reg = read32(pconf0_addr); - reg &= ~0x7; - reg |= func & 0x7; - write32(pconf0_addr, reg); -} +void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap); +struct soc_gpio_config *mainboard_get_gpios(void); -static inline void ssus_select_func(int pad, int func) +static inline void ncore_select_func(int pad, int func) { - uint32_t reg; - uint32_t *pconf0_addr = ssus_pconf0(pad); - reg = read32(pconf0_addr); - reg &= ~0x7; - reg |= func & 0x7; - write32(pconf0_addr, reg); } /* These functions require that the input pad be configured as an input GPIO */ -static inline int score_get_gpio(int pad) -{ - uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - return read32(val_addr) & PAD_VAL_HIGH; -} static inline int ssus_get_gpio(int pad) { - uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - return read32(val_addr) & PAD_VAL_HIGH; + return 0; } static inline void ssus_disable_internal_pull(int pad) { - const uint32_t pull_mask = ~(0xf << 7); - write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask); } -#endif /* _BAYTRAIL_GPIO_H_ */ +int get_gpio(int community_base, int pad0_offset); +uint16_t gpio_family_number(uint8_t community, uint8_t pad); +uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad); + +#endif /* _SOC_GPIO_H_ */ diff --git a/src/soc/intel/braswell/include/soc/hda.h b/src/soc/intel/braswell/include/soc/hda.h new file mode 100644 index 0000000..11fd404 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/hda.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _SOC_HDA_H_ +#define _SOC_HDA_H_ + +/* + * PCI config registers. + */ + +#define HDA_DCKSTS 0x4d +# define HDA_DCKSTS_DS (1 << 7) +# define HDA_DCKSTS_DM (1 << 0) + +#define HDA_DEVC 0x78 +# define HDA_DEVC_MRRS 0x7000 +# define HDA_DEVC_NSNPEN (1 << 11) +# define HDA_DEVC_AUXPEN (1 << 10) +# define HDA_DEVC_PEEN (1 << 9) +# define HDA_DEVC_ETEN (1 << 8) +# define HDA_DEVC_MAXPAY 0x00e0 +# define HDA_DEVC_ROEN (1 << 4) +# define HDA_DEVC_URREN (1 << 3) +# define HDA_DEVC_FEREN (1 << 2) +# define HDA_DEVC_NFEREN (1 << 1) +# define HDA_DEVC_CEREN (1 << 0) + +#endif /* _SOC_HDA_H_ */ diff --git a/src/soc/intel/braswell/include/soc/iomap.h b/src/soc/intel/braswell/include/soc/iomap.h index 5c5e9ab..c4775ea 100644 --- a/src/soc/intel/braswell/include/soc/iomap.h +++ b/src/soc/intel/braswell/include/soc/iomap.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_IOMAP_H_ -#define _BAYTRAIL_IOMAP_H_ +#ifndef _SOC_IOMAP_H_ +#define _SOC_IOMAP_H_ /* @@ -38,11 +39,12 @@ #define PMC_BASE_SIZE 0x400 /* IO Memory */ -#define IO_BASE_ADDRESS 0xfed0c000 -#define IO_BASE_OFFSET_GPSCORE 0x0000 -#define IO_BASE_OFFSET_GPNCORE 0x1000 -#define IO_BASE_OFFSET_GPSSUS 0x2000 +#define IO_BASE_ADDRESS 0xfed80000 #define IO_BASE_SIZE 0x4000 +#define COMMUNITY_OFFSET_GPSOUTHWEST 0x00000 +#define COMMUNITY_OFFSET_GPNORTH 0x08000 +#define COMMUNITY_OFFSET_GPEAST 0x10000 +#define COMMUNITY_OFFSET_GPSOUTHEAST 0x18000 /* Intel Legacy Block */ #define ILB_BASE_ADDRESS 0xfed08000 @@ -53,11 +55,11 @@ #define SPI_BASE_SIZE 0x400 /* MODPHY */ -#define MPHY_BASE_ADDRESS 0xfef00000 +#define MPHY_BASE_ADDRESS 0xfea00000 #define MPHY_BASE_SIZE 0x100000 /* Power Management Unit */ -#define PUNIT_BASE_ADDRESS 0xfed05000 +#define PUNIT_BASE_ADDRESS 0xfed06000 #define PUNIT_BASE_SIZE 0x800 /* Root Complex Base Address */ @@ -87,4 +89,4 @@ uint32_t nc_read_top_of_low_memory(void); #endif -#endif /* _BAYTRAIL_IOMAP_H_ */ +#endif /* _SOC_IOMAP_H_ */ diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index bf67294..60763d9 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -17,29 +18,33 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_IOSF_H_ -#define _BAYTRAIL_IOSF_H_ +#ifndef _SOC_IOSF_H_ +#define _SOC_IOSF_H_ #include <stdint.h> +#if ENV_RAMSTAGE +#include <device/device.h> +#include <reg_script.h> +#endif /* ENV_RAMSTAGE */ #include <soc/pci_devs.h> /* - * The Bay Trail SoC has a message network called IOSF Sideband. The access + * The SoC has a message network called IOSF Sideband. The access * routines are through 3 registers in PCI config space of 00:00.0: * MCR - control register * MDR - data register * MCRX - control register extension - * The extension regist is only used for addresses that don't fit into the - * 8 bit register address. + * The extension register is only used for addresses that don't fit + * into the 8 bit register address. */ #ifndef PCI_DEV #define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12)) #endif -#define IOSF_PCI_DEV PCI_DEV(0,SOC_DEV,SOC_FUNC) +#define IOSF_PCI_DEV PCI_DEV(0, SOC_DEV, SOC_FUNC) #define MCR_REG 0xd0 #define IOSF_OPCODE(x) ((x) << 24) @@ -55,63 +60,29 @@ #define MDR_REG 0xd4 #define MCRX_REG 0xd8 -uint32_t iosf_aunit_read(int reg); -void iosf_aunit_write(int reg, uint32_t val); -uint32_t iosf_cpu_bus_read(int reg); -void iosf_cpu_bus_write(int reg, uint32_t val); uint32_t iosf_bunit_read(int reg); void iosf_bunit_write(int reg, uint32_t val); -uint32_t iosf_dunit_read(int reg); -void iosf_dunit_write(int reg, uint32_t val); -/* Some registers are per channel while the globals live in dunit 0 */ -uint32_t iosf_dunit_ch0_read(int reg); -uint32_t iosf_dunit_ch1_read(int reg); uint32_t iosf_punit_read(int reg); void iosf_punit_write(int reg, uint32_t val); -uint32_t iosf_usbphy_read(int reg); -void iosf_usbphy_write(int reg, uint32_t val); -uint32_t iosf_ushphy_read(int reg); -void iosf_ushphy_write(int reg, uint32_t val); -uint32_t iosf_sec_read(int reg); -void iosf_sec_write(int reg, uint32_t val); -uint32_t iosf_port45_read(int reg); -void iosf_port45_write(int reg, uint32_t val); -uint32_t iosf_port46_read(int reg); -void iosf_port46_write(int reg, uint32_t val); -uint32_t iosf_port47_read(int reg); -void iosf_port47_write(int reg, uint32_t val); -uint32_t iosf_port55_read(int reg); -void iosf_port55_write(int reg, uint32_t val); -uint32_t iosf_port58_read(int reg); -void iosf_port58_write(int reg, uint32_t val); -uint32_t iosf_port59_read(int reg); -void iosf_port59_write(int reg, uint32_t val); -uint32_t iosf_port5a_read(int reg); -void iosf_port5a_write(int reg, uint32_t val); -uint32_t iosf_lpss_read(int reg); -void iosf_lpss_write(int reg, uint32_t val); -uint32_t iosf_ccu_read(int reg); -void iosf_ccu_write(int reg, uint32_t val); uint32_t iosf_score_read(int reg); void iosf_score_write(int reg, uint32_t val); +uint32_t iosf_lpss_read(int reg); +void iosf_lpss_write(int reg, uint32_t val); +uint32_t iosf_port58_read(int reg); +void iosf_port58_write(int reg, uint32_t val); uint32_t iosf_scc_read(int reg); void iosf_scc_write(int reg, uint32_t val); -uint32_t iosf_porta2_read(int reg); -void iosf_porta2_write(int reg, uint32_t val); -uint32_t iosf_ssus_read(int reg); -void iosf_ssus_write(int reg, uint32_t val); + +#if ENV_RAMSTAGE +uint64_t reg_script_read_iosf(struct reg_script_context *ctx); +void reg_script_write_iosf(struct reg_script_context *ctx); +#endif /* ENV_RAMSTAGE */ /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ -#define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ -#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ #define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */ #define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */ #define IOSF_PORT_PMC 0x04 /* Power Management Controller */ -#define IOSF_PORT_GFX 0x06 /* Graphics Adapter */ -#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ -#define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ -#define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_SEC 0x44 /* SEC */ #define IOSF_PORT_0x45 0x45 #define IOSF_PORT_0x46 0x46 @@ -125,148 +96,42 @@ void iosf_ssus_write(int reg, uint32_t val); #define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_0xa2 0xa2 -#define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ -#define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ #define IOSF_PORT_SSUS 0xa8 /* SUS */ #define IOSF_PORT_CCU 0xa9 /* Clock control unit. */ /* Read and write opcodes differ per port. */ -#define IOSF_OP_READ_AUNIT 0x10 -#define IOSF_OP_WRITE_AUNIT (IOSF_OP_READ_AUNIT | 1) -#define IOSF_OP_READ_SYSMEMC 0x10 -#define IOSF_OP_WRITE_SYSMEMC (IOSF_OP_READ_SYSMEMC | 1) -#define IOSF_OP_READ_CPU_BUS 0x10 -#define IOSF_OP_WRITE_CPU_BUS (IOSF_OP_READ_CPU_BUS | 1) #define IOSF_OP_READ_BUNIT 0x10 #define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1) #define IOSF_OP_READ_PMC 0x06 #define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1) -#define IOSF_OP_READ_GFX 0x00 -#define IOSF_OP_WRITE_GFX (IOSF_OP_READ_GFX | 1) -#define IOSF_OP_READ_SYSMEMIO 0x06 -#define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) -#define IOSF_OP_READ_USBPHY 0x06 -#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) -#define IOSF_OP_READ_SEC 0x04 -#define IOSF_OP_WRITE_SEC (IOSF_OP_READ_SEC | 1) -#define IOSF_OP_READ_0x45 0x06 -#define IOSF_OP_WRITE_0x45 (IOSF_OP_READ_0x45 | 1) -#define IOSF_OP_READ_0x46 0x06 -#define IOSF_OP_WRITE_0x46 (IOSF_OP_READ_0x46 | 1) -#define IOSF_OP_READ_0x47 0x06 -#define IOSF_OP_WRITE_0x47 (IOSF_OP_READ_0x47 | 1) #define IOSF_OP_READ_SCORE 0x06 #define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1) -#define IOSF_OP_READ_0x55 0x04 -#define IOSF_OP_WRITE_0x55 (IOSF_OP_READ_0x55 | 1) -#define IOSF_OP_READ_0x58 0x06 -#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) -#define IOSF_OP_READ_0x59 0x06 -#define IOSF_OP_WRITE_0x59 (IOSF_OP_READ_0x59 | 1) -#define IOSF_OP_READ_0x5a 0x04 -#define IOSF_OP_WRITE_0x5a (IOSF_OP_READ_0x5a | 1) -#define IOSF_OP_READ_USHPHY 0x06 -#define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) -#define IOSF_OP_READ_SCC 0x06 -#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) #define IOSF_OP_READ_LPSS 0x06 #define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) -#define IOSF_OP_READ_0xa2 0x06 -#define IOSF_OP_WRITE_0xa2 (IOSF_OP_READ_0xa2 | 1) -#define IOSF_OP_READ_SATAPHY 0x00 -#define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) -#define IOSF_OP_READ_PCIEPHY 0x00 -#define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1) -#define IOSF_OP_READ_SSUS 0x10 -#define IOSF_OP_WRITE_SSUS (IOSF_OP_READ_SSUS | 1) -#define IOSF_OP_READ_CCU 0x06 -#define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1) +#define IOSF_OP_READ_0x58 0x06 +#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) +#define IOSF_OP_READ_SCC 0x06 +#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) /* * BUNIT Registers. */ -#define BNOCACHE 0x23 /* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ #define BUNIT_BMBOUND 0x25 -/* BMBOUND_HI describes the available ram above 4GiB. It has a +/* + * BMBOUND_HI describes the available ram above 4GiB. It has a * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB * granularity care needs to be taken with the e820 map to account for a hole - * in the ram. */ + * in the ram. + */ #define BUNIT_BMBOUND_HI 0x26 #define BUNIT_MMCONF_REG 0x27 +#define BUNIT_BMISC 0x28 /* The SMMRR registers define the SMM region in MiB granularity. */ -#define BUNIT_SMRCP 0x2b -#define BUNIT_SMRRAC 0x2c -#define BUNIT_SMRWAC 0x2d #define BUNIT_SMRRL 0x2e #define BUNIT_SMRRH 0x2f -# define BUNIT_SMRR_ENABLE (1 << 31) - -/* SA ID bits. */ -#define SAI_IA_UNTRUSTED (1 << 0) -#define SAI_IA_SMM (1 << 2) -#define SAI_IA_BOOT (1 << 4) - -/* - * DUNIT Registers. - */ - -#define DRP 0x00 -# define DRP_DIMM0_RANK0_EN (0x01 << 0) -# define DRP_DIMM0_RANK1_EN (0x01 << 1) -# define DRP_DIMM1_RANK0_EN (0x01 << 2) -# define DRP_DIMM1_RANK1_EN (0x01 << 3) -# define DRP_RANK_MASK (DRP_DIMM0_RANK0_EN | DRP_DIMM0_RANK1_EN | \ - DRP_DIMM1_RANK0_EN | DRP_DIMM1_RANK1_EN) -#define DTR0 0x01 -# define DTR0_SPEED_MASK 0x03 -# define DTR0_SPEED_800 0x00 -# define DTR0_SPEED_1066 0x01 -# define DTR0_SPEED_1333 0x02 -# define DTR0_SPEED_1600 0x03 - -/* - * PUNIT Registers - */ -#define SB_BIOS_CONFIG 0x06 -# define SB_BIOS_CONFIG_ECC_EN (1 << 31) -# define SB_BIOS_CONFIG_DUAL_CH_DIS (1 << 30) -# define SB_BIOS_CONFIG_EFF_ECC (1 << 29) -# define SB_BIOS_CONFIG_EFF_DUAL_CH_DIS (1 << 28) -# define SB_BIOS_CONFIG_PERF_MODE (1 << 17) -# define SB_BIOS_CONFIG_PDM_MODE (1 << 16) -# define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8) -# define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7) -# define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3) -# define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2) -# define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1) -# define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0) -#define BIOS_RESET_CPL 0x05 -# define BIOS_RESET_CPL_ALL_DONE (1 << 1) -# define BIOS_RESET_CPL_RESET_DONE (1 << 0) -#define PUNIT_PWRGT_CONTROL 0x60 -#define PUNIT_PWRGT_STATUS 0x61 -#define PUNIT_GPU_EC_VIRUS 0xd2 - -#define PUNIT_SOC_POWER_BUDGET 0x02 -#define PUNIT_SOC_ENERGY_CREDIT 0x03 -#define PUNIT_PTMC 0x80 -#define PUNIT_GFXT 0x88 -#define PUNIT_VEDT 0x89 -#define PUNIT_ISPT 0x8c -#define PUNIT_PTPS 0xb2 -#define PUNIT_TE_AUX0 0xb5 -#define PUNIT_TE_AUX1 0xb6 -#define PUNIT_TE_AUX2 0xb7 -#define PUNIT_TE_AUX3 0xb8 -#define PUNIT_TTE_VRIccMax 0xb9 -#define PUNIT_TTE_VRHot 0xba -#define PUNIT_TTE_XXPROCHOT 0xbb -#define PUNIT_TTE_SLM0 0xbc -#define PUNIT_TTE_SLM1 0xbd -#define PUNIT_TTE_SWT 0xbf /* * LPSS Registers @@ -296,54 +161,37 @@ void iosf_ssus_write(int reg, uint32_t val); */ #define SCC_SD_CTL 0x504 #define SCC_SDIO_CTL 0x508 -#define SCC_MMC_CTL 0x50c +#define SCC_MMC_CTL 0x500 # define SCC_CTL_PCI_CFG_DIS (1 << 0) # define SCC_CTL_ACPI_INT_EN (1 << 1) /* - * CCU Registers - */ - -#define PLT_CLK_CTRL_0 0x3c -#define PLT_CLK_CTRL_1 0x40 -#define PLT_CLK_CTRL_2 0x44 -#define PLT_CLK_CTRL_3 0x48 -#define PLT_CLK_CTRL_4 0x4c -#define PLT_CLK_CTRL_5 0x50 -# define PLT_CLK_CTRL_19P2MHZ_FREQ (0 << 1) -# define PLT_CLK_CTRL_25MHZ_FREQ (1 << 1) -# define PLT_CLK_CTRL_SELECT_FREQ (1 << 0) - -/* - * USBPHY Registers - */ -#define USBPHY_COMPBG 0x7f04 -#define USBPHY_PER_PORT_LANE0 0x4100 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP0 0x4122 -#define USBPHY_PER_PORT_LANE1 0x4200 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP1 0x4222 -#define USBPHY_PER_PORT_LANE2 0x4300 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP2 0x4322 -#define USBPHY_PER_PORT_LANE3 0x4400 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP3 0x4422 - -/* - * USHPHY Registers - */ -#define USHPHY_CDN_PLL_CONTROL 0x03c0 -#define USHPHY_CDN_VCO_START_CAL_POINT 0x0054 -#define USHPHY_CCDRLF 0x8040 -#define USHPHY_PEAKING_AMP_CONFIG_DIAG 0x80a8 -#define USHPHY_OFFSET_COR_CONFIG_DIAG 0x80b0 -#define USHPHY_VGA_GAIN_CONFIG_DIAG 0x8080 -#define USHPHY_REE_DAC_CONTROL 0x80b8 -#define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000 - -/* * LPE Registers */ #define LPE_PCICFGCTR1 0x0500 # define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0) # define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1) -#endif /* _BAYTRAIL_IOSF_H_ */ +/* + * IO Sideband Function + */ + +#if ENV_RAMSTAGE +#define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ + REG_SCRIPT_TYPE_IOSF, \ + REG_SCRIPT_SIZE_32, \ + reg_, mask_, value_, timeout_, unit_) +#define REG_IOSF_READ(unit_, reg_) \ + REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0) +#define REG_IOSF_WRITE(unit_, reg_, value_) \ + REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0) +#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \ + REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0) +#define REG_IOSF_OR(unit_, reg_, value_) \ + REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_) +#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \ + REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) +#endif /* ENV_RAMSTAGE */ + +#endif /* _SOC_IOSF_H_ */ diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h index 4f9f059..3367873 100644 --- a/src/soc/intel/braswell/include/soc/irq.h +++ b/src/soc/intel/braswell/include/soc/irq.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_IRQ_H_ -#define _BAYTRAIL_IRQ_H_ +#ifndef _SOC_IRQ_H_ +#define _SOC_IRQ_H_ #define PIRQA_APIC_IRQ 16 #define PIRQB_APIC_IRQ 17 @@ -28,6 +29,7 @@ #define PIRQF_APIC_IRQ 21 #define PIRQG_APIC_IRQ 22 #define PIRQH_APIC_IRQ 23 + /* The below IRQs are for when devices are in ACPI mode. Active low. */ #define LPE_DMA0_IRQ 24 #define LPE_DMA1_IRQ 25 @@ -47,50 +49,101 @@ #define LPSS_SPI_IRQ 41 #define LPSS_DMA1_IRQ 42 #define LPSS_DMA2_IRQ 43 -#define SCC_EMMC_IRQ 44 +#define SCC_EMMC_IRQ 45 #define SCC_SDIO_IRQ 46 -#define SCC_SD_IRQ 47 -#define GPIO_NC_IRQ 48 -#define GPIO_SC_IRQ 49 -#define GPIO_SUS_IRQ 50 +#define SCC_SD_IRQ 47 + +#define GPIO_N_IRQ 48 +#define GPIO_SW_IRQ 49 +#define GPIO_E_IRQ 50 + /* GPIO direct / dedicated IRQs. */ -#define GPIO_S0_DED_IRQ_0 51 -#define GPIO_S0_DED_IRQ_1 52 -#define GPIO_S0_DED_IRQ_2 53 -#define GPIO_S0_DED_IRQ_3 54 -#define GPIO_S0_DED_IRQ_4 55 -#define GPIO_S0_DED_IRQ_5 56 -#define GPIO_S0_DED_IRQ_6 57 -#define GPIO_S0_DED_IRQ_7 58 -#define GPIO_S0_DED_IRQ_8 59 -#define GPIO_S0_DED_IRQ_9 60 -#define GPIO_S0_DED_IRQ_10 61 -#define GPIO_S0_DED_IRQ_11 62 -#define GPIO_S0_DED_IRQ_12 63 -#define GPIO_S0_DED_IRQ_13 64 -#define GPIO_S0_DED_IRQ_14 65 -#define GPIO_S0_DED_IRQ_15 66 -#define GPIO_S5_DED_IRQ_0 67 -#define GPIO_S5_DED_IRQ_1 68 -#define GPIO_S5_DED_IRQ_2 69 -#define GPIO_S5_DED_IRQ_3 70 -#define GPIO_S5_DED_IRQ_4 71 -#define GPIO_S5_DED_IRQ_5 72 -#define GPIO_S5_DED_IRQ_6 73 -#define GPIO_S5_DED_IRQ_7 74 -#define GPIO_S5_DED_IRQ_8 75 -#define GPIO_S5_DED_IRQ_9 76 -#define GPIO_S5_DED_IRQ_10 77 -#define GPIO_S5_DED_IRQ_11 78 -#define GPIO_S5_DED_IRQ_12 79 -#define GPIO_S5_DED_IRQ_13 80 -#define GPIO_S5_DED_IRQ_14 81 -#define GPIO_S5_DED_IRQ_15 82 + +/* NORTH COMMUNITY */ +#define GPIO_N_DED_IRQ_0 51 +#define GPIO_N_DED_IRQ_1 52 +#define GPIO_N_DED_IRQ_2 53 +#define GPIO_N_DED_IRQ_3 54 +#define GPIO_N_DED_IRQ_4 55 +#define GPIO_N_DED_IRQ_5 56 +#define GPIO_N_DED_IRQ_6 57 +#define GPIO_N_DED_IRQ_7 58 + +/* SOUTH WEST COMMUNITY */ +#define GPIO_SW_DED_IRQ_0 59 +#define GPIO_SW_DED_IRQ_1 60 +#define GPIO_SW_DED_IRQ_2 61 +#define GPIO_SW_DED_IRQ_3 62 +#define GPIO_SW_DED_IRQ_4 63 +#define GPIO_SW_DED_IRQ_5 64 +#define GPIO_SW_DED_IRQ_6 65 +#define GPIO_SW_DED_IRQ_7 66 + +/* EAST COMMUNITY */ +#define GPIO_E_DED_IRQ_0 67 +#define GPIO_E_DED_IRQ_1 68 +#define GPIO_E_DED_IRQ_2 69 +#define GPIO_E_DED_IRQ_3 70 +#define GPIO_E_DED_IRQ_4 71 +#define GPIO_E_DED_IRQ_5 72 +#define GPIO_E_DED_IRQ_6 73 +#define GPIO_E_DED_IRQ_7 74 +#define GPIO_E_DED_IRQ_8 75 +#define GPIO_E_DED_IRQ_9 76 +#define GPIO_E_DED_IRQ_10 77 +#define GPIO_E_DED_IRQ_11 78 +#define GPIO_E_DED_IRQ_12 79 +#define GPIO_E_DED_IRQ_13 80 +#define GPIO_E_DED_IRQ_14 81 +#define GPIO_E_DED_IRQ_15 82 + +/* More IRQ */ +#define LPSS_SPI2_IRQ 89 +#define LPSS_SPI3_IRQ 90 +#define GPIO_SE_IRQ 91 + +/* GPIO direct / dedicated IRQs. */ +/* SOUTH EAST COMMUNITY */ +#define GPIO_SE_DED_IRQ_0 92 +#define GPIO_SE_DED_IRQ_1 93 +#define GPIO_SE_DED_IRQ_2 94 +#define GPIO_SE_DED_IRQ_3 95 +#define GPIO_SE_DED_IRQ_4 96 +#define GPIO_SE_DED_IRQ_5 97 +#define GPIO_SE_DED_IRQ_6 98 +#define GPIO_SE_DED_IRQ_7 99 +#define GPIO_SE_DED_IRQ_8 100 +#define GPIO_SE_DED_IRQ_9 101 +#define GPIO_SE_DED_IRQ_10 102 +#define GPIO_SE_DED_IRQ_11 103 +#define GPIO_SE_DED_IRQ_12 104 +#define GPIO_SE_DED_IRQ_13 105 +#define GPIO_SE_DED_IRQ_14 106 +#define GPIO_SE_DED_IRQ_15 107 + +/* OTHER IRQs */ +#define GPIO_VIRTUAL 108 +#define LPE_DMA2 109 +#define LPE_SSP3 110 +#define LPE_SSP4 111 +#define LPE_SSP5 112 + /* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */ -#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot -#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot -#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) -#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) +#define _GPIO_N_DED_IRQ(slot) GPIO_N_DED_IRQ_##slot +#define _GPIO_SW_DED_IRQ(slot) GPIO_SW_DED_IRQ_##slot +#define _GPIO_E_DED_IRQ(slot) GPIO_E_DED_IRQ_##slot +#define _GPIO_SE_DED_IRQ(slot) GPIO_SE_DED_IRQ_##slot +#define GPIO_N_DED_IRQ(slot) _GPIO_N_DED_IRQ(slot) +#define GPIO_SW_DED_IRQ(slot) _GPIO_SW_DED_IRQ(slot) +#define GPIO_E_DED_IRQ(slot) _GPIO_E_DED_IRQ(slot) +#define GPIO_SE_DED_IRQ(slot) _GPIO_SE_DED_IRQ(slot) + +/* TODO NEED TO UPDATE THESE IN onboard.h */ +#define _GPIO_S0_DED_IRQ(slot) GPIO_N_DED_IRQ_##slot +#define _GPIO_S5_DED_IRQ(slot) GPIO_SE_DED_IRQ_##slot +#define GPIO_S0_DED_IRQ(slot) _GPIO_N_DED_IRQ(slot) +#define GPIO_S5_DED_IRQ(slot) _GPIO_E_DED_IRQ(slot) + /* PIC IRQ settings. */ #define PIRQ_PIC_IRQDISABLE 0x0 @@ -127,9 +180,11 @@ # define SCIS_IRQ22 0x06 # define SCIS_IRQ23 0x07 -/* In each mainboard directory there should exist a header file irqroute.h that +/* + * In each mainbaord directory there should exist a header file irqroute.h that * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which - * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ + * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. + */ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) #include <stdint.h> @@ -137,28 +192,29 @@ #define NUM_IR_DEVS 32 #define NUM_PIRQS 8 -struct baytrail_irq_route { +struct soc_irq_route { /* Per device configuration. */ uint16_t pcidev[NUM_IR_DEVS]; /* Route path for each internal PIRQx in PIC mode. */ uint8_t pic[NUM_PIRQS]; }; -extern const struct baytrail_irq_route global_baytrail_irq_route; +extern const struct soc_irq_route global_soc_irq_route; #define DEFINE_IRQ_ROUTES \ - const struct baytrail_irq_route global_baytrail_irq_route = { \ + const struct soc_irq_route global_soc_irq_route = { \ .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ .pic = { PIRQ_PIC_ROUTES, }, \ } +/* The following macros are used for ACPI by the ASL compiler */ #define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ - [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ - ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) + [dev_] = (((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ + ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0)) #define PIRQ_PIC(pirq_, pic_irq_) \ [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ -#endif /* _BAYTRAIL_IRQ_H_ */ +#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h index 7247080..032cf9a 100644 --- a/src/soc/intel/braswell/include/soc/lpc.h +++ b/src/soc/intel/braswell/include/soc/lpc.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_LPC_H_ -#define _BAYTRAIL_LPC_H_ +#ifndef _SOC_LPC_H_ +#define _SOC_LPC_H_ /* PCI config registers in LPC bridge. */ #define REVID 0x08 @@ -37,7 +38,7 @@ #define RID_A_STEPPING_START 1 #define RID_B_STEPPING_START 5 #define RID_C_STEPPING_START 0xe -enum baytrail_stepping { +enum soc_stepping { STEP_A0, STEP_A1, STEP_B0, @@ -51,4 +52,4 @@ enum baytrail_stepping { #define GCS 0x00 # define BILD (1 << 0) -#endif /* _BAYTRAIL_LPC_H_ */ +#endif /* _SOC_LPC_H_ */ diff --git a/src/soc/intel/braswell/include/soc/mrc_wrapper.h b/src/soc/intel/braswell/include/soc/mrc_wrapper.h deleted file mode 100644 index 355dce0..0000000 --- a/src/soc/intel/braswell/include/soc/mrc_wrapper.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * MRC wrapper definitions - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _MRC_WRAPPER_H_ -#define _MRC_WRAPPER_H_ - -#define MRC_PARAMS_VER 5 - -#define NUM_CHANNELS 2 - -/* Provide generic x86 calling conventions. */ -#define ABI_X86 __attribute((regparm(0))) - -enum { - DRAM_INFO_SPD_SMBUS, /* Use the typical SPD smbus access. */ - DRAM_INFO_SPD_MEM, /* SPD info in memory. */ - DRAM_INFO_DETAILED, /* Timing info not in SPD format. */ -}; - -enum dram_type { - DRAM_DDR3, - DRAM_DDR3L, - DRAM_LPDDR3, -}; - -/* Errors returned by the MRC wrapper. */ -enum mrc_wrapper_error { - INVALID_VER = -1, - INVALID_DRAM_TYPE = -2, - INVALID_SLEEP_MODE = -3, - PLATFORM_SETTINGS_FAIL = -4, - DIMM_DETECTION_FAILURE = -5, - MEMORY_CONFIG_FAILURE = -6, - INVALID_CPU_ODT_SETTING = -7, - INVALID_DRAM_ODT_SETTING = -8, -}; - -struct mrc_mainboard_params { - int dram_type; - int dram_info_location; /* DRAM_INFO_* */ - int dram_is_slotted; /* mobo has DRAM slots. */ - /* - * The below ODT settings are only honored when !dram_is_slotted. - * Additionally, weaker_odt_settings being non-zero causes - * cpu_odt_value to not be honored as weaker_odt_settings have a - * special training path. - */ - int weaker_odt_settings; - /* Allowed settings: 60, 80, 100, 120, and 150. */ - int cpu_odt_value; - /* Allowed settings: 60 and 120. */ - int dram_odt_value; - int spd_addrs[NUM_CHANNELS]; - void *dram_data[NUM_CHANNELS]; /* SPD or Timing specific data. */ -} __attribute__((packed)); - -struct mrc_params { - /* Mainboard Inputs */ - int version; - - struct mrc_mainboard_params mainboard; - - void ABI_X86 (*console_out)(unsigned char byte); - - int prev_sleep_state; - - int saved_data_size; - const void *saved_data; - - int txe_size_mb; /* TXE memory size in megabytes. */ - int rmt_enabled; /* Enable RMT training + prints. */ - int io_hole_mb; /* Size of IO hole in MiB. */ - - /* Outputs */ - void *txe_base_address; - int data_to_save_size; - void *data_to_save; -} __attribute__((packed)); - -/* Call into wrapper. */ -typedef int ABI_X86 (*mrc_wrapper_entry_t)(struct mrc_params *); - -#endif /* _MRC_WRAPPER_H_ */ diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 668eebf..7426629 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -17,17 +18,18 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_MSR_H_ -#define _BAYTRAIL_MSR_H_ +#ifndef _SOC_MSR_H_ +#define _SOC_MSR_H_ #define MSR_IA32_PLATFORM_ID 0x17 +#define MSR_IA32_BIOS_SIGN_ID 0x8B #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define SINGLE_PCTL (1 << 11) +#define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 -#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) -#define ENABLE_INDP_AUTOCM_MASK (1 << 3) +#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) +#define ENABLE_INDP_AUTOCM_MASK (1 << 3) #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc @@ -45,7 +47,6 @@ #define MSR_CPU_THERM_CFG2 0x674 #define MSR_CPU_THERM_SENS_CFG 0x675 -/* Read BCLK from MSR */ -unsigned bus_freq_khz(void); +#define BUS_FREQ_KHZ 100000 /* 100 MHz */ -#endif /* _BAYTRAIL_MSR_H_ */ +#endif /* _SOC_MSR_H_ */ diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 9304c4a..1c25cb2 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -3,6 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 Google Inc + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,8 +19,8 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_NVS_H_ -#define _BAYTRAIL_NVS_H_ +#ifndef _SOC_NVS_H_ +#define _SOC_NVS_H_ #include <vendorcode/google/chromeos/gnvs.h> #include <soc/device_nvs.h> @@ -39,12 +40,13 @@ typedef struct { u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u8 lids; /* 0x0f - LID state (open = 1) */ u8 pwrs; /* 0x10 - Power state (AC = 1) */ - u8 pcnt; /* 0x11 - Processor Count */ + u8 pcnt; /* 0x11 - Processor Count */ u8 tpmp; /* 0x12 - TPM Present and Enabled */ u8 tlvl; /* 0x13 - Throttle Level */ u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */ - u8 rsvd1[7]; + u8 bdid; /* 0x19 - Board ID */ + u8 rsvd1[6]; /* Device Config */ u8 s5u0; /* 0x20 - Enable USB0 in S5 */ @@ -58,21 +60,22 @@ typedef struct { u8 rsvd2[8]; /* Base Addresses */ - u32 obsolete_cmem; /* 0x30 - CBMEM TOC */ + u32 cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[196]; - /* ChromeOS specific (0x100-0xfff)*/ + /* ChromeOS specific (0x100-0xfff) */ chromeos_acpi_t chromeos; - /* Baytrail LPSS (0x1000) */ + /* LPSS (0x1000) */ device_nvs_t dev; } __attribute__((packed)) global_nvs_t; +void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif -#endif /* _BAYTRAIL_NVS_H_ */ +#endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pattrs.h b/src/soc/intel/braswell/include/soc/pattrs.h index 852de40..6328dfe 100644 --- a/src/soc/intel/braswell/include/soc/pattrs.h +++ b/src/soc/intel/braswell/include/soc/pattrs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc. */ -#ifndef _PATTRS_H_ -#define _PATTRS_H_ +#ifndef _SOC_PATTRS_H_ +#define _SOC_PATTRS_H_ #include <stdint.h> #include <cpu/x86/msr.h> @@ -31,7 +32,8 @@ enum { IACORE_END }; -/* The pattrs structure is a common place to stash pertinent information +/* + * The pattrs structure is a common place to stash pertinent information * about the processor or platform. Instead of going to the source (msrs, cpuid) * every time an attribute is needed use the pattrs structure. */ @@ -49,16 +51,14 @@ struct pattrs { unsigned bclk_khz; }; -/* This is just to hide the abstraction w/o relying on how the underlying - * storage is allocated. */ -#define PATTRS_GLOB_NAME __global_pattrs -#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME -extern DEFINE_PATTRS; - +/* + * This is just to hide the abstraction w/o relying on how the underlying + * storage is allocated. + */ +extern struct pattrs __global_pattrs; static inline const struct pattrs *pattrs_get(void) { - return &PATTRS_GLOB_NAME; + return &__global_pattrs; } - -#endif /* _PATTRS_H_ */ +#endif /* _SOC_PATTRS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pci_devs.h b/src/soc/intel/braswell/include/soc/pci_devs.h index bb75f34..5594675 100644 --- a/src/soc/intel/braswell/include/soc/pci_devs.h +++ b/src/soc/intel/braswell/include/soc/pci_devs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,139 +18,137 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_PCI_DEVS_H_ -#define _BAYTRAIL_PCI_DEVS_H_ +#ifndef _SOC_PCI_DEVS_H_ +#define _SOC_PCI_DEVS_H_ /* All these devices live on bus 0 with the associated device and function */ /* SoC transaction router */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEVID 0x0f00 +# define SOC_DEVID 0x2280 /* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 -# define GFX_DEVID 0x0f31 +# define GFX_DEVID 0x22b1 + +/* MMC Port */ +#define MMC_DEV 0x10 +#define MMC_FUNC 0 +# define MMC_DEVID 0x2294 /* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 -# define SDIO_DEVID 0x0f15 +# define SDIO_DEVID 0x2295 /* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 -# define SD_DEVID 0x0f16 +# define SD_DEVID 0x2296 /* SATA */ #define SATA_DEV 0x13 #define SATA_FUNC 0 -#define IDE1_DEVID 0x0f20 -#define IDE2_DEVID 0x0f21 -#define AHCI1_DEVID 0x0f22 -#define AHCI2_DEVID 0x0f23 +#define AHCI1_DEVID 0x22a3 /* xHCI */ #define XHCI_DEV 0x14 #define XHCI_FUNC 0 -# define XHCI_DEVID 0x0f35 +#define XHCI_DEVID 0x22b5 /* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 -# define LPE_DEVID 0x0f28 - -/* MMC Port */ -#define MMC_DEV 0x17 -#define MMC_FUNC 0 -# define MMC_DEVID 0x0f50 +# define LPE_DEVID 0x22a8 /* Serial IO 1 */ #define SIO1_DEV 0x18 # define SIO_DMA1_DEV SIO1_DEV # define SIO_DMA1_FUNC 0 -# define SIO_DMA1_DEVID 0x0f40 +# define SIO_DMA1_DEVID 0x22c0 # define I2C1_DEV SIO1_DEV # define I2C1_FUNC 1 -# define I2C1_DEVID 0x0f41 +# define I2C1_DEVID 0x22c1 # define I2C2_DEV SIO1_DEV # define I2C2_FUNC 2 -# define I2C2_DEVID 0x0f42 +# define I2C2_DEVID 0x22c2 # define I2C3_DEV SIO1_DEV # define I2C3_FUNC 3 -# define I2C3_DEVID 0x0f43 +# define I2C3_DEVID 0x22c3 # define I2C4_DEV SIO1_DEV # define I2C4_FUNC 4 -# define I2C4_DEVID 0x0f44 +# define I2C4_DEVID 0x22c4 # define I2C5_DEV SIO1_DEV # define I2C5_FUNC 5 -# define I2C5_DEVID 0x0f45 +# define I2C5_DEVID 0x22c5 # define I2C6_DEV SIO1_DEV # define I2C6_FUNC 6 -# define I2C6_DEVID 0x0f46 +# define I2C6_DEVID 0x22c6 # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 -# define I2C7_DEVID 0x0f47 +# define I2C7_DEVID 0x22c7 /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 -# define TXE_DEVID 0x0f18 +# define TXE_DEVID 0x2298 /* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 -# define HDA_DEVID 0x0f04 +# define HDA_DEVID 0x2284 /* PCIe Ports */ #define PCIE_DEV 0x1c # define PCIE_PORT1_DEV PCIE_DEV # define PCIE_PORT1_FUNC 0 -# define PCIE_PORT1_DEVID 0x0f48 +# define PCIE_PORT1_DEVID 0x22c8 # define PCIE_PORT2_DEV PCIE_DEV # define PCIE_PORT2_FUNC 1 -# define PCIE_PORT2_DEVID 0x0f4a +# define PCIE_PORT2_DEVID 0x22ca # define PCIE_PORT3_DEV PCIE_DEV # define PCIE_PORT3_FUNC 2 -# define PCIE_PORT3_DEVID 0x0f4c +# define PCIE_PORT3_DEVID 0x22cc # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 -# define PCIE_PORT4_DEVID 0x0f4e - -/* EHCI */ -#define EHCI_DEV 0x1d -#define EHCI_FUNC 0 -# define EHCI_DEVID 0x0f34 +# define PCIE_PORT4_DEVID 0x22ce +/* Total number of ROOT PORTS */ +#define MAX_ROOT_PORTS_BSW 4 /* Serial IO 2 */ #define SIO2_DEV 0x1e # define SIO_DMA2_DEV SIO2_DEV # define SIO_DMA2_FUNC 0 -# define SIO_DMA2_DEVID 0x0f06 +# define SIO_DMA2_DEVID 0x2286 # define PWM1_DEV SIO2_DEV # define PWM1_FUNC 1 -# define PWM1_DEVID 0x0f08 +# define PWM1_DEVID 0x2288 # define PWM2_DEV SIO2_DEV # define PWM2_FUNC 2 -# define PWM2_DEVID 0x0f09 +# define PWM2_DEVID 0x2289 # define HSUART1_DEV SIO2_DEV # define HSUART1_FUNC 3 -# define HSUART1_DEVID 0x0f0a +# define HSUART1_DEVID 0x228a # define HSUART2_DEV SIO2_DEV # define HSUART2_FUNC 4 -# define HSUART2_DEVID 0x0f0c +# define HSUART2_DEVID 0x228c # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 -# define SPI_DEVID 0xf0e +# define SPI_DEVID 0x228e /* Platform Controller Unit */ #define PCU_DEV 0x1f # define LPC_DEV PCU_DEV # define LPC_FUNC 0 -# define LPC_DEVID 0x0f1c +# define LPC_DEVID 0x229c # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 # define SMBUS_DEVID 0x0f12 -#endif /* _BAYTRAIL_PCI_DEVS_H_ */ +/* PCH SCC Device Modes */ +#define PCH_DISABLED 0 +#define PCH_PCI_MODE 1 +#define PCH_ACPI_MODE 2 +#endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pcie.h b/src/soc/intel/braswell/include/soc/pcie.h index dd0b90d..9307d9b 100644 --- a/src/soc/intel/braswell/include/soc/pcie.h +++ b/src/soc/intel/braswell/include/soc/pcie.h @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -17,8 +18,8 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_PCIE_H_ -#define _BAYTRAIL_PCIE_H_ +#ifndef _SOC_PCIE_H_ +#define _SOC_PCIE_H_ /* PCIe root port config space registers. */ #define XCAP 0x40 @@ -98,5 +99,4 @@ #define PHYCTL4 0x408 # define SQDIS (1 << 27) -#define PCIE_ROOT_PORT_COUNT 4 -#endif /* _BAYTRAIL_PCIE_H_ */ +#endif /* _SOC_PCIE_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pei_data.h b/src/soc/intel/braswell/include/soc/pei_data.h new file mode 100644 index 0000000..d9e5a67 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/pei_data.h @@ -0,0 +1,62 @@ +/* + * Broadwell UEFI PEI wrapper + * + * Copyright (C) 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Google Inc. nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PEI_DATA_H_ +#define _PEI_DATA_H_ + +#include <types.h> + +#define PEI_VERSION 22 + +#define ABI_X86 __attribute__((regparm(0))) + +typedef void ABI_X86(*tx_byte_func)(unsigned char byte); + +struct pei_data { + /* Chip settings */ + void *spd_data_ch0; + void *spd_data_ch1; + uint8_t spd_ch0_config; + uint8_t spd_ch1_config; + + /* System state information */ + int boot_mode; + + /* Fast boot and S3 resume MRC data */ + int saved_data_size; + const void *saved_data; + int disable_saved_data; + + /* New save data from MRC */ + int data_to_save_size; + void *data_to_save; +}; + +typedef struct pei_data PEI_DATA; + +#endif /* _PEI_DATA_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pei_wrapper.h b/src/soc/intel/braswell/include/soc/pei_wrapper.h new file mode 100644 index 0000000..59f2bb3 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/pei_wrapper.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _SOC_PEI_WRAPPER_H_ +#define _SOC_PEI_WRAPPER_H_ + +#include <soc/pei_data.h> + +typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); + +void broadwell_fill_pei_data(struct pei_data *pei_data); +void mainboard_fill_pei_data(struct pei_data *pei_data); + +#endif diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h new file mode 100644 index 0000000..ca06819 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -0,0 +1,267 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + + +#define IOCOM1 0x3f8 + +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x00 +# define PMC_WDT_STS (1 << 15) +# define SEC_GBLRST_STS (1 << 7) +# define SEC_WDT_STS (1 << 6) +# define WOL_OVR_WK_STS (1 << 5) +# define PMC_WAKE_STS (1 << 4) +#define PMC_CFG 0x08 +# define SPS (1 << 5) +# define NO_REBOOT (1 << 4) +# define SX_ENT_TO_EN (1 << 3) +# define TIMING_T581_SHIFT (0) +# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT) +# define TIMING_T581_10uS (0 << TIMING_T581_SHIFT) +# define TIMING_T581_100uS (1 << TIMING_T581_SHIFT) +# define TIMING_T581_1mS (2 << TIMING_T581_SHIFT) +# define TIMING_T581_10mS (3 << TIMING_T581_SHIFT) +#define VLV_PM_STS 0x0c +# define PMC_MSG_FULL_STS (1 << 24) +# define PMC_MSG_4_FULL_STS (1 << 23) +# define PMC_MSG_3_FULL_STS (1 << 22) +# define PMC_MSG_2_FULL_STS (1 << 21) +# define PMC_MSG_1_FULL_STS (1 << 20) +# define CODE_REQ (1 << 8) +# define HPR_ENT_TO (1 << 2) +# define SX_ENT_TO (1 << 1) +#define GEN_PMCON1 0x20 +# define UART_EN (1 << 24) +# define DISB (1 << 23) +# define MEM_SR (1 << 21) +# define SRS (1 << 20) +# define CTS (1 << 19) +# define MS4V (1 << 18) +# define PWR_FLR (1 << 16) +# define PME_B0_S5_DIS (1 << 15) +# define SUS_PWR_FLR (1 << 14) +# define WOL_EN_OVRD (1 << 13) +# define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +# define GEN_RST_STS (1 << 9) +# define RPS (1 << 2) +# define AFTERG3_EN (1 << 0) +#define GEN_PMCON2 0x24 +# define SLPSX_STR_POL_LOCK (1 << 18) +# define BIOS_PCI_EXP_EN (1 << 10) +# define PWRBTN_LVL (1 << 9) +# define SMI_LOCK (1 << 4) +#define ETR 0x48 +# define CF9LOCK (1 << 31) +# define LTR_DEF (1 << 22) +# define IGNORE_HPET (1 << 21) +# define CF9GR (1 << 20) +# define CWORWRE (1 << 18) +#define FUNC_DIS 0x34 +# define SIO_DMA2_DIS (1 << 0) +# define PWM1_DIS (1 << 1) +# define PWM2_DIS (1 << 2) +# define HSUART1_DIS (1 << 3) +# define HSUART2_DIS (1 << 4) +# define SPI_DIS (1 << 5) +# define SDIO_DIS (1 << 9) +# define SD_DIS (1 << 10) +# define MMC_DIS (1 << 11) +# define HDA_DIS (1 << 12) +# define LPE_DIS (1 << 13) +# define OTG_DIS (1 << 14) +# define XHCI_DIS (1 << 15) +# define SATA_DIS (1 << 17) +# define EHCI_DIS (1 << 18) +# define TXE_DIS (1 << 19) +# define PCIE_PORT1_DIS (1 << 20) +# define PCIE_PORT2_DIS (1 << 21) +# define PCIE_PORT3_DIS (1 << 22) +# define PCIE_PORT4_DIS (1 << 23) +# define SIO_DMA1_DIS (1 << 24) +# define I2C1_DIS (1 << 25) +# define I2C2_DIS (1 << 26) +# define I2C3_DIS (1 << 27) +# define I2C4_DIS (1 << 28) +# define I2C5_DIS (1 << 29) +# define I2C6_DIS (1 << 30) +# define I2C7_DIS (1 << 31) +#define FUNC_DIS2 0x38 +# define USH_SS_PHY_DIS (1 << 2) +# define OTG_SS_PHY_DIS (1 << 1) +# define SMBUS_DIS (1 << 0) +#define GPIO_ROUT 0x58 +# define ROUTE_MASK 3 +# define ROUTE_NONE 0 +# define ROUTE_SMI 1 +# define ROUTE_SCI 2 +#define PLT_CLK_CTL_0 0x60 +#define PLT_CLK_CTL_1 0x64 +#define PLT_CLK_CTL_2 0x68 +#define PLT_CLK_CTL_3 0x6c +#define PLT_CLK_CTL_4 0x70 +#define PLT_CLK_CTL_5 0x74 +# define CLK_FREQ_25MHZ (0x0 << 2) +# define CLK_FREQ_19P2MHZ (0x1 << 2) +# define CLK_CTL_D3_LPE (0x0 << 0) +# define CLK_CTL_ON (0x1 << 0) +# define CLK_CTL_OFF (0x2 << 0) +#define PME_STS 0xc0 +#define GPE_LEVEL_EDGE 0xc4 +# define GPE_EDGE 0 +# define GPE_LEVEL 1 +#define GPE_POLARITY 0xc8 +# define GPE_ACTIVE_HIGH 1 +# define GPE_ACTIVE_LOW 0 +#define LOCK 0xcc + +/* IO Mapped registers behind ACPI_BASE_ADDRESS */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define USB_STS (1 << 13) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define USB_WAKE_EN (1 << 13) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define GPE0_STS 0x20 +#define GPE0_EN 0x28 +#define SUS_GPIO_EN7_BIT 23 +#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT) +#define SUS_GPIO_EN6_BIT 22 +#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT) +#define SUS_GPIO_EN5_BIT 21 +#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT) +#define SUS_GPIO_EN4_BIT 20 +#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT) +#define SUS_GPIO_EN3_BIT 19 +#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT) +#define SUS_GPIO_EN2_BIT 18 +#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT) +#define SUS_GPIO_EN1_BIT 17 +#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT) +#define SUS_GPIO_EN0_BIT 16 +#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT) +#define SUS_GPIO_STS0 (1 << 16) +#define PCIE_WAKE3_STS (1 << 8) +#define PCIE_WAKE2_STS (1 << 7) +#define PCIE_WAKE1_STS (1 << 6) +#define PCIE_WAKE0_STS (1 << 3) +#define PCI_EXP_STS (1 << 9) +#define PME_B0_EN (1 << 13) +#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT +#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) +#define SMI_EN 0x30 +#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ +#define USB_EN (1 << 17) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ +#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ +#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ +#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ +#define SLP_SMI_EN (1 << 4) /* Write to SLP_EN in PM1_CNT asserts SMI# */ +#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ +#define EOS (1 << 1) /* End of SMI (deassert SMI#) */ +#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ +#define SMI_STS 0x34 +#define ALT_GPIO_SMI 0x38 +#define UPRWC 0x3c +# define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ +#define GPE_CTRL 0x40 +#define PM2A_CNT_BLK 0x50 +#define TCO_RLD 0x60 +#define TCO_STS 0x64 +# define SECOND_TO_STS (1 << 17) +# define TCO_TIMEOUT (1 << 3) +#define TCO1_CNT 0x68 +# define TCO_LOCK (1 << 12) +# define TCO_TMR_HALT (1 << 11) +#define TCO_TMR 0x70 + +/* Generic sleep state types */ +#define SLEEP_STATE_S0 0 +#define SLEEP_STATE_S3 3 +#define SLEEP_STATE_S5 5 + +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) + +/* Track power state from reset to log events. */ +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint32_t gpe0_sts; + uint32_t gpe0_en; + uint32_t tco_sts; + uint32_t prsts; + uint32_t gen_pmcon1; + uint32_t gen_pmcon2; + int prev_sleep_state; +} __attribute__((packed)); + +/* Power Management Utility Functions. */ +uint16_t get_pmbase(void); +uint32_t clear_smi_status(void); +uint16_t clear_pm1_status(void); +uint32_t clear_tco_status(void); +uint32_t clear_gpe_status(void); +uint32_t clear_alt_status(void); +void clear_pmc_status(void); +void enable_smi(uint32_t mask); +void disable_smi(uint32_t mask); +void enable_pm1(uint16_t events); +void enable_pm1_control(uint32_t mask); +void disable_pm1_control(uint32_t mask); +void enable_gpe(uint32_t mask); +void disable_gpe(uint32_t mask); +void disable_all_gpe(void); + +#if IS_ENABLED(CONFIG_ELOG) +void southcluster_log_state(void); +#else +static inline void southcluster_log_state(void) {} +#endif + +#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ + +#endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pmc.h b/src/soc/intel/braswell/include/soc/pmc.h deleted file mode 100644 index e5ae617..0000000 --- a/src/soc/intel/braswell/include/soc/pmc.h +++ /dev/null @@ -1,303 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef _BAYTRAIL_PMC_H_ -#define _BAYTRAIL_PMC_H_ - - -#define IOCOM1 0x3f8 - -/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ -#define PRSTS 0x00 -# define PMC_WDT_STS (1 << 15) -# define SEC_GBLRST_STS (1 << 7) -# define SEC_WDT_STS (1 << 6) -# define WOL_OVR_WK_STS (1 << 5) -# define PMC_WAKE_STS (1 << 4) -#define PMC_CFG 0x08 -# define SPS (1 << 5) -# define NO_REBOOT (1 << 4) -# define SX_ENT_TO_EN (1 << 3) -# define TIMING_T581_SHIFT (0) -# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT) -# define TIMING_T581_10uS (0 << TIMING_T581_SHIFT) -# define TIMING_T581_100uS (1 << TIMING_T581_SHIFT) -# define TIMING_T581_1mS (2 << TIMING_T581_SHIFT) -# define TIMING_T581_10mS (3 << TIMING_T581_SHIFT) -#define VLV_PM_STS 0x0c -# define PMC_MSG_FULL_STS (1 << 24) -# define PMC_MSG_4_FULL_STS (1 << 23) -# define PMC_MSG_3_FULL_STS (1 << 22) -# define PMC_MSG_2_FULL_STS (1 << 21) -# define PMC_MSG_1_FULL_STS (1 << 20) -# define CODE_REQ (1 << 8) -# define HPR_ENT_TO (1 << 2) -# define SX_ENT_TO (1 << 1) -#define GEN_PMCON1 0x20 -# define UART_EN (1 << 24) -# define DISB (1 << 23) -# define MEM_SR (1 << 21) -# define SRS (1 << 20) -# define CTS (1 << 19) -# define MS4V (1 << 18) -# define PWR_FLR (1 << 16) -# define PME_B0_S5_DIS (1 << 15) -# define SUS_PWR_FLR (1 << 14) -# define WOL_EN_OVRD (1 << 13) -# define DIS_SLP_X_STRCH_SUS_UP (1 << 12) -# define GEN_RST_STS (1 << 9) -# define RPS (1 << 2) -# define AFTERG3_EN (1 << 0) -#define GEN_PMCON2 0x24 -# define SLPSX_STR_POL_LOCK (1 << 18) -# define BIOS_PCI_EXP_EN (1 << 10) -# define PWRBTN_LVL (1 << 9) -# define SMI_LOCK (1 << 4) -#define ETR 0x48 -# define CF9LOCK (1 << 31) -# define LTR_DEF (1 << 22) -# define IGNORE_HPET (1 << 21) -# define CF9GR (1 << 20) -# define CWORWRE (1 << 18) -#define FUNC_DIS 0x34 -# define SIO_DMA2_DIS (1 << 0) -# define PWM1_DIS (1 << 1) -# define PWM2_DIS (1 << 2) -# define HSUART1_DIS (1 << 3) -# define HSUART2_DIS (1 << 4) -# define SPI_DIS (1 << 5) -# define SDIO_DIS (1 << 9) -# define SD_DIS (1 << 10) -# define MMC_DIS (1 << 11) -# define HDA_DIS (1 << 12) -# define LPE_DIS (1 << 13) -# define OTG_DIS (1 << 14) -# define XHCI_DIS (1 << 15) -# define SATA_DIS (1 << 17) -# define EHCI_DIS (1 << 18) -# define TXE_DIS (1 << 19) -# define PCIE_PORT1_DIS (1 << 20) -# define PCIE_PORT2_DIS (1 << 21) -# define PCIE_PORT3_DIS (1 << 22) -# define PCIE_PORT4_DIS (1 << 23) -# define SIO_DMA1_DIS (1 << 24) -# define I2C1_DIS (1 << 25) -# define I2C2_DIS (1 << 26) -# define I2C3_DIS (1 << 27) -# define I2C4_DIS (1 << 28) -# define I2C5_DIS (1 << 29) -# define I2C6_DIS (1 << 30) -# define I2C7_DIS (1 << 31) -#define FUNC_DIS2 0x38 -# define USH_SS_PHY_DIS (1 << 2) -# define OTG_SS_PHY_DIS (1 << 1) -# define SMBUS_DIS (1 << 0) -#define GPIO_ROUT 0x58 -# define ROUTE_MASK 3 -# define ROUTE_NONE 0 -# define ROUTE_SMI 1 -# define ROUTE_SCI 2 -#define PLT_CLK_CTL_0 0x60 -#define PLT_CLK_CTL_1 0x64 -#define PLT_CLK_CTL_2 0x68 -#define PLT_CLK_CTL_3 0x6c -#define PLT_CLK_CTL_4 0x70 -#define PLT_CLK_CTL_5 0x74 -# define CLK_FREQ_25MHZ (0x0 << 2) -# define CLK_FREQ_19P2MHZ (0x1 << 2) -# define CLK_CTL_D3_LPE (0x0 << 0) -# define CLK_CTL_ON (0x1 << 0) -# define CLK_CTL_OFF (0x2 << 0) -#define PME_STS 0xc0 -#define GPE_LEVEL_EDGE 0xc4 -# define GPE_EDGE 0 -# define GPE_LEVEL 1 -#define GPE_POLARITY 0xc8 -# define GPE_ACTIVE_HIGH 1 -# define GPE_ACTIVE_LOW 0 -#define LOCK 0xcc - -/* IO Mapped registers behind ACPI_BASE_ADDRESS */ -#define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define USB_STS (1 << 13) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define TMROF_STS (1 << 0) -#define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define USB_WAKE_EN (1 << 13) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) -#define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP_SHIFT 10 -#define SLP_TYP (7 << SLP_TYP_SHIFT) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) -#define PM1_TMR 0x08 -#define GPE0_STS 0x20 -#define CORE_GPIO_STS7 (1 << 31) -#define CORE_GPIO_STS6 (1 << 30) -#define CORE_GPIO_STS5 (1 << 29) -#define CORE_GPIO_STS4 (1 << 28) -#define CORE_GPIO_STS3 (1 << 27) -#define CORE_GPIO_STS2 (1 << 26) -#define CORE_GPIO_STS1 (1 << 25) -#define CORE_GPIO_STS0 (1 << 24) -#define SUS_GPIO_STS7 (1 << 23) -#define SUS_GPIO_STS6 (1 << 22) -#define SUS_GPIO_STS5 (1 << 21) -#define SUS_GPIO_STS4 (1 << 20) -#define SUS_GPIO_STS3 (1 << 19) -#define SUS_GPIO_STS2 (1 << 18) -#define SUS_GPIO_STS1 (1 << 17) -#define SUS_GPIO_STS0 (1 << 16) -#define PME_B0_STS (1 << 13) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define PCIE_WAKE3_STS (1 << 8) -#define PCIE_WAKE2_STS (1 << 7) -#define PCIE_WAKE1_STS (1 << 6) -#define GUNIT_SCI_STS (1 << 5) -#define PUNIT_SCI_STS (1 << 4) -#define PCIE_WAKE0_STS (1 << 3) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define GPE0_EN 0x28 -#define CORE_GPIO_EN7 (1 << 31) -#define CORE_GPIO_EN6 (1 << 30) -#define CORE_GPIO_EN5 (1 << 29) -#define CORE_GPIO_EN4 (1 << 28) -#define CORE_GPIO_EN3 (1 << 27) -#define CORE_GPIO_EN2 (1 << 26) -#define CORE_GPIO_EN1 (1 << 25) -#define CORE_GPIO_EN0 (1 << 24) -#define SUS_GPIO_EN7_BIT 23 -#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT) -#define SUS_GPIO_EN6_BIT 22 -#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT) -#define SUS_GPIO_EN5_BIT 21 -#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT) -#define SUS_GPIO_EN4_BIT 20 -#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT) -#define SUS_GPIO_EN3_BIT 19 -#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT) -#define SUS_GPIO_EN2_BIT 18 -#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT) -#define SUS_GPIO_EN1_BIT 17 -#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT) -#define SUS_GPIO_EN0_BIT 16 -#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT) -#define PME_B0_EN (1 << 13) -#define BATLOW_EN (1 << 10) -#define PCI_EXP_EN (1 << 9) -#define PCIE_WAKE3_EN (1 << 8) -#define PCIE_WAKE2_EN (1 << 7) -#define PCIE_WAKE1_EN (1 << 6) -#define PCIE_WAKE0_EN (1 << 3) -#define SWGPE_EN (1 << 2) -#define HOT_PLUG_EN (1 << 1) -#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT -#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) -#define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define USB_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? -#define SMI_STS 0x34 -#define ALT_GPIO_SMI 0x38 -#define UPRWC 0x3c -# define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable -#define GPE_CTRL 0x40 -#define PM2A_CNT_BLK 0x50 -#define TCO_RLD 0x60 -#define TCO_STS 0x64 -# define SECOND_TO_STS (1 << 17) -# define TCO_TIMEOUT (1 << 3) -#define TCO1_CNT 0x68 -# define TCO_LOCK (1 << 12) -# define TCO_TMR_HALT (1 << 11) -#define TCO_TMR 0x70 - -/* I/O ports */ -#define RST_CNT 0xcf9 -# define FULL_RST (1 << 3) -# define RST_CPU (1 << 2) -# define SYS_RST (1 << 1) - -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) - -/* Track power state from reset to log events. */ -struct chipset_power_state { - uint16_t pm1_sts; - uint16_t pm1_en; - uint32_t pm1_cnt; - uint32_t gpe0_sts; - uint32_t gpe0_en; - uint32_t tco_sts; - uint32_t prsts; - uint32_t gen_pmcon1; - uint32_t gen_pmcon2; -} __attribute__((packed)); - -/* Power Management Utility Functions. */ -uint16_t get_pmbase(void); -uint32_t clear_smi_status(void); -uint16_t clear_pm1_status(void); -uint32_t clear_tco_status(void); -uint32_t clear_gpe_status(void); -uint32_t clear_alt_status(void); -void clear_pmc_status(void); -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); -void enable_pm1(uint16_t events); -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); -void enable_gpe(uint32_t mask); -void disable_gpe(uint32_t mask); -void disable_all_gpe(void); - -#if CONFIG_ELOG -void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - -#endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index fc2b614..f171243 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,26 +18,23 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_RAMSTAGE_H_ -#define _BAYTRAIL_RAMSTAGE_H_ +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ +#include <chip.h> #include <device/device.h> -#include <soc/intel/baytrail/chip.h> +#include <soc/intel/common/ramstage.h> -/* The baytrail_init_pre_device() function is called prior to device - * initialization, but it's after console and cbmem has been reinitialized. */ -void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); -void baytrail_init_cpus(device_t dev); +/* + * The soc_init_pre_device() function is called prior to device + * initialization, but it's after console and cbmem has been reinitialized. + */ +void soc_init_pre_device(struct soc_intel_braswell_config *config); +void soc_init_cpus(device_t dev); void set_max_freq(void); void southcluster_enable_dev(device_t dev); -#if CONFIG_HAVE_REFCODE_BLOB -void baytrail_run_reference_code(void); -#else -static inline void baytrail_run_reference_code(void) {} -#endif -void baytrail_init_scc(void); void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; -#endif /* _BAYTRAIL_RAMSTAGE_H_ */ +#endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/braswell/include/soc/reset.h b/src/soc/intel/braswell/include/soc/reset.h deleted file mode 100644 index 23569d1..0000000 --- a/src/soc/intel/braswell/include/soc/reset.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef _BAYTRAIL_RESET_H_ -#define _BAYTRAIL_RESET_H_ -#include <reset.h> - -/* Bay Trail has the following types of resets: - * - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 - * - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 - * - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 - * - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 - * - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but - * with ETR[20] set. - */ - -void cold_reset(void); -void warm_reset(void); - -#endif /* _BAYTRAIL_RESET_H_ */ diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 4e0256a..770a39d 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,38 +18,25 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_ROMSTAGE_H_ -#define _BAYTRAIL_ROMSTAGE_H_ - -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ #include <stdint.h> #include <arch/cpu.h> -#include <soc/mrc_wrapper.h> - -struct romstage_params { - unsigned long bist; - struct mrc_params *mrc_params; -}; +#include <fsp_util.h> +#include <soc/pei_data.h> +#include <soc/pm.h> +#include <soc/intel/common/romstage.h> -void mainboard_romstage_entry(struct romstage_params *params); -void romstage_common(struct romstage_params *params); -void * asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo, - uint32_t tsc_high); -void asmlinkage romstage_after_car(void); -void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); void punit_init(void); -void set_max_freq(void); int early_spi_read_wpsr(u8 *sr); +void mainboard_fill_spd_data(struct pei_data *pei_data); -#if CONFIG_ENABLE_BUILTIN_COM1 -void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif +/* romstage_common.c functions */ +void program_base_addresses(void); +struct chipset_power_state *fill_power_state(void); +int chipset_prev_sleep_state(struct chipset_power_state *ps); -#endif /* _BAYTRAIL_ROMSTAGE_H_ */ +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/braswell/include/soc/sata.h b/src/soc/intel/braswell/include/soc/sata.h index 8bd73c6..aca8901 100644 --- a/src/soc/intel/braswell/include/soc/sata.h +++ b/src/soc/intel/braswell/include/soc/sata.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,10 +18,138 @@ * Foundation, Inc. */ -#ifndef BAYTRAIL_SATA_H -#define BAYTRAIL_SATA_H +#ifndef _SOC_SATA_H_ +#define _SOC_SATA_H_ + +#define SATA_PORT_SUPPORT 0x03 +#define SATA_PORT_MASK 0x3f + +/* PCI Configuration Space */ +#define SATA_PID 0x70 +#define SATA_PID_NEXT 0xff00 +#define SATA_PID_CID 0xff + +#define SATA_MAP 0x90 +#define SATA_MAP_SPD3 (1 << 11) +#define SATA_MAP_SPD2 (1 << 10) +#define SATA_MAP_SPD1 (1 << 9) +#define SATA_MAP_SPD0 (1 << 8) +#define SATA_MAP_SPD_MASK (SATA_MAP_SPD0 | SATA_MAP_SPD1 \ + | SATA_MAP_SPD2 | SATA_MAP_SPD3) +#define SATA_MAP_SMS_RAID 0x40 + +#define SATA_PCS 0x92 +#define SATA_PCS_ORM (1 << 15) +#define SATA_PCS_PORT5 (1 << 5) +#define SATA_PCS_PORT4 (1 << 4) +#define SATA_PCS_PORT3 (1 << 3) +#define SATA_PCS_PORT2 (1 << 2) +#define SATA_PCS_PORT1 (1 << 1) +#define SATA_PCS_PORT0 (1 << 0) +#define SATA_PCS_PORTS (SATA_PCS_PORT0 | SATA_PCS_PORT1 | SATA_PCS_PORT2 \ + | SATA_PCS_PORT3 | SATA_PCS_PORT4 | SATA_PCS_PORT5) + +#define SATA_TM 0x94 +#define SATA_TM_PCD5 (1 << 29) +#define SATA_TM_PCD4 (1 << 28) +#define SATA_TM_PCD3 (1 << 27) +#define SATA_TM_PCD2 (1 << 26) +#define SATA_TM_PCD1 (1 << 25) +#define SATA_TM_PCD0 (1 << 24) +#define SATA_TM_PCD_MASK (SATA_TM_PCD0 | SATA_TM_PCD1 | SATA_TM_PCD2 \ + | SATA_TM_PCD3 | SATA_TM_PCD4 | SATA_TM_PCD5) #define SATA_SIRI 0xa0 #define SATA_SIRD 0xa4 -#endif +/* Memory Mapped I/O Space */ +#define AHCI_GHC_CAP 0 +#define AHCI_GHC_CAP_S64A (1 << 31) +#define AHCI_GHC_CAP_SCQA (1 << 30) +#define AHCI_GHC_CAP_SSNTF (1 << 29) +#define AHCI_GHC_CAP_SMPS (1 << 28) +#define AHCI_GHC_CAP_SSS (1 << 27) +#define AHCI_GHC_CAP_SALP (1 << 26) +#define AHCI_GHC_CAP_SAL (1 << 25) +#define AHCI_GHC_CAP_SCLO (1 << 24) +#define AHCI_GHC_CAP_ISS 0x00f00000 +#define AHCI_GHC_CAP_ISS_GEN1 (1 << 20) +#define AHCI_GHC_CAP_ISS_GEN2 (2 << 20) +#define AHCI_GHC_CAP_ISS_GEN3 (3 << 20) +#define AHCI_GHC_CAP_SNZO (1 << 19) +#define AHCI_GHC_CAP_SAM (1 << 18) +#define AHCI_GHC_CAP_SMP (1 << 17) +#define AHCI_GHC_CAP_FBSS (1 << 16) +#define AHCI_GHC_CAP_PMD (1 << 15) +#define AHCI_GHC_CAP_SSC (1 << 14) +#define AHCI_GHC_CAP_PSC (1 << 13) +#define AHCI_GHC_CAP_NCS 0x00000f00 +#define AHCI_GHC_CAP_CCCS (1 << 7) +#define AHCI_GHC_CAP_EMS (1 << 6) +#define AHCI_GHC_CAP_SXS (1 << 5) +#define AHCI_GHC_CAP_NP 0x0000001f + +#define AHCI_HBA_CTRL 4 +#define AHCI_HBA_CTRL_AE (1 << 31) +#define AHCI_HBA_CTRL_MRSM (1 << 2) +#define AHCI_HBA_CTRL_IE (1 << 1) +#define AHCI_HBA_CTRL_HR (1 << 0) + +#define AHCI_GHC_PI 0x000c +#define AHCI_GHC_CAP2 0x0024 +#define AHCI_GHC_CAP2_DESO (1 << 5) +#define AHCI_GHC_CAP2_SADM (1 << 4) +#define AHCI_GHC_CAP2_SDS (1 << 3) +#define AHCI_GHC_CAP2_APST (1 << 2) +#define AHCI_GHC_CAP2_BOH (1 << 0) + +#define AHCI_VSP 0x00a0 +#define AHCI_VSP_SFMS (1 << 6) +#define AHCI_VSP_PFS (1 << 5) +#define AHCI_VSP_PT (1 << 4) +#define AHCI_VSP_SRPIR (1 << 3) + +#define AHCI_SFM 0xc8 +#define AHCI_SFM_OROM_UI 0x0c00 +#define AHCI_SFM_OROM_UI_2SEC 0 +#define AHCI_SFM_OROM_UI_4SEC (1 << 10) +#define AHCI_SFM_OROM_UI_6SEC (2 << 10) +#define AHCI_SFM_OROM_UI_8SEC (3 << 10) +#define AHCI_SFM_SRT (1 << 9) +#define AHCI_SFM_RRT_ESATA (1 << 8) +#define AHCI_SFM_LED (1 << 7) +#define AHCI_SFM_HDDUNLOCK (1 << 6) +#define AHCI_SFM_OROM_UI_BANNER (1 << 5) +#define AHCI_SFM_RRT (1 << 4) +#define AHCI_SFM_R5 (1 << 3) +#define AHCI_SFM_R10 (1 << 2) +#define AHCI_SFM_R1 (1 << 1) +#define AHCI_SFM_R0 (1 << 0) + +#define AHCI_PXCMD0 0x0118 +#define AHCI_PXCMD1 0x0198 + +#define AHCI_PXCMD_ICC 0xf0000000 +#define AHCI_PXCMD_ASP (1 << 27) +#define AHCI_PXCMD_ALPE (1 << 26) +#define AHCI_PXCMD_DLAE (1 << 25) +#define AHCI_PXCMD_ATAPI (1 << 24) +#define AHCI_PXCMD_APSTE (1 << 23) +#define AHCI_PXCMD_FBSCP (1 << 22) +#define AHCI_PXCMD_ESP (1 << 21) +#define AHCI_PXCMD_CPD (1 << 20) +#define AHCI_PXCMD_MPSP (1 << 19) +#define AHCI_PXCMD_HPCP (1 << 18) +#define AHCI_PXCMD_PMA (1 << 17) +#define AHCI_PXCMD_CR (1 << 15) +#define AHCI_PXCMD_FR (1 << 14) +#define AHCI_PXCMD_MPSS (1 << 13) +#define AHCI_PXCMD_CCS 0x00001f00 +#define AHCI_PXCMD_PSP (1 << 6) +#define AHCI_PXCMD_FRE (1 << 4) +#define AHCI_PXCMD_CLO (1 << 3) +#define AHCI_PXCMD_POD (1 << 2) +#define AHCI_PXCMD_SUD (1 << 1) +#define AHCI_PXCMD_ST (1 << 0) + +#endif /* _SOC_SATA_H_ */ diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h index 63ac983..fb38e86 100644 --- a/src/soc/intel/braswell/include/soc/smm.h +++ b/src/soc/intel/braswell/include/soc/smm.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,23 +18,12 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_SMM_H_ -#define _BAYTRAIL_SMM_H_ +#ifndef _SOC_SMM_H_ +#define _SOC_SMM_H_ -/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig - * is included after chipset code. This causes the chipset's Kconfig to be - * clobbered by the arch/x86/Kconfig if they have the same name. */ -static inline int smm_region_size(void) -{ - /* Make it 8MiB by default. */ - if (CONFIG_SMM_TSEG_SIZE == 0) - return (8 << 20); - return CONFIG_SMM_TSEG_SIZE; -} +#include <rules.h> -uintptr_t smm_region_start(void); - -#if !defined(__PRE_RAM__) && !defined(__SMM___) +#if ENV_RAMSTAGE #include <stdint.h> void southcluster_smm_clear_state(void); void southcluster_smm_enable_smi(void); @@ -46,4 +36,4 @@ enum { SMM_SAVE_PARAM_COUNT }; -#endif /* _BAYTRAIL_SMM_H_ */ +#endif /* _SOC_SMM_H_ */ diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h index 60df280..f8354ec 100644 --- a/src/soc/intel/braswell/include/soc/spi.h +++ b/src/soc/intel/braswell/include/soc/spi.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc. */ -#ifndef _BAYTRAIL_SPI_H_ -#define _BAYTRAIL_SPI_H_ +#ifndef _SOC_SPI_H_ +#define _SOC_SPI_H_ #include <stdint.h> @@ -71,4 +72,4 @@ struct spi_config { /* Return 0 on success < 0 on failure. */ int mainboard_get_spi_config(struct spi_config *cfg); -#endif /* _BAYTRAIL_SPI_H_ */ +#endif /* _SOC_SPI_H_ */ diff --git a/src/soc/intel/braswell/include/soc/xhci.h b/src/soc/intel/braswell/include/soc/xhci.h index 4399a16..0563757 100644 --- a/src/soc/intel/braswell/include/soc/xhci.h +++ b/src/soc/intel/braswell/include/soc/xhci.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc. */ -#ifndef BAYTRAIL_XHCI_H -#define BAYTRAIL_XHCI_H +#ifndef _SOC_XHCI_H +#define _SOC_XHCI_H /* XHCI PCI Registers */ #define XHCI_PWR_CTL_STS 0x74 @@ -37,7 +38,7 @@ # define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ # define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ # define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ +# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ # define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ # define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ # define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ @@ -45,12 +46,6 @@ # define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ # define XHCI_PLSW_ENABLE (5 << 5) /* Enable port */ -/* The Fuse register is incorrect for Baytrail-M so use hardcoded values */ -#define BYTM_USB2_PORT_COUNT 4 -#define BYTM_USB2_PORT_MAP 0xf -#define BYTM_USB3_PORT_COUNT 1 -#define BYTM_USB3_PORT_MAP 0x1 - #define XHCI_RESET_TIMEOUT 100000 /* 100ms */ -#endif /* BAYTRAIL_XHCI_H */ +#endif /* _SOC_XHCI_H */ diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index f1ac606..98495db 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -18,18 +19,19 @@ */ #include <arch/io.h> +#include <console/console.h> #include <soc/iosf.h> -#if !defined(__PRE_RAM__) +#if ENV_RAMSTAGE #define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12)) static inline void write_iosf_reg(int reg, uint32_t value) { - write32((u32 *)(IOSF_PCI_BASE + reg), value); + write32((void *)(IOSF_PCI_BASE + reg), value); } static inline uint32_t read_iosf_reg(int reg) { - return read32((u32 *)(IOSF_PCI_BASE + reg)); + return read32((void *)(IOSF_PCI_BASE + reg)); } #else static inline void write_iosf_reg(int reg, uint32_t value) @@ -40,7 +42,7 @@ static inline uint32_t read_iosf_reg(int reg) { return pci_read_config32(IOSF_PCI_DEV, reg); } -#endif +#endif /* ENV_RAMSTAGE */ /* Common sequences for all the port accesses. */ static uint32_t iosf_read_port(uint32_t cr, int reg) @@ -60,9 +62,9 @@ static void iosf_write_port(uint32_t cr, int reg, uint32_t val) } #define IOSF_READ(port) \ - IOSF_OPCODE(IOSF_OP_READ_##port) | IOSF_PORT(IOSF_PORT_##port) + (IOSF_OPCODE(IOSF_OP_READ_##port) | IOSF_PORT(IOSF_PORT_##port)) #define IOSF_WRITE(port) \ - IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port) + (IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port)) uint32_t iosf_bunit_read(int reg) { @@ -74,28 +76,6 @@ void iosf_bunit_write(int reg, uint32_t val) iosf_write_port(IOSF_WRITE(BUNIT), reg, val); } -uint32_t iosf_dunit_read(int reg) -{ - return iosf_read_port(IOSF_READ(SYSMEMC), reg); -} - -uint32_t iosf_dunit_ch0_read(int reg) -{ - return iosf_dunit_read(reg); -} - -uint32_t iosf_dunit_ch1_read(int reg) -{ - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | - IOSF_PORT(IOSF_PORT_DUNIT_CH1); - return iosf_read_port(cr, reg); -} - -void iosf_dunit_write(int reg, uint32_t val) -{ - iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); -} - uint32_t iosf_punit_read(int reg) { return iosf_read_port(IOSF_READ(PMC), reg); @@ -106,24 +86,14 @@ void iosf_punit_write(int reg, uint32_t val) iosf_write_port(IOSF_WRITE(PMC), reg, val); } -uint32_t iosf_usbphy_read(int reg) -{ - return iosf_read_port(IOSF_READ(USBPHY), reg); -} - -void iosf_usbphy_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); -} - -uint32_t iosf_ushphy_read(int reg) +uint32_t iosf_score_read(int reg) { - return iosf_read_port(IOSF_READ(USHPHY), reg); + return iosf_read_port(IOSF_READ(SCORE), reg); } -void iosf_ushphy_write(int reg, uint32_t val) +void iosf_score_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(USHPHY), reg, val); + iosf_write_port(IOSF_WRITE(SCORE), reg, val); } uint32_t iosf_lpss_read(int reg) @@ -133,27 +103,17 @@ uint32_t iosf_lpss_read(int reg) void iosf_lpss_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(LPSS), reg, val); -} - -uint32_t iosf_ccu_read(int reg) -{ - return iosf_read_port(IOSF_READ(CCU), reg); -} - -void iosf_ccu_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(CCU), reg, val); + iosf_write_port(IOSF_WRITE(LPSS), reg, val); } -uint32_t iosf_score_read(int reg) +uint32_t iosf_port58_read(int reg) { - return iosf_read_port(IOSF_READ(SCORE), reg); + return iosf_read_port(IOSF_READ(0x58), reg); } -void iosf_score_write(int reg, uint32_t val) +void iosf_port58_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(SCORE), reg, val); + iosf_write_port(IOSF_WRITE(0x58), reg, val); } uint32_t iosf_scc_read(int reg) @@ -166,122 +126,71 @@ void iosf_scc_write(int reg, uint32_t val) return iosf_write_port(IOSF_WRITE(SCC), reg, val); } -uint32_t iosf_aunit_read(int reg) -{ - return iosf_read_port(IOSF_READ(AUNIT), reg); -} - -void iosf_aunit_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(AUNIT), reg, val); -} - -uint32_t iosf_cpu_bus_read(int reg) -{ - return iosf_read_port(IOSF_READ(CPU_BUS), reg); -} - -void iosf_cpu_bus_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val); -} - -uint32_t iosf_sec_read(int reg) -{ - return iosf_read_port(IOSF_READ(SEC), reg); -} - -void iosf_sec_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(SEC), reg, val); -} - -uint32_t iosf_port45_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x45), reg); -} - -void iosf_port45_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x45), reg, val); -} - -uint32_t iosf_port46_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x46), reg); -} - -void iosf_port46_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x46), reg, val); -} -uint32_t iosf_port47_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x47), reg); -} - -void iosf_port47_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x47), reg, val); -} - -uint32_t iosf_port55_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x55), reg); -} - -void iosf_port55_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x55), reg, val); -} - -uint32_t iosf_port58_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x58), reg); -} - -void iosf_port58_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x58), reg, val); -} - -uint32_t iosf_port59_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x59), reg); -} - -void iosf_port59_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x59), reg, val); -} - -uint32_t iosf_port5a_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x5a), reg); -} - -void iosf_port5a_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x5a), reg, val); -} - -uint32_t iosf_porta2_read(int reg) -{ - return iosf_read_port(IOSF_READ(0xa2), reg); -} - -void iosf_porta2_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0xa2), reg, val); -} - -uint32_t iosf_ssus_read(int reg) -{ - return iosf_read_port(IOSF_READ(SSUS), reg); -} - -void iosf_ssus_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(SSUS), reg, val); -} +#if ENV_RAMSTAGE +uint64_t reg_script_read_iosf(struct reg_script_context *ctx) +{ + const struct reg_script *step = ctx->step; + + /* Process the request */ + switch (step->id) { + case IOSF_PORT_BUNIT: + return iosf_bunit_read(step->reg); + case IOSF_PORT_SCORE: + return iosf_score_read(step->reg); + case IOSF_PORT_LPSS: + return iosf_lpss_read(step->reg); + case IOSF_PORT_0x58: + return iosf_port58_read(step->reg); + case IOSF_PORT_SCC: + return iosf_scc_read(step->reg); + default: + printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n", + step->id); + break; + } + return 0; +} + +void reg_script_write_iosf(struct reg_script_context *ctx) +{ + const struct reg_script *step = ctx->step; + + /* Process the request */ + switch (step->id) { + case IOSF_PORT_BUNIT: + iosf_bunit_write(step->reg, step->value); + break; + case IOSF_PORT_SCORE: + iosf_score_write(step->reg, step->value); + break; + case IOSF_PORT_LPSS: + iosf_lpss_write(step->reg, step->value); + break; + case IOSF_PORT_0x58: + iosf_port58_write(step->reg, step->value); + break; + case IOSF_PORT_SCC: + iosf_scc_write(step->reg, step->value); + break; + + default: + printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n", + step->id); + break; + } +} + +const struct reg_script_bus_entry reg_script_bus_table[] = { + {REG_SCRIPT_TYPE_IOSF, reg_script_read_iosf, reg_script_write_iosf} +}; + +const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries) +{ + /* Return the table size and address */ + *table_entries = sizeof(reg_script_bus_table) + / sizeof(reg_script_bus_table[0]); + return &reg_script_bus_table[0]; +} + +#endif /* ENV_RAMSTAGE */ diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index fdac299..fa4b695 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,13 +32,15 @@ #include <soc/nvs.h> #include <soc/pattrs.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/ramstage.h> #include "chip.h" -/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB - * address. Just take 1MiB @ 512MiB. */ +/* + * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB + * address. Just take 1MiB @ 512MiB. + */ #define FIRMWARE_PHYS_BASE (512 << 20) #define FIRMWARE_PHYS_LENGTH (1 << 20) #define FIRMWARE_PCI_REG_BASE 0xa8 @@ -59,7 +62,8 @@ static void lpe_enable_acpi_mode(device_t dev) static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, LPE_PCICFGCTR1_PCI_CFG_DIS | @@ -69,7 +73,7 @@ static void lpe_enable_acpi_mode(device_t dev) global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { printk(BIOS_ERR, "Unable to locate Global NVS\n"); return; @@ -77,7 +81,8 @@ static void lpe_enable_acpi_mode(device_t dev) /* Save BAR0, BAR1, and firmware base to ACPI NVS */ assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); - assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); + /* LPE seems does not have BAR at PCI_BASE_ADDRESS_1 so disable it. */ + /* assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); */ assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); /* Device is enabled in ACPI mode */ @@ -91,7 +96,7 @@ static void setup_codec_clock(device_t dev) { uint32_t reg; u32 *clk_reg; - struct soc_intel_baytrail_config *config; + struct soc_intel_braswell_config *config; const char *freq_str; config = dev->chip_info; @@ -119,7 +124,7 @@ static void setup_codec_clock(device_t dev) printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); - clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0); + clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0); clk_reg += config->lpe_codec_clk_num; write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); @@ -129,34 +134,35 @@ static void lpe_stash_firmware_info(device_t dev) { struct resource *res; struct resource *mmio; - const struct pattrs *pattrs = pattrs_get(); res = find_resource(dev, FIRMWARE_PCI_REG_BASE); if (res == NULL) { printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); return; } + printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32) res->base); /* Continue using old way of informing firmware address / size. */ pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); - /* C0 and later steppings use an offset in the MMIO space. */ - if (pattrs->stepping >= STEP_C0) { - mmio = find_resource(dev, PCI_BASE_ADDRESS_0); - write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), - res->base); - write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), - res->size); - } + /* Also put the address in MMIO space like on C0 BTM */ + mmio = find_resource(dev, PCI_BASE_ADDRESS_0); + write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), \ + res->base); + write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), \ + res->size); } + static void lpe_init(device_t dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; - lpe_stash_firmware_info(dev); + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + lpe_stash_firmware_info(dev); setup_codec_clock(dev); if (config->lpe_acpi_mode) diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index e70c090..f580fbf 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -48,7 +49,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { printk(BIOS_ERR, "Unable to locate Global NVS\n"); return; @@ -70,26 +71,16 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) reg_script_run_on_dev(dev, ops); } -static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) -{ - struct reg_script ops[] = { - REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, - ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), - LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), - REG_SCRIPT_END, - }; - - reg_script_run_on_dev(dev, ops); -} - static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) { *iosf_reg = -1; *nvs_index = -1; #define SET_IOSF_REG(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ - *iosf_reg = LPSS_ ## name_ ## _CTL; \ - *nvs_index = LPSS_NVS_ ## name_ + do { \ + *iosf_reg = LPSS_ ## name_ ## _CTL; \ + *nvs_index = LPSS_NVS_ ## name_; \ + } while (0) switch (dev->path.pci.devfn) { SET_IOSF_REG(SIO_DMA1); @@ -135,13 +126,13 @@ static void i2c_disable_resets(device_t dev) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) switch (dev->path.pci.devfn) { - CASE_I2C(I2C1): - CASE_I2C(I2C2): - CASE_I2C(I2C3): - CASE_I2C(I2C4): - CASE_I2C(I2C5): - CASE_I2C(I2C6): - CASE_I2C(I2C7): + CASE_I2C(I2C1) : + CASE_I2C(I2C2) : + CASE_I2C(I2C3) : + CASE_I2C(I2C4) : + CASE_I2C(I2C5) : + CASE_I2C(I2C6) : + CASE_I2C(I2C7) : printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); reg_script_run_on_dev(dev, ops); break; @@ -152,9 +143,15 @@ static void i2c_disable_resets(device_t dev) static void lpss_init(device_t dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; int iosf_reg, nvs_index; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s - %s\n", + get_pci_class_name(dev), + get_pci_subclass_name(dev)); + dev_ctl_reg(dev, &iosf_reg, &nvs_index); if (iosf_reg < 0) { @@ -164,7 +161,7 @@ static void lpss_init(device_t dev) slot, func); return; } - dev_enable_snoop_and_pm(dev, iosf_reg); + i2c_disable_resets(dev); if (config->lpss_acpi_mode) diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 110dc45..28156a3 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -19,15 +20,66 @@ #include <arch/io.h> #include <cbmem.h> +#include <console/console.h> +#include <soc/intel/common/memmap.h> #include <soc/iosf.h> #include <soc/smm.h> -uintptr_t smm_region_start(void) +static size_t smm_region_size(void) { - return (iosf_bunit_read(BUNIT_SMRRL) << 20); + u32 smm_size; + smm_size = iosf_bunit_read(BUNIT_SMRRH) & 0xFFFF; + smm_size -= iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF; + smm_size = (smm_size + 1) << 20; + return smm_size; +} + +void smm_region(void **start, size_t *size) +{ + *start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20); + *size = smm_region_size(); +} + +size_t mmap_region_granluarity(void) +{ + /* Align to TSEG size when SMM is in use, and 8MiB by default */ + return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? smm_region_size() + : 8 << 20; } void *cbmem_top(void) { - return (void *) smm_region_start(); + char *smm_base; + size_t smm_size; + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + smm_region((void **)&smm_base, &smm_size); + return (void *)(smm_base - CONFIG_CHIPSET_RESERVED_MEM_BYTES); } diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc index 09bd454..936dd85 100644 --- a/src/soc/intel/braswell/microcode/Makefile.inc +++ b/src/soc/intel/braswell/microcode/Makefile.inc @@ -1 +1,13 @@ -cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c +# Add CPU uCode source to list of files to build. +cpu_microcode-y += microcode_blob.c + +# This section overrides the default build process for the microcode to place +# it at a known location in the CBFS. This only needs to be enabled if FSP is +# being used. +# Define the correct offset for the file in CBFS +fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) + +# Override the location that was supplied by the core code. +add-cpu-microcode-to-cbfs = \ + $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 -b $(fsp_ucode_cbfs_base) + diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c index 7c7b6f1..bcadcfe 100644 --- a/src/soc/intel/braswell/microcode/microcode_blob.c +++ b/src/soc/intel/braswell/microcode/microcode_blob.c @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + unsigned microcode[] = { -#include "../../../../../3rdparty/soc/intel/baytrail/microcode_blob.h" +#include <microcode_blob.h> }; diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index af0fa50..d5d7268 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,19 +18,24 @@ * Foundation, Inc. */ +#include <arch/acpi.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <vendorcode/google/chromeos/chromeos.h> - +#include <fsp_util.h> +#include <soc/intel/common/memmap.h> #include <soc/iomap.h> #include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include <soc/smm.h> +#include <vendorcode/google/chromeos/chromeos.h> -/* Host Memory Map: +/* + * Host Memory Map: * * +--------------------------+ BMBOUND_HI * | Usable DRAM | @@ -46,11 +52,13 @@ * +--------------------------+ SMMRRH, IRM0 * | TSEG | * +--------------------------+ SMMRRL + * | FSP Reserved Mem | + * +--------------------------+ SMMRRL - CONFIG_CHIPSET_RESERVED_MEM_BYTES * | Usable DRAM | * +--------------------------+ 0 * * Note that there are really only a few regions that need to enumerated w.r.t. - * coreboot's resource model: + * coreboot's resrouce model: * * +--------------------------+ BMBOUND_HI * | Cacheable/Usable | @@ -64,7 +72,7 @@ * | Cacheable/Usable | * +--------------------------+ 0 */ -#define RES_IN_KiB(r) ((r) >> 10) +#define RES_IN_KIB(r) ((r) >> 10) uint32_t nc_read_top_of_low_memory(void) { @@ -74,10 +82,13 @@ uint32_t nc_read_top_of_low_memory(void) static void nc_read_resources(device_t dev) { unsigned long mmconf; - unsigned long bmbound; + unsigned long bmbound_k; unsigned long bmbound_hi; - unsigned long smmrrh; - unsigned long smmrrl; + void *smm_base; + size_t smm_size; + unsigned long tseg_base_k; + unsigned long tseg_top_k; + unsigned long fsp_res_base_k; unsigned long base_k, size_k; const unsigned long four_gig_kib = (4 << (30 - 10)); int index = 0; @@ -85,60 +96,64 @@ static void nc_read_resources(device_t dev) /* Read standard PCI resources. */ pci_dev_read_resources(dev); + /* Determine TSEG data */ + smm_region(&smm_base, &smm_size); + tseg_base_k = RES_IN_KIB((unsigned long) smm_base); + tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size); + + /* Determine the base of the FSP reserved memory */ + fsp_res_base_k = RES_IN_KIB((unsigned long) cbmem_top()); + /* PCIe memory-mapped config space access - 256 MiB. */ mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); - mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); + mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KIB(mmconf), 256 * 1024); /* 0 -> 0xa0000 */ - base_k = RES_IN_KiB(0); - size_k = RES_IN_KiB(0xa0000) - base_k; + base_k = RES_IN_KIB(0); + size_k = RES_IN_KIB(0xa0000) - base_k; ram_resource(dev, index++, base_k, size_k); - /* The SMMRR registers are 1MiB granularity with smmrrh being - * inclusive of the SMM region. */ - smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) << 10; - smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) << 10; - - /* 0xc0000 -> smrrl - cacheable and usable */ - base_k = RES_IN_KiB(0xc0000); - size_k = smmrrl - base_k; + /* 0xc0000 -> fsp_res_base - cacheable and usable */ + base_k = RES_IN_KIB(0xc0000); + size_k = fsp_res_base_k - base_k; ram_resource(dev, index++, base_k, size_k); - if (smmrrh > smmrrl) - reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl); + /* fsp_res_base -> tseg_top - Reserved */ + base_k = fsp_res_base_k; + size_k = tseg_top_k - base_k; + reserved_ram_resource(dev, index++, base_k, size_k); - /* All address space between bmbound and smmrrh is unusable. */ - bmbound = RES_IN_KiB(nc_read_top_of_low_memory()); - mmio_resource(dev, index++, smmrrh, bmbound - smmrrh); + /* TSEG TOP -> bmbound is memory backed mmio. */ + bmbound_k = RES_IN_KIB(nc_read_top_of_low_memory()); + mmio_resource(dev, index++, tseg_top_k, bmbound_k - tseg_top_k); - /* The BMBOUND_HI register matches register bits of 31:24 with address - * bits of 35:28. Therefore, shift register to align properly. */ + /* + * The BMBOUND_HI register matches register bits of 31:24 with address + * bits of 35:28. Therefore, shift register to align properly. + */ bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); - bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; + bmbound_hi = RES_IN_KIB(bmbound_hi) << 4; if (bmbound_hi > four_gig_kib) ram_resource(dev, index++, four_gig_kib, - bmbound_hi - four_gig_kib); + bmbound_hi - four_gig_kib); - /* Reserve everything between A segment and 1MB: + /* + * Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + (0x100000 - 0xc0000) >> 10); chromeos_reserve_ram_oops(dev, index++); } static struct device_operations nc_ops = { - .read_resources = nc_read_resources, - .set_resources = NULL, - .enable_resources = NULL, - .init = NULL, - .enable = NULL, - .scan_bus = NULL, - .ops_pci = &soc_pci_ops, + .acpi_fill_ssdt_generator = generate_cpu_entries, + .read_resources = nc_read_resources, + .ops_pci = &soc_pci_ops, }; static const struct pci_driver nc_driver __pci_driver = { diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index e4c0654..608d724 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,20 +18,18 @@ * Foundation, Inc. */ +#include "chip.h" #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pciexp.h> #include <device/pci_ids.h> #include <reg_script.h> - #include <soc/pci_devs.h> #include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/smm.h> -#include "chip.h" - static int pll_en_off; static uint32_t strpfusecfg; @@ -47,11 +46,13 @@ static inline int is_first_port(device_t dev) static const struct reg_script init_static_before_exit_latency[] = { /* Disable optimized buffer flush fill and latency tolerant reporting */ REG_PCI_RMW32(DCAP2, ~(OBFFS | LTRMS), 0), - REG_PCI_RMW32(DSTS2, ~(OBFFEN| LTRME), 0), + REG_PCI_RMW32(DSTS2, ~(OBFFEN | LTRME), 0), /* Set maximum payload size. */ REG_PCI_RMW32(DCAP, ~MPS_MASK, 0), - /* Disable transmit datapath flush timer, clear transmit config change - * wait time, clear sideband interface idle counter. */ + /* + * Disable transmit datapath flush timer, clear transmit config change + * wait time, clear sideband interface idle counter. + */ REG_PCI_RMW32(PHYCTL2_IOSFBCTL, ~(TDFT | TXCFGCHWAIT | SIID), 0), REG_SCRIPT_END, }; @@ -67,8 +68,10 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_PCI_RMW32(RTP, 0xff000000, 0x854c74), /* Set IOSF packet fast transmit mode and link speed training policy. */ REG_PCI_OR16(MPC2, IPF | LSTP), - /* Channel configuration - enable upstream posted split, set non-posted - * and posted request size */ + /* + * Channel configuration - enable upstream posted split, set non-posted + * and posted request size + */ REG_PCI_RMW32(CHCFG, ~UPSD, UNRS | UPRS), /* Completion status replay enable and set TLP grant count */ REG_PCI_RMW32(CFG2, ~(LATGC_MASK), CSREN | (3 << LATGC_SHIFT)), @@ -80,7 +83,7 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_PCI_RMW16(DSTS2, ~CTD, 0x6), /* Enable AER */ REG_PCI_OR16(DCTL_DSTS, URE | FEE | NFE | CEE), - /* Read and write back capability registers. */ + /* Read and write back capabaility registers. */ REG_PCI_OR32(0x34, 0), REG_PCI_OR32(0x80, 0), /* Retrain the link. */ @@ -88,14 +91,16 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_SCRIPT_END, }; -static void byt_pcie_init(device_t dev) +static void pcie_init(device_t dev) { struct reg_script init_script[] = { REG_SCRIPT_NEXT(init_static_before_exit_latency), - /* Exit latency configuration based on - * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ + /* + * Exit latency configuration based on + * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1 + */ REG_PCI_RMW32(LCAP, ~L1EXIT_MASK, - 2 << (L1EXIT_SHIFT + pll_en_off)), + 2 << (L1EXIT_MASK + pll_en_off)), REG_SCRIPT_NEXT(init_static_after_exit_latency), /* Disable hot plug, set power to 10W, set slot number. */ REG_PCI_RMW32(SLCAP, ~(HPC | HPS), @@ -108,10 +113,13 @@ static void byt_pcie_init(device_t dev) REG_SCRIPT_END, }; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + reg_script_run_on_dev(dev, init_script); if (is_first_port(dev)) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; uint32_t reg = pci_read_config32(dev, RPPGEN); reg |= SRDLCGEN | SRDBCGEN; @@ -133,6 +141,9 @@ static void check_port_enabled(device_t dev) { int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + switch (root_port_offset(dev)) { case PCIE_PORT1_FUNC: /* Port 1 cannot be disabled from strapping config. */ @@ -155,63 +166,66 @@ static void check_port_enabled(device_t dev) } } -static u8 all_ports_no_dev_present(device_t dev) -{ - u8 func; - u8 temp = dev->path.pci.devfn; - u8 device_not_present = 1; - u8 data; - - for (func = 1; func < PCIE_ROOT_PORT_COUNT; func++) { - dev->path.pci.devfn &= ~0x7; - dev->path.pci.devfn |= func; - - /* is pcie device there */ - if (pci_read_config32(dev, 0) == 0xFFFFFFFF) - continue; - - data = pci_read_config8(dev, XCAP + 3) | (SI >> 24); - pci_write_config8(dev, XCAP + 3, data); - - /* is any device present */ - if ((pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { - device_not_present = 0; - break; - } - } - - dev->path.pci.devfn = temp; - return device_not_present; -} - static void check_device_present(device_t dev) { + /* port1_dev will store the dev struct pointer of the PORT1 */ + static device_t port1_dev; + + /* + * The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW. + * For each port initial assumption is that, each port will have + * devices connected to it. Later we will scan each PORT and if + * the device is not attached to that port we will update + * rootports_in_use. If none of the root port is in use we will + * disable PORT1 otherwise we will keep PORT1 enabled per spec. + * In future if the Soc has more number of PCIe Root ports then + * change MAX_ROOT_PORTS_BSW value accordingly. + */ + + static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW; + + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); /* No device present. */ if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { - printk(BIOS_DEBUG, "No PCIe device present.\n"); - if (is_first_port(dev)) { - if (all_ports_no_dev_present(dev)) { - reg_script_run_on_dev(dev, no_dev_behind_port); - dev->enabled = 0; - } - } else { + rootports_in_use--; + printk(BIOS_DEBUG, "No PCIe device present."); + + /* + * Defer PORT1 disabling for now. When we are at Last port + * we will check rootports_in_use and disable PORT1 if none + * of the port has any device connected + */ + if (!is_first_port(dev)) { reg_script_run_on_dev(dev, no_dev_behind_port); dev->enabled = 0; + } else + port1_dev = dev; + /* + * If none of the ROOT PORT has devices connected then + * disable PORT1 else keep the PORT1 enable + */ + if (!rootports_in_use) { + reg_script_run_on_dev(port1_dev, no_dev_behind_port); + port1_dev->enabled = 0; + southcluster_enable_dev(port1_dev); } - } else if(!dev->enabled) { + } else if (!dev->enabled) { /* Port is disabled, but device present. Disable link. */ pci_write_config32(dev, LCTL, pci_read_config32(dev, LCTL) | LD); } } -static void byt_pcie_enable(device_t dev) +static void pcie_enable(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); if (is_first_port(dev)) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); pll_en_off = !!(reg & PLL_OFF_EN); @@ -230,21 +244,10 @@ static void byt_pcie_enable(device_t dev) southcluster_enable_dev(dev); } -static unsigned int byt_pciexp_scan_bridge(device_t dev, unsigned int max) -{ - static const struct reg_script wait_for_link_active[] = { - REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000), - REG_SCRIPT_END, - }; - - /* wait for Link Active with 50ms timeout */ - reg_script_run_on_dev(dev, wait_for_link_active); - - return do_pci_scan_bridge(dev, max, pciexp_scan_bus); -} - static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) { + printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", + __FILE__, __func__, dev_name(dev), vid, did); uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); if (!didvid) @@ -260,9 +263,9 @@ static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = byt_pcie_init, - .scan_bus = byt_pciexp_scan_bridge, - .enable = byt_pcie_enable, + .init = pcie_init, + .scan_bus = pciexp_scan_bridge, + .enable = pcie_enable, .ops_pci = &pcie_root_ops, }; diff --git a/src/soc/intel/braswell/perf_power.c b/src/soc/intel/braswell/perf_power.c deleted file mode 100644 index 336ba3f..0000000 --- a/src/soc/intel/braswell/perf_power.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <bootstate.h> -#include <console/console.h> -#include <reg_script.h> -#include <soc/iosf.h> - -#define MAKE_MASK_INCLUSIVE(msb) \ - ((1ULL << (1 + (msb))) - 1) -#define MAKE_MASK(msb) \ - ((1ULL << (msb)) - 1) -#define MASK_VAL(msb, lsb, val) \ - ~(MAKE_MASK_INCLUSIVE(msb) & ~MAKE_MASK(lsb)), (val) << (lsb) - -#define E(arg1, arg2, args) \ - REG_IOSF_RMW(IOSF_PORT_##arg1, arg2, args) - -static const struct reg_script perf_power_settings[] = { -E(AUNIT, 0x18, MASK_VAL(22, 22, 0x1)), // ACKGATE.AMESSAGE_MSGIF -E(AUNIT, 0x18, MASK_VAL(21, 21, 0x1)), // ACKGATE.AREQDOWN_SCL0_ARB -E(AUNIT, 0x18, MASK_VAL(20, 20, 0x1)), // ACKGATE.AREQUP_MIRROR -E(AUNIT, 0x18, MASK_VAL(19, 19, 0x1)), // ACKGATE.AREQTAHACK -E(AUNIT, 0x18, MASK_VAL(18, 18, 0x1)), // ACKGATE.AREQDOWN_TAREQQ -E(AUNIT, 0x18, MASK_VAL(17, 17, 0x1)), // ACKGATE.AREQDOWN_CREDIT -E(AUNIT, 0x18, MASK_VAL(16, 16, 0x1)), // ACKGATE.ASCLUP_FAIR_ARBITER -E(AUNIT, 0x18, MASK_VAL(15, 15, 0x1)), // ACKGATE.AIOSFDOWN_DATA -E(AUNIT, 0x18, MASK_VAL(14, 14, 0x1)), // ACKGATE.ASCLUP_IOSF_ADAPTER -E(AUNIT, 0x18, MASK_VAL(12, 12, 0x1)), // ACKGATE.ASCLUP_CMD_QUEUE -E(AUNIT, 0x18, MASK_VAL(11, 11, 0x1)), // ACKGATE.ASCLUP_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(10, 10, 0x1)), // ACKGATE.AREQUP_CMD_QUEUE -E(AUNIT, 0x18, MASK_VAL(9, 9, 0x1)), // ACKGATE.AREQUP_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(8, 8, 0x1)), // ACKGATE.AREQDOWN_RSP_QUEUE -E(AUNIT, 0x18, MASK_VAL(7, 7, 0x1)), // ACKGATE.AREQDOWN_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(6, 6, 0x1)), // ACKGATE.AIOSFDOWN_CMD_DRVR -E(AUNIT, 0x18, MASK_VAL(5, 5, 0x1)), // ACKGATE.AIOSFDOWN_CMD_DATA_BUFF -E(AUNIT, 0x18, MASK_VAL(4, 4, 0x1)), // ACKGATE.AT_REQ_QUEUE -E(AUNIT, 0x18, MASK_VAL(3, 3, 0x1)), // ACKGATE.AT_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(2, 2, 0x1)), // ACKGATE.TA_REQ_QUEUE -E(AUNIT, 0x18, MASK_VAL(1, 1, 0x1)), // ACKGATE.TA_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(0, 0, 0x1)), // ACKGATE.CONFIG_REGS -E(AUNIT, 0x20, MASK_VAL(26, 24, 0x2)), // AISOCHCTL.CHANNEL_AB_DEADLINE_EN -E(AUNIT, 0x20, MASK_VAL(8, 0, 0x1)), // AISOCHCTL.VC1_ISOC_CH_DEFAULT_DDLINE_DLY -E(AUNIT, 0x21, MASK_VAL(31, 31, 0x1)), // AVCCTL.EFFICIENT_PERF_UP_EN -E(AUNIT, 0x21, MASK_VAL(8, 8, 0x0)), // AVCCTL.VC_EN_PRIORITY_DNARB -E(AUNIT, 0x0C0, MASK_VAL(11, 8, 0x4)), // AARBCTL0.IOSF0VC2_WGT -E(AUNIT, 0x0C0, MASK_VAL(7, 4, 0x4)), // AARBCTL0.IOSF0VC1_WGT -E(AUNIT, 0x0C0, MASK_VAL(3, 0, 0x4)), // AARBCTL0.IOSF0VC0_WGT -E(BUNIT, 0x3, MASK_VAL(29, 24, 0x4)), // BARBCTRL0.AGENT3_WEIGHT -E(BUNIT, 0x3, MASK_VAL(21, 16, 0x4)), // BARBCTRL0.AGENT2_WEIGHT -E(BUNIT, 0x3, MASK_VAL(13, 8, 0x4)), // BARBCTRL0.AGENT1_WEIGHT -E(BUNIT, 0x3, MASK_VAL(5, 0, 0x4)), // BARBCTRL0.AGENT0_WEIGHT -E(BUNIT, 0x4, MASK_VAL(29, 24, 0x4)), // BARBCTRL1.AGENT7_WEIGHT -E(BUNIT, 0x4, MASK_VAL(21, 16, 0x4)), // BARBCTRL1.AGENT6_WEIGHT -E(BUNIT, 0x4, MASK_VAL(13, 8, 0x4)), // BARBCTRL1.AGENT5_WEIGHT -E(BUNIT, 0x4, MASK_VAL(5, 0, 0x4)), // BARBCTRL1.AGENT4_WEIGHT -E(BUNIT, 0x5, MASK_VAL(21, 16, 0x4)), // BARBCTRL2.AGENT10_WEIGHT -E(BUNIT, 0x5, MASK_VAL(13, 8, 0x4)), // BARBCTRL2.AGENT9_WEIGHT -E(BUNIT, 0x5, MASK_VAL(5, 0, 0x8)), // BARBCTRL2.AGENT8_WEIGHT -E(BUNIT, 0x7, MASK_VAL(31, 24, 0x20)), // BWFLUSH.FLUSH_THRSHOLD -E(BUNIT, 0x7, MASK_VAL(15, 8, 0x0A)), // BWFLUSH.DIRTY_LWM -E(BUNIT, 0x7, MASK_VAL(7, 0, 0x10)), // BWFLUSH.DIRTY_HWM -E(BUNIT, 0x8, MASK_VAL(23, 0, 0x0)), // BBANKMASK.BANK_MASK -E(BUNIT, 0x9, MASK_VAL(23, 0, 0x3FFFFC)), // BROWMASK.ROW_MASK -E(BUNIT, 0x0A, MASK_VAL(9, 0, 0x080)), // BRANKMASK.RANK_MASK -E(BUNIT, 0x0B, MASK_VAL(29, 24, 0x1F)), // BALIMIT0.AGENT3_LIMIT -E(BUNIT, 0x0B, MASK_VAL(21, 16, 0x2F)), // BALIMIT0.AGENT2_LIMIT -E(BUNIT, 0x0B, MASK_VAL(13, 8, 0x2F)), // BALIMIT0.AGENT1_LIMIT -E(BUNIT, 0x0B, MASK_VAL(5, 0, 0x2F)), // BALIMIT0.AGENT0_LIMIT -E(BUNIT, 0x0C, MASK_VAL(29, 24, 0x2F)), // BALIMIT1.AGENT7_LIMIT -E(BUNIT, 0x0C, MASK_VAL(21, 16, 0x2F)), // BALIMIT1.AGENT6_LIMIT -E(BUNIT, 0x0C, MASK_VAL(13, 8, 0x2F)), // BALIMIT1.AGENT5_LIMIT -E(BUNIT, 0x0C, MASK_VAL(5, 0, 0x2B)), // BALIMIT1.AGENT4_LIMIT -E(BUNIT, 0x0D, MASK_VAL(21, 16, 0x2F)), // BALIMIT2.AGENT10_LIMIT -E(BUNIT, 0x0D, MASK_VAL(13, 8, 0x2F)), // BALIMIT2.AGENT9_LIMIT -E(BUNIT, 0x0D, MASK_VAL(5, 0, 0x2F)), // BALIMIT2.AGENT8_LIMIT -E(BUNIT, 0x0F, MASK_VAL(29, 28, 0x0)), // BARES0.AGENT7_RSVD -E(BUNIT, 0x0F, MASK_VAL(25, 24, 0x0)), // BARES0.AGENT6_RSVD -E(BUNIT, 0x0F, MASK_VAL(21, 20, 0x0)), // BARES0.AGENT5_RSVD -E(BUNIT, 0x0F, MASK_VAL(17, 16, 0x0)), // BARES0.AGENT4_RSVD -E(BUNIT, 0x0F, MASK_VAL(13, 12, 0x0)), // BARES0.AGENT3_RSVD -E(BUNIT, 0x0F, MASK_VAL(9, 8, 0x0)), // BARES0.AGENT2_RSVD -E(BUNIT, 0x0F, MASK_VAL(5, 4, 0x0)), // BARES0.AGENT1_RSVD -E(BUNIT, 0x0F, MASK_VAL(1, 0, 0x0)), // BARES0.AGENT0_RSVD -E(BUNIT, 0x10, MASK_VAL(9, 8, 0x0)), // BARES1.AGENT10_RSVD -E(BUNIT, 0x10, MASK_VAL(5, 4, 0x0)), // BARES1.AGENT9_RSVD -E(BUNIT, 0x10, MASK_VAL(1, 0, 0x0)), // BARES1.AGENT8_RSVD -E(BUNIT, 0x11, MASK_VAL(31, 22, 0x20)), // BISOC.ENTER_SELF_REFRESH_THRSH -E(BUNIT, 0x11, MASK_VAL(18, 18, 0x1)), // BISOC.SR_EXIT_SYNC_EN -E(BUNIT, 0x11, MASK_VAL(17, 12, 0x4)), // BISOC.ENTER_SELF_REFRESH_DLY -E(BUNIT, 0x11, MASK_VAL(11, 8, 0x8)), // BISOC.SCHEDULER_LATENCY -E(BUNIT, 0x12, MASK_VAL(31, 30, 0x0)), // BCOSCAT.COS_CAT_AGENT15 and BCOSCAT.BUS_LOCK_THROTTLE_ENABLE -E(BUNIT, 0x12, MASK_VAL(29, 28, 0x0)), // BCOSCAT.COS_CAT_AGENT14 -E(BUNIT, 0x12, MASK_VAL(27, 26, 0x0)), // BCOSCAT.COS_CAT_AGENT13 -E(BUNIT, 0x12, MASK_VAL(25, 24, 0x0)), // BCOSCAT.COS_CAT_AGENT12 -E(BUNIT, 0x12, MASK_VAL(23, 22, 0x0)), // BCOSCAT.COS_CAT_AGENT11 -E(BUNIT, 0x12, MASK_VAL(21, 20, 0x0)), // BCOSCAT.COS_CAT_AGENT10 -E(BUNIT, 0x12, MASK_VAL(19, 18, 0x0)), // BCOSCAT.COS_CAT_AGENT9 -E(BUNIT, 0x12, MASK_VAL(17, 16, 0x1)), // BCOSCAT.COS_CAT_AGENT8 -E(BUNIT, 0x12, MASK_VAL(15, 14, 0x0)), // BCOSCAT.COS_CAT_AGENT7 -E(BUNIT, 0x12, MASK_VAL(13, 12, 0x0)), // BCOSCAT.COS_CAT_AGENT6 -E(BUNIT, 0x12, MASK_VAL(11, 10, 0x1)), // BCOSCAT.COS_CAT_AGENT5 -E(BUNIT, 0x12, MASK_VAL(9, 8, 0x1)), // BCOSCAT.COS_CAT_AGENT4 -E(BUNIT, 0x12, MASK_VAL(7, 6, 0x0)), // BCOSCAT.COS_CAT_AGENT3 -E(BUNIT, 0x12, MASK_VAL(5, 4, 0x0)), // BCOSCAT.COS_CAT_AGENT2 -E(BUNIT, 0x12, MASK_VAL(3, 2, 0x0)), // BCOSCAT.COS_CAT_AGENT1 -E(BUNIT, 0x12, MASK_VAL(1, 0, 0x0)), // BCOSCAT.COS_CAT_AGENT0 -E(BUNIT, 0x14, MASK_VAL(31, 31, 0x0)), // BFLWT.DISABLE_FLUSH_WEIGHTS -E(BUNIT, 0x14, MASK_VAL(30, 30, 0x0)), // BFLWT.ENABLE_READ_INVALIDATE_TIMER -E(BUNIT, 0x14, MASK_VAL(13, 8, 0x8)), // BFLWT.WRITE_WEIGHTS -E(BUNIT, 0x14, MASK_VAL(5, 0, 0x10)), // BFLWT.READ_WEIGHTS -E(BUNIT, 0x16, MASK_VAL(31, 31, 0x0)), // BISOCWT.ENABLE_ISOC_WEIGHTS -E(BUNIT, 0x16, MASK_VAL(13, 8, 0x3F)), // BISOCWT.ISOC_REQUEST_WEIGHTS -E(BUNIT, 0x16, MASK_VAL(5, 0, 0x8)), // BISOCWT.NON_ISOC_REQUEST_WEIGHTS -E(BUNIT, 0x18, MASK_VAL(31, 24, 0x20)), // BSCHCTRL0.BEST_EFFORT_MAX_LATENCY -E(BUNIT, 0x18, MASK_VAL(23, 21, 0x6)), // BSCHCTRL0.PAGE_HIT_DELAY -E(BUNIT, 0x18, MASK_VAL(13, 7, 0x0)), // BSCHCTRL0.ISOC_BANK_PREFETCH -E(BUNIT, 0x18, MASK_VAL(6, 0, 0x20)), // BSCHCTRL0.BEST_EFFORT_BANK_PREFETCH -E(BUNIT, 0x3B, MASK_VAL(23, 16, 0x4)), // BDEBUG0.CASUAL_TIMER -E(BUNIT, 0x3B, MASK_VAL(9, 9, 0x0)), // BDEBUG0.DISABLE_BADMIT_URGENT_ISOC -E(BUNIT, 0x3B, MASK_VAL(7, 0, 0x0A)), // BDEBUG0.CASUAL_WATER_MARK -E(BUNIT, 0x3C, MASK_VAL(31, 16, 0x0FFFF)), // BDEBUG1.AGENT_WEIGHT_ENABLE -E(BUNIT, 0x3C, MASK_VAL(2, 2, 0x0)), // BDEBUG1.EXIT_SR_FOR_CASUAL_FLUSH -E(BUNIT, 0x3C, MASK_VAL(1, 1, 0x0)), // BDEBUG1.ENABLE_DRAM_SELF_RFRSH -E(BUNIT, 0x3D, MASK_VAL(14, 14, 0x1)), // BCTRL.BANK_STATUS_ENABLE -E(BUNIT, 0x3D, MASK_VAL(13, 13, 0x0)), // BCTRL.DISABLE_OWNED -E(BUNIT, 0x3D, MASK_VAL(12, 12, 0x0)), // BCTRL.INORDER_READ_ENABLE -E(BUNIT, 0x3D, MASK_VAL(11, 11, 0x0)), // BCTRL.INORDER_FLUSH_ENABLE -E(BUNIT, 0x3D, MASK_VAL(8, 8, 0x0)), // BCTRL.MISS_VALID_ENTRIES -E(BUNIT, 0x3D, MASK_VAL(7, 7, 0x0)), // BCTRL.DIRTY_STALL -E(BUNIT, 0x3D, MASK_VAL(6, 6, 0x0)), // BCTRL.SINGLE_TAG_ACCESS -E(BUNIT, 0x3D, MASK_VAL(5, 5, 0x0)), // BCTRL.SINGLE_CHUNK_ACCESS -E(BUNIT, 0x3D, MASK_VAL(2, 2, 0x1)), // BCTRL.BECLK_GATE_EN -E(BUNIT, 0x3D, MASK_VAL(1, 1, 0x1)), // BCTRL.MASTERCLK_GATE_EN -E(BUNIT, 0x3D, MASK_VAL(0, 0, 0x1)), // BCTRL.REQUESTCLK_GATE_EN -E(BUNIT, 0x3E, MASK_VAL(31, 16, 0x0)), // BTHCTRL.AGENT_THROTTLING_ENABLE -E(BUNIT, 0x3E, MASK_VAL(7, 0, 0x0)), // BTHCTRL.RANK_SELECTION_MASK -E(BUNIT, 0x3F, MASK_VAL(31, 24, 0x0FF)), // BTHMASK.ORWRITE_MASK -E(BUNIT, 0x3F, MASK_VAL(23, 16, 0x0FF)), // BTHMASK.ORREAD_MASK -E(BUNIT, 0x3F, MASK_VAL(15, 8, 0x0FF)), // BTHMASK.ERWRITE_MASK -E(BUNIT, 0x3F, MASK_VAL(7, 0, 0x0FF)), // BTHMASK.ERREAD_MASK - //0x02, 0x0, 2, 0, 0x1, //T_INTR_REDIR_CTL.REDIR_MODE_SEL -E(CPU_BUS, 0x3, MASK_VAL(20, 20, 0x1)), // T_CTL.SPLIT_GOIWP_MODE -E(CPU_BUS, 0x3, MASK_VAL(19, 19, 0x0)), // T_CTL.DISABLE_TRDY_RDGO -E(CPU_BUS, 0x3, MASK_VAL(18, 18, 0x0)), // T_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN -E(CPU_BUS, 0x3, MASK_VAL(17, 17, 0x0)), // T_CTL.ENABLE_NPC_COLLECTOR -E(CPU_BUS, 0x3, MASK_VAL(16, 16, 0x1)), // T_CTL.ENABLE_IN_ORDER_APIC -E(CPU_BUS, 0x3, MASK_VAL(15, 15, 0x0)), // T_CTL.TG_HIGHPRI_WRITE_PULLS - //0x02, 0x3, 12, 12, 0x1, // T_CTL.TG_NDRAMSNP -E(CPU_BUS, 0x3, MASK_VAL(10, 10, 0x1)), // T_CTL.TG_DW_POST_PUSH_LOG -E(CPU_BUS, 0x3, MASK_VAL(3, 3, 0x0)), // T_CTL.ALWAYS_SNP_IDI -E(CPU_BUS, 0x3, MASK_VAL(2, 2, 0x0)), // T_CTL.DIS_LIVE_BRAM_BYP_IDI -E(CPU_BUS, 0x4, MASK_VAL(18, 18, 0x1)), // T_MISC_CTL.DISABLE_IOSF_OUTBOUND_THROTTLE -E(CPU_BUS, 0x4, MASK_VAL(4, 1, 0x8)), // T_MISC_CTL.DPTE_CNT -E(CPU_BUS, 0x4, MASK_VAL(0, 0, 0x0)), // T_MISC_CTL.DPTE_EN -E(CPU_BUS, 0x5, MASK_VAL(27, 27, 0x1)), // T_CLKGATE_CTL.XUNIT_4_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(26, 26, 0x1)), // T_CLKGATE_CTL.XUNIT_3_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(25, 25, 0x1)), // T_CLKGATE_CTL.XUNIT_2_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(24, 24, 0x1)), // T_CLKGATE_CTL.XUNIT_1_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(23, 23, 0x1)), // T_CLKGATE_CTL.MON_LOG_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(22, 22, 0x1)), // T_CLKGATE_CTL.A2T_Q_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(21, 21, 0x1)), // T_CLKGATE_CTL.T2A_Q_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(20, 20, 0x1)), // T_CLKGATE_CTL.A2TAPIC_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(19, 19, 0x1)), // T_CLKGATE_CTL.B2X_DATSEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(18, 18, 0x1)), // T_CLKGATE_CTL.X2B_DATSEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(17, 17, 0x1)), // T_CLKGATE_CTL.S2C_RESP_SEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(16, 16, 0x1)), // T_CLKGATE_CTL.T2A_REQ_SEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(15, 15, 0x1)), // T_CLKGATE_CTL.C2APIC_FIFO_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(14, 14, 0x1)), // T_CLKGATE_CTL.S2C_REQ_FIFO_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(13, 13, 0x1)), // T_CLKGATE_CTL.S2C_REQ_SEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(12, 12, 0x1)), // T_CLKGATE_CTL.TRKR_SB_LLST_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(11, 11, 0x1)), // T_CLKGATE_CTL.TRKR_SB_OLDST_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(10, 10, 0x1)), // T_CLKGATE_CTL.TRKR_SB_S2C_RESP_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(9, 9, 0x1)), // T_CLKGATE_CTL.TRKR_SB_T2A_REQSTAT_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(8, 8, 0x1)), // T_CLKGATE_CTL.TRKR_SB_B2X_DATSTAT_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(7, 7, 0x1)), // T_CLKGATE_CTL.TRKR_SB_WRSTAT_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(6, 6, 0x1)), // T_CLKGATE_CTL.TRKR_SB_SNP_STAT_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(5, 5, 0x1)), // T_CLKGATE_CTL.TRKR_SB_REQ_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(4, 4, 0x1)), // T_CLKGATE_CTL.TRKR_SB_VIOL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(3, 3, 0x1)), // T_CLKGATE_CTL.TRKR_SB_VALID_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(2, 2, 0x1)), // T_CLKGATE_CTL.TRKR_SB_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(1, 1, 0x1)), // T_CLKGATE_CTL.IOSF_SB_CFG_REG_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(0, 0, 0x1)), // T_CLKGATE_CTL.IOSF_SB_MSG_CLK_GATE_EN -E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN -E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN -E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN -E(0x55, 0x54, MASK_VAL(1, 0, 0x0)), // SMB_Config_PMCSR.PS -E(0x55, 0x0FC, MASK_VAL(17, 17, 0x0)), // SMB_Config_CGC.FUNC_CLK_CGD -E(0x55, 0x0FC, MASK_VAL(9, 9, 0x0)), // SMB_Config_CGC.SB_LOCAL_CGD -E(0xa2, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable -E(0x47, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable -E(0x45, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable -E(0x46, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable -E(PMC, 0x0, MASK_VAL(11, 11, 0x1)), // PUNIT_CONTROL.MODE_DEMOTE_EN -E(PMC, 0x0, MASK_VAL(10, 10, 0x1)), // PUNIT_CONTROL.CORE_DEMOTE_EN - - // - //s0ix_PnP_Settings - // -E(0x58, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.audio.lpe.bridge.pmctl.iosfprim_trunk_gate_en -E(0x58, 0x1e0, MASK_VAL(0, 0, 0x0)), //vlv.audio.lpe.bridge.pmctl.iosfprimclk_gate_en -E(0x58, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.audio.lpe.bridge.pmctl.iosfsb_trunk_gate_en -E(0x58, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.audio.lpe.bridge.pmctl.pmctl.iosfsbclk_gate_en -E(0x58, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.audio.lpe.bridge.pmctl.ocpclk_gate_en -E(0x58, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.audio.lpe.bridge.pmctl.ocpclk_trunk_gate_en -E(CCU, 0x28, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate -E(CCU, 0x38, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate_2 -E(CCU, 0x1c, MASK_VAL(29, 28, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_pri_clkgate_en -E(CCU, 0x1c, MASK_VAL(25, 24, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_sb_clkgate_en -E(CCU, 0x1c, MASK_VAL( 1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en -E(CCU, 0x54, MASK_VAL(17, 16, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_func_ip_clkgate_en -E(CCU, 0x54, MASK_VAL(13, 12, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_osc_ip_clk_en -E(CCU, 0x54, MASK_VAL(15, 14, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en -E(CCU, 0x54, MASK_VAL(26, 24, 0x0)), //vlv.ccu.clkgate_en_3.psf_pri_clkgate_en -E(CCU, 0x24, MASK_VAL(24, 20, 0x0)), //vlv.ccu.iclk_clkgate_ctrl.iopcibuffen_force_on -E(0x59, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprim_trunk_gate_en -E(0x59, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprimclk_gate_en -E(0x59, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsb_trunk_gate_en -E(0x59, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsbclk_gate_en -E(0x59, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_gate_en -E(0x59, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_trunk_gate_en -E(0x5a, 0xd0, MASK_VAL(8, 0, 0x3f)), //vlv.usb.xhci.controller.usb2pr.usb2hcsel -E(0x5a, 0x40, MASK_VAL(21, 19, 0x6)), //vlv.usb.xhci.controller.xhcc1.iil1e -E(0x5a, 0x40, MASK_VAL(10, 8, 0x1)), //vlv.usb.xhci.controller.xhcc1.l23hrawc -E(0x5a, 0x40, MASK_VAL(18, 18, 0x1)), //vlv.usb.xhci.controller.xhcc1.xhcil1e -E(0x5a, 0x50, MASK_VAL(3, 3, 0x1)), //vlv.usb.xhci.controller.xhclkgten.hsltcge -E(0x5a, 0x50, MASK_VAL(0, 0, 0x1)), //vlv.usb.xhci.controller.xhclkgten.iosfblcge -E(0x5a, 0x50, MASK_VAL(1, 1, 0x1)), //vlv.usb.xhci.controller.xhclkgten.iosfbtcge -E(0x5a, 0x50, MASK_VAL(2, 2, 0x1)), //vlv.usb.xhci.controller.xhclkgten.ssltcge -E(0x5a, 0x50, MASK_VAL(7, 5, 0x2)), //vlv.usb.xhci.controller.xhclkgten.sspllsue -E(0x5a, 0x50, MASK_VAL(13, 13, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcbbtcgipiso -E(0x5a, 0x50, MASK_VAL(4, 4, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcblcge -E(0x5a, 0x50, MASK_VAL(14, 14, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcftclkse -E(0x5a, 0x50, MASK_VAL(12, 12, 0x0)), //vlv.usb.xhci.controller.xhclkgten.xhchstcgu2nrwe -E(0x5a, 0x50, MASK_VAL(11, 10, 0x3)), //vlv.usb.xhci.controller.xhclkgten.xhcusb2pllsdle -E(SCORE, 0x4900, MASK_VAL(16, 16, 0x1)), //vlv.gpio.gpscore.cfio_regs_com_cfg_score_pb_config.sb_clkgaten -E(SSUS, 0x4900, MASK_VAL(16, 16, 0x1)), //vlv.gpio.gpssus.cfio_regs_com_cfg_ssus_pb_config.sb_clkgaten -E(LPSS, 0x180, MASK_VAL(1, 1, 0x1)), //vlv.lpss.iosf2ahb.pmctl.ahb_clk_gate_en -E(LPSS, 0x180, MASK_VAL(4, 4, 0x1)), //vlv.lpss.iosf2ahb.pmctl.ahb_trunk_gate_enable -E(LPSS, 0x180, MASK_VAL(0, 0, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosf_clk_gate_enable -E(LPSS, 0x180, MASK_VAL(3, 3, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosfprim_trunk_gate_enable -E(LPSS, 0x180, MASK_VAL(5, 5, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosfsb_trunk_gate_enable -E(LPSS, 0x180, MASK_VAL(2, 2, 0x1)), //vlv.lpss.iosf2ahb.pmctl.side_clk_gate_enable - //0x54, 0xfc, 31, 0, 0x0, //vlv.pcu.iosfahbep.clock_gating_control - //0x55, 0xfc, 1, 1, 0x0, //vlv.pcu.smbus.smb_config_cgc.pri_local_cgd - //0x55, 0xfc, 0, 0, 0x0, //vlv.pcu.smbus.smb_config_cgc.pri_trunk_cgd - //0x55, 0xfc, 8, 8, 0x0, //vlv.pcu.smbus.smb_config_cgc.sb_trunk_cgd -E(SCC, 0x600, MASK_VAL(31, 15, 0x5)), //vlv.scc.iosf2ocp.gen_regrw1.gen_reg_rw1 -E(SCC, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprim_trunk_gate_en -E(SCC, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprimclk_gate_en -E(SCC, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsb_trunk_gate_en -E(SCC, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsbclk_gate_en -E(SCC, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_gate_en -E(SCC, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_trunk_gate_en -E(SEC, 0x88, MASK_VAL(7, 7, 0x0)), //vlv.sec.clk_gate_dis.nfc_cg_dis -E(SEC, 0x88, MASK_VAL(1, 1, 0x0)), //vlv.sec.clk_gate_dis.prim_cg_dis -E(SEC, 0x88, MASK_VAL(2, 2, 0x0)), //vlv.sec.clk_gate_dis.prim_clkreq_dis -E(SEC, 0x88, MASK_VAL(3, 3, 0x0)), //vlv.sec.clk_gate_dis.prim_xsm_clkreq_dis -E(SEC, 0x88, MASK_VAL(4, 4, 0x0)), //vlv.sec.clk_gate_dis.sap_cg_dis -E(SEC, 0x88, MASK_VAL(6, 6, 0x0)), //vlv.sec.clk_gate_dis.sap_clkidle_dis -E(SEC, 0x88, MASK_VAL(5, 5, 0x0)), //vlv.sec.clk_gate_dis.sap_ip_cg_dis -E(SEC, 0x88, MASK_VAL(0, 0, 0x0)), //vlv.sec.clk_gate_dis.sb_cg_dis -REG_SCRIPT_END, -}; - - -static void perf_power(void *unused) -{ - printk(BIOS_DEBUG, "Applying perf/power settings.\n"); - reg_script_run(perf_power_settings); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL); diff --git a/src/soc/intel/braswell/placeholders.c b/src/soc/intel/braswell/placeholders.c index 3495c30..92ce00b 100644 --- a/src/soc/intel/braswell/placeholders.c +++ b/src/soc/intel/braswell/placeholders.c @@ -4,8 +4,5 @@ #include <device/pci_rom.h> #include <soc/acpi.h> - -void smm_init(void) {} - /* Rmodules don't like weak symbols. */ u32 map_oprom_vendev(u32 vendev) { return vendev; } diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index b305af5..2cdeaaf 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,14 +18,13 @@ * Foundation, Inc. */ -#include <stdint.h> #include <arch/io.h> #include <console/console.h> - #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> +#include <stdint.h> #if defined(__SMM__) @@ -54,7 +54,7 @@ uint16_t get_pmbase(void) } static void print_num_status_bits(int num_bits, uint32_t status, - const char *bit_names[]) + const char * const bit_names[]) { int i; @@ -71,14 +71,14 @@ static void print_num_status_bits(int num_bits, uint32_t status, } } -static void print_status_bits(uint32_t status, const char *bit_names[]) +static void print_status_bits(uint32_t status, const char * const bit_names[]) { print_num_status_bits(32, status, bit_names); } static uint32_t print_smi_status(uint32_t smi_sts) { - static const char *smi_sts_bits[] = { + static const char * const smi_sts_bits[] = { [2] = "BIOS", [4] = "SLP_SMI", [5] = "APM", @@ -163,7 +163,7 @@ static uint16_t reset_pm1_status(void) static uint16_t print_pm1_status(uint16_t pm1_sts) { - static const char *pm1_sts_bits[] = { + static const char * const pm1_sts_bits[] = { [0] = "TMROF", [5] = "GBL", [8] = "PWRBTN", @@ -196,7 +196,7 @@ void enable_pm1(uint16_t events) static uint32_t print_tco_status(uint32_t tco_sts) { - static const char *tco_sts_bits[] = { + static const char * const tco_sts_bits[] = { [3] = "TIMEOUT", [17] = "SECOND_TO", }; @@ -258,7 +258,7 @@ static uint32_t reset_gpe_status(void) static uint32_t print_gpe_sts(uint32_t gpe_sts) { - static const char *gpe_sts_bits[] = { + static const char * const gpe_sts_bits[] = { [1] = "HOTPLUG", [2] = "SWGPE", [3] = "PCIE_WAKE0", @@ -314,7 +314,7 @@ static uint32_t reset_alt_status(void) static uint32_t print_alt_sts(uint32_t alt_gpio_smi) { uint32_t alt_gpio_sts; - static const char *alt_gpio_smi_sts_bits[] = { + static const char * const alt_gpio_smi_sts_bits[] = { [0] = "SUS_GPIO_0", [1] = "SUS_GPIO_1", [2] = "SUS_GPIO_2", @@ -355,10 +355,10 @@ void clear_pmc_status(void) uint32_t prsts; uint32_t gen_pmcon1; - prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); + gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); /* Clear the status bits. The RPS field is cleared on a 0 write. */ - write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); - write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts); + write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); + write32((void *)(PMC_BASE_ADDRESS + PRSTS), prsts); } diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 95288b4..3e1e02f 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,6 +20,7 @@ #include <arch/cpu.h> #include <arch/acpi.h> +#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> @@ -27,24 +29,24 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <stdlib.h> -#include <string.h> - +#include <fsp_util.h> +#include <romstage_handoff.h> #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/msr.h> #include <soc/nvs.h> #include <soc/pattrs.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/ramstage.h> -#include <soc/iosf.h> - -/* Global PATTRS */ -DEFINE_PATTRS; +#include <soc/intel/common/ramstage.h> +#include <boardid.h> +#include <stdlib.h> #define SHOW_PATTRS 1 +struct pattrs __global_pattrs; + static void detect_num_cpus(struct pattrs *attrs) { int ecx = 0; @@ -54,8 +56,10 @@ static void detect_num_cpus(struct pattrs *attrs) leaf_b = cpuid_ext(0xb, ecx); - /* Bay Trail doesn't have hyperthreading so just determine the - * number of cores by from level type (ecx[15:8] == * 2). */ + /* + * The SOC doesn't have hyperthreading so just determine the + * number of cores by from level type (ecx[15:8] == * 2). + */ if ((leaf_b.ecx & 0xff00) == 0x0200) { attrs->num_cpus = leaf_b.ebx & 0xffff; break; @@ -73,7 +77,7 @@ static inline void fill_in_msr(msr_t *msr, int idx) } } -static const char *stepping_str[] = { +static const char * const stepping_str[] = { "A0", "A1", "B0", "B1", "B2", "B3", "C0" }; @@ -103,7 +107,7 @@ static void fill_in_pattrs(void) detect_num_cpus(attrs); if (SHOW_PATTRS) { - printk(BIOS_DEBUG, "BYT: cpuid %08x cpus %d rid %02x step %s\n", + printk(BIOS_DEBUG, "Cpuid %08x cpus %d rid %02x step %s\n", attrs->cpuid, attrs->num_cpus, attrs->revid, (attrs->stepping >= ARRAY_SIZE(stepping_str)) ? "??" : stepping_str[attrs->stepping]); @@ -113,22 +117,29 @@ static void fill_in_pattrs(void) fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); /* Set IA core speed ratio and voltages */ - msr = rdmsr(MSR_IACORE_RATIOS); + fill_in_msr(&msr, MSR_IACORE_RATIOS); attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f; attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f; - msr = rdmsr(MSR_IACORE_TURBO_RATIOS); + fill_in_msr(&msr, MSR_IACORE_TURBO_RATIOS); attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ - msr = rdmsr(MSR_IACORE_VIDS); + fill_in_msr(&msr, MSR_IACORE_VIDS); attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f; attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f; - msr = rdmsr(MSR_IACORE_TURBO_VIDS); + fill_in_msr(&msr, MSR_IACORE_TURBO_VIDS); attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ /* Set bus clock speed */ - attrs->bclk_khz = bus_freq_khz(); + attrs->bclk_khz = BUS_FREQ_KHZ; +} + +static inline void set_acpi_sleep_type(int val) +{ +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + acpi_slp_type = val; +#endif } /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ @@ -160,47 +171,52 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) static void s3_resume_prepare(void) { global_nvs_t *gnvs; + struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (gnvs == NULL) + + romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { + if (gnvs != NULL) + memset(gnvs, 0, sizeof(global_nvs_t)); + set_acpi_sleep_type(0); return; + } + + set_acpi_sleep_type(3); - if (!acpi_is_wakeup_s3()) - memset(gnvs, 0, sizeof(global_nvs_t)); - else - s3_save_acpi_wake_source(gnvs); + s3_save_acpi_wake_source(gnvs); } -static void baytrail_enable_2x_refresh_rate(void) +static void set_board_id(void) { - u32 reg; - reg = iosf_dunit_read(0x8); - reg = reg & ~0x7000; - reg = reg | 0x2000; - iosf_dunit_write(0x8, reg); + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + gnvs->bdid = board_id(); } -void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) +void soc_init_pre_device(struct soc_intel_braswell_config *config) { struct soc_gpio_config *gpio_config; fill_in_pattrs(); - if (!config->disable_ddr_2x_refresh_rate) - baytrail_enable_2x_refresh_rate(); - /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); /* Indicate S3 resume to rest of ramstage. */ s3_resume_prepare(); - /* Run reference code. */ - baytrail_run_reference_code(); + /* Perform silicon specific init. */ + intel_silicon_init(); + set_board_id(); /* Get GPIO initial states from mainboard */ gpio_config = mainboard_get_gpios(); setup_soc_gpios(gpio_config, config->enable_xdp_tap); - - baytrail_init_scc(); } diff --git a/src/soc/intel/braswell/refcode.c b/src/soc/intel/braswell/refcode.c deleted file mode 100644 index 55901be..0000000 --- a/src/soc/intel/braswell/refcode.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <string.h> -#include <arch/acpi.h> -#include <cbmem.h> -#include <console/console.h> -#include <console/streams.h> -#include <cpu/x86/tsc.h> -#include <program_loading.h> -#include <rmodule.h> -#include <stage_cache.h> -#if IS_ENABLED(CONFIG_CHROMEOS) -#include <vendorcode/google/chromeos/vboot_handoff.h> -#endif - -#include <soc/ramstage.h> -#include <soc/efi_wrapper.h> - -static void ABI_X86 send_to_console(unsigned char b) -{ - console_tx_byte(b); -} - -static efi_wrapper_entry_t load_refcode_from_cache(void) -{ - struct prog refcode; - - printk(BIOS_DEBUG, "refcode loading from cache.\n"); - - stage_cache_load_stage(STAGE_REFCODE, &refcode); - - return (efi_wrapper_entry_t)prog_entry(&refcode); -} - -static void cache_refcode(const struct rmod_stage_load *rsl) -{ - stage_cache_add(STAGE_REFCODE, rsl->prog); -} - -#if IS_ENABLED(CONFIG_CHROMEOS) -static int load_refcode_from_vboot(struct rmod_stage_load *refcode) -{ - struct vboot_handoff *vboot_handoff; - const struct firmware_component *fwc; - struct cbfs_stage *stage; - - vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - fwc = &vboot_handoff->components[CONFIG_VBOOT_REFCODE_INDEX]; - - if (vboot_handoff == NULL || - vboot_handoff->selected_firmware == VB_SELECT_FIRMWARE_READONLY || - CONFIG_VBOOT_REFCODE_INDEX >= MAX_PARSED_FW_COMPONENTS || - fwc->size == 0 || fwc->address == 0) - return -1; - - printk(BIOS_DEBUG, "refcode loading from vboot rw area.\n"); - stage = (void *)(uintptr_t)fwc->address; - - if (rmodule_stage_load(refcode, stage)) { - printk(BIOS_DEBUG, "Error loading reference code.\n"); - return -1; - } - return 0; -} -#else -static int load_refcode_from_vboot(struct rmod_stage_load *refcode) -{ - return -1; -} -#endif - -static int load_refcode_from_cbfs(struct rmod_stage_load *refcode) -{ - printk(BIOS_DEBUG, "refcode loading from cbfs.\n"); - - if (rmodule_stage_load_from_cbfs(refcode)) { - printk(BIOS_DEBUG, "Error loading reference code.\n"); - return -1; - } - - return 0; -} - -static efi_wrapper_entry_t load_reference_code(void) -{ - struct prog prog = { - .name = CONFIG_CBFS_PREFIX "/refcode", - }; - struct rmod_stage_load refcode = { - .cbmem_id = CBMEM_ID_REFCODE, - .prog = &prog, - }; - - if (acpi_is_wakeup_s3()) { - return load_refcode_from_cache(); - } - - if (load_refcode_from_vboot(&refcode) || - load_refcode_from_cbfs(&refcode)) - return NULL; - - /* Cache loaded reference code. */ - cache_refcode(&refcode); - - return prog_entry(&prog); -} - -void baytrail_run_reference_code(void) -{ - int ret; - efi_wrapper_entry_t entry; - struct efi_wrapper_params wrp = { - .version = EFI_WRAPPER_VER, - .console_out = send_to_console, - }; - - entry = load_reference_code(); - - if (entry == NULL) - return; - - wrp.tsc_ticks_per_microsecond = tsc_freq_mhz(); - - /* Call into reference code. */ - ret = entry(&wrp); - - if (ret != 0) { - printk(BIOS_DEBUG, "Reference code returned %d\n", ret); - return; - } -} diff --git a/src/soc/intel/braswell/reset.c b/src/soc/intel/braswell/reset.c deleted file mode 100644 index 7fa65ff..0000000 --- a/src/soc/intel/braswell/reset.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <soc/pmc.h> -#include <soc/reset.h> - -void cold_reset(void) -{ - /* S0->S5->S0 trip. */ - outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); -} - -void warm_reset(void) -{ - /* PMC_PLTRST# asserted. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void soft_reset(void) -{ - /* Sends INIT# to CPU */ - outb(RST_CPU, RST_CNT); -} - -void hard_reset(void) -{ - /* Don't power cycle on hard_reset(). It's not really clear what the - * semantics should be for the meaning of hard_reset(). */ - warm_reset(); -} diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index 345037d..4149d22 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,7 +1,4 @@ -cpu_incs += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc -romstage-y += romstage.c -romstage-y += raminit.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c -romstage-y += gfx.c +romstage-y += early_spi.c romstage-y += pmc.c -romstage-y += early_spi.c \ No newline at end of file +romstage-y += romstage.c + diff --git a/src/soc/intel/braswell/romstage/cache_as_ram.inc b/src/soc/intel/braswell/romstage/cache_as_ram.inc deleted file mode 100644 index 7c6a67f..0000000 --- a/src/soc/intel/braswell/romstage/cache_as_ram.inc +++ /dev/null @@ -1,284 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> -#include <cbmem.h> - -/* The full cache-as-ram size includes the cache-as-ram portion from coreboot - * and the space used by the reference code. These 2 values combined should - * be a power of 2 because the MTRR setup assumes that. */ -#define CACHE_AS_RAM_SIZE \ - (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - -/* Cache all of CBFS just below 4GiB as Write-Protect type. */ -#define CODE_CACHE_SIZE (CONFIG_CBFS_SIZE) -#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) -#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) -#define CPU_PHYSMASK_HI ((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) - -#define NoEvictMod_MSR 0x2e0 -#define BBL_CR_CTL3_MSR 0x11e -#define MCG_CAP_MSR 0x179 - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* All CPUs need to be in Wait for SIPI state */ -wait_for_sipi: - movl (%esi), %eax - bt $12, %eax - jc wait_for_sipi - - post_code(0x21) - /* Configure the default memory type to uncacheable as well as disable - * fixed and variable range mtrrs. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - post_code(0x22) - /* Zero the variable MTRRs. */ - movl $MCG_CAP_MSR, %ecx - rdmsr - movzx %al, %ebx - /* First variable MTRR. */ - movl $0x200, %ecx - xorl %eax, %eax - xorl %edx, %edx - 1: - wrmsr - inc %ecx - dec %ebx - jnz 1b - - /* Zero out all fixed range and variable range MTRRs. */ - movl $fixed_mtrr_table, %esi - movl $((fixed_mtrr_table_end - fixed_mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx - 1: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz 1b - - post_code(0x23) - /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - post_code(0x24) - /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x25) - /* Set code caching up for romstage. */ - movl $(MTRRphysBase_MSR(1)), %ecx - movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - - movl $(MTRRphysMask_MSR(1)), %ecx - movl $(CODE_CACHE_MASK | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x26) - - /* Enable the L2 cache. */ - movl $BBL_CR_CTL3_MSR, %ecx - rdmsr - orl $0x100, %eax - wrmsr - - post_code(0x27) - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $1, %eax - wrmsr - - post_code(0x28) - - /* Clear the cache memory region. This will also fill up the cache */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - xorl %eax, %eax - rep stosl - - /* enable no evict mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $2, %eax - wrmsr - - post_code(0x29) - - /* Setup the stack. */ - movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax - movl %eax, %esp - - /* Push the initial TSC value from boot block. The low 32 bits are - * in mm0, and the high 32 bits are in mm1. */ - movd %mm1, %eax - pushl %eax - movd %mm0, %eax - pushl %eax - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - -before_romstage: - post_code(0x2a) - /* Call romstage.c main function. */ - call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. It also contains the information - * for setting up MTRRs. */ - movl %eax, %ebx - - post_code(0x2b) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x2c) - - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~MTRRdefTypeEn), %eax - wrmsr - - invd - - post_code(0x2d) - - /* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx - rdmsr - andl $~2, %eax - wrmsr - - /* Disable the no eviction mode */ - rdmsr - andl $~1, %eax - wrmsr - - post_code(0x2e) - - /* Setup stack as indicated by return value from ramstage_main(). */ - movl %ebx, %esp - - /* Get number of MTRRs. */ - popl %ebx - movl $MTRRphysBase_MSR(0), %ecx -1: - testl %ebx, %ebx - jz 1f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 1b -1: - post_code(0x2f) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x30) - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x31) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call romstage_after_car - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -/* Fixed MTRRs */ -fixed_mtrr_table: - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F -fixed_mtrr_table_end: diff --git a/src/soc/intel/braswell/romstage/early_spi.c b/src/soc/intel/braswell/romstage/early_spi.c index 773a4a2..31be1e9 100644 --- a/src/soc/intel/braswell/romstage/early_spi.c +++ b/src/soc/intel/braswell/romstage/early_spi.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. All rights reserved. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -26,16 +27,18 @@ #include <soc/romstage.h> #include <soc/spi.h> -#define SPI_CYCLE_DELAY 10 /* 10us */ -#define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */ +#define SPI_CYCLE_DELAY 10 /* 10us */ +#define SPI_CYCLE_TIMEOUT (400000 / SPI_CYCLE_DELAY) /* 400ms */ -#define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x)) -#define SPI16(x) *((volatile u16 *)(SPI_BASE_ADDRESS + x)) -#define SPI32(x) *((volatile u32 *)(SPI_BASE_ADDRESS + x)) +#define SPI8(x) (*((volatile u8 *)(SPI_BASE_ADDRESS + (x)))) +#define SPI16(x) (*((volatile u16 *)(SPI_BASE_ADDRESS + (x)))) +#define SPI32(x) (*((volatile u32 *)(SPI_BASE_ADDRESS + (x)))) -/* Minimal set of commands to read wpsr from SPI. Don't use this code outside +/* + * Minimal set of commands to read wpsr from SPI. Don't use this code outside * romstage -- it trashes the opmenu table. - * Returns 0 on success, < 0 on failure. */ + * Returns 0 on success, < 0 on failure. + */ int early_spi_read_wpsr(u8 *sr) { int timeout = SPI_CYCLE_TIMEOUT; @@ -49,7 +52,7 @@ int early_spi_read_wpsr(u8 *sr) SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO; /* Wait for error / complete status */ - while(timeout--) { + while (timeout--) { u16 status = SPI16(SSFS); if (status & FLASH_CYCLE_ERROR) { printk(BIOS_ERR, "SPI rdsr failed\n"); diff --git a/src/soc/intel/braswell/romstage/gfx.c b/src/soc/intel/braswell/romstage/gfx.c deleted file mode 100644 index 434bc9c..0000000 --- a/src/soc/intel/braswell/romstage/gfx.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <soc/gfx.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> - -void gfx_init(void) -{ - uint32_t ggc; - uint8_t msac; - const unsigned int gfx_dev = PCI_DEV(0, GFX_DEV, GFX_FUNC); - - /* The GFX device needs to set the aperture, gtt stolen size, and - * graphics stolen memory stolen size before running MRC. For now - * just hard code the defaults. Options can be added to the device - * tree if needed. */ - - ggc = pci_read_config32(gfx_dev, GGC); - msac = pci_read_config8(gfx_dev, MSAC); - - ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK); - /* 32MB GSM is not supported with <C0 stepping. */ - ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_64MB; - /* Enable VGA decoding as well. */ - ggc &= ~(GGC_VGA_DISABLE); - - msac &= ~(APERTURE_SIZE_MASK); - msac |= APERTURE_SIZE_256MB; - - pci_write_config32(gfx_dev, GGC, ggc); - pci_write_config8(gfx_dev, MSAC, msac); -} diff --git a/src/soc/intel/braswell/romstage/pmc.c b/src/soc/intel/braswell/romstage/pmc.c index ae627a6..68031f6 100644 --- a/src/soc/intel/braswell/romstage/pmc.c +++ b/src/soc/intel/braswell/romstage/pmc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,18 +18,9 @@ * Foundation, Inc. */ -#include <stddef.h> #include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> #include <soc/iomap.h> -#include <soc/iosf.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> #include <soc/romstage.h> -#include "../chip.h" void tco_disable(void) { @@ -38,44 +30,3 @@ void tco_disable(void) reg |= TCO_TMR_HALT; outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); } - -/* This sequence signals the PUNIT to start running. */ -void punit_init(void) -{ - uint32_t reg; - uint8_t rid; - const struct device *dev; - const struct soc_intel_baytrail_config *cfg = NULL; - - rid = pci_read_config8(IOSF_PCI_DEV, REVID); - dev = dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC)); - - if (dev) - cfg = dev->chip_info; - - reg = iosf_punit_read(SB_BIOS_CONFIG); - /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ - reg |= SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; - /* Configure VR low power mode for C0 and above. */ - if (rid >= RID_C_STEPPING_START && cfg != NULL && - (cfg->vnn_ps2_enable || cfg->vcc_ps2_enable)) { - printk(BIOS_DEBUG, "Enabling VR PS2 mode: "); - if (cfg->vnn_ps2_enable) { - reg |= SB_BIOS_CONFIG_PS2_EN_VNN; - printk(BIOS_DEBUG, "VNN "); - } - if (cfg->vcc_ps2_enable) { - reg |= SB_BIOS_CONFIG_PS2_EN_VCC; - printk(BIOS_DEBUG, "VCC "); - } - printk(BIOS_DEBUG, "\n"); - } - iosf_punit_write(SB_BIOS_CONFIG, reg); - - /* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */ - reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE; - pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg); - reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) | - IOSF_REG(BIOS_RESET_CPL) | IOSF_BYTE_EN_0; - pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg); -} diff --git a/src/soc/intel/braswell/romstage/raminit.c b/src/soc/intel/braswell/romstage/raminit.c deleted file mode 100644 index d4f1711..0000000 --- a/src/soc/intel/braswell/romstage/raminit.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <stddef.h> -#include <arch/io.h> -#include <bootmode.h> -#include <cbfs.h> -#include <cbmem.h> -#include <console/console.h> -#include <device/pci_def.h> -#include <halt.h> -#include <soc/gpio.h> -#include <soc/intel/common/mrc_cache.h> -#include <soc/iomap.h> -#include <soc/iosf.h> -#include <soc/pci_devs.h> -#include <soc/reset.h> -#include <soc/romstage.h> -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> - -static void reset_system(void) -{ - warm_reset(); - halt(); -} - -static void enable_smbus(void) -{ - uint32_t reg; - const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); - - /* SMBus I/O BAR */ - reg = SMBUS_BASE_ADDRESS | 2; - pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); - /* Enable decode of I/O space. */ - reg = pci_read_config16(smbus_dev, PCI_COMMAND); - reg |= 0x1; - pci_write_config16(smbus_dev, PCI_COMMAND, reg); - /* Enable Host Controller */ - reg = pci_read_config8(smbus_dev, 0x40); - reg |= 1; - pci_write_config8(smbus_dev, 0x40, reg); - - /* Configure pads to be used for SMBus */ - score_select_func(PCU_SMB_CLK_PAD, 1); - score_select_func(PCU_SMB_DATA_PAD, 1); -} - -static void ABI_X86 send_to_console(unsigned char b) -{ - do_putchar(b); -} - -static void print_dram_info(void) -{ - const int mrc_ver_reg = 0xf0; - const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); - uint32_t reg; - int num_channels; - int speed; - uint32_t ch0; - uint32_t ch1; - - reg = pci_read_config32(soc_dev, mrc_ver_reg); - - printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff); - - /* Number of channels enabled and DDR3 type. Determine number of - * channels by keying of the rank enable bits [3:0]. * */ - ch0 = iosf_dunit_ch0_read(DRP); - ch1 = iosf_dunit_ch1_read(DRP); - num_channels = 0; - if (ch0 & DRP_RANK_MASK) - num_channels++; - if (ch1 & DRP_RANK_MASK) - num_channels++; - - printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels, - (reg & (1 << 22)) ? "LP" : ""); - - /* DRAM frequency -- all channels run at same frequency. */ - reg = iosf_dunit_read(DTR0); - switch (reg & 0x3) { - case 0: - speed = 800; break; - case 1: - speed = 1066; break; - case 2: - speed = 1333; break; - case 3: - speed = 1600; break; - } - printk(BIOS_INFO, "%dMHz\n", speed); -} - -void raminit(struct mrc_params *mp, int prev_sleep_state) -{ - int ret; - mrc_wrapper_entry_t mrc_entry; - const struct mrc_saved_data *cache; - - /* Fill in default entries. */ - mp->version = MRC_PARAMS_VER; - mp->console_out = &send_to_console; - mp->prev_sleep_state = prev_sleep_state; - mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); - - /* Default to 2GiB IO hole. */ - if (!mp->io_hole_mb) - mp->io_hole_mb = 2048; - - if (recovery_mode_enabled()) { - printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (!mrc_cache_get_current(&cache)) { - mp->saved_data_size = cache->size; - mp->saved_data = &cache->data[0]; - } else if (prev_sleep_state == 3) { - /* If waking from S3 and no cache then. */ - printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); - reset_system(); - } else { - printk(BIOS_DEBUG, "No MRC cache found.\n"); -#if CONFIG_EC_GOOGLE_CHROMEEC - if (prev_sleep_state == 0) { - /* Ensure EC is running RO firmware. */ - google_chromeec_check_ec_image(EC_IMAGE_RO); - } -#endif - } - - /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL) == NULL) { - printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); - return; - } - - /* - * The entry point is currently the first instruction. Handle the - * case of an ELF file being put in the cbfs by setting the entry - * to the CONFIG_MRC_BIN_ADDRESS. - */ - mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS; - - if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) - enable_smbus(); - - ret = mrc_entry(mp); - - print_dram_info(); - - if (prev_sleep_state != 3) { - cbmem_initialize_empty(); - } else if (cbmem_initialize()) { - #if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); - /* Failed S3 resume, reset to come up cleanly */ - reset_system(); - #endif - } - - printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, - mp->data_to_save_size); - - if (mp->data_to_save != NULL && mp->data_to_save_size > 0) - mrc_cache_stash_data(mp->data_to_save, mp->data_to_save_size); -} diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 67716d4..df6efd8 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,45 +18,41 @@ * Foundation, Inc. */ +#include <cbmem.h> #include <stddef.h> +#include <arch/early_variables.h> #include <arch/cpu.h> #include <arch/io.h> +#include <arch/cbfs.h> #include <arch/stages.h> -#include <arch/early_variables.h> -#include <console/console.h> -#include <cbfs.h> #include <cbmem.h> +#include <chip.h> #include <cpu/x86/mtrr.h> -#if CONFIG_EC_GOOGLE_CHROMEEC +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> #endif #include <elog.h> #include <romstage_handoff.h> -#include <stage_cache.h> #include <timestamp.h> +#include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <fsp_util.h> +#include <soc/intel/common/mrc_cache.h> #include <soc/gpio.h> #include <soc/iomap.h> +#include <soc/iosf.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> -#include <soc/reset.h> #include <soc/romstage.h> #include <soc/smm.h> #include <soc/spi.h> #include <tpm.h> -/* The cache-as-ram assembly file calls romstage_main() after setting up - * cache-as-ram. romstage_main() will then call the mainboards's - * mainboard_romstage_entry() function. That function then calls - * romstage_common() below. The reason for the back and forth is to provide - * common entry point from cache-as-ram while still allowing for code sharing. - * Because we can't use global variables the stack is used for allocations -- - * thus the need to call back and forth. */ - -static void *setup_stack_and_mttrs(void); - -static void program_base_addresses(void) +void program_base_addresses(void) { uint32_t reg; const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); @@ -85,8 +82,8 @@ static void program_base_addresses(void) static void spi_init(void) { - u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + void *scs = (void *)(SPI_BASE_ADDRESS + SCS); + void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); uint32_t reg; /* Disable generating SMI when setting WPD bit. */ @@ -100,51 +97,9 @@ static void spi_init(void) write32(bcr, reg); } -/* Entry from cache-as-ram.inc. */ -void * asmlinkage romstage_main(unsigned long bist, - uint32_t tsc_low, uint32_t tsc_hi) -{ - struct romstage_params rp = { - .bist = bist, - .mrc_params = NULL, - }; - - /* Save initial timestamp from bootblock. */ - timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - - program_base_addresses(); - - tco_disable(); - - byt_config_com1_and_enable(); - - console_init(); - - spi_init(); - - set_max_freq(); - - punit_init(); - - gfx_init(); - -#if CONFIG_EC_GOOGLE_CHROMEEC - /* Ensure the EC is in the right mode for recovery */ - google_chromeec_early_init(); -#endif - - /* Call into mainboard. */ - mainboard_romstage_entry(&rp); - - return setup_stack_and_mttrs(); -} - static struct chipset_power_state power_state CAR_GLOBAL; -static void migrate_power_state(void) +static void migrate_power_state(int is_recovery) { struct chipset_power_state *ps_cbmem; struct chipset_power_state *ps_car; @@ -158,9 +113,9 @@ static void migrate_power_state(void) } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -CAR_MIGRATE(migrate_power_state); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); -static struct chipset_power_state *fill_power_state(void) +struct chipset_power_state *fill_power_state(void) { struct chipset_power_state *ps = car_get_var_ptr(&power_state); @@ -170,9 +125,11 @@ static struct chipset_power_state *fill_power_state(void) ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); - ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); - ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2)); + ps->prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); + ps->gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + ps->gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)); + + ps->prev_sleep_state = chipset_prev_sleep_state(ps); printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); @@ -180,193 +137,116 @@ static struct chipset_power_state *fill_power_state(void) ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); - + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps; } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -static int chipset_prev_sleep_state(struct chipset_power_state *ps) +int chipset_prev_sleep_state(struct chipset_power_state *ps) { /* Default to S0. */ - int prev_sleep_state = 0; + int prev_sleep_state = SLEEP_STATE_S0; if (ps->pm1_sts & WAK_STS) { switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { - #if CONFIG_HAVE_ACPI_RESUME + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) case SLP_TYP_S3: - prev_sleep_state = 3; + prev_sleep_state = SLEEP_STATE_S3; break; #endif case SLP_TYP_S5: - prev_sleep_state = 5; + prev_sleep_state = SLEEP_STATE_S5; break; } + /* Clear SLP_TYP. */ outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); } - if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { - prev_sleep_state = 5; - } + if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = SLEEP_STATE_S5; return prev_sleep_state; } -/* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) -{ - struct romstage_handoff *handoff; - struct chipset_power_state *ps; - int prev_sleep_state; - - timestamp_add_now(TS_BEFORE_INITRAM); - - ps = fill_power_state(); - prev_sleep_state = chipset_prev_sleep_state(ps); - - printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); - -#if CONFIG_ELOG_BOOT_COUNT - if (prev_sleep_state != 3) - boot_count_increment(); -#endif - - - /* Initialize RAM */ - raminit(params->mrc_params, prev_sleep_state); - - timestamp_add_now(TS_AFTER_INITRAM); - - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = (prev_sleep_state == 3); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - - if (CONFIG_LPC_TPM) { - init_tpm(prev_sleep_state == 3); - } -} - -void asmlinkage romstage_after_car(void) -{ - timestamp_add_now(TS_END_ROMSTAGE); - - /* Load the ramstage. */ - copy_and_run(); - while (1); -} - -static inline uint32_t *stack_push(u32 *stack, u32 value) +/* SOC initialization before the console is enabled */ +void soc_pre_console_init(struct romstage_params *params) { - stack = &stack[-1]; - *stack = value; - return stack; + /* Early chipset initialization */ + program_base_addresses(); + tco_disable(); } -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -static unsigned long choose_top_of_stack(void) +/* SOC initialization after console is enabled */ +void soc_romstage_init(struct romstage_params *params) { - unsigned long stack_top; - const unsigned long romstage_ram_stack_size = 0x5000; + /* Continue chipset initialization */ + spi_init(); - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Ensure the EC is in the right mode for recovery */ + google_chromeec_early_init(); +#endif } -/* setup_stack_and_mttrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void *setup_stack_and_mttrs(void) +/* SOC initialization after RAM is enabled */ +void soc_after_ram_init(struct romstage_params *params) { - unsigned long top_of_stack; - int num_mtrrs; - uint32_t *slot; - uint32_t mtrr_mask_upper; - uint32_t top_of_ram; - - /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; - slot = (void *)top_of_stack; - num_mtrrs = 0; + u32 value; - /* The upper bits of the MTRR mask need to set according to the number - * of physical address bits. */ - mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; - - /* The order for each MTRR is value then base with upper 32-bits of - * each value coming before the lower 32-bits. The reasoning for - * this ordering is to create a stack layout like the following: - * +0: Number of MTRRs - * +4: MTRR base 0 31:0 - * +8: MTRR base 0 63:32 - * +12: MTRR mask 0 31:0 - * +16: MTRR mask 0 63:32 - * +20: MTRR base 1 31:0 - * +24: MTRR base 1 63:32 - * +28: MTRR mask 1 31:0 - * +32: MTRR mask 1 63:32 - */ - - /* Cache the ROM as WP just below 4GiB. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); - num_mtrrs++; - - /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); - num_mtrrs++; - - top_of_ram = (uint32_t)cbmem_top(); - /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the - * start of the TSEG region. It is required to be 8MiB aligned. Set - * this area as cacheable so it can be used later for ramstage before - * setting up the entire RAM as cacheable. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); - num_mtrrs++; - - /* Cache 8MiB at the top of ram. Top of ram is where the TSEG - * region resides. However, it is not restricted to SMM mode until - * SMM has been relocated. By setting the region to cacheable it - * provides faster access when relocating the SMM handler as well - * as using the TSEG region for other purposes. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); - num_mtrrs++; - - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. */ - slot = stack_push(slot, num_mtrrs); - - return slot; + /* Make sure that E0000 and F0000 are RAM */ + printk(BIOS_DEBUG, "Disable ROM shadow below 1MB.\n"); + value = iosf_bunit_read(BUNIT_BMISC); + value |= 3; + iosf_bunit_write(BUNIT_BMISC, value); } -void ramstage_cache_invalid(void) +/* Initialize the UPD parameters for MemoryInit */ +void soc_memory_init_params(MEMORY_INIT_UPD *params) { -#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE - /* Perform cold reset on invalid ramstage cache. */ - cold_reset(); -#endif + const struct device *dev; + const struct soc_intel_braswell_config *config; + + /* Set the parameters for MemoryInit */ + dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + config = dev->chip_info; + printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); + params->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->PcdMrcInitTsegSize : 0; + params->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; + params->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; + params->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; + params->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc; + params->PcdApertureSize = config->PcdApertureSize; + params->PcdGttSize = config->PcdGttSize; + params->PcdLegacySegDecode = config->PcdLegacySegDecode; } -#if CONFIG_CHROMEOS -int vboot_get_sw_write_protect(void) +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, + MEMORY_INIT_UPD *new) { - u8 status; - /* Return unprotected status if status read fails. */ - return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80)); + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + soc_display_upd_value("PcdMrcInitTsegSize", 2, + old->PcdMrcInitTsegSize, new->PcdMrcInitTsegSize); + soc_display_upd_value("PcdMrcInitMmioSize", 2, + old->PcdMrcInitMmioSize, new->PcdMrcInitMmioSize); + soc_display_upd_value("PcdMrcInitSpdAddr1", 1, + old->PcdMrcInitSpdAddr1, new->PcdMrcInitSpdAddr1); + soc_display_upd_value("PcdMrcInitSpdAddr2", 1, + old->PcdMrcInitSpdAddr2, new->PcdMrcInitSpdAddr2); + soc_display_upd_value("PcdMemChannel0Config", 1, + old->PcdMemChannel0Config, new->PcdMemChannel0Config); + soc_display_upd_value("PcdMemChannel1Config", 1, + old->PcdMemChannel1Config, new->PcdMemChannel1Config); + soc_display_upd_value("PcdMemorySpdPtr", 4, + old->PcdMemorySpdPtr, new->PcdMemorySpdPtr); + soc_display_upd_value("PcdIgdDvmt50PreAlloc", 1, + old->PcdIgdDvmt50PreAlloc, new->PcdIgdDvmt50PreAlloc); + soc_display_upd_value("PcdApertureSize", 1, + old->PcdApertureSize, new->PcdApertureSize); + soc_display_upd_value("PcdGttSize", 1, + old->PcdGttSize, new->PcdGttSize); + soc_display_upd_value("PcdLegacySegDecode", 1, + old->PcdLegacySegDecode, new->PcdLegacySegDecode); } -#endif diff --git a/src/soc/intel/braswell/romstage/uart.c b/src/soc/intel/braswell/romstage/uart.c deleted file mode 100644 index 3677608..0000000 --- a/src/soc/intel/braswell/romstage/uart.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> - -void byt_config_com1_and_enable(void) -{ - uint32_t reg; - - /* Enable the UART hardware for COM1. */ - reg = 1; - pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); - - /* Set up the pads to select the UART function */ - score_select_func(UART_RXD_PAD, 1); - score_select_func(UART_TXD_PAD, 1); -} diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c index 6906b7f..00b651e 100644 --- a/src/soc/intel/braswell/sata.c +++ b/src/soc/intel/braswell/sata.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,192 +30,17 @@ #include "chip.h" -typedef struct soc_intel_baytrail_config config_t; - -static inline void sir_write(struct device *dev, int idx, u32 value) -{ - pci_write_config32(dev, SATA_SIRI, idx); - pci_write_config32(dev, SATA_SIRD, value); -} +typedef struct soc_intel_braswell_config config_t; static void sata_init(struct device *dev) { - config_t *config = dev->chip_info; - u32 reg32; - u16 reg16; - u8 reg8; - - printk(BIOS_DEBUG, "SATA: Initializing...\n"); - - if (config == NULL) { - printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); - return; - } - - if (!config->sata_ahci) { - /* Set legacy or native decoding mode */ - if (config->ide_legacy_combined) { - reg8 = pci_read_config8(dev, 0x09); - reg8 &= ~0x5; - pci_write_config8(dev, 0x09, reg8); - } else { - reg8 = pci_read_config8(dev, 0x09); - reg8 |= 0x5; - pci_write_config8(dev, 0x09, reg8); - } - - /* Set capabilities pointer */ - pci_write_config8(dev, 0x34, 0x70); - reg16 = pci_read_config16(dev, 0x70); - reg16 &= ~0xFF00; - pci_write_config16(dev, 0x70, reg16); - } - - /* Primary timing - decode enable */ - reg16 = pci_read_config16(dev, 0x40); - reg16 |= 1 << 15; - pci_write_config16(dev, 0x40, reg16); - - /* Secondary timing - decode enable */ - reg16 = pci_read_config16(dev, 0x42); - reg16 |= 1 << 15; - pci_write_config16(dev, 0x42, reg16); - - /* Port mapping enables */ - reg16 = pci_read_config16(dev, 0x90); - reg16 |= (config->sata_port_map ^ 0x3) << 8; - pci_write_config16(dev, 0x90, reg16); - - /* Port control enables */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x003f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - if (config->sata_ahci) { - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - - /* Enable CR memory space decoding */ - reg16 = pci_read_config16(dev, 0x04); - reg16 |= 0x2; - pci_write_config16(dev, 0x04, reg16); - - /* Set capability register */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM - reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits - reg32 |= (0x3 << 20); // Gen3 SATA - write32(abar + 0x00, reg32); - - /* Ports enabled */ - reg32 = read32(abar + 0x0c); - reg32 &= (u32)(~0x3f); - reg32 |= config->sata_port_map; - write32(abar + 0xc, reg32); - /* Two extra reads to latch */ - read32(abar + 0x0c); - read32(abar + 0x0c); - - /* Set cap2 - Support devslp */ - reg32 = (1 << 5) | (1 << 4) | (1 << 3); - write32(abar + 0x24, reg32); - - /* Set PxCMD registers */ - reg32 = read32(abar + 0x118); - reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | - (1 << 19) | (1 << 18) | (1 << 1)); - reg32 |= 2; - write32(abar + 0x118, reg32); - - reg32 = read32(abar + 0x198); - reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | - (1 << 19) | (1 << 18) | (1 << 1)); - reg32 |= 2; - write32(abar + 0x198, reg32); - - /* Clear reset features */ - write32(abar + 0xc8, 0); - - /* Enable interrupts */ - reg8 = read8(abar + 0x04); - reg8 |= 0x02; - write8(abar + 0x04, reg8); - - } else { - /* TODO(shawnn): Configure IDE SATA speed regs */ - } - - /* 1.4 us delay after configuring port / enable bits */ - udelay(2); - - /* Enable clock for ports */ - reg32 = pci_read_config32(dev, 0x94); - reg32 |= 0x3f << 24; - pci_write_config32(dev, 0x94, reg32); - reg32 &= (config->sata_port_map ^ 0x3) << 24; - pci_write_config32(dev, 0x94, reg32); - - /* Lock SataGc register */ - reg32 = (0x1 << 31) | (0x7 << 12); - pci_write_config32(dev, 0x98, reg32); + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); } static void sata_enable(device_t dev) { - config_t *config = dev->chip_info; - u8 reg8; - u16 reg16; - u32 reg32; - southcluster_enable_dev(dev); - if (!config) - return; - - /* Port mapping -- mask off SPD + SMS + SC bits, then re-set */ - reg16 = pci_read_config16(dev, 0x90); - reg16 &= ~0x03e0; - reg16 |= (config->sata_port_map ^ 0x3) << 8; - if(config->sata_ahci) - reg16 |= 0x60; - pci_write_config16(dev, 0x90, reg16); - - /* Set reg 0x94 before starting configuration */ - reg32 = pci_read_config32(dev, 0x94); - reg32 &= (u32)(~0x1ff); - reg32 |= 0x183; - pci_write_config32(dev, 0x94, reg32); - - /* Set ORM bit */ - reg16 = pci_read_config16(dev, 0x92); - reg16 |= (1 << 15); - pci_write_config16(dev, 0x92, reg16); - - /* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */ - reg32 = pci_read_config32(dev, 0x98); - reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5)); - reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) | - (1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5); - pci_write_config32(dev, 0x98, reg32); - - /* CMD reg - set bus master enable (BME) */ - reg8 = pci_read_config8(dev, 0x04); - reg8 |= (1 << 2); - pci_write_config8(dev, 0x04, reg8); - - /* "Test mode registers" */ - sir_write(dev, 0x70, 0x00288301); - sir_write(dev, 0x54, 0x00000300); - sir_write(dev, 0x58, 0x50000000); - /* "OOB Detection Margin */ - sir_write(dev, 0x6c, 0x130C0603); - /* "Gasket Control" */ - sir_write(dev, 0xf4, 0); - - /* PCS - Enable requested SATA ports */ - reg8 = pci_read_config8(dev, 0x92); - reg8 &= ~0x03; - reg8 |= config->sata_port_map; - pci_write_config8(dev, 0x92, reg8); } static struct device_operations sata_ops = { @@ -223,17 +49,15 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; static const unsigned short pci_device_ids[] = { - IDE1_DEVID, IDE2_DEVID, /* IDE */ - AHCI1_DEVID, AHCI2_DEVID, /* AHCI */ + AHCI1_DEVID, /* AHCI */ 0, }; -static const struct pci_driver baytrail_sata __pci_driver = { +static const struct pci_driver soc_sata __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index c9aca51..b562865 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,86 +24,20 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <reg_script.h> - #include <soc/iosf.h> #include <soc/nvs.h> #include <soc/ramstage.h> -static const struct reg_script scc_start_dll[] = { - /* Configure master DLL. */ - REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4964, 0x00078000), - /* Configure Swing,FSM for Master DLL */ - REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00000133), - /* Run+Local Reset on Master DLL */ - REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00001933), - REG_SCRIPT_END, -}; - -static const struct reg_script scc_after_dll[] = { - /* Configure Write Path */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4954, ~0x7fff, 0x35ad), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4958, ~0x7fff, 0x35ad), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x495c, ~0x7fff, 0x35ad), - /* Configure Read Path */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x43e4, ~0x7fff, 0x35ad), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4324, ~0x7fff, 0x35ad), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x42b4, ~0x7fff, 0x35ad), - /* eMMC 4.5 TX and RX DLL */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a4, ~0x1f001f, 0xa000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a8, ~0x1f001f, 0xd000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49ac, ~0x1f001f, 0xd000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b0, ~0x1f001f, 0xd000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b4, ~0x1f001f, 0xd000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b8, ~0x1, 0x0), - /* cfio_regs_mmc1_ELECTRICAL.nslew/pslew */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x0), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x0), - /* - * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_ocp = 01 - * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_xin = 01 - */ - REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0xf, 0x5), - /* Enable IOSF Snoop */ - REG_IOSF_OR(IOSF_PORT_SCC, 0x00, (1 << 7)), - /* SDIO 3V Support. */ - REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0x30, 0x30), - REG_SCRIPT_END, -}; - -void baytrail_init_scc(void) -{ - uint32_t dll_values; - - printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n"); - - /* Common Sideband Initialization for SCC */ - reg_script_run(scc_start_dll); - - /* Override Slave Path - populate DLL settings. */ - dll_values = iosf_score_read(0x496c) & 0x7ffff; - dll_values |= iosf_score_read(0x4950) & ~0xfffff; - iosf_score_write(0x4950, dll_values | (1 << 19)); - - reg_script_run(scc_after_dll); -} - void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) { - struct reg_script ops[] = { - /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), - /* Enable ACPI mode */ - REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, - SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN), - REG_SCRIPT_END - }; struct resource *bar; global_nvs_t *gnvs; + printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x )\n", + __FILE__, __func__, dev_name(dev), iosf_reg, nvs_index); + /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { printk(BIOS_ERR, "Unable to locate Global NVS\n"); return; @@ -113,13 +48,6 @@ void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) if (bar) gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base; - bar = find_resource(dev, PCI_BASE_ADDRESS_1); - if (bar) - gnvs->dev.scc_bar1[nvs_index] = (u32)bar->base; - /* Device is enabled in ACPI mode */ gnvs->dev.scc_en[nvs_index] = 1; - - /* Put device in ACPI mode */ - reg_script_run_on_dev(dev, ops); } diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c index d3e28a8..1fb7e9f 100644 --- a/src/soc/intel/braswell/sd.c +++ b/src/soc/intel/braswell/sd.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,7 +37,10 @@ static void sd_init(device_t dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; + + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); if (config == NULL) return; @@ -44,12 +48,12 @@ static void sd_init(device_t dev) if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) { printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n"); pci_write_config32(dev, CAP_OVERRIDE_LOW, - config->sdcard_cap_low); + config->sdcard_cap_low); pci_write_config32(dev, CAP_OVERRIDE_HIGH, - config->sdcard_cap_high | USE_CAP_OVERRIDES); + config->sdcard_cap_high | USE_CAP_OVERRIDES); } - if (config->scc_acpi_mode) + if (config->sd_acpi_mode) scc_enable_acpi_mode(dev, SCC_SD_CTL, SCC_NVS_SD); } @@ -58,8 +62,6 @@ static const struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sd_init, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index b8eaa6d..eb8ee63 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,21 +18,20 @@ * Foundation, Inc. */ -#include <stdint.h> -#include <stdlib.h> +#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <elog.h> -#include <halt.h> -#include <spi-generic.h> - -#include <soc/iosf.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> #include <soc/nvs.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <spi-generic.h> +#include <stdint.h> +#include <stdlib.h> +#include <soc/gpio.h> /* GNVS needs to be set by coreboot initiating a software SMI. */ static global_nvs_t *gnvs; @@ -42,7 +42,8 @@ int southbridge_io_trap_handler(int smif) switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* + * gnvs->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ @@ -99,6 +100,36 @@ static void busmaster_disable_on_bus(int bus) } } +static void tristate_gpios(uint32_t val) +{ + /* Tri-state eMMC */ + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + + SDMMC1_CMD_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + + SDMMC1_D0_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + + SDMMC1_D1_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + + SDMMC1_D2_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + + SDMMC1_D3_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + + MMC1_D4_SD_WE_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + + MMC1_D5_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + + MMC1_D6_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + + MMC1_D7_MMIO_OFFSET, val); + + /* Tri-state HDMI */ + write32((void *)COMMUNITY_GPNORTH_BASE + + HV_DDI2_DDC_SDA_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPNORTH_BASE + + HV_DDI2_DDC_SCL_MMIO_OFFSET, val); +} + + static void southbridge_smi_sleep(void) { uint32_t reg32; @@ -116,14 +147,15 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ-2); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= 5) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); #endif + /* Clear pending GPE events */ + clear_gpe_status(); - /* Next, do the deed. - */ + /* Next, do the deed. */ switch (slp_typ) { case SLP_TYP_S0: @@ -154,8 +186,16 @@ static void southbridge_smi_sleep(void) printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; } + /* Clear pending wake status bit to avoid immediate wake */ + write32((void *)(0xfed88000 + 0x0200), + read32((void *)(0xfed88000 + 0x0200))); + + /* Tri-state specific GPIOS to avoid leakage during S3/S5 */ + if ((slp_typ == SLP_TYP_S3) || (slp_typ == SLP_TYP_S5)) + tristate_gpios(PAD_CONTROL_REG0_TRISTATE); - /* Write back to the SLP register to cause the originally intended + /* + * Write back to the SLP register to cause the originally intended * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ @@ -163,9 +203,10 @@ static void southbridge_smi_sleep(void) /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) - halt(); + hlt(); - /* In most sleep states, the code flow of this function ends at + /* + * In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ @@ -212,7 +253,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -224,11 +265,11 @@ static void southbridge_smi_gsmi(void) return; /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; + ret = (u32 *)&io_smi->rax; sub_command = (uint8_t)(*ret >> 8); /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + param = (u32 *)&io_smi->rbx; /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); @@ -245,66 +286,12 @@ static void finalize(void) } finalize_done = 1; -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif } -/* - * soc_legacy: A payload (Depthcharge) has indicated that the - * legacy payload (SeaBIOS) is being loaded. Switch devices that are - * in ACPI mode to PCI mode so that non-ACPI drivers may work. - * - */ -static void soc_legacy(void) -{ - u32 reg32; - - /* LPE Device */ - if (gnvs->dev.lpe_en) { - reg32 = iosf_port58_read(LPE_PCICFGCTR1); - reg32 &= - ~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN); - iosf_port58_write(LPE_PCICFGCTR1, reg32); - } - - /* SCC Devices */ -#define SCC_ACPI_MODE_DISABLE(name_) \ - do { if (gnvs->dev.scc_en[SCC_NVS_ ## name_]) { \ - reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \ - reg32 &= ~(SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \ - iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \ - } } while (0) - - SCC_ACPI_MODE_DISABLE(MMC); - SCC_ACPI_MODE_DISABLE(SD); - SCC_ACPI_MODE_DISABLE(SDIO); - - /* LPSS Devices */ -#define LPSS_ACPI_MODE_DISABLE(name_) \ - do { if (gnvs->dev.lpss_en[LPSS_NVS_ ## name_]) { \ - reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \ - reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \ - iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \ - } } while (0) - - LPSS_ACPI_MODE_DISABLE(SIO_DMA1); - LPSS_ACPI_MODE_DISABLE(I2C1); - LPSS_ACPI_MODE_DISABLE(I2C2); - LPSS_ACPI_MODE_DISABLE(I2C3); - LPSS_ACPI_MODE_DISABLE(I2C4); - LPSS_ACPI_MODE_DISABLE(I2C5); - LPSS_ACPI_MODE_DISABLE(I2C6); - LPSS_ACPI_MODE_DISABLE(I2C7); - LPSS_ACPI_MODE_DISABLE(SIO_DMA2); - LPSS_ACPI_MODE_DISABLE(PWM1); - LPSS_ACPI_MODE_DISABLE(PWM2); - LPSS_ACPI_MODE_DISABLE(HSUART1); - LPSS_ACPI_MODE_DISABLE(HSUART2); - LPSS_ACPI_MODE_DISABLE(SPI); -} - static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -315,14 +302,16 @@ static void southbridge_smi_apmc(void) reg8 = inb(APM_CNT); switch (reg8) { case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause + /* + * Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ printk(BIOS_DEBUG, "C-state control\n"); break; case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause + /* + * Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ @@ -350,7 +339,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -358,10 +347,6 @@ static void southbridge_smi_apmc(void) case APM_CNT_FINALIZE: finalize(); break; - - case APM_CNT_LEGACY: - soc_legacy(); - break; } mainboard_smi_apmc(reg8); @@ -371,12 +356,13 @@ static void southbridge_smi_pm1(void) { uint16_t pm1_sts = clear_pm1_status(); - /* While OSPM is not active, poweroff immediately + /* + * While OSPM is not active, poweroff immediately * on a power button event. */ if (pm1_sts & PWRBTN_STS) { - // power button pressed -#if CONFIG_ELOG_GSMI + /* power button pressed */ +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); @@ -419,38 +405,38 @@ static void southbridge_smi_periodic(void) typedef void (*smi_handler_t)(void); static const smi_handler_t southbridge_smi[32] = { - NULL, // [0] reserved - NULL, // [1] reserved - NULL, // [2] BIOS_STS - NULL, // [3] LEGACY_USB_STS - southbridge_smi_sleep, // [4] SLP_SMI_STS - southbridge_smi_apmc, // [5] APM_STS - NULL, // [6] SWSMI_TMR_STS - NULL, // [7] reserved - southbridge_smi_pm1, // [8] PM1_STS - southbridge_smi_gpe0, // [9] GPE0_STS - NULL, // [10] reserved - NULL, // [11] reserved - NULL, // [12] reserved - southbridge_smi_tco, // [13] TCO_STS - southbridge_smi_periodic, // [14] PERIODIC_STS - NULL, // [15] SERIRQ_SMI_STS - NULL, // [16] SMBUS_SMI_STS - NULL, // [17] LEGACY_USB2_STS - NULL, // [18] INTEL_USB2_STS - NULL, // [19] reserved - NULL, // [20] PCI_EXP_SMI_STS - NULL, // [21] reserved - NULL, // [22] reserved - NULL, // [23] reserved - NULL, // [24] reserved - NULL, // [25] reserved - NULL, // [26] SPI_STS - NULL, // [27] reserved - NULL, // [28] PUNIT - NULL, // [29] GUNIT - NULL, // [30] reserved - NULL // [31] reserved + NULL, /* [0] reserved */ + NULL, /* [1] reserved */ + NULL, /* [2] BIOS_STS */ + NULL, /* [3] LEGACY_USB_STS */ + southbridge_smi_sleep, /* [4] SLP_SMI_STS */ + southbridge_smi_apmc, /* [5] APM_STS */ + NULL, /* [6] SWSMI_TMR_STS */ + NULL, /* [7] reserved */ + southbridge_smi_pm1, /* [8] PM1_STS */ + southbridge_smi_gpe0, /* [9] GPE0_STS */ + NULL, /* [10] reserved */ + NULL, /* [11] reserved */ + NULL, /* [12] reserved */ + southbridge_smi_tco, /* [13] TCO_STS */ + southbridge_smi_periodic, /* [14] PERIODIC_STS */ + NULL, /* [15] SERIRQ_SMI_STS */ + NULL, /* [16] SMBUS_SMI_STS */ + NULL, /* [17] LEGACY_USB2_STS */ + NULL, /* [18] INTEL_USB2_STS */ + NULL, /* [19] reserved */ + NULL, /* [20] PCI_EXP_SMI_STS */ + NULL, /* [21] reserved */ + NULL, /* [22] reserved */ + NULL, /* [23] reserved */ + NULL, /* [24] reserved */ + NULL, /* [25] reserved */ + NULL, /* [26] SPI_STS */ + NULL, /* [27] reserved */ + NULL, /* [28] PUNIT */ + NULL, /* [29] GUNIT */ + NULL, /* [30] reserved */ + NULL /* [31] reserved */ }; void southbridge_smi_handler(void) @@ -458,7 +444,8 @@ void southbridge_smi_handler(void) int i; uint32_t smi_sts; - /* We need to clear the SMI status registers, or we won't see what's + /* + * We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ smi_sts = clear_smi_status(); @@ -472,12 +459,14 @@ void southbridge_smi_handler(void) southbridge_smi[i](); } else { printk(BIOS_DEBUG, - "SMI_STS[%d] occurred, but no " + "SMI_STS[%d] occured, but no " "handler available.\n", i); } } - /* The GPIO SMI events do not have a status bit in SMI_STS. Therefore, - * these events need to be cleared and checked unconditionally. */ + /* + * The GPIO SMI events do not have a status bit in SMI_STS. Therefore, + * these events need to be cleared and checked unconditionally. + */ mainboard_smi_gpi(clear_alt_status()); } diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index e75bfb2..876ec36 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -18,21 +19,24 @@ * Foundation, Inc. */ -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> #include <arch/io.h> +#include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/smm.h> -#include <string.h> - +#include <device/device.h> +#include <device/pci.h> #include <soc/iomap.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/smm.h> +#include <string.h> /* Save settings which will be committed in SMI functions. */ static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT]; +void smm_init(void) +{ +} + void southcluster_smm_save_param(int param, uint32_t data) { smm_save_params[param] = data; @@ -65,7 +69,7 @@ void southcluster_smm_clear_state(void) static void southcluster_smm_route_gpios(void) { - u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT); + void *gpio_rout = (void *)(PMC_BASE_ADDRESS + GPIO_ROUT); const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; uint32_t alt_gpio_reg = 0; uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE]; @@ -78,9 +82,8 @@ static void southcluster_smm_route_gpios(void) /* Enable SMIs for the gpios that are set to trigger the SMI. */ for (i = 0; i < 16; i++) { - if ((route_reg & ROUTE_MASK) == ROUTE_SMI) { + if ((route_reg & ROUTE_MASK) == ROUTE_SMI) alt_gpio_reg |= (1 << i); - } route_reg >>= 2; } printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg); @@ -101,7 +104,8 @@ void southcluster_smm_enable_smi(void) /* Set up the GPIO route. */ southcluster_smm_route_gpios(); - /* Enable SMI generation: + /* + * Enable SMI generation: * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 1aebd07..5a3ad9d 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -3,6 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,37 +19,40 @@ * Foundation, Inc. */ -#include <stdint.h> #include <arch/io.h> #include <arch/acpi.h> #include <bootstate.h> #include <cbmem.h> +#include "chip.h" #include <console/console.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> -#include <drivers/uart/uart8250reg.h> - +#include <romstage_handoff.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/lpc.h> -#include <soc/nvs.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/ramstage.h> #include <soc/spi.h> -#include "chip.h" +#include <spi-generic.h> +#include <stdint.h> static inline void add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) { + printk(BIOS_SPEW, "%s/%s ( %s, 0x%016lx, 0x%016lx )\n", + __FILE__, __func__, dev_name(dev), addr, size); mmio_resource(dev, i, addr >> 10, size >> 10); } static void sc_add_mmio_resources(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); @@ -86,6 +90,9 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) { struct resource *res; + printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x, 0x%08x )\n", + __FILE__, __func__, dev_name(dev), base, size, index); + if (io_range_in_default(base, size)) return; @@ -99,6 +106,9 @@ static void sc_add_io_resources(device_t dev) { struct resource *res; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); res->base = LPC_DEFAULT_IO_RANGE_LOWER; @@ -114,6 +124,9 @@ static void sc_add_io_resources(device_t dev) static void sc_read_resources(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -130,75 +143,43 @@ static void sc_rtc_init(void) int rtc_fail; struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - if (ps != NULL) { + printk(BIOS_SPEW, "%s/%s\n", + __FILE__, __func__); + if (ps != NULL) gen_pmcon1 = ps->gen_pmcon1; - } else { - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - } + else + gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); rtc_fail = !!(gen_pmcon1 & RPS); - if (rtc_fail) { + if (rtc_fail) printk(BIOS_DEBUG, "RTC failure.\n"); - } cmos_init(rtc_fail); } -/* - * The UART hardware loses power while in suspend. Because of this the kernel - * can hang because it doesn't re-initialize serial ports it is using for - * consoles at resume time. The following function configures the UART - * if the hardware is enabled though it may not be the correct baud rate - * or configuration. This is definitely a hack, but it helps the kernel - * along. - */ -static void com1_configure_resume(device_t dev) -{ - const uint16_t port = 0x3f8; - - /* Is the UART I/O port enabled? */ - if (!(pci_read_config32(dev, UART_CONT) & 1)) - return; - - /* Disable interrupts */ - outb(0x0, port + UART8250_IER); - - /* Enable FIFOs */ - outb(UART8250_FCR_FIFO_EN, port + UART8250_FCR); - - /* assert DTR and RTS so the other end is happy */ - outb(UART8250_MCR_DTR | UART8250_MCR_RTS, port + UART8250_MCR); - - /* DLAB on */ - outb(UART8250_LCR_DLAB | 3, port + UART8250_LCR); - - /* Set Baud Rate Divisor. 1 ==> 115200 Baud */ - outb(1, port + UART8250_DLL); - outb(0, port + UART8250_DLM); - - /* Set to 3 for 8N1 */ - outb(3, port + UART8250_LCR); -} - static void sc_init(device_t dev) { int i; - u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); - u16 *ir_base = (u16 *)ILB_BASE_ADDRESS + 0x20; - u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); - u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); - const struct baytrail_irq_route *ir = &global_baytrail_irq_route; - struct soc_intel_baytrail_config *config = dev->chip_info; + const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; + const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; + void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1); + void *actl = (void *)(ILB_BASE_ADDRESS + ACTL); + const struct soc_irq_route *ir = &global_soc_irq_route; + struct soc_intel_braswell_config *config = dev->chip_info; + + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); /* Set up the PIRQ PIC routing based on static config. */ - for (i = 0; i < NUM_PIRQS; i++) { - write8(pr_base + i, ir->pic[i]); - } + for (i = 0; i < NUM_PIRQS; i++) + write8((void *)(pr_base + i*sizeof(ir->pic[i])), + ir->pic[i]); + /* Set up the per device PIRQ routing base on static config. */ - for (i = 0; i < NUM_IR_DEVS; i++) { - write16(ir_base + i, ir->pcidev[i]); - } + for (i = 0; i < NUM_IR_DEVS; i++) + write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), + ir->pcidev[i]); /* Route SCI to IRQ9 */ write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); @@ -214,108 +195,86 @@ static void sc_init(device_t dev) read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } - if (acpi_is_wakeup_s3()) - com1_configure_resume(dev); } /* * Common code for the south cluster devices. */ -/* Set bit in function disable register to hide this device. */ +/* Set bit in function disble register to hide this device. */ static void sc_disable_devfn(device_t dev) { - u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS); - u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2); + void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); + void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2); uint32_t mask = 0; uint32_t mask2 = 0; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + +#define SET_DIS_MASK(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + mask |= name_ ## _DIS +#define SET_DIS_MASK2(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + mask2 |= name_ ## _DIS + switch (dev->path.pci.devfn) { - case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): - mask |= SDIO_DIS; + SET_DIS_MASK(SDIO); break; - case PCI_DEVFN(SD_DEV, SD_FUNC): - mask |= SD_DIS; + SET_DIS_MASK(SD); break; - case PCI_DEVFN(SATA_DEV, SATA_FUNC): - mask |= SATA_DIS; + SET_DIS_MASK(SATA); break; - case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): - mask |= XHCI_DIS; + SET_DIS_MASK(XHCI); /* Disable super speed PHY when XHCI is not available. */ mask2 |= USH_SS_PHY_DIS; break; - case PCI_DEVFN(LPE_DEV, LPE_FUNC): - mask |= LPE_DIS; + SET_DIS_MASK(LPE); break; - case PCI_DEVFN(MMC_DEV, MMC_FUNC): - mask |= MMC_DIS; + SET_DIS_MASK(MMC); break; - case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): - mask |= SIO_DMA1_DIS; + SET_DIS_MASK(SIO_DMA1); break; - case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): - mask |= I2C1_DIS; + SET_DIS_MASK(I2C1); break; - case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): - mask |= I2C1_DIS; + SET_DIS_MASK(I2C2); break; - case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): - mask |= I2C3_DIS; + SET_DIS_MASK(I2C3); break; - case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): - mask |= I2C4_DIS; + SET_DIS_MASK(I2C4); break; - case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): - mask |= I2C5_DIS; + SET_DIS_MASK(I2C5); break; - case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): - mask |= I2C6_DIS; + SET_DIS_MASK(I2C6); break; - case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): - mask |= I2C7_DIS; + SET_DIS_MASK(I2C7); break; - case PCI_DEVFN(TXE_DEV, TXE_FUNC): - mask |= TXE_DIS; + SET_DIS_MASK(TXE); break; - case PCI_DEVFN(HDA_DEV, HDA_FUNC): - mask |= HDA_DIS; + SET_DIS_MASK(HDA); break; - case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): - mask |= PCIE_PORT1_DIS; + SET_DIS_MASK(PCIE_PORT1); break; - case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): - mask |= PCIE_PORT2_DIS; + SET_DIS_MASK(PCIE_PORT2); break; - case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): - mask |= PCIE_PORT3_DIS; + SET_DIS_MASK(PCIE_PORT3); break; - case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): - mask |= PCIE_PORT4_DIS; + SET_DIS_MASK(PCIE_PORT4); break; - case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): - mask |= EHCI_DIS; + SET_DIS_MASK(SIO_DMA2); break; - case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): - mask |= SIO_DMA2_DIS; + SET_DIS_MASK(PWM1); break; - case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): - mask |= PWM1_DIS; + SET_DIS_MASK(PWM2); break; - case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): - mask |= PWM2_DIS; + SET_DIS_MASK(HSUART1); break; - case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): - mask |= HSUART1_DIS; + SET_DIS_MASK(HSUART2); break; - case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): - mask |= HSUART2_DIS; + SET_DIS_MASK(SPI); break; - case PCI_DEVFN(SPI_DEV, SPI_FUNC): - mask |= SPI_DIS; - break; - case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): - mask2 |= SMBUS_DIS; + SET_DIS_MASK2(SMBUS); break; } @@ -335,24 +294,34 @@ static void sc_disable_devfn(device_t dev) static inline void set_d3hot_bits(device_t dev, int offset) { uint32_t reg8; + + printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x )\n", + __FILE__, __func__, dev_name(dev), offset); printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); reg8 = pci_read_config8(dev, offset + 4); reg8 |= 0x3; pci_write_config8(dev, offset + 4, reg8); } -/* Parts of the audio subsystem are powered by the HDA device. Therefore, one +/* + * Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of - * the audio paths work for LPE audio. */ + * the audio paths work for LPE audio. + */ static void hda_work_around(device_t dev) { - u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8); + void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); + + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); /* Need to set magic register 0x43 to 0xd7 in config space. */ pci_write_config8(dev, 0x43, 0xd7); - /* Need to set bit 0 of GCTL to take the device out of reset. However, - * that requires setting up the 64-bit BAR. */ + /* + * Need to set bit 0 of GCTL to take the device out of reset. However, + * that requires setting up the 64-bit BAR. + */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); @@ -365,8 +334,13 @@ static int place_device_in_d3hot(device_t dev) { unsigned offset; - /* Parts of the HDA block are used for LPE audio as well. - * Therefore assume the HDA will never be put into D3Hot. */ + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + + /* + * Parts of the HDA block are used for LPE audio as well. + * Therefore assume the HDA will never be put into D3Hot. + */ if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { hda_work_around(dev); return 0; @@ -379,91 +353,50 @@ static int place_device_in_d3hot(device_t dev) return 0; } - /* For some reason some of the devices don't have the capability - * pointer set correctly. Work around this by hard coding the offset. */ + /* + * For some reason some of the devices don't have the capability + * pointer set correctly. Work around this by hard coding the offset. + */ +#define DEV_CASE(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + switch (dev->path.pci.devfn) { - case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): + DEV_CASE(SDIO) : + DEV_CASE(SD) : + DEV_CASE(MMC) : + DEV_CASE(LPE) : + DEV_CASE(SIO_DMA1) : + DEV_CASE(I2C1) : + DEV_CASE(I2C2) : + DEV_CASE(I2C3) : + DEV_CASE(I2C4) : + DEV_CASE(I2C5) : + DEV_CASE(I2C6) : + DEV_CASE(I2C7) : + DEV_CASE(SIO_DMA2) : + DEV_CASE(PWM1) : + DEV_CASE(PWM2) : + DEV_CASE(HSUART1) : + DEV_CASE(HSUART2) : + DEV_CASE(SPI) : offset = 0x80; break; - case PCI_DEVFN(SD_DEV, SD_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(MMC_DEV, MMC_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(LPE_DEV, LPE_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(SPI_DEV, SPI_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(SATA_DEV, SATA_FUNC): - offset = 0x70; - break; - case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): + DEV_CASE(SATA) : + DEV_CASE(XHCI) : offset = 0x70; break; - case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): - offset = 0x70; - break; - case PCI_DEVFN(HDA_DEV, HDA_FUNC): + DEV_CASE(HDA) : + DEV_CASE(SMBUS) : offset = 0x50; break; - case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): - offset = 0x50; - break; - case PCI_DEVFN(TXE_DEV, TXE_FUNC): + DEV_CASE(TXE) : /* TXE cannot be placed in D3Hot. */ return 0; - case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): - offset = 0xa0; break; - case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): - offset = 0xa0; - break; - case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): - offset = 0xa0; - break; - case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): + DEV_CASE(PCIE_PORT1) : + DEV_CASE(PCIE_PORT2) : + DEV_CASE(PCIE_PORT3) : + DEV_CASE(PCIE_PORT4) : offset = 0xa0; break; } @@ -481,6 +414,8 @@ void southcluster_enable_dev(device_t dev) { uint32_t reg32; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); if (!dev->enabled) { int slot = PCI_SLOT(dev->path.pci.devfn); int func = PCI_FUNC(dev->path.pci.devfn); @@ -516,7 +451,7 @@ static struct device_operations device_ops = { .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &soc_pci_ops, }; @@ -528,18 +463,23 @@ static const struct pci_driver southcluster __pci_driver = { int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg) { + printk(BIOS_SPEW, "%s/%s ( 0x%p )\n", + __FILE__, __func__, (void *)cfg); return -1; } static void finalize_chipset(void *unused) { - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); - u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS); - u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2); - u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR); - u8 *spi = (u8 *)SPI_BASE_ADDRESS; + void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); + void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS); + void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); + void *etr = (void *)(PMC_BASE_ADDRESS + ETR); + uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; struct spi_config cfg; + printk(BIOS_SPEW, "%s/%s ( 0x%p )\n", + __FILE__, __func__, unused); + /* Set the lock enable on the BIOS control register. */ write32(bcr, read32(bcr) | BCR_LE); @@ -563,6 +503,7 @@ static void finalize_chipset(void *unused) write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); } + spi_init(); printk(BIOS_DEBUG, "Finalizing SMM.\n"); outb(APM_CNT_FINALIZE, APM_CNT); diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index b1fc692..16fb465 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * See file CREDITS for list of people who contributed to this * project. @@ -20,18 +21,17 @@ */ /* This file is derived from the flashrom project. */ -#include <stdint.h> -#include <stdlib.h> -#include <string.h> -#include <bootstate.h> -#include <delay.h> #include <arch/io.h> +#include <bootstate.h> #include <console/console.h> +#include <delay.h> #include <device/pci_ids.h> -#include <spi_flash.h> - #include <soc/lpc.h> #include <soc/pci_devs.h> +#include <spi_flash.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> #ifdef __SMM__ #define pci_read_config_byte(dev, reg, targ)\ @@ -84,20 +84,6 @@ typedef struct ich9_spi_regs { uint16_t preop; uint16_t optype; uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; } __attribute__((packed)) ich9_spi_regs; typedef struct ich_spi_controller { @@ -112,7 +98,6 @@ typedef struct ich_spi_controller { unsigned databytes; uint8_t *status; uint16_t *control; - uint32_t *bbar; } ich_spi_controller; static ich_spi_controller cntlr; @@ -167,51 +152,45 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) -static u8 readb_(const void *addr) +static u8 readb_(void *addr) { - u8 v = read8((unsigned long)addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + u8 v = read8(addr); + printk(BIOS_DEBUG, "0x%p --> 0x%2.2x\n", addr, v); return v; } -static u16 readw_(const void *addr) +static u16 readw_(void *addr) { - u16 v = read16((unsigned long)addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + u16 v = read16(addr); + printk(BIOS_DEBUG, "0x%p --> 0x%4.4x\n", addr, v); return v; } -static u32 readl_(const void *addr) +static u32 readl_(void *addr) { - u32 v = read32((unsigned long)addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + u32 v = read32(addr); + printk(BIOS_DEBUG, "0x%p --> 0x%8.8x\n", addr, v); return v; } -static void writeb_(u8 b, const void *addr) +static void writeb_(u8 b, void *addr) { + printk(BIOS_DEBUG, "0x%p <-- 0x%2.2x\n", addr, b); write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); } -static void writew_(u16 b, const void *addr) +static void writew_(u16 b, void *addr) { + printk(BIOS_DEBUG, "0x%p <-- 0x%4.4x\n", addr, b); write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); } -static void writel_(u32 b, const void *addr) +static void writel_(u32 b, void *addr) { + printk(BIOS_DEBUG, "0x%p <-- 0x%8.8x\n", addr, b); write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); } #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ @@ -240,9 +219,9 @@ static void write_reg(const void *value, void *dest, uint32_t size) } } -static void read_reg(const void *src, void *value, uint32_t size) +static void read_reg(void *src, void *value, uint32_t size) { - const uint8_t *bsrc = src; + uint8_t *bsrc = src; uint8_t *bvalue = value; while (size >= 4) { @@ -255,23 +234,12 @@ static void read_reg(const void *src, void *value, uint32_t size) } } -static void ich_set_bbar(uint32_t minaddr) -{ - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; - - minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr.bbar); -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { ich_spi_slave *slave = malloc(sizeof(*slave)); if (!slave) { - printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); + printk(BIOS_ERR, "ICH SPI: Bad allocation\n"); return NULL; } @@ -292,6 +260,11 @@ static ich9_spi_regs *spi_regs(void) #else dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif + if (!dev) { + printk(BIOS_ERR, "%s: PCI device not found", __func__); + return NULL; + } + pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; @@ -300,7 +273,14 @@ static ich9_spi_regs *spi_regs(void) void spi_init(void) { - ich9_spi_regs *ich9_spi = spi_regs(); + ich9_spi_regs *ich9_spi; + + ich9_spi = spi_regs(); + if (!ich9_spi) { + printk(BIOS_ERR, "Not initialising spi as %s returned NULL\n", + __func__); + return; + } ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; cntlr.opmenu = ich9_spi->opmenu; @@ -311,19 +291,19 @@ void spi_init(void) cntlr.databytes = sizeof(ich9_spi->fdata); cntlr.status = &ich9_spi->ssfs; cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; cntlr.preop = &ich9_spi->preop; - ich_set_bbar(0); } -#ifndef __SMM__ +#if ENV_RAMSTAGE + static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif + +#endif /* ENV_RAMSTAGE */ int spi_claim_bus(struct spi_slave *slave) { @@ -460,13 +440,14 @@ static int spi_setup_offset(spi_transaction *trans) spi_use_out(trans, 3); return 1; default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); + printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", + trans->type); return -1; } } /* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set + * Wait for up to 400ms til status register bit(s) turn 1 (in case wait_til_set * below is True) or 0. In case the wait was for the bit(s) to set - write * those bits back, which would cause resetting them. * @@ -477,6 +458,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) int timeout = 40000; /* This will result in 400 ms */ u16 status = 0; + wait_til_set &= 1; while (timeout--) { status = readw_(cntlr.status); if (wait_til_set ^ ((status & bitmask) == 0)) { @@ -487,7 +469,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) udelay(10); } - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", + printk(BIOS_ERR, "ICH SPI: SCIP timeout, read %x, expected %x\n", status, bitmask); return -1; } @@ -528,9 +510,11 @@ int spi_xfer(struct spi_slave *slave, const void *dout, writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); spi_setup_type(&trans); - if ((opcode_index = spi_setup_opcode(&trans)) < 0) + opcode_index = spi_setup_opcode(&trans); + if (opcode_index < 0) return -1; - if ((with_address = spi_setup_offset(&trans)) < 0) + with_address = spi_setup_offset(&trans); + if (with_address < 0) return -1; if (trans.opcode == SPI_OPCODE_WREN) { @@ -570,7 +554,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return -1; if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); + printk(BIOS_ERR, "ICH SPI: Command transaction error\n"); return -1; } @@ -585,8 +569,9 @@ int spi_xfer(struct spi_slave *slave, const void *dout, * by the SPI chip driver. */ if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " spi_crop_chunk()?\n"); + printk(BIOS_DEBUG, + "ICH SPI: Too much to write. Does your SPI chip driver use" + " CONTROLLER_PAGE_LIMIT?\n"); return -1; } @@ -627,7 +612,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return -1; if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); + printk(BIOS_ERR, "ICH SPI: Data transaction error\n"); return -1; } diff --git a/src/soc/intel/braswell/spi_loading.c b/src/soc/intel/braswell/spi_loading.c new file mode 100644 index 0000000..4130045 --- /dev/null +++ b/src/soc/intel/braswell/spi_loading.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + + +#include <arch/byteorder.h> +#include <boot/coreboot_tables.h> +#include <cbmem.h> +#include <cbfs.h> +#include <console/console.h> +#include <stdlib.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#define CACHELINE_SIZE 64 +#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) +#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) + +static void *find_mirror_buffer(int len) +{ + int nentries; + int i; + struct lb_memory *mem; + void *buffer; + + len = ALIGN(len, 4096); + + mem = get_lb_mem(); + nentries = (mem->size - sizeof(*mem)) / sizeof(mem->map[0]); + + /* + * Find the highest RAM entry that accommodates the lenth provide + * while falling below 4GiB. + */ + buffer = NULL; + for (i = 0; i < nentries; i++) { + const uint64_t max_addr = 1ULL << 32; + uint64_t start; + uint64_t size; + struct lb_memory_range *r; + + r = &mem->map[i]; + + if (r->type != LB_MEM_RAM) + continue; + + start = unpack_lb64(r->start); + if (start >= max_addr) + continue; + + size = unpack_lb64(r->size); + if (size < len) + continue; + + /* Adjust size of buffer if range exceeds max address. */ + if (start + size > max_addr) + size = max_addr - start; + + if (size < len) + continue; + + buffer = (void *)(uintptr_t)(start + size - len); + } + + return buffer; +} + +/* + * Mirror the payload file to the default SMM location if it is small enough. + * The default SMM region can be used since no one is using the memory at this + * location at this stage in the boot. + */ +static void *spi_mirror(void *file_start, int file_len) +{ + int alignment_diff; + char *src; + char *dest; + + alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); + + /* + * Adjust file length so that the start and end points are aligned to a + * cacheline. Coupled with the ROM caching in the CPU the SPI hardware + * will read and cache full length cachelines. It will also prefetch + * data as well. Once things are mirrored in memory all accesses should + * hit the CPUs cache. + */ + file_len += alignment_diff; + file_len = ALIGN(file_len, CACHELINE_SIZE); + + printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); + + dest = find_mirror_buffer(file_len); + + /* + * Just pass back the pointer to ROM space if a buffer could not + * be found to mirror into. + */ + if (dest == NULL) + return file_start; + + src = (void *)(CACHELINE_MASK & (long)file_start); + /* + * Note that if mempcy is not using 32-bit moves the performance will + * degrade because the SPI hardware prefetchers look for + * cacheline-aligned 32-bit accesses to kick in. + */ + memcpy(dest, src, file_len); + + /* Provide pointer into mirrored space. */ + return &dest[alignment_diff]; +} + +void *cbfs_load_payload(struct cbfs_media *media, const char *name) +{ + int file_len; + void *file_start; + struct cbfs_file *file; + + file_start = vboot_get_payload(&file_len); + + if (file_start != NULL) + return spi_mirror(file_start, file_len); + + file = cbfs_get_file(media, name); + + if (file == NULL) + return NULL; + + if (ntohl(file->type) != CBFS_TYPE_PAYLOAD) + return NULL; + + file_len = ntohl(file->len); + + file_start = CBFS_SUBHEADER(file); + + return spi_mirror(file_start, file_len); +} diff --git a/src/soc/intel/braswell/stage_cache.c b/src/soc/intel/braswell/stage_cache.c deleted file mode 100644 index 47d756c..0000000 --- a/src/soc/intel/braswell/stage_cache.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <cbmem.h> -#include <stage_cache.h> -#include <soc/smm.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - char *smm_base; - /* 1MiB cache size */ - const long cache_size = CONFIG_SMM_RESERVED_SIZE; - - /* Ramstage cache lives in TSEG region which is the definition of - * cbmem_top(). */ - smm_base = cbmem_top(); - *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; -} diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index e5129d8..e7a1c13 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,46 +18,26 @@ * Foundation, Inc. */ -#include <stdint.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <soc/msr.h> - -unsigned bus_freq_khz(void) -{ - msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); - switch (clk_info.lo & 0x3) { - case 0: - return 83333; - case 1: - return 100000; - case 2: - return 133333; - case 3: - return 116666; - default: - return 0; - } -} +#include <console/console.h> +#if ENV_RAMSTAGE +#include <soc/ramstage.h> +#else +#include <soc/romstage.h> +#endif +#include <stdint.h> unsigned long tsc_freq_mhz(void) { - msr_t platform_info; - unsigned bclk_khz = bus_freq_khz(); - - if (!bclk_khz) - return 0; + msr_t ia_core_ratios; - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; + ia_core_ratios = rdmsr(MSR_IACORE_RATIOS); + return (BUS_FREQ_KHZ * ((ia_core_ratios.lo >> 16) & 0x3f)) / 1000; } #if !defined(__SMM__) -#if !defined(__PRE_RAM__) -#include <soc/ramstage.h> -#else -#include <soc/romstage.h> -#endif void set_max_freq(void) { @@ -68,12 +49,17 @@ void set_max_freq(void) msr.lo |= (1 << 16); wrmsr(MSR_IA32_MISC_ENABLES, msr); - /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of - * the PERF_CTL. */ + /* + * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of + * the PERF_CTL. + */ msr = rdmsr(MSR_IACORE_RATIOS); perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; - /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of - * the PERF_CTL. */ + + /* + * Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of + * the PERF_CTL. + */ msr = rdmsr(MSR_IACORE_VIDS); perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c deleted file mode 100644 index 69399ef..0000000 --- a/src/soc/intel/braswell/xhci.c +++ /dev/null @@ -1,259 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/acpi.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <reg_script.h> - -#include <soc/iomap.h> -#include <soc/iosf.h> -#include <soc/lpc.h> -#include <soc/pattrs.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> -#include <soc/ramstage.h> -#include <soc/xhci.h> - -#include "chip.h" - -struct reg_script usb3_phy_script[] = { - /* USB3PHYInit() */ - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_PLL_CONTROL, - ~0x00700000, 0x00500000), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_VCO_START_CAL_POINT, - ~0x001f0000, 0x000A0000), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CCDRLF, - ~0x0000000f, 0x0000000b), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_PEAKING_AMP_CONFIG_DIAG, - ~0x000000f0, 0x000000f0), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_OFFSET_COR_CONFIG_DIAG, - ~0x000001c0, 0x00000000), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_VGA_GAIN_CONFIG_DIAG, - ~0x00000070, 0x00000020), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_REE_DAC_CONTROL, - ~0x00000002, 0x00000002), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_U1_POWER_STATE_DEF, - ~0x00000000, 0x00040000), - REG_SCRIPT_END -}; - -const struct reg_script xhci_init_script[] = { - /* CommonXhciHcInit() */ - /* BAR + 0x0c[31:16] = 0x0200 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0x0000ffff, 0x02000000), - /* BAR + 0x0c[7:0] = 0x0a */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0xffffff00, 0x0000000a), - /* BAR + 0x8094[23,21,14]=111b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8094, 0x00a04000), - /* BAR + 0x8110[20,11,8,2]=1100b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8110, ~0x00000104, 0x00100800), - /* BAR + 0x8144[8,7,6]=111b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8144, 0x000001c0), - /* BAR + 0x8154[21,13,3]=010b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8154, ~0x00200008, 0x80002000), - /* BAR + 0x816c[19:0]=1110x100000000111100b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x816c, 0xfff08000, 0x000e0030), - /* BAR + 0x8188[26,24]=11b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8188, 0x05000000), - /* BAR + 0x8174=0x1000c0a*/ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8174, 0xfe000000, 0x01000c0a), - /* BAR + 0x854c[29]=0b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x854c, ~0x20000000, 0), - /* BAR + 0x8178[12:0]=0b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8178, ~0xffffe000, 0), - /* BAR + 0x8164[7:0]=0xff */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8164, 0x000000ff), - /* BAR + 0x0010[10,9,5]=110b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0010, ~0x00000020, 0x00000600), - /* BAR + 0x8058[20,16,8]=110b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000), - /* BAR + 0x8060[25]=1b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8060, 0x02000000), - /* BAR + 0x80f0[20]=0b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80f0, ~0x00100000, 0), - /* BAR + 0x8008[19]=1b (to enable LPM) */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8008, 0x00080000), - /* BAR + 0x80fc[25]=1b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x80fc, 0x02000000), - /* 0x40/0x44 are written as bytes to avoid touching bit31 */ - /* D20:F0:40[21,20,18,10,9,8]=111001b (don't write byte3) */ - REG_PCI_RMW8(0x41, ~0x06, 0x01), - /* Except [21,20,19,18]=0001b USB wake W/A is disable IIL1E */ - REG_PCI_RMW8(0x42, 0x3c, 0x04), - /* D20:F0:44[19:14,10,9,7,3:0]=1 (don't write byte3) */ - REG_PCI_RMW8(0x44, 0x00, 0x8f), - REG_PCI_RMW8(0x45, ~0xcf, 0xc6), - REG_PCI_RMW8(0x46, ~0x0f, 0x0f), - /* BAR + 0x8140 = 0xff00f03c */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8140, 0, 0xff00f03c), - REG_SCRIPT_END -}; - -const struct reg_script xhci_init_boot_script[] = { - /* Setup USB3 phy */ - REG_SCRIPT_NEXT(usb3_phy_script), - /* Initialize host controller */ - REG_SCRIPT_NEXT(xhci_init_script), - /* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040), - /* BAR + 0x80e0 toggle bit 24=0 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0), - REG_SCRIPT_END -}; - -const struct reg_script xhci_init_resume_script[] = { - /* Setup USB3 phy */ - REG_SCRIPT_NEXT(usb3_phy_script), - /* Initialize host controller */ - REG_SCRIPT_NEXT(xhci_init_script), - /* BAR + 0x80e0[16,9,6]=001b, leave bit 24=0 to prevent HC reset */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01010200, 0x00000040), - REG_SCRIPT_END -}; - -const struct reg_script xhci_clock_gating_script[] = { - /* ConfigureXhciClockGating() */ - /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ - REG_PCI_RMW16(0x40, ~0x0600, 0x0100), - REG_PCI_RMW8(0x42, ~0x38, 0x04), - /* D20:F0:44[5:3]=001b */ - REG_PCI_RMW16(0x44, ~0x0030, 0x0008), - /* D20:F0:A0[19:18]=01b */ - REG_PCI_RMW32(0xa0, ~0x00080000, 0x00040000), - /* D20:F0:A4[15:0]=0x00 */ - REG_PCI_WRITE16(0xa4, 0x0000), - /* D20:F0:B0[21:17,14:13]=0000000b */ - REG_PCI_RMW32(0xb0, ~0x00376000, 0x00000000), - /* D20:F0:50[31:0]=0x0bce6e5f */ - REG_PCI_WRITE32(0x50, 0x0bce6e5f), - REG_SCRIPT_END -}; - -/* Warm Reset a USB3 port */ -static void xhci_reset_port_usb3(device_t dev, int port) -{ - struct reg_script reset_port_usb3_script[] = { - /* Issue Warm Port Rest to the port */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), - XHCI_USB3_PORTSC_WPR), - /* Wait up to 100ms for it to complete */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), - XHCI_USB3_PORTSC_WRC, XHCI_USB3_PORTSC_WRC, - XHCI_RESET_TIMEOUT), - /* Clear change status bits, do not set PED */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), - ~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST), - REG_SCRIPT_END - }; - reg_script_run_on_dev(dev, reset_port_usb3_script); -} - -/* Prepare ports to be routed to EHCI or XHCI */ -static void xhci_route_all(device_t dev) -{ - static const struct reg_script xhci_route_all_script[] = { - /* USB3 SuperSpeed Enable */ - REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP), - /* USB2 Port Route to XHCI */ - REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP), - REG_SCRIPT_END - }; - u32 port_disabled; - int port; - - printk(BIOS_INFO, "USB: Route ports to XHCI controller\n"); - - /* Route ports to XHCI controller */ - reg_script_run_on_dev(dev, xhci_route_all_script); - - if (acpi_is_wakeup_s3()) - return; - - /* Reset enabled USB3 ports */ - port_disabled = pci_read_config32(dev, XHCI_USB3PDO); - for (port = 0; port < BYTM_USB3_PORT_COUNT; port++) { - if (port_disabled & (1 << port)) - continue; - xhci_reset_port_usb3(dev, port); - } -} - -static void xhci_init(device_t dev) -{ - struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script xhci_hc_init[] = { - /* Initialize clock gating */ - REG_SCRIPT_NEXT(xhci_clock_gating_script), - /* Finalize XHCC1 and XHCC2 */ - REG_PCI_RMW32(0x44, ~0x00000000, 0x83c00000), - REG_PCI_RMW32(0x40, ~0x00800000, 0x80000000), - /* Set USB2 Port Routing Mask */ - REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP), - /* Set USB3 Port Routing Mask */ - REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP), - /* - * Disable ports if requested - */ - /* Open per-port disable control override */ - REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), - REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask), - REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask), - /* Close per-port disable control override */ - REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), - REG_SCRIPT_END - }; - - /* Initialize XHCI controller for boot or resume path */ - if (acpi_is_wakeup_s3()) - reg_script_run_on_dev(dev, xhci_init_resume_script); - else - reg_script_run_on_dev(dev, xhci_init_boot_script); - - /* C0 steppings change iCLK/USB PLL VCO settings from 5 to 7 */ - if (pattrs_get()->stepping == STEP_C0) { - uint32_t reg = iosf_ushphy_read(USHPHY_CDN_PLL_CONTROL); - reg |= 0x00700000; - iosf_ushphy_write(USHPHY_CDN_PLL_CONTROL, reg); - } - - /* Finalize Initialization */ - reg_script_run_on_dev(dev, xhci_hc_init); - - /* Route all ports to XHCI if requested */ - if (config->usb_route_to_xhci) - xhci_route_all(dev); -} - -static struct device_operations xhci_device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = xhci_init, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver baytrail_xhci __pci_driver = { - .ops = &xhci_device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = XHCI_DEVID -};

1 0

Patch set updated for coreboot: mainboard/google/cyan: Cyan board support
by Leroy P Leahy 24 Jun '15

24 Jun '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10182 -gerrit commit 71a83467985e1510961f6844ec178e13532478dd Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 11 17:24:31 2015 -0700 mainboard/google/cyan: Cyan board support Add initial files for the cyan board. BRANCH=none BUG=None Test=Build and run on cyan Change-Id: I935839be033c25e197e78fbee306104b4162a99a Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/google/cyan/Kconfig | 72 ++++++ src/mainboard/google/cyan/Kconfig.name | 2 + src/mainboard/google/cyan/Makefile.inc | 35 +++ src/mainboard/google/cyan/acpi/chromeos.asl | 37 +++ src/mainboard/google/cyan/acpi/dptf.asl | 93 +++++++ src/mainboard/google/cyan/acpi/ec.asl | 25 ++ src/mainboard/google/cyan/acpi/mainboard.asl | 288 +++++++++++++++++++++ src/mainboard/google/cyan/acpi/superio.asl | 34 +++ src/mainboard/google/cyan/acpi_tables.c | 66 +++++ src/mainboard/google/cyan/boardid.c | 35 +++ src/mainboard/google/cyan/chromeos.c | 135 ++++++++++ src/mainboard/google/cyan/cmos.layout | 140 ++++++++++ src/mainboard/google/cyan/com_init.c | 48 ++++ src/mainboard/google/cyan/devicetree.cb | 142 ++++++++++ src/mainboard/google/cyan/dsdt.asl | 58 +++++ src/mainboard/google/cyan/ec.c | 59 +++++ src/mainboard/google/cyan/ec.h | 69 +++++ src/mainboard/google/cyan/fadt.c | 51 ++++ src/mainboard/google/cyan/gpio.c | 276 ++++++++++++++++++++ src/mainboard/google/cyan/gpio.h | 24 ++ src/mainboard/google/cyan/gpio_pre_evt.c | 271 +++++++++++++++++++ src/mainboard/google/cyan/irqroute.c | 23 ++ src/mainboard/google/cyan/irqroute.h | 64 +++++ src/mainboard/google/cyan/mainboard.c | 44 ++++ src/mainboard/google/cyan/onboard.h | 86 ++++++ src/mainboard/google/cyan/ramstage.c | 28 ++ src/mainboard/google/cyan/romstage.c | 47 ++++ src/mainboard/google/cyan/smihandler.c | 166 ++++++++++++ src/mainboard/google/cyan/spd/Makefile.inc | 42 +++ .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 +++ ...nix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 32 +++ .../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 32 +++ src/mainboard/google/cyan/spd/spd.c | 192 ++++++++++++++ src/mainboard/google/cyan/w25q64.c | 75 ++++++ 34 files changed, 2823 insertions(+) diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig new file mode 100644 index 0000000..010cdf9 --- /dev/null +++ b/src/mainboard/google/cyan/Kconfig @@ -0,0 +1,72 @@ +if BOARD_GOOGLE_CYAN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ALWAYS_LOAD_OPROM + select BOARD_ROMSIZE_KB_8192 + select CHROMEOS + select CHROMEOS_VBNV_CMOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_MEC + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP +# select EC_SOFTWARE_SYNC + select ENABLE_BUILTIN_COM1 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select LID_SWITCH + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM + select SOC_INTEL_BRASWELL + select VBOOT_DYNAMIC_WORK_BUFFER + select VIRTUAL_DEV_SWITCH + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory configuration data. + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory SPD data. + +config DYNAMIC_VNN_SUPPORT + bool "Enables support for Dynamic VNN" + default n + +config MAINBOARD_DIR + string + default google/cyan + +config MAINBOARD_PART_NUMBER + string + default "Cyan" + +config MAINBOARD_VENDOR + string + default "Google" + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config VBOOT_REFCODE_INDEX + hex + default 0x3 + +if !CONFIG_GOP_SUPPORT +config VGA_BIOS_FILE + string + default "3rdparty/blobs/mainboard/intel/strago/vgabios_c0.bin" if C0_DISP_SUPPORT + default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" if !C0_DISP_SUPPORT + +config VGA_BIOS_ID + string + default "8086,22b1" if C0_DISP_SUPPORT + default "8086,22b0" if !C0_DISP_SUPPORT +endif + +endif # BOARD_GOOGLE_CYAN diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name new file mode 100644 index 0000000..a4562d3 --- /dev/null +++ b/src/mainboard/google/cyan/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_CYAN + bool "Cyan" diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc new file mode 100755 index 0000000..03e90df --- /dev/null +++ b/src/mainboard/google/cyan/Makefile.inc @@ -0,0 +1,35 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += spd + +romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c + +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio_pre_evt.c +ramstage-y += irqroute.c +ramstage-y += ramstage.c +ramstage-y += w25q64.c +ramstage-y += boardid.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/cyan/acpi/chromeos.asl b/src/mainboard/google/cyan/acpi/chromeos.asl new file mode 100644 index 0000000..7db294d --- /dev/null +++ b/src/mainboard/google/cyan/acpi/chromeos.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Fields are in the following order. + * - Type: recovery = 1 developer mode = 2 write protect = 3 + * - Active Level - if -1 not a valid gpio + * - GPIO number encoding - if -1 not a valid gpio + * - Chipset Name + * + * Note: We need to encode gpios within the 4 separate banks + * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded + * as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. + */ + +Name(OIPG, Package() { + /* No physical recovery button */ + Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, + Package () { 0x0003, 1, 0x10016, "Braswell" }, +}) diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl new file mode 100755 index 0000000..67bdbb4 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 6200, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/braswell/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/cyan/acpi/ec.asl b/src/mainboard/google/cyan/acpi/ec.asl new file mode 100644 index 0000000..5736c27 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/ec.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include <mainboard/google/cyan/ec.h> + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl new file mode 100755 index 0000000..718494e --- /dev/null +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -0,0 +1,288 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <mainboard/google/cyan/onboard.h> + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} + +Scope (\_SB.I2C1) +{ + Device (ETSA) + { + Name (_HID, "ELAN0001") + Name (_DDN, "Elan Touchscreen ") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Method(_CRS, 0x0, NotSerialized) + { + Name(BUF0,ResourceTemplate () + { + I2CSerialBus( + 0x10, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C1", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { CYAN_TOUCH_GPIO_INDEX } + + } ) + Name(BUF1,ResourceTemplate () + { + I2CSerialBus( + 0x10, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C1", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { CYAN_EVT_TOUCH_GPIO_INDEX } + + } ) + If (LEqual (\BDID, BOARD_EVT)) { + Return (BUF1) + } Else { + Return (BUF0) + } + } + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.I2C2) +{ + /* Maxim Audio Codec */ + Device (MAXM) /* Audio Codec driver I2C */ + { + Name (_ADR, 0) + Name (_HID, AUDIO_CODEC_HID) + Name (_CID, AUDIO_CODEC_CID) + Name (_DDN, AUDIO_CODEC_DDN) + Name (_UID, 1) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { CYAN_JACK_MAXIM_GPIO_INDEX } + } ) + Return (SBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } + Device (TISW) /* TI Switch driver I2C */ + { + Name (_ADR, 0) + Name (_HID, TI_SWITCH_HID) + Name (_CID, TI_SWITCH_CID) + Name (_DDN, TI_SWITCH_DDN) + Name (_UID, 1) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { CYAN_JACK_TI_GPIO_INDEX } + + } ) + Return (SBUF) + } + + Method (_STA) + { + Return (0xF) + } + } +} + +Scope (\_SB.I2C5) +{ + Device (ALSI) + { + /* + * TODO(dlaurie): Need official HID. + * + * The current HID is created from the Intersil PNP + * Vendor ID "LSD" and a shortened device identifier. + */ + Name (_HID, EisaId ("LSD2918")) + Name (_DDN, "Intersil 29018 Ambient Light Sensor") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x44, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C5", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_ALS_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.I2C6) +{ + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x15, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C6", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { CYAN_TRACKPAD_GPIO_INDEX } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { CYAN_JACK_MAXIM_GPIO_INDEX } + }) +} + +Scope (\_SB.GPNC) +{ + Method (_AEI, 0, NotSerialized) // _AEI: ACPI Event Interrupts + { + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { CYAN_SCI_GPIO_INDEX } + }) + Return (RBUF) + } + + Method (_E0F, 0, NotSerialized) // _Exx: Edge-Triggered GPE + { + } +} diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl new file mode 100755 index 0000000..018fdb0 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include <mainboard/google/cyan/ec.h> +#include <mainboard/google/cyan/onboard.h> + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Override default IRQ settings */ +#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow){\ + BOARD_I8042_IRQ} + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c new file mode 100755 index 0000000..a88abed --- /dev/null +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <string.h> +#include <types.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* Enable DPTF */ + gnvs->dpte = 1; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/google/cyan/boardid.c b/src/mainboard/google/cyan/boardid.c new file mode 100644 index 0000000..9b0aa73 --- /dev/null +++ b/src/mainboard/google/cyan/boardid.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <boardid.h> +#include <stdlib.h> +#include "ec/google/chromeec/ec.h" + +uint8_t board_id(void) +{ + static int id = -1; + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (id < 0) + id = google_chromeec_get_board_version(); +#endif + return id; +} + diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c new file mode 100644 index 0000000..ed869ba --- /dev/null +++ b/src/mainboard/google/cyan/chromeos.c @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#endif +#include <soc/gpio.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The WP status pin lives on MF_ISH_GPIO_4 */ +#define WP_STATUS_PAD_CFG0 0x4838 +#define WP_STATUS_PAD_CFG1 0x483C + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +static int get_lid_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u8 ec_switches; + + mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1, + &ec_switches, NULL); + return !!(ec_switches & EC_SWITCH_LID_OPEN); +#else + /* Default to force open. */ + return 1; +#endif +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", + get_write_protect_state()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", + recovery_mode_enabled()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); +} +#endif /* ENV_RAMSTAGE */ + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u8 ec_switches; + u32 ec_events; + + mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1, + &ec_switches, NULL); + + /* If a switch is set, we don't need to look at events. */ + if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) + return 1; + + /* Else check if the EC has posted the keyboard recovery event. */ + ec_events = google_chromeec_get_events_b(); + + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +#else + return 0; +#endif +} + +int clear_recovery_mode_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + const uint32_t kb_rec_mask = + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY); + /* Unconditionally clear the EC recovery request. */ + return google_chromeec_clear_events_b(kb_rec_mask); +#else + return 0; +#endif +} + +int get_write_protect_state(void) +{ + /* + * The vboot loader queries this function in romstage. The GPIOs have + * not been set up yet as that configuration is done in ramstage. + * Configuring this GPIO as input so that there isn't any ambiguity + * in the reading. + */ +#if ENV_ROMSTAGE + write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0), + (PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT)); + write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1), + PAD_CONFIG1_DEFAULT0); +#endif + + /* WP is enabled when the pin is reading high. */ + return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0)) + & PAD_VAL_HIGH); +} diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout new file mode 100644 index 0000000..18bf4ce --- /dev/null +++ b/src/mainboard/google/cyan/cmos.layout @@ -0,0 +1,140 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c new file mode 100644 index 0000000..b07b205 --- /dev/null +++ b/src/mainboard/google/cyan/com_init.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/gpio.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void mainboard_pre_console_init(struct romstage_params *params) +{ + uint32_t reg; + uint32_t *pad_config_reg; + + /* Enable the UART hardware for COM1. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* + * Set up the pads to select the UART function for Cyan + * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Set Mode 2 for UART0_RXD + * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Set Mode 2 for UART0_TXD + */ + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, + M2)); + + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, + M2)); +} diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb new file mode 100755 index 0000000..8ad0910 --- /dev/null +++ b/src/mainboard/google/cyan/devicetree.cb @@ -0,0 +1,142 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_ACPI_MODE" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "1" + register "PcdEnableAzalia" = "1" + register "PcdEnableSata" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "1" + register "PcdEnableDma1" = "1" + register "PcdEnableI2C0" = "1" + register "PcdEnableI2C1" = "1" + register "PcdEnableI2C2" = "1" + register "PcdEnableI2C3" = "1" + register "PcdEnableI2C4" = "1" + register "PcdEnableI2C5" = "1" + register "PcdEnableI2C6" = "1" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "SVID_CONFIG1" + register "PcdEmmcMode" = "PCH_ACPI_MODE" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "0" # Disable SATA + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "3" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "1" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # Enable devices in ACPI mode + register "lpss_acpi_mode" = "1" + register "emmc_acpi_mode" = "1" + register "sd_acpi_mode" = "1" + register "lpe_acpi_mode" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + # EDS Table 24-4, Figure 24-5 + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 on end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 on end # 8086 22dc - ? + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 11.0 off end # 8086 0F15 - SDIO Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 13.0 off end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 on end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 on end # 8086 22c3 - I2C Port 3 + device pci 18.4 on end # 8086 22c4 - I2C Port 4 + device pci 18.5 on end # 8086 22c5 - I2C Port 5 + device pci 18.6 on end # 8086 22c6 - I2C Port 6 + device pci 18.7 on end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine + device pci 1b.0 on end # 8086 0F04 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.1 off end # 8086 0F08 - PWM 1 + device pci 1e.2 off end # 8086 0F09 - PWM 2 + device pci 1e.3 on end # 8086 228a - HSUART 1 + device pci 1e.4 on end # 8086 228c - HSUART 2 + device pci 1e.5 on end # 8086 228e - SPI 1 + device pci 1e.6 on end # 8086 2290 - SPI 2 + device pci 1e.7 on end # 8086 22ac - SPI 3 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Bridge + device pci 1f.3 off end # 8086 0F12 - SMBus 0 + end +end diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl new file mode 100755 index 0000000..9f1db24 --- /dev/null +++ b/src/mainboard/google/cyan/dsdt.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, /* DSDT revision: ACPI v5.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <soc/intel/braswell/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/braswell/acpi/globalnvs.asl> + + #include <soc/intel/braswell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + /* #include <soc/intel/braswell/acpi/northcluster.asl> */ + #include <soc/intel/braswell/acpi/southcluster.asl> + #include <soc/intel/braswell/acpi/dptf/cpu.asl> + } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/braswell/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c new file mode 100755 index 0000000..2ed2f52 --- /dev/null +++ b/src/mainboard/google/cyan/ec.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" +#include <vendorcode/google/chromeos/chromeos.h> +#include <types.h> + +void mainboard_ec_init(void) +{ + printk(BIOS_DEBUG, "mainboard_ec_init\n"); + post_code(0xf0); + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Restore SCI event mask on resume. */ + if (acpi_slp_type == 3) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + /* + * Set SCI mask.OS may not generate SMI event to set + * this on S3 resume. + */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); +#endif + post_code(0xf1); +} diff --git a/src/mainboard/google/cyan/ec.h b/src/mainboard/google/cyan/ec.h new file mode 100755 index 0000000..7e70d48 --- /dev/null +++ b/src/mainboard/google/cyan/ec.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +/* GPIO_S0_000 is EC_SCI#, but it is bit 16 in GPE_STS */ +#define EC_SCI_GPI 16 +/* GPIO_S5_07 is EC_SMI#, but it is bit 19 in GPE_STS and ALT_GPIO_SMI. */ +#define EC_SMI_GPI 19 + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c new file mode 100644 index 0000000..45a680a --- /dev/null +++ b/src/mainboard/google/cyan/fadt.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/acpi.h> +#include <string.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c new file mode 100644 index 0000000..537dfe9 --- /dev/null +++ b/src/mainboard/google/cyan/gpio.c @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" +#include <soc/gpio.h> +#include <stdlib.h> +#include "gpio.h" + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + Native_M1, /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* SPI1_CS1_B 66 */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + /* GPIO_ALERT 77 */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + GPIO_NC, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPIO_NC, /* 82 spkr asummed gpio number */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN,/* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + GPIO_NC, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + GPIO_NC, /* 03 FST_SPI_D3 */ + GPIO_NC, /* GPO FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + Native_M2, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + Native_M2, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + GPIO_NC, /* 30 MF_HDA_CLK */ + GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ + GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + GPIO_NC, /* 33 MF_HDA_SDO */ + GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 34 MF_HDA_DOCKRSTB */ + GPIO_NC, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU20K(2), /* 47 I2C6_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ + GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ + GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ + GPIO_OUT_HIGH, /* 75 SATA_GP0 */ + GPIO_NC, /* 76 GPI SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */ + Native_M1, /* 79 MF_SMB_ALERTB */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ + Native_M1, /* 92 GP_SSP_2_CLK */ + NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + Native_M1, /* 94 GP_SSP_2_RXD */ + GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + Native_M1, /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + Native_M5, /* 00 GPIO_DFX0 */ + Native_M5, /* 01 GPIO_DFX3 */ + Native_M1, /* 02 GPIO_DFX7 */ + Native_M5, /* 03 GPIO_DFX1 */ + Native_M1, /* 04 GPIO_DFX5 */ + Native_M1, /* 05 GPIO_DFX4 */ + GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), + /* 06 GPIO_DFX8 */ + Native_M5, /* 07 GPIO_DFX2 */ + Native_M8, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, + /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPO_FUNC(0, 0), /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + Native_M2, /* 45 GP_CAMERASB05 */ + Native_M2, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + Native_M2, /* 48 GP_CAMERASB00 */ + Native_M2, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + Native_M2, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + Native_M2, /* 53 GP_CAMERASB01 */ + Native_M2, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + Native_M2, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + GPIO_NC, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + /* gpio configuration for EVT board which + * is the default configuration for Cyan. + */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return get_override_gpios(&gpio_config); +} + +__attribute__((weak)) struct soc_gpio_config *get_override_gpios( + struct soc_gpio_config *config) +{ + return config; +} diff --git a/src/mainboard/google/cyan/gpio.h b/src/mainboard/google/cyan/gpio.h new file mode 100644 index 0000000..78f4f0e --- /dev/null +++ b/src/mainboard/google/cyan/gpio.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef _BOARD_GPIO_H_ +#define _BOARD_GPIO_H_ + +struct soc_gpio_config *get_override_gpios(struct soc_gpio_config *config); +#endif diff --git a/src/mainboard/google/cyan/gpio_pre_evt.c b/src/mainboard/google/cyan/gpio_pre_evt.c new file mode 100644 index 0000000..415c33e --- /dev/null +++ b/src/mainboard/google/cyan/gpio_pre_evt.c @@ -0,0 +1,271 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" +#include <soc/gpio.h> +#include <stdlib.h> +#include <boardid.h> +#include "onboard.h" +#include "gpio.h" + + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + Native_M1, /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* SPI1_CS1_B 66 */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + /* GPIO_ALERT 77 */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + GPIO_NC, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPIO_NC, /* 82 spkr asummed gpio number */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN,/* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + GPIO_NC, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + GPIO_NC, /* 03 FST_SPI_D3 */ + GPIO_NC, /* GPO FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + Native_M2, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + Native_M2, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + GPIO_NC, /* 30 MF_HDA_CLK */ + GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ + GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + GPIO_NC, /* 33 MF_HDA_SDO */ + GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 34 MF_HDA_DOCKRSTB */ + GPIO_NC, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ + GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ + GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ + GPIO_OUT_HIGH, /* 75 SATA_GP0 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 76 GPI SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */ + Native_M1, /* 79 MF_SMB_ALERTB */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ + Native_M1, /* 92 GP_SSP_2_CLK */ + NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + Native_M1, /* 94 GP_SSP_2_RXD */ + GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + Native_M1, /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + Native_M5, /* 00 GPIO_DFX0 */ + Native_M5, /* 01 GPIO_DFX3 */ + Native_M1, /* 02 GPIO_DFX7 */ + Native_M5, /* 03 GPIO_DFX1 */ + Native_M1, /* 04 GPIO_DFX5 */ + Native_M1, /* 05 GPIO_DFX4 */ + GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), + /* 06 GPIO_DFX8 */ + Native_M5, /* 07 GPIO_DFX2 */ + Native_M8, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, + /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPO_FUNC(0, 0), /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + Native_M2, /* 45 GP_CAMERASB05 */ + Native_M2, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + Native_M2, /* 48 GP_CAMERASB00 */ + Native_M2, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + Native_M2, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + Native_M2, /* 53 GP_CAMERASB01 */ + Native_M2, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + Native_M2, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + GPIO_NC, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + /* BSW */ + /* gpio configuration for pre-evt board */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *get_override_gpios(struct soc_gpio_config *config) +{ + if (board_id() == BOARD_PRE_EVT) + return &gpio_config; + + return config; +} diff --git a/src/mainboard/google/cyan/irqroute.c b/src/mainboard/google/cyan/irqroute.c new file mode 100644 index 0000000..83207d9 --- /dev/null +++ b/src/mainboard/google/cyan/irqroute.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/google/cyan/irqroute.h b/src/mainboard/google/cyan/irqroute.h new file mode 100644 index 0000000..5353d42 --- /dev/null +++ b/src/mainboard/google/cyan/irqroute.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) + +/* CORE bank DIRQs - up to 16 supported */ +#define TPAD_IRQ_OFFSET 0 +#define TOUCH_IRQ_OFFSET 1 +#define I8042_IRQ_OFFSET 2 +#define ALS_IRQ_OFFSET 3 +/* Corresponding SCORE GPIO pins */ +#define TPAD_IRQ_GPIO 55 +#define TOUCH_IRQ_GPIO 72 +#define I8042_IRQ_GPIO 101 +#define ALS_IRQ_GPIO 70 + +/* SUS bank DIRQs - up to 16 supported */ +#define CODEC_IRQ_OFFSET 0 +/* Corresponding SUS GPIO pins */ +#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c new file mode 100755 index 0000000..b109574 --- /dev/null +++ b/src/mainboard/google/cyan/mainboard.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootstate.h> +#include <device/device.h> +#include <soc/gpio.h> +#include "ec.h" + +static void mainboard_init(device_t dev) +{ + mainboard_ec_init(); +} + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h new file mode 100755 index 0000000..3539ff4 --- /dev/null +++ b/src/mainboard/google/cyan/onboard.h @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include "irqroute.h" + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +/* + * gpio based irq for kbd, 17th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 18 + */ +/* ToDO: change kbd irq to gpio bank index */ +#define CYAN_KBD_IRQ 182 + + +/* SCI: Gpio index in N bank */ +#define CYAN_SCI_GPIO_INDEX 15 +/* Trackpad: Gpio index in N bank */ +#define CYAN_TRACKPAD_GPIO_INDEX 18 +/* Touch: Gpio index in SW bank */ +#define CYAN_TOUCH_GPIO_INDEX 76 +/* EVT Touch: Gpio index in N bank */ +#define CYAN_EVT_TOUCH_GPIO_INDEX 19 +/* TI Audio: Gpio index in SW bank */ +#define CYAN_JACK_TI_GPIO_INDEX 34 +/* MAXIM Audio: Gpio index in SE bank */ +#define CYAN_JACK_MAXIM_GPIO_INDEX 77 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ + +#define BOARD_I8042_IRQ CYAN_KBD_IRQ +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "193C9890" +#define AUDIO_CODEC_CID "193C9890" +#define AUDIO_CODEC_DDN "Maxim 98090 Codec " +#define AUDIO_CODEC_I2C_ADDR 0x10 + +#define TI_SWITCH_HID "104C227E" +#define TI_SWITCH_CID "104C227E" +#define TI_SWITCH_DDN "TI SWITCH " +#define TI_SWITCH_I2C_ADDR 0x3B + +#define BOARD_PRE_EVT 0x01 +#define BOARD_EVT 0x02 +#endif diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c new file mode 100644 index 0000000..136d189 --- /dev/null +++ b/src/mainboard/google/cyan/ramstage.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/ramstage.h> +#include <boardid.h> +#include "onboard.h" + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + if (board_id() == BOARD_PRE_EVT) + params->ChvSvidConfig = SVID_CONFIG3; +} diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c new file mode 100755 index 0000000..22e26b5 --- /dev/null +++ b/src/mainboard/google/cyan/romstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <string.h> + +/* All FSP specific code goes in this block */ +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data *ps = rp->pei_data; + + mainboard_fill_spd_data(ps); + + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); +} + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + /* Update SPD data */ + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c new file mode 100644 index 0000000..5af0421 --- /dev/null +++ b/src/mainboard/google/cyan/smihandler.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#include <elog.h> +#include <soc/nvs.h> +#include <soc/pm.h> + +/* The wake gpio is SUS_GPIO[0]. */ +#define WAKE_GPIO_EN SUS_GPIO_EN0 + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +static uint8_t mainboard_smi_ec(void) +{ + uint8_t cmd = google_chromeec_get_event(); + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt; + +#if IS_ENABLED(CONFIG_ELOG_GSMI) + /* Log this event */ + if (cmd) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); +#endif + + switch (cmd) { + case EC_HOST_EVENT_LID_CLOSED: + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + + /* Go to S5 */ + pm1_cnt = inl(pmbase + PM1_CNT); + pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); + outl(pm1_cnt, pmbase + PM1_CNT); + break; + } + + return cmd; +} +#endif + +/* + * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that + * this includes the enable bits in the lower 16 bits. + */ +void mainboard_smi_gpi(uint32_t alt_gpio_smi) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (alt_gpio_smi & (1 << EC_SMI_GPI)) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0) + ; + } +#endif +} + +void mainboard_smi_sleep(uint8_t slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (smm_get_gnvs()->s3u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s3u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); +#endif + /* Enable wake pin in GPE block. */ + enable_gpe(WAKE_GPIO_EN); + break; + case 5: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (smm_get_gnvs()->s5u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s5u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); +#endif + break; + } + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Disable SCI and SMI events */ + google_chromeec_set_smi_mask(0); + google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + while (google_chromeec_get_event() != 0) + ; +#endif +} + +int mainboard_smi_apmc(uint8_t apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); +#endif + break; + case APM_CNT_ACPI_DISABLE: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); +#endif + break; + } + return 0; +} diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/spd/Makefile.inc new file mode 100644 index 0000000..40a3e0d --- /dev/null +++ b/src/mainboard/google/cyan/spd/Makefile.inc @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab diff --git a/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex new file mode 100644 index 0000000..ff4fd29 --- /dev/null +++ b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex @@ -0,0 +1,32 @@ +92 12 0b 03 04 19 02 02 +03 52 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +20 08 3c 3c 01 40 83 01 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ad 01 +00 00 00 00 00 00 ff ab +48 4d 54 34 32 35 53 36 +41 46 52 36 41 2d 50 42 +20 20 4e 30 80 ad 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex new file mode 100644 index 0000000..fdd1a43 --- /dev/null +++ b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex @@ -0,0 +1,32 @@ +92 13 0B 03 04 19 02 02 +03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 +00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 +43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex new file mode 100644 index 0000000..e0b0ac5 --- /dev/null +++ b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex @@ -0,0 +1,32 @@ +92 12 0B 03 04 19 02 02 +03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 +88 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 +34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c new file mode 100644 index 0000000..0ddf5ee --- /dev/null +++ b/src/mainboard/google/cyan/spd/spd.c @@ -0,0 +1,192 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <lib.h> +#include <memory_info.h> +#include <smbios.h> +#include <spd.h> +#include <soc/gpio.h> +#include <soc/romstage.h> +#include <string.h> + +#define SPD_SIZE 256 +#define SATA_GP3_PAD_CFG0 0x5828 +#define I2C3_SCL_PAD_CFG0 0x5438 +#define MF_PLT_CLK1_PAD_CFG0 0x4410 +#define I2C3_SDA_PAD_CFG0 0x5420 + +/* + * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b0010- 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + */ +static const uint32_t dual_channel_config = (1 << 0) | (1 << 1); + +static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +{ + int ram_id = 0; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1; + ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0) + << 2; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3; + printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); + if (ram_id >= total_spds) + return NULL; + + /* Determine if this is a single or dual channel memory system */ + if (dual_channel_config & (1 << ram_id)) + *dual = 1; + + /* Display the RAM type */ + switch (ram_id) { + case 0: + case 2: + printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646Q-HYK0 1600MHz\n"); + break; + case 1: + case 3: + printk(BIOS_DEBUG, "2GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); + break; + } + + /* Return the serial product data for the RAM */ + return &spd_file_content[SPD_SIZE * ram_id]; +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *ps) +{ + char *spd_file; + size_t spd_file_len; + void *spd_content; + int dual_channel = 0; + + /* Find the SPD data in CBFS. */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < SPD_SIZE) + die("Missing SPD data."); + + /* + * Both channels are always present in SPD data. Always use matched + * DIMMs so use the same SPD data for each DIMM. + */ + spd_content = get_spd_pointer(spd_file, + spd_file_len / SPD_SIZE, + &dual_channel); + if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) { + printk(BIOS_DEBUG, "SPD Data:\n"); + hexdump(spd_content, SPD_SIZE); + printk(BIOS_DEBUG, "\n"); + } + + /* + * Set SPD and memory configuration: + * Memory type: 0=DimmInstalled, + * 1=SolderDownMemory, + * 2=DimmDisabled + */ + if (spd_content != NULL) { + ps->spd_data_ch0 = spd_content; + ps->spd_ch0_config = 1; + printk(BIOS_DEBUG, "Channel 0 DIMM soldered down\n"); + if (dual_channel) { + printk(BIOS_DEBUG, "Channel 1 DIMM soldered down\n"); + ps->spd_data_ch1 = spd_content; + ps->spd_ch1_config = 1; + } else { + printk(BIOS_DEBUG, "Channel 1 DIMM not installed\n"); + ps->spd_ch1_config = 2; + } + } +} + +static void set_dimm_info(uint32_t chips, uint8_t *spd, struct dimm_info *dimm) +{ + uint16_t clock_frequency; + uint32_t log2_chips; + + /* Parse the SPD data to determine the DIMM information */ + dimm->ddr_type = MEMORY_TYPE_DDR3; + dimm->dimm_size = (chips << (spd[4] & 0xf)) << (28 - 3 - 20); /* MiB */ + clock_frequency = 1000 * spd[11] / (spd[10] * spd[12]); /* MHz */ + dimm->ddr_frequency = 2 * clock_frequency; /* Double Data Rate */ + dimm->mod_type = spd[3] & 0xf; + memcpy((char *)&dimm->module_part_number[0], &spd[0x80], + sizeof(dimm->module_part_number) - 1); + dimm->mod_id = *(uint16_t *)&spd[0x94]; + switch (chips) { + case 1: + log2_chips = 0; + break; + + case 2: + log2_chips = 1; + break; + + case 4: + log2_chips = 2; + break; + + case 8: + log2_chips = 3; + break; + } + dimm->bus_width = (uint8_t)(log2_chips + (spd[7] & 7) + 2 - 3); +} + +void mainboard_save_dimm_info(struct romstage_params *params) +{ + struct dimm_info *dimm; + struct memory_info *mem_info; + uint32_t chips; + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (mem_info == NULL) + return; + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first channel memory */ + chips = 4; + dimm = &mem_info->dimm[0]; + set_dimm_info(chips, params->pei_data->spd_data_ch0, dimm); + mem_info->dimm_cnt = 1; + + /* Describe the second channel memory */ + if (params->pei_data->spd_ch1_config == 1) { + dimm = &mem_info->dimm[1]; + set_dimm_info(chips, params->pei_data->spd_data_ch1, dimm); + dimm->channel_num = 1; + mem_info->dimm_cnt = 2; + } +} diff --git a/src/mainboard/google/cyan/w25q64.c b/src/mainboard/google/cyan/w25q64.c new file mode 100644 index 0000000..4399d88 --- /dev/null +++ b/src/mainboard/google/cyan/w25q64.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/spi.h> +#include <string.h> + +/* + * SPI lockdown configuration W25Q64FW. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config = { + .preop = SPI_OPPREFIX, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_config(struct spi_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + + return 0; +}

1 0

Patch set updated for coreboot: Cyan: Remove copyright address
by Leroy P Leahy 24 Jun '15

24 Jun '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10339 -gerrit commit a6663987819c7296d540222e4dc6c15a7aee3188 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed May 27 17:54:31 2015 -0700 Cyan: Remove copyright address Remove the copyright address from all of the files. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I05e9d02bff3d7cfc3a83c57c494cafb70e7da10c Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/google/cyan/Makefile.inc | 2 +- src/mainboard/google/cyan/acpi/chromeos.asl | 2 +- src/mainboard/google/cyan/acpi/dptf.asl | 2 +- src/mainboard/google/cyan/acpi/ec.asl | 2 +- src/mainboard/google/cyan/acpi/mainboard.asl | 3 +-- src/mainboard/google/cyan/acpi/superio.asl | 2 +- src/mainboard/google/cyan/acpi_tables.c | 2 +- src/mainboard/google/cyan/chromeos.c | 2 +- src/mainboard/google/cyan/cmos.layout | 2 +- src/mainboard/google/cyan/com_init.c | 2 +- src/mainboard/google/cyan/dsdt.asl | 2 +- src/mainboard/google/cyan/ec.c | 2 +- src/mainboard/google/cyan/ec.h | 2 +- src/mainboard/google/cyan/fadt.c | 2 +- src/mainboard/google/cyan/gpio.c | 2 +- src/mainboard/google/cyan/gpio.h | 2 +- src/mainboard/google/cyan/gpio_pre_evt.c | 2 +- src/mainboard/google/cyan/irqroute.c | 2 +- src/mainboard/google/cyan/irqroute.h | 2 +- src/mainboard/google/cyan/mainboard.c | 2 +- src/mainboard/google/cyan/onboard.h | 2 +- src/mainboard/google/cyan/ramstage.c | 2 +- src/mainboard/google/cyan/romstage.c | 2 +- src/mainboard/google/cyan/smihandler.c | 2 +- src/mainboard/google/cyan/spd/Makefile.inc | 2 +- src/mainboard/google/cyan/spd/spd.c | 2 +- src/mainboard/google/cyan/w25q64.c | 2 +- 27 files changed, 27 insertions(+), 28 deletions(-) diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 03e90df..0d3a9b1 100755 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -15,7 +15,7 @@ ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## Foundation, Inc. ## subdirs-y += spd diff --git a/src/mainboard/google/cyan/acpi/chromeos.asl b/src/mainboard/google/cyan/acpi/chromeos.asl index 7db294d..4ba3857 100644 --- a/src/mainboard/google/cyan/acpi/chromeos.asl +++ b/src/mainboard/google/cyan/acpi/chromeos.asl @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ /* diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index 67bdbb4..bcc49d5 100755 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #define DPTF_TSR0_SENSOR_ID 0 diff --git a/src/mainboard/google/cyan/acpi/ec.asl b/src/mainboard/google/cyan/acpi/ec.asl index 5736c27..a99d8e3 100644 --- a/src/mainboard/google/cyan/acpi/ec.asl +++ b/src/mainboard/google/cyan/acpi/ec.asl @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ /* mainboard configuration */ diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl index 718494e..82163f8 100755 --- a/src/mainboard/google/cyan/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -16,8 +16,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc. */ #include <mainboard/google/cyan/onboard.h> diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl index 018fdb0..31f6fe6 100755 --- a/src/mainboard/google/cyan/acpi/superio.asl +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ /* mainboard configuration */ diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c index a88abed..d01e65c 100755 --- a/src/mainboard/google/cyan/acpi_tables.c +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <arch/acpi.h> diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index ed869ba..01ca3b0 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <arch/io.h> diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout index 18bf4ce..b773b09 100644 --- a/src/mainboard/google/cyan/cmos.layout +++ b/src/mainboard/google/cyan/cmos.layout @@ -15,7 +15,7 @@ ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## Foundation, Inc. ## # ----------------------------------------------------------------- diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c index b07b205..6225983 100644 --- a/src/mainboard/google/cyan/com_init.c +++ b/src/mainboard/google/cyan/com_init.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <arch/io.h> diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index 9f1db24..143a109 100755 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -16,7 +16,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ DefinitionBlock( diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c index 2ed2f52..bba1b07 100755 --- a/src/mainboard/google/cyan/ec.c +++ b/src/mainboard/google/cyan/ec.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <arch/acpi.h> diff --git a/src/mainboard/google/cyan/ec.h b/src/mainboard/google/cyan/ec.h index 7e70d48..c5315da 100755 --- a/src/mainboard/google/cyan/ec.h +++ b/src/mainboard/google/cyan/ec.h @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #ifndef MAINBOARD_EC_H diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c index 45a680a..9f08240 100644 --- a/src/mainboard/google/cyan/fadt.c +++ b/src/mainboard/google/cyan/fadt.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <soc/acpi.h> diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c index 537dfe9..45b2391 100644 --- a/src/mainboard/google/cyan/gpio.c +++ b/src/mainboard/google/cyan/gpio.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include "irqroute.h" diff --git a/src/mainboard/google/cyan/gpio.h b/src/mainboard/google/cyan/gpio.h index 78f4f0e..618524f 100644 --- a/src/mainboard/google/cyan/gpio.h +++ b/src/mainboard/google/cyan/gpio.h @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #ifndef _BOARD_GPIO_H_ #define _BOARD_GPIO_H_ diff --git a/src/mainboard/google/cyan/gpio_pre_evt.c b/src/mainboard/google/cyan/gpio_pre_evt.c index 415c33e..2ccc5d5 100644 --- a/src/mainboard/google/cyan/gpio_pre_evt.c +++ b/src/mainboard/google/cyan/gpio_pre_evt.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include "irqroute.h" diff --git a/src/mainboard/google/cyan/irqroute.c b/src/mainboard/google/cyan/irqroute.c index 83207d9..e993c7f 100644 --- a/src/mainboard/google/cyan/irqroute.c +++ b/src/mainboard/google/cyan/irqroute.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include "irqroute.h" diff --git a/src/mainboard/google/cyan/irqroute.h b/src/mainboard/google/cyan/irqroute.h index 5353d42..c670bee 100644 --- a/src/mainboard/google/cyan/irqroute.h +++ b/src/mainboard/google/cyan/irqroute.h @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <soc/irq.h> diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index b109574..60165e0 100755 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -16,7 +16,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <bootstate.h> diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h index 3539ff4..eb97f8e 100755 --- a/src/mainboard/google/cyan/onboard.h +++ b/src/mainboard/google/cyan/onboard.h @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #ifndef ONBOARD_H diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c index 136d189..7315785 100644 --- a/src/mainboard/google/cyan/ramstage.c +++ b/src/mainboard/google/cyan/ramstage.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <soc/ramstage.h> diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index 22e26b5..0e47d35 100755 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <cbfs.h> diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 5af0421..d6c75f4 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <arch/io.h> diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/spd/Makefile.inc index 40a3e0d..5b85746 100644 --- a/src/mainboard/google/cyan/spd/Makefile.inc +++ b/src/mainboard/google/cyan/spd/Makefile.inc @@ -15,7 +15,7 @@ ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## Foundation, Inc. ## romstage-y += spd.c diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 0ddf5ee..dccbccf 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <cbfs.h> diff --git a/src/mainboard/google/cyan/w25q64.c b/src/mainboard/google/cyan/w25q64.c index 4399d88..3af7b81 100644 --- a/src/mainboard/google/cyan/w25q64.c +++ b/src/mainboard/google/cyan/w25q64.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <soc/spi.h>

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Patch set updated for coreboot: Strago: Remove copyright address
by Leroy P Leahy 24 Jun '15

24 Jun '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10338 -gerrit commit 799f39e3e74ca7a00ddd0332152c00e48fbed62d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed May 27 17:38:14 2015 -0700 Strago: Remove copyright address Remove the copyright address from all of the files. BRANCH=none BUG=None TEST=Build and run on Strago Change-Id: I50d7984d1c498b61cad4f65e4201d2d65590c4e3 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/strago/Makefile.inc | 2 +- src/mainboard/intel/strago/acpi/chromeos.asl | 2 +- src/mainboard/intel/strago/acpi/ec.asl | 2 +- src/mainboard/intel/strago/acpi/mainboard.asl | 3 +-- src/mainboard/intel/strago/acpi/superio.asl | 2 +- src/mainboard/intel/strago/acpi_tables.c | 2 +- src/mainboard/intel/strago/chromeos.c | 2 +- src/mainboard/intel/strago/cmos.layout | 2 +- src/mainboard/intel/strago/com_init.c | 2 +- src/mainboard/intel/strago/dsdt.asl | 2 +- src/mainboard/intel/strago/ec.c | 2 +- src/mainboard/intel/strago/ec.h | 2 +- src/mainboard/intel/strago/fadt.c | 2 +- src/mainboard/intel/strago/gpio.c | 2 +- src/mainboard/intel/strago/irqroute.c | 2 +- src/mainboard/intel/strago/irqroute.h | 2 +- src/mainboard/intel/strago/mainboard.c | 2 +- src/mainboard/intel/strago/onboard.h | 2 +- src/mainboard/intel/strago/ramstage.c | 2 +- src/mainboard/intel/strago/romstage.c | 2 +- src/mainboard/intel/strago/smihandler.c | 2 +- src/mainboard/intel/strago/spd/Makefile.inc | 2 +- src/mainboard/intel/strago/spd/spd.c | 2 +- src/mainboard/intel/strago/w25q64.c | 2 +- 24 files changed, 24 insertions(+), 25 deletions(-) diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index db5189b..8986465 100755 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -15,7 +15,7 @@ ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## Foundation, Inc. ## subdirs-y += spd diff --git a/src/mainboard/intel/strago/acpi/chromeos.asl b/src/mainboard/intel/strago/acpi/chromeos.asl index 7db294d..4ba3857 100644 --- a/src/mainboard/intel/strago/acpi/chromeos.asl +++ b/src/mainboard/intel/strago/acpi/chromeos.asl @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ /* diff --git a/src/mainboard/intel/strago/acpi/ec.asl b/src/mainboard/intel/strago/acpi/ec.asl index baa0d56..e03c180 100755 --- a/src/mainboard/intel/strago/acpi/ec.asl +++ b/src/mainboard/intel/strago/acpi/ec.asl @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ /* mainboard configuration */ diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl index f99781f..c5cddd1 100755 --- a/src/mainboard/intel/strago/acpi/mainboard.asl +++ b/src/mainboard/intel/strago/acpi/mainboard.asl @@ -16,8 +16,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc. */ #include "onboard.h" diff --git a/src/mainboard/intel/strago/acpi/superio.asl b/src/mainboard/intel/strago/acpi/superio.asl index 2db1013..0d4bc2a 100755 --- a/src/mainboard/intel/strago/acpi/superio.asl +++ b/src/mainboard/intel/strago/acpi/superio.asl @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ /* mainboard configuration */ diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index a88abed..d01e65c 100755 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <arch/acpi.h> diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 67e289c..dd91d7a 100755 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <arch/io.h> diff --git a/src/mainboard/intel/strago/cmos.layout b/src/mainboard/intel/strago/cmos.layout index 18bf4ce..b773b09 100644 --- a/src/mainboard/intel/strago/cmos.layout +++ b/src/mainboard/intel/strago/cmos.layout @@ -15,7 +15,7 @@ ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## Foundation, Inc. ## # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c index d34c2df..a15d8c3 100755 --- a/src/mainboard/intel/strago/com_init.c +++ b/src/mainboard/intel/strago/com_init.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <arch/io.h> diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index d888651..50fc0aa 100755 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -16,7 +16,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ DefinitionBlock( diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c index 89d289b..60e80d3 100755 --- a/src/mainboard/intel/strago/ec.c +++ b/src/mainboard/intel/strago/ec.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <arch/acpi.h> diff --git a/src/mainboard/intel/strago/ec.h b/src/mainboard/intel/strago/ec.h index 7e70d48..c5315da 100755 --- a/src/mainboard/intel/strago/ec.h +++ b/src/mainboard/intel/strago/ec.h @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #ifndef MAINBOARD_EC_H diff --git a/src/mainboard/intel/strago/fadt.c b/src/mainboard/intel/strago/fadt.c index 45a680a..9f08240 100755 --- a/src/mainboard/intel/strago/fadt.c +++ b/src/mainboard/intel/strago/fadt.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <soc/acpi.h> diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index a4f60b2..268a613 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include "irqroute.h" diff --git a/src/mainboard/intel/strago/irqroute.c b/src/mainboard/intel/strago/irqroute.c index 83207d9..e993c7f 100644 --- a/src/mainboard/intel/strago/irqroute.c +++ b/src/mainboard/intel/strago/irqroute.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include "irqroute.h" diff --git a/src/mainboard/intel/strago/irqroute.h b/src/mainboard/intel/strago/irqroute.h index 5353d42..c670bee 100644 --- a/src/mainboard/intel/strago/irqroute.h +++ b/src/mainboard/intel/strago/irqroute.h @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <soc/irq.h> diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index b109574..60165e0 100755 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -16,7 +16,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <bootstate.h> diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index 9d4b8b6..df03a18 100755 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #ifndef ONBOARD_H diff --git a/src/mainboard/intel/strago/ramstage.c b/src/mainboard/intel/strago/ramstage.c index 283ea42..ee750dd 100644 --- a/src/mainboard/intel/strago/ramstage.c +++ b/src/mainboard/intel/strago/ramstage.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <soc/ramstage.h> diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index 22e26b5..0e47d35 100755 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <cbfs.h> diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index 5af0421..d6c75f4 100755 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <arch/io.h> diff --git a/src/mainboard/intel/strago/spd/Makefile.inc b/src/mainboard/intel/strago/spd/Makefile.inc index 4b4bff6..0c3d7c9 100755 --- a/src/mainboard/intel/strago/spd/Makefile.inc +++ b/src/mainboard/intel/strago/spd/Makefile.inc @@ -15,7 +15,7 @@ ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## Foundation, Inc. ## romstage-y += spd.c diff --git a/src/mainboard/intel/strago/spd/spd.c b/src/mainboard/intel/strago/spd/spd.c index 9951708..8ea0078 100755 --- a/src/mainboard/intel/strago/spd/spd.c +++ b/src/mainboard/intel/strago/spd/spd.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <cbfs.h> diff --git a/src/mainboard/intel/strago/w25q64.c b/src/mainboard/intel/strago/w25q64.c index 4399d88..3af7b81 100755 --- a/src/mainboard/intel/strago/w25q64.c +++ b/src/mainboard/intel/strago/w25q64.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <soc/spi.h>

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coreboot-gerrit June 2015