coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: rockchip/rk3288: complete vboot configuration and move to SoC
by Patrick Georgi 25 Jun '15

25 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10662 -gerrit commit 9ca83c9453c9f0b719db3d6f7d33dd9b50e51693 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Jun 25 17:04:31 2015 +0200 rockchip/rk3288: complete vboot configuration and move to SoC Where vboot verification can start, and how the code flow looks like is more a property of the SoC (and its properties, like amount of SRAM) rather than the board. Change-Id: I610153ea4ceddc226d8cc3e17a515e41fc0479cf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/veyron_brain/Kconfig | 1 - src/mainboard/google/veyron_danger/Kconfig | 1 - src/mainboard/google/veyron_jerry/Kconfig | 1 - src/mainboard/google/veyron_mickey/Kconfig | 1 - src/mainboard/google/veyron_mighty/Kconfig | 1 - src/mainboard/google/veyron_pinky/Kconfig | 1 - src/mainboard/google/veyron_rialto/Kconfig | 1 - src/mainboard/google/veyron_romy/Kconfig | 1 - src/mainboard/google/veyron_speedy/Kconfig | 1 - src/soc/rockchip/rk3288/Kconfig | 3 +++ 10 files changed, 3 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig index 76790e7..2391660 100644 --- a/src/mainboard/google/veyron_brain/Kconfig +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS select RAM_CODE_SUPPORT - select RETURN_FROM_VERSTAGE select SOC_ROCKCHIP_RK3288 select SPI_FLASH select SPI_FLASH_GIGADEVICE diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index 2dba2f6..5a41690 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS select RAM_CODE_SUPPORT - select RETURN_FROM_VERSTAGE select SOC_ROCKCHIP_RK3288 select SPI_FLASH select SPI_FLASH_GIGADEVICE diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron_jerry/Kconfig index fa66979..3e65e67 100644 --- a/src/mainboard/google/veyron_jerry/Kconfig +++ b/src/mainboard/google/veyron_jerry/Kconfig @@ -33,7 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select BOARD_ROMSIZE_KB_4096 select HAVE_HARD_RESET - select RETURN_FROM_VERSTAGE select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index d316b6a..d40cbae 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS select RAM_CODE_SUPPORT - select RETURN_FROM_VERSTAGE select SOC_ROCKCHIP_RK3288 select SPI_FLASH select SPI_FLASH_GIGADEVICE diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig index 6f4d012..90cdbb5 100644 --- a/src/mainboard/google/veyron_mighty/Kconfig +++ b/src/mainboard/google/veyron_mighty/Kconfig @@ -33,7 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select BOARD_ROMSIZE_KB_4096 select HAVE_HARD_RESET - select RETURN_FROM_VERSTAGE select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index e681e62..4b0d471 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -33,7 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select BOARD_ROMSIZE_KB_4096 select HAVE_HARD_RESET - select RETURN_FROM_VERSTAGE select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 09098c1..30c54f6 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS select RAM_CODE_SUPPORT - select RETURN_FROM_VERSTAGE select SOC_ROCKCHIP_RK3288 select SPI_FLASH select SPI_FLASH_GIGADEVICE diff --git a/src/mainboard/google/veyron_romy/Kconfig b/src/mainboard/google/veyron_romy/Kconfig index f96a3e9..4734520 100644 --- a/src/mainboard/google/veyron_romy/Kconfig +++ b/src/mainboard/google/veyron_romy/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS select RAM_CODE_SUPPORT - select RETURN_FROM_VERSTAGE select SOC_ROCKCHIP_RK3288 select SPI_FLASH select SPI_FLASH_GIGADEVICE diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig index 2ef7cd6..d4003dc 100644 --- a/src/mainboard/google/veyron_speedy/Kconfig +++ b/src/mainboard/google/veyron_speedy/Kconfig @@ -33,7 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS select HAVE_HARD_RESET - select RETURN_FROM_VERSTAGE select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 1b82515..3a4712e 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -31,6 +31,9 @@ config SOC_ROCKCHIP_RK3288 select UNCOMPRESSED_RAMSTAGE select GENERIC_GPIO_LIB select RTC + select VBOOT_STARTS_IN_BOOTBLOCK + select SEPARATE_VERSTAGE + select RETURN_FROM_VERSTAGE if SOC_ROCKCHIP_RK3288

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New patch to review for coreboot: google/chromeos: always enable VBOOT_VERIFY_FIRMWARE with CHROMEOS
by Patrick Georgi 25 Jun '15

25 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10661 -gerrit commit f6d0370e11d5d95f689b6e6244268fc3b8cb7996 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Jun 25 17:01:26 2015 +0200 google/chromeos: always enable VBOOT_VERIFY_FIRMWARE with CHROMEOS Change-Id: Icc3cf64f259d4ebd7900ad91163276774e5422ab Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/vendorcode/google/chromeos/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index b9530f9..51a04ed 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -31,6 +31,7 @@ config CHROMEOS select BOOTMODE_STRAPS select ELOG select COLLECT_TIMESTAMPS + select VBOOT_VERIFY_FIRMWARE help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported @@ -129,7 +130,7 @@ config VIRTUAL_DEV_SWITCH config VBOOT_VERIFY_FIRMWARE bool "Verify firmware with vboot." default n - depends on CHROMEOS && HAVE_HARD_RESET + depends on HAVE_HARD_RESET help Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the components of the firmware (stages, payload, etc).

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New patch to review for coreboot: vboot: Init vb2 work memory area before calling verstage
by Patrick Georgi 25 Jun '15

25 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10660 -gerrit commit fa0606a3d1faa1b33b4d7b925bac221f16865274 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Jun 25 16:57:57 2015 +0200 vboot: Init vb2 work memory area before calling verstage Otherwise it'll determine some offsets from uninitialized data and hilarity ensues. Change-Id: I6a671987857cfd3f3cd6078aebd13dd09fc79020 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/vendorcode/google/chromeos/vboot2/vboot_loader.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c index cbb5f89..d6e760a 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c @@ -90,6 +90,7 @@ static int vboot_active(struct asset *asset) init_vb2_working_data(); verstage_main(); } else if (verstage_should_load()) { + init_vb2_working_data(); struct prog verstage = PROG_INIT(ASSET_VERSTAGE, CONFIG_CBFS_PREFIX "/verstage");

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New patch to review for coreboot: google/veyron_speedy: Add chromeos.c to romstage
by Patrick Georgi 25 Jun '15

25 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10659 -gerrit commit d952ab43d6249fb4a85106413e3fe85468f7b7ff Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Jun 25 14:31:41 2015 +0200 google/veyron_speedy: Add chromeos.c to romstage vboot requires it. Change-Id: Iae2310c9b9c311c3f64b8417295685261ba404b0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/veyron_speedy/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/veyron_speedy/Makefile.inc b/src/mainboard/google/veyron_speedy/Makefile.inc index a027c6d..ea1c606 100644 --- a/src/mainboard/google/veyron_speedy/Makefile.inc +++ b/src/mainboard/google/veyron_speedy/Makefile.inc @@ -26,6 +26,7 @@ verstage-y += chromeos.c verstage-y += reset.c romstage-y += boardid.c +romstage-y += chromeos.c romstage-y += romstage.c romstage-y += sdram_configs.c romstage-y += reset.c

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Patch set updated for coreboot: Store the payload config and revision in CBFS
by Martin Roth 25 Jun '15

25 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10607 -gerrit commit 823b6132bec8b8e54901d004d589ce059c2a4e74 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 20:50:59 2015 -0600 Store the payload config and revision in CBFS Store the payload .config and version.c files in CBFS if using a SeaBIOS or filo payload if INCLUDE_CONFIG_FILE is enabled. Change-Id: I0c1b4da8f6179b9cee06cecfa76bc631b43196e0 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile.inc | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 2f1fe82..5ee785f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -110,6 +110,17 @@ dir-wildcards=$(addsuffix %,$(1)) # files-in-dir,dir,files files-in-dir=$(filter-out $(call dir-wildcards,$(call filter-out-dirs,$(1),$(sort $(dir $(2))))),$(call files-in-dir-recursive,$(1),$(2))) +###################################################################### +# set up payload config and version files for later inclusion +ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) +PAYLOAD_CONFIG=payloads/external/SeaBIOS/seabios/.config +PAYLOAD_VERSION=payloads/external/SeaBIOS/seabios/out/version.c +endif +ifeq ($(CONFIG_PAYLOAD_FILO),y) +PAYLOAD_CONFIG=payloads/external/FILO/filo/.config +PAYLOAD_VERSION=payloads/external/FILO/filo/build/version.h +endif + ####################################################################### # reduce command line length by linking the objects of each # directory into an intermediate file @@ -636,6 +647,16 @@ ifeq ($(CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD),y) $(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) endif endif +ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) + @printf " CONFIG $(PAYLOAD_CONFIG)\n" + if [ -f "$(PAYLOAD_CONFIG)" ]; then \ + $(CBFSTOOL) $@.tmp add -f "$(PAYLOAD_CONFIG)" -n payload_config -t raw; \ + fi + @printf " REVISION $(PAYLOAD_VERSION)\n" + if [ -f "$(PAYLOAD_VERSION)" ]; then \ + $(CBFSTOOL) $@.tmp add -f "$(PAYLOAD_VERSION)" -n payload_revision -t raw; \ + fi +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print

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Patch set updated for coreboot: mainboard/msi/ms7135: DSDT: fix PCI and AGR interrupts
by Jonathan A. Kollasch 25 Jun '15

25 Jun '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10644 -gerrit commit f9e710a1a166320209422d5a8c3cdce059960279 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Jun 23 10:00:41 2015 -0500 mainboard/msi/ms7135: DSDT: fix PCI and AGR interrupts Tested with interrupting AGP card in AGR slot. PCI slots tested with 3-function OHCI/EHCI USB 2.0 card, covering the INTA-INTC lines in each. Change-Id: I0f8aeba90890a76a7cf9cbee9be7bcf919d1e39a Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/msi/ms7135/dsdt.asl | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/src/mainboard/msi/ms7135/dsdt.asl b/src/mainboard/msi/ms7135/dsdt.asl index 4dbbd3d..eba0ffd 100644 --- a/src/mainboard/msi/ms7135/dsdt.asl +++ b/src/mainboard/msi/ms7135/dsdt.asl @@ -102,11 +102,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 }, Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 }, - Package (0x04) { 0x0009FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0009FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0009FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0009FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 }, Package (0x04) { 0x000BFFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, @@ -135,11 +130,30 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) Name (_ADR, 0x00090000) Name (_UID, 0x00) Name (_PRT, Package () { - /* AGR slot */ - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + /* AGR slot "AGP1" */ + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + + /* PCI slot "PCI1" */ + Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0007FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0007FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + /* Not sure INTD is right, but this is what the OEM BIOS does. */ + Package (0x04) { 0x0007FFFF, 0x03, \_SB.PCI0.LNKE, 0x00 }, + + /* PCI slot "PCI2" */ + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, + + /* PCI slot "PCI3" */ + Package (0x04) { 0x0009FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, }) }

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Patch set updated for coreboot: Store the payload config and revision in CBFS
by Martin Roth 25 Jun '15

25 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10607 -gerrit commit b8e6529dfb734e5ae7fe5a7d02cf374f2c849728 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 20:50:59 2015 -0600 Store the payload config and revision in CBFS Store the payload .config and version.c files in CBFS if using a SeaBIOS or filo payload if INCLUDE_CONFIG_FILE is enabled. Change-Id: I0c1b4da8f6179b9cee06cecfa76bc631b43196e0 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile.inc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 2f1fe82..d017e19 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -110,6 +110,17 @@ dir-wildcards=$(addsuffix %,$(1)) # files-in-dir,dir,files files-in-dir=$(filter-out $(call dir-wildcards,$(call filter-out-dirs,$(1),$(sort $(dir $(2))))),$(call files-in-dir-recursive,$(1),$(2))) +###################################################################### +# set up payload config and version files for later inclusion +ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) +PAYLOAD_CONFIG=payloads/external/SeaBIOS/seabios/.config +PAYLOAD_VERSION=payloads/external/SeaBIOS/seabios/out/version.c +endif +ifeq ($(CONFIG_PAYLOAD_FILO),y) +PAYLOAD_CONFIG=payloads/external/FILO/filo/.config +PAYLOAD_VERSION=payloads/external/FILO/filo/build/version.h +endif + ####################################################################### # reduce command line length by linking the objects of each # directory into an intermediate file @@ -636,6 +647,13 @@ ifeq ($(CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD),y) $(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) endif endif +ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) + @printf " CONFIG $(PAYLOAD_CONFIG)\n" + if [ -f "$(PAYLOAD_CONFIG)" ]; then \ + $(CBFSTOOL) $@.tmp add -f "$(PAYLOAD_CONFIG)" -n payload_config -t raw ; fi + @printf " REVISION $(PAYLOAD_VERSION)\n" + if [ -f "$(PAYLOAD_VERSION)" ]; then $(CBFSTOOL) $@.tmp add -f "$(PAYLOAD_VERSION)" -n payload_revision -t raw; fi +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print

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New patch to review for coreboot: Makefile.inc: Clean up SeaBIOS clean command line
by Martin Roth 25 Jun '15

25 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10656 -gerrit commit 68ebb24714e134cdade234127f14fd94096dc4fc Author: Martin Roth <gaumless(a)gmail.com> Date: Wed Jun 24 20:03:08 2015 -0600 Makefile.inc: Clean up SeaBIOS clean command line Passing the argments to the sub-make is no longer needed. Change-Id: Ie4fa3e36c2911eb25f201506df0e79b415d3e9b9 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 2f1fe82..eb5cc65 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -381,7 +381,7 @@ clean-for-update-target: rm -f $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.* rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm - $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean OUT=$(abspath $(obj)) HOSTCC="$(HOSTCC)" CC="$(CC_x86_32)" LD="$(LD_x86_32)" + $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean clean-target: rm -f $(obj)/coreboot*

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Patch set updated for coreboot: SeaBIOS: Rename Makefile.inc to Makefile
by Martin Roth 25 Jun '15

25 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10605 -gerrit commit e18413e9bacf5de2364c6fd4c63bdedf2df5b2eb Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 20:20:27 2015 -0600 SeaBIOS: Rename Makefile.inc to Makefile The payloads/external/SeaBIOS/Makefile.inc is not actually included in the rest of the coreboot Makefile tree, it's called out explicitly when doing the build. Because of this, the standard CONFIG_ variables need to be passed to it on the command line instead of just being available. Since it's named .inc, it would be expected that similar to other Makefile.inc files, these would just be available for use. Change-Id: I64de18f9e0d88d188705b53921e9e12c2f37f71d Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile.inc | 2 +- payloads/external/SeaBIOS/Makefile | 61 ++++++++++++++++++++++++++++++++++ payloads/external/SeaBIOS/Makefile.inc | 61 ---------------------------------- src/arch/x86/Makefile.inc | 2 +- 4 files changed, 63 insertions(+), 63 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index eb5cc65..783d172 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -381,7 +381,7 @@ clean-for-update-target: rm -f $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.* rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm - $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean + $(MAKE) -C payloads/external/SeaBIOS -f Makefile clean clean-target: rm -f $(obj)/coreboot* diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile new file mode 100644 index 0000000..7fb63d4 --- /dev/null +++ b/payloads/external/SeaBIOS/Makefile @@ -0,0 +1,61 @@ +TAG-$(CONFIG_SEABIOS_MASTER)=origin/master +TAG-$(CONFIG_SEABIOS_STABLE)=e51488c5f8800a52ac5c8da7a31b85cca5cc95d2 + +unexport KCONFIG_AUTOHEADER +unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES + +all: build + +seabios: + echo " Cloning SeaBIOS from Git" + git clone http://review.coreboot.org/p/seabios.git seabios + +fetch: seabios + cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ + then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi + +checkout: fetch + echo " Checking out SeaBIOS revision $(TAG-y)" + cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + +config: checkout + echo " CONFIG SeaBIOS $(TAG-y)" + echo "CONFIG_COREBOOT=y" > seabios/.config +ifeq ($(CONFIG_CONSOLE_SERIAL),y) + echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config + echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config +else + echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config +endif +ifneq ($(CONFIG_SEABIOS_MALLOC_UPPERMEMORY),y) + echo "# CONFIG_MALLOC_UPPERMEMORY is not set" >> seabios/.config +endif +ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) + echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config +endif +ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) + echo "CONFIG_VGA_COREBOOT=y" >> seabios/.config + echo "CONFIG_BUILD_VGABIOS=y" >> seabios/.config +endif + # This shows how to force a previously set .config option *off* + #echo "# CONFIG_SMBIOS is not set" >> seabios/.config + $(MAKE) -C seabios olddefconfig OUT=out/ + +build: config + echo " MAKE SeaBIOS $(TAG-y)" + export VERSION=$$(cd seabios && \ + git describe --tags --long --dirty 2>/dev/null || \ + echo "unknown") ; \ + $(MAKE) -C seabios OUT=out/ + +clean: + test -d seabios/out && rm -rf seabios/out || exit 0 + +distclean: + rm -rf seabios + +.PHONY: checkout config build clean distclean clone fetch diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc deleted file mode 100644 index 7fb63d4..0000000 --- a/payloads/external/SeaBIOS/Makefile.inc +++ /dev/null @@ -1,61 +0,0 @@ -TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=e51488c5f8800a52ac5c8da7a31b85cca5cc95d2 - -unexport KCONFIG_AUTOHEADER -unexport KCONFIG_AUTOCONFIG -unexport KCONFIG_DEPENDENCIES -unexport KCONFIG_SPLITCONFIG -unexport KCONFIG_TRISTATE -unexport KCONFIG_NEGATIVES - -all: build - -seabios: - echo " Cloning SeaBIOS from Git" - git clone http://review.coreboot.org/p/seabios.git seabios - -fetch: seabios - cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ - then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi - -checkout: fetch - echo " Checking out SeaBIOS revision $(TAG-y)" - cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) - -config: checkout - echo " CONFIG SeaBIOS $(TAG-y)" - echo "CONFIG_COREBOOT=y" > seabios/.config -ifeq ($(CONFIG_CONSOLE_SERIAL),y) - echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config - echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config -else - echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config -endif -ifneq ($(CONFIG_SEABIOS_MALLOC_UPPERMEMORY),y) - echo "# CONFIG_MALLOC_UPPERMEMORY is not set" >> seabios/.config -endif -ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) - echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config -endif -ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) - echo "CONFIG_VGA_COREBOOT=y" >> seabios/.config - echo "CONFIG_BUILD_VGABIOS=y" >> seabios/.config -endif - # This shows how to force a previously set .config option *off* - #echo "# CONFIG_SMBIOS is not set" >> seabios/.config - $(MAKE) -C seabios olddefconfig OUT=out/ - -build: config - echo " MAKE SeaBIOS $(TAG-y)" - export VERSION=$$(cd seabios && \ - git describe --tags --long --dirty 2>/dev/null || \ - echo "unknown") ; \ - $(MAKE) -C seabios OUT=out/ - -clean: - test -d seabios/out && rm -rf seabios/out || exit 0 - -distclean: - rm -rf seabios - -.PHONY: checkout config build clean distclean clone fetch diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index eaab2de..c5b92d4 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -327,7 +327,7 @@ endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 ################################################################################ seabios: - $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ + $(MAKE) -C payloads/external/SeaBIOS -f Makefile \ HOSTCC="$(HOSTCC)" \ CC=$(word 1,$(CC_x86_32)) CFLAGS="$(patsubst $(word 1,$(CC_x86_32))%,,$(CC_x86_32))" \ LD=$(word 1,$(LD_x86_32)) LDFLAGS="$(patsubst $(word 1,$(LD_x86_32))%,,$(LD_x86_32))" \

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Patch set updated for coreboot: SeaBIOS: Change clean to just 'rm -rf seabios/out'
by Martin Roth 25 Jun '15

25 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10655 -gerrit commit 86979348098f03031d8600a662ae68a67edcfcc5 Author: Martin Roth <gaumless(a)gmail.com> Date: Wed Jun 24 19:43:17 2015 -0600 SeaBIOS: Change clean to just 'rm -rf seabios/out' When running 'make clean' if the seabios directory is present, we get warnings about not having IASL installed or that the C compiler can't be executed. It fails to actually run the clean because we're not correctly passing in the toolchain. Just do what the SeaBIOS clean does directly and delete the 'out' directory without actually calling the SeaBIOS clean. Here were the previous warnings: % make clean Unable to execute the C compiler (). Please install a working compiler and retry. Makefile:104: *** "Please upgrade the build environment". Stop. or % make clean The SeaBIOS project requires the 'iasl' package be installed. Many Linux distributions have this package. Try: sudo yum install iasl Or: sudo apt-get install iasl Please install iasl and retry. Makefile:106: *** "Please upgrade the build environment". Stop. Change-Id: Ice41376bc242f1f622d849e7628f8a9b6ef47404 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 087b723..7fb63d4 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -53,7 +53,7 @@ build: config $(MAKE) -C seabios OUT=out/ clean: - test -d seabios && $(MAKE) -C seabios clean OUT=out/ || exit 0 + test -d seabios/out && rm -rf seabios/out || exit 0 distclean: rm -rf seabios

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coreboot-gerrit June 2015