coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

1 participants
1226 discussions

Patch set updated for coreboot: Braswell: Remove copyright address
by Leroy P Leahy 24 Jun '15

24 Jun '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10337 -gerrit commit 78bef8d7a6d49dea335b86479c47af257a58ba80 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed May 27 16:51:59 2015 -0700 Braswell: Remove copyright address Remove the copyright address from all of the files. BRANCH=none BUG=None TEST=None Change-Id: I7190e34e165e5652d33902440fa08253b77f4af2 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/braswell/include/soc/pei_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/braswell/include/soc/pei_data.h b/src/soc/intel/braswell/include/soc/pei_data.h index d9e5a67..67e34f7 100644 --- a/src/soc/intel/braswell/include/soc/pei_data.h +++ b/src/soc/intel/braswell/include/soc/pei_data.h @@ -1,5 +1,5 @@ /* - * Broadwell UEFI PEI wrapper + * Braswell UEFI PEI wrapper * * Copyright (C) 2014 Google Inc. *

1 0

Patch set updated for coreboot: intel raminit: properly handle DDR3 DIMMs with address mirroring
by Patrick Rudolph 24 Jun '15

24 Jun '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10652 -gerrit commit a6b0cf98bf425f0a8547e3daac82ffb14deaa616 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Jun 24 19:14:53 2015 +0200 intel raminit: properly handle DDR3 DIMMs with address mirroring Issue observed: DDR3 DIMM with address mirroring enabled doesn't work when placed in slot 1 and slot 0 is empty. It does work when placed in slot 0 and slot 1 is empty. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H * Kingston KVR1066D3N7/4G (address mirroring enabled DIMM) Problem description: The address mirror enable bit is slot-swapped in the DIMM mapping code, but none of the remaining code is aware of DIMM mapping. Removing the code, that is swapping the mirror enable bit, results in the correct behaviour. The DIMM is now working in every slot. Change-Id: I7a51bbc8d156209449fd67c954930835814a40ee Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index a569411..e567cce 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -812,7 +812,6 @@ static void dram_timing_regs(ramctr_timing * ctrl) static void dram_dimm_mapping(dimm_info * info, ramctr_timing * ctrl) { - int t; u32 reg, val32; int channel; @@ -832,11 +831,6 @@ static void dram_dimm_mapping(dimm_info * info, ramctr_timing * ctrl) dimmA = &info->dimm[channel][1]; dimmB = &info->dimm[channel][0]; reg |= (1 << 16); - // swap dimm info - t = ctrl->rank_mirror[channel][1]; - ctrl->rank_mirror[channel][1] = - ctrl->rank_mirror[channel][3]; - ctrl->rank_mirror[channel][3] = t; } // dimmA if (dimmA && (dimmA->ranks > 0)) { @@ -1231,6 +1225,9 @@ static void write_mrreg(ramctr_timing * ctrl, int channel, int slotrank, printram("MRd: %x <= %x\n", reg, val); if (ctrl->rank_mirror[channel][slotrank]) { + /* DDR3 Rank1 Address mirror + * swap the following pins: + * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ reg = ((reg >> 1) & 1) | ((reg << 1) & 2); val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1);

1 0

Patch set updated for coreboot: intel native raminit: properly handle DDR3 DIMMs with address mirroring
by Patrick Rudolph 24 Jun '15

24 Jun '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10652 -gerrit commit 3494de7b548e2ff0a8d0e3c6f3bac0c6df8b47f5 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Jun 24 19:14:53 2015 +0200 intel native raminit: properly handle DDR3 DIMMs with address mirroring Issue observed: DDR3 DIMM with address mirroring enabled doesn't work when placed in slot 1 and slot 0 is empty. It does work when placed in slot 0 and slot 1 is empty. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H * Kingston KVR1066D3N7/4G (address mirroring enabled DIMM) Problem description: The address mirror enable bit is slot-swapped in the DIMM mapping code, but none of the remaining code is aware of DIMM mapping. Removing the code, that is swapping the mirror enable bit, results in the correct behaviour. The DIMM is now working in every slot. Change-Id: I7a51bbc8d156209449fd67c954930835814a40ee Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index a569411..e567cce 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -812,7 +812,6 @@ static void dram_timing_regs(ramctr_timing * ctrl) static void dram_dimm_mapping(dimm_info * info, ramctr_timing * ctrl) { - int t; u32 reg, val32; int channel; @@ -832,11 +831,6 @@ static void dram_dimm_mapping(dimm_info * info, ramctr_timing * ctrl) dimmA = &info->dimm[channel][1]; dimmB = &info->dimm[channel][0]; reg |= (1 << 16); - // swap dimm info - t = ctrl->rank_mirror[channel][1]; - ctrl->rank_mirror[channel][1] = - ctrl->rank_mirror[channel][3]; - ctrl->rank_mirror[channel][3] = t; } // dimmA if (dimmA && (dimmA->ranks > 0)) { @@ -1231,6 +1225,9 @@ static void write_mrreg(ramctr_timing * ctrl, int channel, int slotrank, printram("MRd: %x <= %x\n", reg, val); if (ctrl->rank_mirror[channel][slotrank]) { + /* DDR3 Rank1 Address mirror + * swap the following pins: + * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ reg = ((reg >> 1) & 1) | ((reg << 1) & 2); val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1);

1 0

New patch to review for coreboot: raminit native: properly handle DDR3 DIMMs with address mirroring
by Patrick Rudolph 24 Jun '15

24 Jun '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10652 -gerrit commit 923433711da066cc7dd7e50ce065bf6cb065e74f Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Jun 24 19:14:53 2015 +0200 raminit native: properly handle DDR3 DIMMs with address mirroring Issue observed: DDR3 DIMM with address mirroring enabled doesn't work when placed in slot 1 and slot 0 is empty. It does work when placed in slot 0 and slot 1 is empty. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H * Kingston KVR1066D3N7/4G (address mirroring enabled DIMM) Problem description: The address mirror enable bit is slot-swapped in the DIMM mapping code, but none of the remaining code is aware of DIMM mapping. Removing the code, that is swapping the mirror enable bit, results in the correct behaviour. The DIMM is now working in every slot. Change-Id: I7a51bbc8d156209449fd67c954930835814a40ee Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index a569411..0fda94d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -832,11 +832,6 @@ static void dram_dimm_mapping(dimm_info * info, ramctr_timing * ctrl) dimmA = &info->dimm[channel][1]; dimmB = &info->dimm[channel][0]; reg |= (1 << 16); - // swap dimm info - t = ctrl->rank_mirror[channel][1]; - ctrl->rank_mirror[channel][1] = - ctrl->rank_mirror[channel][3]; - ctrl->rank_mirror[channel][3] = t; } // dimmA if (dimmA && (dimmA->ranks > 0)) { @@ -1231,6 +1226,9 @@ static void write_mrreg(ramctr_timing * ctrl, int channel, int slotrank, printram("MRd: %x <= %x\n", reg, val); if (ctrl->rank_mirror[channel][slotrank]) { + /* DDR3 Rank1 Address mirror + * swap the following pins: + * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ reg = ((reg >> 1) & 1) | ((reg << 1) & 2); val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1);

1 0

Patch merged into coreboot/master: Intel/common: Remove copyright address
by gerrit＠coreboot.org 24 Jun '15

24 Jun '15

the following patch was just integrated into master: commit 40c0543108ed0500b2aaf8db849190105696b466 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed May 27 17:25:47 2015 -0700 Intel/common: Remove copyright address Remove the copyright address from the remaining files. BRANCH=none BUG=None TEST=None Change-Id: I026a0ff2bcb6c9580b45700edab446b787223007 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/10336 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10336 for details. -gerrit

1 0

Patch merged into coreboot/master: Intel Common SOC: Add romstage support
by gerrit＠coreboot.org 24 Jun '15

24 Jun '15

the following patch was just integrated into master: commit 0946ec37aa4660ecf16d66cb1174a68df0afc4f0 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Apr 20 15:24:54 2015 -0700 Intel Common SOC: Add romstage support Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10050 for details. -gerrit

1 0

Patch merged into coreboot/master: FSP 1.1: Bring source up-to-date
by gerrit＠coreboot.org 24 Jun '15

24 Jun '15

the following patch was just integrated into master: commit 4a8c19cc90464ad215395bd116c9dc95fc682cac Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jun 16 14:33:30 2015 -0700 FSP 1.1: Bring source up-to-date Use 3rdparty/blobs subdirectory for binary files Display the MTRRs after TempRamExit and before the MTRR setup Clear all of the variable MTRRs before the MTRR setup Define the FSP attributes location and bits Properly display the FSP_RESERVED_MEMORY_RESOURCE_HOB and the FSP_BOOTLOADER_TOLUM_HOB. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I788a5f1e7676b1a06c1bcd66ddbd0a2249cad47c Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/10589 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10589 for details. -gerrit

1 0

Patch merged into coreboot/master: cpu/x86: Add more MTRR symbols
by gerrit＠coreboot.org 24 Jun '15

24 Jun '15

the following patch was just integrated into master: commit bfdf2489f071d8ee1d1c510e503b488526111eb7 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jun 18 10:55:19 2015 -0700 cpu/x86: Add more MTRR symbols BRANCH=none BUG=None TEST=Build and run on strago Change-Id: Ia3740353eb16f2a2192cad8c45645f845bf39475 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/10588 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10588 for details. -gerrit

1 0

Patch merged into coreboot/master: Intel vendorcode: Add FSP_SMBIOS_MEMORY_INFO_GUID
by gerrit＠coreboot.org 24 Jun '15

24 Jun '15

the following patch was just integrated into master: commit edf0d58fffeadb1b813594b1e6ce96c0b4257288 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jun 18 10:45:21 2015 -0700 Intel vendorcode: Add FSP_SMBIOS_MEMORY_INFO_GUID Add new GUID for FSP. BRANCH=none BUG=None TEST=Build and run on strago Change-Id: I539a59b513f67535436f581e0a79ab53f05682ca Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/10587 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10587 for details. -gerrit

1 0

Patch set updated for coreboot: amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0
by Zheng Bao 24 Jun '15

24 Jun '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10651 -gerrit commit 7a97745766f7ef8291cf72a09eb6f2fde42788d8 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Jun 17 20:03:29 2015 -0400 amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0 Besides the first five DWORDs, the offsets 0x40 & 0x41 are used to save SPI settings. They should only be 0xFF for being written. Other parts in ROMSIG are also changed to 0xFF for potential requirement. Change-Id: I61ea8295d5ee8ffbbd0cfcf9e4bece770d70e1f2 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index ccca421..235ce1e 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -116,7 +116,7 @@ $(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ $(obj)/config.h echo " Hudson FW $@" - dd if=/dev/zero of=$@ count=$(ROMSIG_SIZE) ibs=1 status=noxfer 2>/dev/null; \ + printf %d $(ROMSIG_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@; \ for fwm in 1437226410 \ $(HUDSON_IMC_POSITION) \ $(HUDSON_GEC_POSITION) \

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2015