Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9528
-gerrit
commit 9affe848d1d4a01b8be5c79aa53002100705d08f
Author: Tom Warren <twarren(a)nvidia.com>
Date: Wed Nov 19 16:26:41 2014 -0700
tegra132: Increase size of bootblock due to overflow
The bootblock on Rush had bumped up into the verstage
allocation, causing the build to break. Reduced verstage from
60K to 58K and increased bootblock from 20K to 22K. Rush and
Ryu both build fine now.
BUG=none
BRANCH=none
TEST=Built both Rush and Ryu OK. Verifed verstage size
using cbfstool and it's around 55K, so plenty of room.
Change-Id: Iaa3a5838c5235ec78c740a977bc032d8b5e270ef
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 928a4d2d1efabe1e1d6a7fadc22ee0ac4269190e
Original-Change-Id: I7018f027d72d5e8aeb894857a5ac6a0bdc1de388
Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/230824
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 3e2f246..5f45911 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -38,6 +38,8 @@ SECTIONS
STACK(0x40018000, 2K)
BOOTBLOCK(0x40019000, 20K)
VERSTAGE(0x4001E000, 60K)
+ BOOTBLOCK(0x40019000, 22K)
+ VERSTAGE(0x4001E800, 58K)
ROMSTAGE(0x4002D000, 76K)
SRAM_END(0x40040000)
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9529
-gerrit
commit c7f5bdc75ad6c50a319501507bc429fadf27e0c0
Author: Jimmy Zhang <jimmzhang(a)nvidia.com>
Date: Thu Nov 20 15:43:04 2014 -0800
google/rush_ryu: Remove long delay when turning on AVDD_DSI_CSI
Based on TPS65913, the max LDO turn on time is 500us. Since it is requested
the default delay of 500us when calling function pmic_write_reg(), it is
safe to remove this 100ms delay.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Change-Id: I2cfda38728db223c26f9122b70d37e828921459a
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 271b7e95f66f4b8611a0d408e59f428c315074f3
Original-Change-Id: I53aecc273484edfa502231b44f6bcd7f5d8f9331
Original-Reviewed-on: https://chromium-review.googlesource.com/231170
Original-Tested-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Jimmy Zhang <jimmzhang(a)nvidia.com>
---
src/mainboard/google/rush_ryu/mainboard.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c
index 81c15b4..9673aa5 100644
--- a/src/mainboard/google/rush_ryu/mainboard.c
+++ b/src/mainboard/google/rush_ryu/mainboard.c
@@ -123,8 +123,6 @@ static int enable_lcd_vdd(void)
VSEL_1200, 1);
pmic_write_reg(I2CPWR_BUS, TI65913_LDO5_CTRL,
TI65913_MODE_ACTIVE_ON, 1);
- /* wait for 100ms */
- mdelay(100);
/*
* Enable VDD_LCD
Sergej Ivanov (getinaks(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9291
-gerrit
commit 2598056fd1687c820ecba44d9dabbf0e3e4b64b5
Author: Sergej Ivanov <getinaks(a)gmail.com>
Date: Fri Apr 3 16:53:49 2015 +0300
vendorcode/amd/agesa/f16kb: Enable support for AM1 socket
Adds option FORCE_AM1_SOCKET_SUPPORT to disable
package type mismatch check between cpu and northbridge.
Default agesa for kabini doesn't know about AM1 socket
so it returns FALSE, that stops memory config code.
With this hack current agesa version supports the AM1 socket.
Change-Id: I99e9cec5cd558087092cf195094df20489f6d3b5
Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com>
---
src/cpu/amd/agesa/family16kb/Kconfig | 11 +++++++++++
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c | 5 ++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig
index d36652b..d22a09d 100644
--- a/src/cpu/amd/agesa/family16kb/Kconfig
+++ b/src/cpu/amd/agesa/family16kb/Kconfig
@@ -62,4 +62,15 @@ config HIGH_SCRATCH_MEMORY_SIZE
# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
default 0xA1000
+config FORCE_AM1_SOCKET_SUPPORT
+ bool
+ default n
+ help
+ Force AGESA to ignore package type mismatch between CPU and northbridge
+ in memory code. This enables Socket AM1 support with current AGESA
+ version for Kabini platform.
+ Enable this option only if you have Socket AM1 board.
+ Note that the AGESA release shipped with coreboot does not officially
+ support the AM1 socket. Selecting this option might damage your hardware.
+
endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
index 348f704..b4a60a1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
@@ -489,7 +489,10 @@ MemPIsIdSupported (
return TRUE;
}
}
- return FALSE;
+ if (IS_ENABLED(CONFIG_FORCE_AM1_SOCKET_SUPPORT))
+ return TRUE;
+ else
+ return FALSE;
}
/* -----------------------------------------------------------------------------*/