Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9529
-gerrit
commit 28a7510ffb4235d45f712389b7b06c31677ed9ea
Author: Jimmy Zhang <jimmzhang(a)nvidia.com>
Date: Thu Nov 20 15:43:04 2014 -0800
google/rush_ryu: Remove long delay when turning on AVDD_DSI_CSI
Based on TPS65913, the max LDO turn on time is 500us. Since it is requested
the default delay of 500us when calling function pmic_write_reg(), it is
safe to remove this 100ms delay.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Change-Id: I2cfda38728db223c26f9122b70d37e828921459a
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 271b7e95f66f4b8611a0d408e59f428c315074f3
Original-Change-Id: I53aecc273484edfa502231b44f6bcd7f5d8f9331
Original-Reviewed-on: https://chromium-review.googlesource.com/231170
Original-Tested-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Jimmy Zhang <jimmzhang(a)nvidia.com>
---
src/mainboard/google/rush_ryu/mainboard.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c
index 81c15b4..9673aa5 100644
--- a/src/mainboard/google/rush_ryu/mainboard.c
+++ b/src/mainboard/google/rush_ryu/mainboard.c
@@ -123,8 +123,6 @@ static int enable_lcd_vdd(void)
VSEL_1200, 1);
pmic_write_reg(I2CPWR_BUS, TI65913_LDO5_CTRL,
TI65913_MODE_ACTIVE_ON, 1);
- /* wait for 100ms */
- mdelay(100);
/*
* Enable VDD_LCD
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9528
-gerrit
commit acc15b8023f1095edca130362d949476b4eeb6f2
Author: Tom Warren <twarren(a)nvidia.com>
Date: Wed Nov 19 16:26:41 2014 -0700
tegra132: Increase size of bootblock due to overflow
The bootblock on Rush had bumped up into the verstage
allocation, causing the build to break. Reduced verstage from
60K to 58K and increased bootblock from 20K to 22K. Rush and
Ryu both build fine now.
BUG=none
BRANCH=none
TEST=Built both Rush and Ryu OK. Verifed verstage size
using cbfstool and it's around 55K, so plenty of room.
Change-Id: Iaa3a5838c5235ec78c740a977bc032d8b5e270ef
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 928a4d2d1efabe1e1d6a7fadc22ee0ac4269190e
Original-Change-Id: I7018f027d72d5e8aeb894857a5ac6a0bdc1de388
Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/230824
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 3e2f246..5f45911 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -38,6 +38,8 @@ SECTIONS
STACK(0x40018000, 2K)
BOOTBLOCK(0x40019000, 20K)
VERSTAGE(0x4001E000, 60K)
+ BOOTBLOCK(0x40019000, 22K)
+ VERSTAGE(0x4001E800, 58K)
ROMSTAGE(0x4002D000, 76K)
SRAM_END(0x40040000)
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9527
-gerrit
commit f5049653a29d39421c0509378974899338f62722
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Nov 20 22:17:54 2014 -0600
arm64: ensure secondary CPU's stack tops are not in the cache
Secondary CPUs were intermittently not coming online as expected.
Upon investigation it was found that a cache line needed to be
invalidated that corresponded to the top of the stack for the
failing CPU.
Currently the secondary CPUs come online with caching disabled.
However, the code paths are using C and thus the stack it is assigned.
The MMU is enabled in C after it's pushed its return path onto the
stack that went directly to ram. When the cache line corresponding
to its stack is valid in the cache it will hit once the MMU is enabled.
That hit will have invalid data w.r.t. the return addresses pushed
directly into ram.
This is not the best solution as the only way to guarantee we don't
hit such a situation is to tightly manage resource usage up until
the point of MMU enablement. That can be done in a followup patch.
BUG=chrome-os-partner:33962
BRANCH=None
TEST=On ryu where secondary CPUs weren't coming online consistently,
they now come up.
Change-Id: I03237656da180d1f74df3a8e00029ba8d778bca8
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 06ab6afc996cf92c45d4cd6850e31167c2946a95
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Change-Id: I32de749ea48c19e23442e6dc5678c5369ac3b2b6
Original-Reviewed-on: https://chromium-review.googlesource.com/231219
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
---
src/arch/arm64/cpu_ramstage.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c
index ce81f93..ec1ac0f 100644
--- a/src/arch/arm64/cpu_ramstage.c
+++ b/src/arch/arm64/cpu_ramstage.c
@@ -19,6 +19,7 @@
#include <stdint.h>
#include <stdlib.h>
+#include <arch/cache.h>
#include <arch/lib_helpers.h>
#include <cpu/cpu.h>
#include <console/console.h>
@@ -155,6 +156,13 @@ static void init_cpu_info(struct bus *bus)
cpu_mark_online(cpu_info());
}
+static void invalidate_cpu_stack_top(unsigned int id)
+{
+ const size_t size = 128;
+ char *stack = cpu_get_stack(id);
+ dcache_invalidate_by_mva(stack - size, size);
+}
+
void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops)
{
size_t max_cpus;
@@ -208,6 +216,10 @@ void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops)
if (!cpu_online(ci)) {
/* Start the CPU. */
printk(BIOS_DEBUG, "Starting CPU%x\n", ci->id);
+
+ /* Ensure CPU's top of stack is not in the cache. */
+ invalidate_cpu_stack_top(ci->id);
+
if (cntrl_ops->start_cpu(ci->id, entry)) {
printk(BIOS_ERR,
"Failed to start CPU%x\n", ci->id);
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9526
-gerrit
commit e7a174b50a15f1090da553a3f22dc7d171f326b6
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Nov 20 11:11:01 2014 -0600
arm64: add timeout waiting for CPUs to come online
The initial MP code assumed all CPUs would come online. That's not
very defensive, and it is a bad assumption. Provide a timeout
mechanism for bring CPUs online.
BUG=chrome-os-partner:33962
BRANCH=None
TEST=Multiple times with CPUs working and not working. Boot to kernel.
Change-Id: Ib0aef31f5c732816d65c2e4b3c6a89e159974fdc
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 9cf5bc2844c8f4ad987cfcb69ef33c73551f0083
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Change-Id: Ifb3b72e3f122b79e9def554c037c9b3d6049a151
Original-Reviewed-on: https://chromium-review.googlesource.com/231070
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
---
src/arch/arm64/cpu_ramstage.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c
index f286678..ce81f93 100644
--- a/src/arch/arm64/cpu_ramstage.c
+++ b/src/arch/arm64/cpu_ramstage.c
@@ -23,6 +23,7 @@
#include <cpu/cpu.h>
#include <console/console.h>
#include <gic.h>
+#include <timer.h>
#include "cpu-internal.h"
static inline void cpu_disable_dev(device_t dev)
@@ -191,6 +192,7 @@ void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops)
for (i = 0; i < max_cpus; i++) {
device_t dev;
struct cpu_action action;
+ struct stopwatch sw;
ci = cpu_info_for_cpu(i);
dev = ci->cpu;
@@ -211,9 +213,23 @@ void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops)
"Failed to start CPU%x\n", ci->id);
continue;
}
+ stopwatch_init_msecs_expire(&sw, 1000);
/* Wait for CPU to come online. */
- while (!cpu_online(ci));
- printk(BIOS_DEBUG, "CPU%x online.\n", ci->id);
+ while (!stopwatch_expired(&sw)) {
+ if (!cpu_online(ci))
+ continue;
+ printk(BIOS_DEBUG,
+ "CPU%x online in %ld usecs.\n",
+ ci->id, stopwatch_duration_usecs(&sw));
+ break;
+ }
+ }
+
+ if (!cpu_online(ci)) {
+ printk(BIOS_DEBUG,
+ "CPU%x failed to come online in %ld usecs.\n",
+ ci->id, stopwatch_duration_usecs(&sw));
+ continue;
}
/* Send it the init action. */
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9525
-gerrit
commit a3ed49faf5b322aa63ebf726b0141fc184545229
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Nov 19 12:01:39 2014 -0600
tegra132: always bring up PLLD
The kernel does not correctly function without PLLD being enabled.
Additionally, PLLD can be the source for other clocks in the system.
Therefore, initialize PLLD to 300MHz unconditionally at BS_DEV_INIT
time in ramstage.
BUG=chrome-os-partner:33825
BRANCH=None
TEST=Built and booted ryu with display coming up both in dev mode as
well as normal mode.
Change-Id: Ib2a60bb9aafc03dc23aa932a480184d87f677c65
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 4c49f964b55c3c33d03b95363277b262b679e740
Original-Change-Id: Ic5905e25051a042cea5010b8c6d61b1fb89a0a81
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230774
Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Tested-by: Sean Paul <seanpaul(a)chromium.org>
---
src/soc/nvidia/tegra132/soc.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index d80a388..5593be7 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -22,6 +22,7 @@
#include <arch/cache.h>
#include <arch/spintable.h>
#include <cpu/cpu.h>
+#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
@@ -141,3 +142,20 @@ static const struct cpu_driver driver __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = ids,
};
+
+static void enable_plld(void *unused)
+{
+ /*
+ * Configure a conservative 300MHz clock for PLLD. The kernel cannot
+ * handle PLLD not being configured so enable PLLD unconditionally
+ * with a default clock rate.
+ */
+ clock_configure_plld(300 * MHz);
+}
+
+/*
+ * The PLLD being enabled is done at BS_DEV_INIT time because mainboard_init()
+ * is the first thing called. This ensures PLLD is up and functional before
+ * anything that mainboard can do that implicitly relies on PLLD.
+ */
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, enable_plld, NULL);