Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9524
-gerrit
commit a6d425dc6b056161501362f55b530cbe290e5597
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Nov 19 11:57:47 2014 -0600
tegra132: rename clock_display() to clock_configure_plld()
Provide an explicit name for configuring PLLD. The new name,
clock_configure_plld(), provides an explicit semantic to
what it is doing. Also, provide the printk() about actual
frequency vs requested frequency as most of the callers
were doing this themselves.
BUG=chrome-os-partner:33825
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: I1880f0f305e69674922b070d282aac3acdc86aad
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: c51d5b0864d8bd0db5927380803cec46ccd74d48
Original-Change-Id: If744332b466d9486f83b08d0ab4e9006fadfecdd
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230773
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com>
Original-Reviewed-by: Sean Paul <seanpaul(a)chromium.org>
---
src/soc/nvidia/tegra132/clock.c | 11 +++++------
src/soc/nvidia/tegra132/display.c | 7 +++----
src/soc/nvidia/tegra132/include/soc/clock.h | 6 +++++-
src/soc/nvidia/tegra132/tegra_dsi.c | 2 +-
4 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c
index 49c2f19..661d38a 100644
--- a/src/soc/nvidia/tegra132/clock.c
+++ b/src/soc/nvidia/tegra132/clock.c
@@ -291,10 +291,6 @@ static void graphics_pll(void)
/* leave dither and undoc bits set, release clamp */
scfg = (1<<28) | (1<<24);
writel(scfg, cfg);
-
- /* disp1 will be set when panel information (pixel clock) is
- * retrieved (clock_display).
- */
}
/*
@@ -304,8 +300,7 @@ static void graphics_pll(void)
*
* Return the plld frequency if success, otherwise return 0.
*/
-u32
-clock_display(u32 frequency)
+u32 clock_configure_plld(u32 frequency)
{
/**
* plld (fo) = vco >> p, where 500MHz < vco < 1000MHz
@@ -388,6 +383,10 @@ clock_display(u32 frequency)
init_pll(CLK_RST_REG(plld_base), CLK_RST_REG(plld_misc), plld,
(PLLUD_MISC_LOCK_ENABLE | PLLD_MISC_CLK_ENABLE));
+ if (rounded_rate != frequency)
+ printk(BIOS_DEBUG, "PLLD rate: %u vs %u\n", rounded_rate,
+ frequency);
+
return rounded_rate;
}
diff --git a/src/soc/nvidia/tegra132/display.c b/src/soc/nvidia/tegra132/display.c
index 4fc312e..d616b73 100644
--- a/src/soc/nvidia/tegra132/display.c
+++ b/src/soc/nvidia/tegra132/display.c
@@ -135,7 +135,8 @@ static int update_display_mode(struct display_controller *disp_ctrl,
* has some requirements to have VCO in range 500MHz~1000MHz (see
* clock.c for more detail). To simplify calculation, we set
* PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values
- * may be calculated by clock_display, to allow wider frequency range.
+ * may be calculated by clock_configure_plld(), to allow wider
+ * frequency range.
*
* Note ShiftClockDiv is a 7.1 format value.
*/
@@ -265,12 +266,10 @@ void display_startup(device_t dev)
* update_display_mode() for detail.
*/
/* set default plld */
- plld_rate = clock_display(config->pixel_clock * 2);
+ plld_rate = clock_configure_plld(config->pixel_clock * 2);
if (plld_rate == 0) {
printk(BIOS_ERR, "dc: clock init failed\n");
return;
- } else if (plld_rate != config->pixel_clock * 2) {
- printk(BIOS_WARNING, "dc: plld rounded to %u\n", plld_rate);
}
/* set disp1's clock source to PLLD_OUT0 */
diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h
index 7fabff7..5fadbd0 100644
--- a/src/soc/nvidia/tegra132/include/soc/clock.h
+++ b/src/soc/nvidia/tegra132/include/soc/clock.h
@@ -378,7 +378,11 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
int clock_get_osc_khz(void);
int clock_get_pll_input_khz(void);
-u32 clock_display(u32 frequency);
+/*
+ * Configure PLLD to requested frequency. Returned value is closest match
+ * within the PLLD's constraints or 0 if an error.
+ */
+u32 clock_configure_plld(u32 frequency);
void clock_early_uart(void);
void clock_external_output(int clk_id);
void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
diff --git a/src/soc/nvidia/tegra132/tegra_dsi.c b/src/soc/nvidia/tegra132/tegra_dsi.c
index 3a7949d..f1e7c9f 100644
--- a/src/soc/nvidia/tegra132/tegra_dsi.c
+++ b/src/soc/nvidia/tegra132/tegra_dsi.c
@@ -463,7 +463,7 @@ static int tegra_output_dsi_setup_clock(struct tegra_dsi *dsi,
dsi->slave->clk_rate = dsi->clk_rate;
/* set up plld */
- plld = clock_display(plld);
+ plld = clock_configure_plld(plld);
if (plld == 0) {
printk(BIOS_ERR, "%s: clock init failed\n", __func__);
return -1;
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9523
-gerrit
commit 30b4bffbe634373db7ac60ea14323f1666c50923
Author: Tom Warren <twarren(a)nvidia.com>
Date: Mon Nov 17 16:09:38 2014 -0700
google/rush_ryu: audio: Setup clocks for AHUB, I2S1, codec, etc.
The Ryu RT5677 audio codec uses EXTPERIPH1 clock (12MHz)
for MCLK1, I2S1 for input. AHUB needs all of its child
peripherals taken out of reset and enabled, too.
This just sets up the audio clocks. More work still to
be done in the codec driver, and some kind of stub needs
to be created/hacked to set up the AD4567 speaker amp
regs for mono output on P1.
BUG=chrome-os-partner:32582
BRANCH=none
TEST=Dumped clock regs and saw correct values
Change-Id: Ifb6551f1e09b38f440f3bb7c759b5e6c0b9e4e44
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 48f989a0291044f5fb4340cc89546325d819d82f
Original-Change-Id: I6c9e760ac39def92a6054d673f781facdbfd70a2
Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229993
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/rush_ryu/mainboard.c | 31 +++++++++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c
index 2b71c98..81c15b4 100644
--- a/src/mainboard/google/rush_ryu/mainboard.c
+++ b/src/mainboard/google/rush_ryu/mainboard.c
@@ -57,8 +57,8 @@ static const struct pad_config mmcpads[] = {
static const struct pad_config audio_codec_pads[] = {
/* H1 is CODEC_RST_L and R2(ROW2) is AUDIO_ENABLE */
- PAD_CFG_GPIO_OUT1(GPIO_PH1, PINMUX_PULL_DOWN),
- PAD_CFG_GPIO_OUT1(KB_ROW2, PINMUX_PULL_DOWN),
+ PAD_CFG_GPIO_OUT1(GPIO_PH1, PINMUX_PULL_DOWN),
+ PAD_CFG_GPIO_OUT1(KB_ROW2, PINMUX_PULL_DOWN),
};
static const struct funit_cfg funits[] = {
@@ -186,6 +186,30 @@ static int configure_display_blocks(void)
return 0;
}
+/* Audio init: clocks and enables/resets */
+static void setup_audio(void)
+{
+ /* External peripheral 1: audio codec (RT5677) using 12MHz CLK1 */
+ clock_configure_source(extperiph1, CLK_M, 12000);
+
+ /*
+ * We need 1.5MHz for I2S1. So, we use CLK_M. CLK_DIVIDER macro
+ * returns a divisor (0xe) a little bit off from the ideal value (0xd),
+ * but it's good enough for beeps.
+ */
+ clock_configure_source(i2s1, CLK_M, 1500);
+
+ clock_external_output(1); /* For external RT5677 audio codec. */
+
+ /*
+ * Confirmed by NVIDIA hardware team, we need to take ALL audio devices
+ * connected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
+ * of reset and clock-enabled, otherwise reading AHUB devices (in our
+ * case, I2S/APBIF/AUDIO<XBAR>) will hang.
+ */
+ clock_enable_audio();
+}
+
static void mainboard_init(device_t dev)
{
soc_configure_funits(funits, ARRAY_SIZE(funits));
@@ -193,6 +217,9 @@ static void mainboard_init(device_t dev)
/* I2C6 bus (audio, etc.) */
soc_configure_i2c6pad();
i2c_init(I2C6_BUS);
+
+ setup_audio();
+
elog_init();
elog_add_boot_reason();
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9521
-gerrit
commit 7cc8f6dc88f629bbdbc2f1a5017ff14bf704733a
Author: Jimmy Zhang <jimmzhang(a)nvidia.com>
Date: Fri Nov 14 15:47:12 2014 -0800
google/rush_ryu: devicetree: Add framebuffer resolution settings
When displaying a 800x600 bitmap on 2560x1800 panel, the image
is shown very small. So, set the fb to 1280x800 (based on tegra
dsi driver default mode setting), a 800x600 image can be shown
relatively proportional to panel size.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Change-Id: I1e360aeaec97b9df5d86e46951ab1326610260d2
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 67c2a381322721a24b1b7f9ac366073b7e3c490c
Original-Change-Id: I62cbe9de1d1002293df20f8b1d752905c6ef33aa
Original-Reviewed-on: https://chromium-review.googlesource.com/229912
Original-Tested-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/rush_ryu/devicetree.cb | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/google/rush_ryu/devicetree.cb b/src/mainboard/google/rush_ryu/devicetree.cb
index c0af141..b5c9981 100644
--- a/src/mainboard/google/rush_ryu/devicetree.cb
+++ b/src/mainboard/google/rush_ryu/devicetree.cb
@@ -33,6 +33,10 @@ chip soc/nvidia/tegra132
register "framebuffer_bits_per_pixel" = "32"
register "color_depth" = "12"
+ # framebuffer resolution
+ register "display_xres" = "1280"
+ register "display_yres" = "800"
+
register "href_to_sync" = "1"
register "hfront_porch" = "80"
register "hsync_width" = "80"
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9520
-gerrit
commit fb9249c406d5bccb139567c9e4ea635b7dcc1be9
Author: Jimmy Zhang <jimmzhang(a)nvidia.com>
Date: Fri Nov 14 20:44:40 2014 -0800
tegra132: Add framebuffer parameters
Framebuffer line size and number of lines can have different
values than panel's resolution.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Change-Id: I228f1dd7fafc6577a8e8a987ff31ba73f7a655ed
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 9a4929dc5831076f2f2a5dd2e13f24b3477e197b
Original-Change-Id: Iedeef796f02286bb03920413420f8952cf34334a
Original-Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229915
Original-Tested-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/nvidia/tegra132/chip.h | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h
index 35e72d5..2468870 100644
--- a/src/soc/nvidia/tegra132/chip.h
+++ b/src/soc/nvidia/tegra132/chip.h
@@ -27,7 +27,8 @@ struct soc_nvidia_tegra132_config {
uintptr_t spintable_addr;
/*
- * panel default specification
+ * panel resolution
+ * The two parameters below provides dc about panel spec.
*/
u32 xres; /* the width of H display active area */
u32 yres; /* the height of V display active area */
@@ -45,6 +46,15 @@ struct soc_nvidia_tegra132_config {
*/
u32 framebuffer_size;
+ /*
+ * Framebuffer resolution
+ * The two parameters below provides dc about framebuffer's sdram size.
+ * When they are not the same as panel resolution, we need to program
+ * dc's DDA_INCREMENT and some other registers to resize dc output.
+ */
+ u32 display_xres;
+ u32 display_yres;
+
int href_to_sync; /* HSYNC position with respect to line start */
int hsync_width; /* the width of HSYNC pulses */
int hback_porch; /* the distance between HSYNC trailing edge to
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9515
-gerrit
commit f0d05231d8bc49002b0e28d8cf852e5c601b4d55
Author: Jimmy Zhang <jimmzhang(a)nvidia.com>
Date: Fri Nov 14 21:12:27 2014 -0800
tegra132: Add panel mode spec
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Change-Id: I23dae7bfdeb8e33a6ea5c9de0fb953a7c4d31345
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 6cac26deeea0e024f2f6bd1850a41894f801bc5f
Original-Change-Id: Ie77f8df4ba3425e0dd4e4243dd38157480de0efb
Original-Reviewed-on: https://chromium-review.googlesource.com/229913
Original-Tested-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/nvidia/tegra132/chip.h | 35 ++++++++++++++++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h
index f2936dd..23f2cd8 100644
--- a/src/soc/nvidia/tegra132/chip.h
+++ b/src/soc/nvidia/tegra132/chip.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2013 Google Inc.
+ * Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -29,6 +29,39 @@
struct soc_nvidia_tegra132_config {
/* Address to monitor if spintable employed. */
uintptr_t spintable_addr;
+
+ /*
+ * panel default specification
+ */
+ u32 xres; /* the width of H display active area */
+ u32 yres; /* the height of V display active area */
+ u32 framebuffer_bits_per_pixel;
+ u32 color_depth; /* color format */
+
+ u64 display_controller; /* dc block base address */
+ u32 framebuffer_base;
+
+ /*
+ * Technically, we can compute this. At the same time, some platforms
+ * might want to specify a specific size for their own reasons. If it
+ * is zero the soc code will compute it as
+ * xres*yres*framebuffer_bits_per_pixel/8
+ */
+ u32 framebuffer_size;
+
+ int href_to_sync; /* HSYNC position with respect to line start */
+ int hsync_width; /* the width of HSYNC pulses */
+ int hback_porch; /* the distance between HSYNC trailing edge to
+ beginning of H display active area */
+ int hfront_porch; /* the distance between end of H display active
+ area to the leading edge of HSYNC */
+ int vref_to_sync;
+ int vsync_width;
+ int vback_porch;
+ int vfront_porch;
+ int refresh; /* display refresh rate */
+
+ int pixel_clock; /* dc pixel clock source rate */
};
#endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */