the following patch was just integrated into master:
commit 1e83536f8ca529b88bdd75108a2f991d5c93c6b3
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Thu Apr 9 13:31:02 2015 +0200
ipq806x: Remove extra INCLUDES
That variable isn't used anymore and the include statement
is already covered in CPPFLAGS_common further down that file.
Change-Id: I3e4fd3281dc0d3f73b238e121dbdfc0d29102b27
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9448
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9448 for details.
-gerrit
the following patch was just integrated into master:
commit 8315622ff1bd898d839144abf0310524a35f8e1a
Author: Tom Warren <twarren(a)nvidia.com>
Date: Thu Nov 13 13:16:28 2014 -0700
google/rush: Add I2C1 init and audio clock enable/resets
This should allow the max98090 codec to play beeps via
AHUB/I2S1 thru the depthcharge sound driver.
BUG=none
BRANCH=none
TEST=Saw max98090 codec init signon and register dump.
No sound yet.
Change-Id: I1ee0b61f5cbfe587ebd16b7dd9dce08d9d62c2c5
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: f4ee2ce3704711a9e00531b7599a1bcf194203ec
Original-Change-Id: I0bc8401e76b2c80a01083ac933a39f6cd4d1b78a
Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229496
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Mike Frysinger <vapier(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9429
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9429 for details.
-gerrit
the following patch was just integrated into master:
commit 9f7d3ad1369d7964d7e1afb11ac6229ba57ab386
Author: Tom Warren <twarren(a)nvidia.com>
Date: Fri Nov 14 15:42:42 2014 -0700
tegra132: Add routine to enable all audio periphs under AHUB
If all devices under AHUB (AUDIO/I2S/DAM/ADX/etc) aren't
clocked and taken out of reset, any access to any audio
peripheral will hang the system.
BUG=none
BRANCH=none
TEST=built both Rush and Ryu OK.
Change-Id: Iee8e33f005c5abaf09a14104c0b243b06eb4af24
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 0016bd533864942225f2fb8e08ce871a186f2746
Original-Change-Id: I741d5ba4dd8bd963b6d261fbf41cfb77c274cb79
Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229910
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Mike Frysinger <vapier(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9428
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9428 for details.
-gerrit
the following patch was just integrated into master:
commit bc7e387a0f0cafc53456af5d038da8394d7a6f66
Author: Tom Warren <twarren(a)nvidia.com>
Date: Thu Nov 13 12:51:01 2014 -0700
tegra132: Add I2C1 support to funit
I2C1 was missing in the funit/i2c/addressmap tables/code.
BUG=none
BRANCH=none
TEST=Built Rush and Ryu. Built Rush w/code in mainboard.c
to enable I2C1 for the MAX98090 audio codec - codec could be
configured.
Change-Id: I0c678d21546eedb7404a1d3d4329da777430fc97
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 4b623097a2adc4464c17bceed96ec3838beda985
Original-Change-Id: Ibe4f012fa2d427b95cd4672687132b47576b6a9a
Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229574
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9427
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9427 for details.
-gerrit
the following patch was just integrated into master:
commit 8a1ee9bf70d1777636b297158882a5f465af66b7
Author: Furquan Shaikh <furquan(a)google.com>
Date: Wed Nov 12 16:23:00 2014 -0800
rtc: Add an RTC driver for the TI TPS65913 PMIC.
The TPS65913 PMIC has an RTC built into it. This change adds
a driver for it which implements the new RTC API.
BUG=chrome-os-partner:33764
BRANCH=None
TEST=Compiles and boots to kernel prompt on ryu. Timestamps for event log
verified across multiple boots.
Change-Id: I49ec9b78afc53f1cbd4be09e448cdae6077fb710
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: c16c11e620c830e7a73a2a24fe4823ccea0f3c39
Original-Change-Id: If1d549ea2361d0de6be75fd24b9e9810a6df7457
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229414
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9425
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9425 for details.
-gerrit
the following patch was just integrated into master:
commit 0179fcfaab2fdbff0da00bf76be08e913d5a0f47
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 30 13:13:50 2014 -0500
arm64: Implement PSCI command support
Provide support for SoCs to participate in PSCI commands.
There are 2 steps to a command:
1. prepare() - look at request and adjust state accordingly
2. commit() - take action on the command
The prepare() function is called with psci locks held while
the commit() function is called with the locks dropped.
No SoC implements the appropriate logic yet.
BUG=chrome-os-partner:32136
BRANCH=None
TEST=Booted PSCI kernel -- no SMP because cmd_prepare()
knowingly fails. Spintable kernel still brings up both
CPUs.
Change-Id: I2ae4d1c3f3eac4d1060c1b41472909933815d078
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 698d38b53bbc2bc043548792cea7219542b5fe6b
Original-Change-Id: I0821dc2ee8dc6bd1e8bc1c10f8b98b10e24fc97e
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226485
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9423
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/9423 for details.
-gerrit
the following patch was just integrated into master:
commit 6cdacb37f0e84666831d78f4bf9af2cbc30cbb81
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Nov 6 15:17:33 2014 -0600
arm64: secmon: add entry point for turned on CPUs
Newly turned on CPUs need a place to go bring its EL3
state inline with expectations. Plumb this path in for
CPUs turning on as well as waking up from a power down
state. Some of the infrastructure declarations were
moved around for easier consumption in ramstage and
secmon. Lastly, a psci_soc_init() is added to
inform the SoC of the CPU's entry point as well do
any initialization.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Built and booted. On entry point not actually utilized.
Change-Id: I2af424c2906df159f78ed5e0a26a6bc0ba2ba24f
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: dbefec678a111e8b42acf2ae162c1ccdd7f9fd40
Original-Change-Id: I7b8c8c828ffb73752ca3ac1117cd895a5aa275d8
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228296
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9422
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/9422 for details.
-gerrit