the following patch was just integrated into master:
commit 7a89d8550ddd3546e15a089da94436606bb75cc0
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Nov 6 17:32:58 2014 -0800
rk3288: Adjust CBFS header and ROM offsets
Our CBFS header offset on rk3288 was very low and overlapped with the
end of the bootblock on recent Pinky builds. This can create all kinds
of fun effects like BSS variables suddenly being initialized to
something else than zero, in an effect that jumps somewhere else for
every slightest code size change.
This patch moves the CBFS header offset up a bit and the CBFS ROM offset
down (because there's really no point in leaving such a large gap). This
resolves our immediate booting problems, and I'll also start on a patch
to add further checks somewhere that catch these overlaps in the future.
BRANCH=None
BUG=None
TEST=Created a Pinky image from the exact same commit version as the
official 6443.0.0 build, with a KERNELREVISION string of the exact same
length as the builder (which for some arcane reason is different than
running emerge locally, shifting the whole bootblock around with it).
Confirmed that I saw the same "Not enough room for another
sub-pagetable!" hang, and that this patch fixes it.
Change-Id: I9e59a282b3cd0af3b0d224d64c10b7c4d312ad02
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 1a142cd2c51c6f51a1597c21ad513feb151e0938
Original-Change-Id: I8be5b7b7e87021cc1b3a91d336e8d233546ee188
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228326
Original-Reviewed-by: Gediminas Ramanauskas <gedis(a)chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9410
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9410 for details.
-gerrit
the following patch was just integrated into master:
commit 335d9f123c33dae8df66b08c6c603f7a7c62f825
Author: huang lin <hl(a)rock-chips.com>
Date: Fri Nov 7 10:56:35 2014 +0800
rk3288: don't log LAST_TSHUT bit
Since the LAST_THSUT bit is uncertain value when it cold-reboot,
we remove the printout about this status bit in coreboot.
BUG=chrome-os-partner:33521
TEST=Boot on veyron_pinky rev2
Change-Id: I3b9791ffdffeff0721e3d86378db6255c5abc9ea
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 16464d3229ad1001952ef1b50fe3e606d1583462
Original-Change-Id: I258750797e32c28f86e73a01eede005e890a6906
Original-Signed-off-by: huang lin <hl(a)rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/228391
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9409
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9409 for details.
-gerrit
the following patch was just integrated into master:
commit d1bdef008a33e4e9583606feb8747a4d0d249ef1
Author: huang lin <hl(a)rock-chips.com>
Date: Fri Oct 31 16:40:42 2014 +0800
rk3288: slowly raise to max cpu voltage to prevent overshoot
slowly raise to max cpu voltage to prevent overshoot,
and in our experience,when cpu run in 1.8GHz,the
vdd_cpu must up to 1.4V
BUG=chrome-os-partner:32716, chrome-os-partner:31896
TEST=Boot on veyron_pinky rev2,check the rk808 buck1 voltage 1400mv
and measure the overshoot is 1440mv
Change-Id: I759840bd8cf57a5589bf1862d04803f80f804164
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 567f616ff091883ed3275b407859c9399db981b2
Original-Change-Id: I9bb739b49ae4b4f7a60133fa38b0fe51b95c0d78
Original-Signed-off-by: huang lin <hl(a)rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/226753
Original-Reviewed-by: Doug Anderson <dianders(a)chromium.org>
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9408
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9408 for details.
-gerrit
the following patch was just integrated into master:
commit c06a962271053d1fbb280e28e1cd5788132d942c
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Nov 5 14:10:56 2014 -0600
ryu: update board id definitions
There are changes in upcoming board revs that need to take
different action depending on board revision. Update the
enumeration to reflect upcoming reality.
BUG=chrome-os-partner:33578
BRANCH=None
TEST=Built and booted.
Change-Id: Ib51393e04d3255bbd44e5d77a2a7903109beebf4
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: de8d629678c0ae17af9f7145e04d95f43c927ee0
Original-Change-Id: I64cdeab806e7a665051f1d47bbf044413f7a1196
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227681
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9407
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/9407 for details.
-gerrit
the following patch was just integrated into master:
commit 33b31152b0e7310d872449f548cd8e3da211f7ea
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Nov 5 14:01:29 2014 -0600
ryu: remove board id normalization
The gpio_get_tristates() function prints out the values
observed while processing the GPIOs. Additionally, the
values for the normalization were completely consecutive.
Therefore, this indirection can be removed.
BUG=chrome-os-partner:33578
BRANCH=None
TEST=Built and booted.
Change-Id: I088a2f1c7601c014a7f8a9eb228efa9bb80f1e01
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 02e52554b9cbf85034feb9aedc50f09b70893e32
Original-Change-Id: I17d85891087e3128790329a5f05cbdab4cbc950e
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227680
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9406
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9406 for details.
-gerrit
the following patch was just integrated into master:
commit 1fd91a19664a96022cc036fcb3f6d53fe7ff8868
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Wed Oct 29 11:14:53 2014 -0700
tpm: allow 0 as valid i2c bus number
tpm driver uses bus=0 as indication of uninitialized tpm device. this
change allows 0 as a valid i2c bus number.
BUG=None
BRANCH=ToT
TEST=Built cosmos.
Change-Id: Ie8d285abff11643cc3efc0fa30e4afcc3ca1c0d5
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 493077b68cf46b08f0d1ddfe57bf6064d714d537
Original-Change-Id: Iac55e88db4ef757a292270e7201d8fdd37a90b50
Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226294
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9405
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9405 for details.
-gerrit
the following patch was just integrated into master:
commit 644afa70478483144e31e08857c66c83765737fb
Author: Dan Ehrenberg <dehrenberg(a)chromium.org>
Date: Fri Oct 24 13:22:05 2014 -0700
google/storm: Minor board ID changes
- Add the Whirlwind board ID to the enum
- Replace comparisons of the board ID with 0 to the proto0 constant
TEST=Booted Storm with this coreboot version
BUG=none
BRANCH=none
Change-Id: I53be0b06c3444936a8bd67653e03b93bcb87e328
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 7e055ef27ef1e07be09d80b2298384889214bf0d
Original-Change-Id: I75c7c98732c3d4569611de54d7aa149dd3b0fb7d
Original-Signed-off-by: Dan Ehrenberg <dehrenberg(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225460
Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9404
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9404 for details.
-gerrit
the following patch was just integrated into master:
commit 127c3393b44830987e83ce8c8e7a77f79dd4f5c1
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Wed Oct 22 17:39:24 2014 -0700
chromeos: add another VPD access API
The new API allows to find VPD objects in the VPD cache. There is no
need for the caller to allocate or free the per object memory.
The existing API (cros_vpd_gets) now uses the new function as well.
BRANCH=storm
BUG=chrome-os-partner:32611
TEST=verified that MAC addresses still show up in the device tree on
the booted storm device
Change-Id: Id06be315981cdaa2285fc1ec61b96b62b1178a4b
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 99a34344448a5521cee8ad3918aefb1fde28417d
Original-Change-Id: I6c0b11bb844d6235930124d642da632319142d88
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225258
Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9403
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9403 for details.
-gerrit
the following patch was just integrated into master:
commit cb3b0c5a0dd5164fb4a8c0c6b8d2656948748343
Author: Dan Ehrenberg <dehrenberg(a)chromium.org>
Date: Thu Oct 23 17:46:39 2014 -0700
storm: Initialize clock, pinmux for NAND if present on board
This patch runs basic NAND initialization code on Proto 0.2 boards which
have been reworked for NAND. It makes sense to do this in coreboot for
two reasons:
- In general, it is reasonable for coreboot to initialize clocks and such
in preparation for depthcharge's use. Waiting times can be pooled, and
the initialization itself here is very fast.
- There is a kernel bug which requires that the clock is already initialized
before the kernel loads NAND support. coreboot is a more sensible place
to put a workaround than depthcharge because depthcharge initializes
things lazily, but when booting from USB, depthcharge won't need to look
at NAND.
This change involves bringing in an additional header file, ebi2.h, from U-Boot.
TEST=Booted a kernel from USB and verified that NAND came up without any
depthcharge hacks, whereas previously a USB-booted kernel would be unable
to access NAND even with the same drivers compiled in due to an initialization
failure.
BUG=chromium:403432
BRANCH=none
Change-Id: I04e99cb39d16848a6ed75fe0229b8f79bdf2e035
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 9be29da5ccad9982f146ae00344f30598ef2371c
Original-Signed-off-by: Dan Ehrenberg <dehrenberg(a)chromium.org>
Original-Change-Id: I1760ecb4e47438311d80e34326e45578c608481c
Original-Reviewed-on: https://chromium-review.googlesource.com/225277
Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9402
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9402 for details.
-gerrit
the following patch was just integrated into master:
commit 886d29bcd808476e0e83f68e3f7905fba4304b0a
Author: Julius Werner <jwerner(a)chromium.org>
Date: Wed Sep 24 15:40:49 2014 -0700
gpio: Remove non-ternary tristate mode, make ternaries easier
The function to read board IDs from tristate GPIOs currently supports
two output modes: a normal base-3 integer, or a custom format where
every two bits represent one tristate pin. Each board decides which
representation to use on its own, which is inconsistent and provides
another possible gotcha to trip over when reading unfamiliar code.
The two-bits-per-pin format creates the additional problem that a
complete list of IDs (such as some boards use to build board-ID tables)
necessarily has "holes" in them (since 0b11 does not correspond to a
possible pin state), which makes them extremely tricky to write, read
and expand. It's also very unintuitive in my opinion, although it was
intended to make it easier to read individual pin states from a hex
representation.
This patch switches all boards over to base-3 and removes the other
format to improve consistency. The tristate reading function will just
print the pin states as they are read to make it easier to debug them,
and we add a new BASE3() macro that can generate ternary numbers from
pin states. Also change the order of all static initializers of board ID
pin lists to write the most significant bit first, hoping that this can
help clear up confusion about the endianness of the pins.
CQ-DEPEND=CL:219902
BUG=None
TEST=Booted on a Nyan_Blaze (with board ID 1, unfortunately the only one
I have). Compiled on Daisy, Peach_Pit, Nyan, Nyan_Big, Nyan_Blaze, Rush,
Rush_Ryu, Storm, Veryon_Pinky and Falco for good measure.
Change-Id: I3ce5a0829f260db7d7df77e6788c2c6d13901b8f
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 2fa9545ac431c9af111ee4444d593ee4cf49554d
Original-Change-Id: I6133cdaf01ed6590ae07e88d9e85a33dc013211a
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219901
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9401
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9401 for details.
-gerrit