the following patch was just integrated into master:
commit eaa9c4596b083ee1d1a48c5e7632abdb5b7e5297
Author: Julius Werner <jwerner(a)chromium.org>
Date: Wed Sep 24 15:40:49 2014 -0700
gpio: Extend common GPIO header, simplify function names
We've had gpiolib.h which defines a few common GPIO access functions for
a while, but it wasn't really complete. This patch adds the missing
gpio_output() function, and also renames the unwieldy
gpio_get_in_value() and gpio_set_out_value() to the much easier to
handle gpio_get() and gpio_set(). The header is renamed to the simpler
gpio.h while we're at it (there was never really anything "lib" about
it, and it was presumably just chosen due to the IPQ806x include/
conflict problem that is now resolved).
It also moves the definition of gpio_t into SoC-specific code, so that
different implementations are free to encode their platform-specific
GPIO parameters in those 4 bytes in the most convenient way (such as the
rk3288 with a bitfield struct). Every SoC intending to use this common
API should supply a <soc/gpio.h> that typedefs gpio_t to a type at most
4 bytes in length. Files accessing the API only need to include <gpio.h>
which may pull in additional things (like a gpio_t creation macro) from
<soc/gpio.h> on its own.
For now the API is still only used on non-x86 SoCs. Whether it makes
sense to expand it to x86 as well should be separately evaluated at a
later point (by someone who understands those systems better). Also,
Exynos retains its old, incompatible GPIO API even though it would be a
prime candidate, because it's currently just not worth the effort.
BUG=None
TEST=Compiled on Daisy, Peach_Pit, Nyan_Blaze, Rush_Ryu, Storm and
Veyron_Pinky.
Change-Id: Ieee77373c2bd13d07ece26fa7f8b08be324842fe
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 9e04902ada56b929e3829f2c3b4aeb618682096e
Original-Change-Id: I6c1e7d1e154d9b02288aabedb397e21e1aadfa15
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220975
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9400
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9400 for details.
-gerrit
the following patch was just integrated into master:
commit e9e0eec4faa46ff3879c3350000c4a20b9053270
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Thu Oct 16 13:26:59 2014 -0700
storm: retrieve MAC address from VPD
Retrieving MAC address from VPD should be the board responsibility,
add a call to the recently introduced function.
BRANCH=storm
BUG=chromium:417117
TEST=verified that MAC addresses still show up in the device tree on
storm
Change-Id: Ib8ddc88ccd859e0b36e65aaaeb5c9473077c8c02
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 285cb256e619ef41c7f11680b3fa5310b1d93cf1
Original-Change-Id: I3913b10a425d8e8621b832567871ed4861756381
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223797
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9399
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com>
See http://review.coreboot.org/9399 for details.
-gerrit
the following patch was just integrated into master:
commit dd94b5f023b5449b6d2555ccd1d3f294ef2a99d0
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Thu Oct 16 13:02:37 2014 -0700
chromeos: move VPD MAC address retrieval function
Retrieval of the MAC address from the VPD is a Chrome OS specific
feature, required just on one platform so far. There is no need to
look for the MAC address in the VPD on all other Chrome OS boards.
BRANCH=storm
BUG=chromium:417117
TEST=with the upcoming patch applied verified that MAC addresses still
show up in the device tree on storm
Change-Id: If5fd4895bffc758563df7d21f38995f0c8594330
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: fb4906ac559634321a01b4814f338611b9e98b2b
Original-Change-Id: I8e6f8dc38294d3ab11965931be575360fd12b2fc
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223796
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9398
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9398 for details.
-gerrit
the following patch was just integrated into master:
commit 931a218d685610d85b570b72889b341270e2d00a
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Nov 5 11:19:21 2014 -0600
arm64: secmon: pass online CPUs to secmon
Instead of relying on CONFIG_MAX_CPUS to be the number of
CPUs running a platform pass the number of online cpus
from coreboot secmon. That allows for actually enabled
CPUs < CONFIG_MAX_CPUS.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Booted SMP kernel.
Change-Id: Iaf1591e77fcb5ccf5fe271b6c84ea8866e19c59d
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 3827af876c247fc42cd6be5dd67f8517457b36e7
Original-Change-Id: Ice10b8ab45bb1190a42678e67776846eec4eb79a
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227529
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9397
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9397 for details.
-gerrit
the following patch was just integrated into master:
commit 9fd7b1c1a9ab42b428af2599f497a328a04dbe92
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Nov 5 10:45:05 2014 -0600
arm64: psci: use struct cpu_action to track startup entry
The struct cpu_action already tracks entry/arg pointers. Use that
instead of duplicating the same information.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Built and booted.
Change-Id: I70e1b471ca15eac2ea4e6ca3dab7d8dc2774a241
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: cdddfd8d74d227cb5cbdf15b6871480839fa20d8
Original-Change-Id: I4070ef0df19bb1141a1a47c4570a894928d6a5a4
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227549
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9396
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9396 for details.
-gerrit
the following patch was just integrated into master:
commit be3e2387c6e01cf5dd2346aa0f12e35d8229f2a6
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Nov 5 10:48:16 2014 -0600
arm64: secmon: prepare for passing more state into secmon
The current implementation of secmon assumes just entry/arg
are passed to secmon for starting up a CPU. That's lacking
in flexibility. Therefore change secmon_params to contain
both the BSP and secondary CPUs' entry/arg information.
That way more information can be added to secmon_params when
needed.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Built and booted SMP kernel using PSCI and spin table.
Change-Id: I84c478ccefdfa4580fcc078a2491f49f86a9757a
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: c5fb5bd857a4318174f5b9b48e28406e60a466f8
Original-Change-Id: Iafb82d5cabc806b6625799a6b3dff8d77bdb27e9
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227548
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9395
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9395 for details.
-gerrit
the following patch was just integrated into master:
commit f793d432b9ef562c1a609261faf627d5936d9331
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Nov 5 10:23:33 2014 -0600
arm64: secmon: wait for all CPUs to enter secmon
There is state within the system that relies on having
all CPUs present in order to proceed with initialization.
The current expectation is that all CPUs are online and
entering the secure monitor. Therefore, wait until all
CONFIG_MAX_CPUs show up.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Can get all CPUs up in kernel using PSCI.
Change-Id: I741a09128e99e0cb0c9f4046b1c0d27582fda963
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 030535b7c9821b40bf4a51f88e289eab8af9aa13
Original-Change-Id: Ia0f744c93766efc694b522ab0af9aedf7329ac43
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227547
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9394 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9425
-gerrit
commit c4221f60bf3dd3ac5a109c9797ca9ef57781abfd
Author: Furquan Shaikh <furquan(a)google.com>
Date: Wed Nov 12 16:23:00 2014 -0800
rtc: Add an RTC driver for the TI TPS65913 PMIC.
The TPS65913 PMIC has an RTC built into it. This change adds
a driver for it which implements the new RTC API.
BUG=chrome-os-partner:33764
BRANCH=None
TEST=Compiles and boots to kernel prompt on ryu. Timestamps for event log
verified across multiple boots.
Change-Id: I49ec9b78afc53f1cbd4be09e448cdae6077fb710
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: c16c11e620c830e7a73a2a24fe4823ccea0f3c39
Original-Change-Id: If1d549ea2361d0de6be75fd24b9e9810a6df7457
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229414
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
---
src/drivers/ti/Kconfig | 1 +
src/drivers/ti/Makefile.inc | 2 +
src/drivers/ti/tps65913/Kconfig | 35 ++++++++
src/drivers/ti/tps65913/Makefile.inc | 20 +++++
src/drivers/ti/tps65913/tps65913rtc.c | 155 ++++++++++++++++++++++++++++++++++
5 files changed, 213 insertions(+)
diff --git a/src/drivers/ti/Kconfig b/src/drivers/ti/Kconfig
index b3aded8..42ead03 100644
--- a/src/drivers/ti/Kconfig
+++ b/src/drivers/ti/Kconfig
@@ -18,3 +18,4 @@
##
source src/drivers/ti/tps65090/Kconfig
+source src/drivers/ti/tps65913/Kconfig
diff --git a/src/drivers/ti/Makefile.inc b/src/drivers/ti/Makefile.inc
index c0ed9c0..037da94 100644
--- a/src/drivers/ti/Makefile.inc
+++ b/src/drivers/ti/Makefile.inc
@@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2012 The Chromium OS Authors.
+## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -18,3 +19,4 @@
##
subdirs-$(CONFIG_DRIVER_TI_TPS65090) += tps65090/
+subdirs-$(CONFIG_DRIVERS_TI_TPS65913) += tps65913/
diff --git a/src/drivers/ti/tps65913/Kconfig b/src/drivers/ti/tps65913/Kconfig
new file mode 100644
index 0000000..bd24bae
--- /dev/null
+++ b/src/drivers/ti/tps65913/Kconfig
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config DRIVERS_TI_TPS65913
+ bool "TI TPS65913 support"
+ default n
+
+config DRIVERS_TI_TPS65913_RTC
+ bool "TI TPS65913 RTC support"
+ default n
+ select DRIVERS_TI_TPS65913
+
+config DRIVERS_TI_TPS65913_RTC_BUS
+ int "TI TPS65913 RTC bus"
+ depends on DRIVERS_TI_TPS65913_RTC
+
+config DRIVERS_TI_TPS65913_RTC_ADDR
+ hex "TI TPS65913 RTC chip address"
+ depends on DRIVERS_TI_TPS65913_RTC
diff --git a/src/drivers/ti/tps65913/Makefile.inc b/src/drivers/ti/tps65913/Makefile.inc
new file mode 100644
index 0000000..272b026
--- /dev/null
+++ b/src/drivers/ti/tps65913/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-$(CONFIG_DRIVERS_TI_TPS65913_RTC) += tps65913rtc.c
diff --git a/src/drivers/ti/tps65913/tps65913rtc.c b/src/drivers/ti/tps65913/tps65913rtc.c
new file mode 100644
index 0000000..46dd4f9
--- /dev/null
+++ b/src/drivers/ti/tps65913/tps65913rtc.c
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <bcd.h>
+#include <console/console.h>
+#include <device/i2c.h>
+#include <rtc.h>
+#include <stdint.h>
+
+enum TPS65913_RTC_REG {
+ TPS65913_SECONDS_REG = 0x00,
+ TPS65913_MINUTES_REG = 0x01,
+ TPS65913_HOURS_REG = 0x02,
+ TPS65913_DAYS_REG = 0x03,
+ TPS65913_MONTHS_REG = 0x04,
+ TPS65913_YEARS_REG = 0x05,
+ TPS65913_WEEKS_REG = 0x06,
+ TPS65913_RTC_CTRL_REG = 0x10,
+ TPS65913_RTC_STATUS_REG = 0x11,
+ TPS65913_RTC_INTERRUPS_REG = 0x12,
+};
+
+enum {
+ TPS65913_RTC_CTRL_STOP = (1 << 0),
+ TPS65913_RTC_CTRL_GET_TIME = (1 << 6),
+
+ TPS65913_RTC_STATUS_RUN = (1 << 1),
+ TPS65913_RTC_RUNNING = (1 << 1),
+ TPS65913_RTC_FROZEN = (0 << 1),
+};
+
+static inline uint8_t tps65913_read(enum TPS65913_RTC_REG reg)
+{
+ uint8_t val;
+ i2c_readb(CONFIG_DRIVERS_TI_TPS65913_RTC_BUS,
+ CONFIG_DRIVERS_TI_TPS65913_RTC_ADDR, reg, &val);
+ return val;
+}
+
+static inline void tps65913_write(enum TPS65913_RTC_REG reg, uint8_t val)
+{
+ i2c_writeb(CONFIG_DRIVERS_TI_TPS65913_RTC_BUS,
+ CONFIG_DRIVERS_TI_TPS65913_RTC_ADDR, reg, val);
+}
+
+static void tps65913_rtc_ctrl_clear(uint8_t bit)
+{
+ uint8_t control = tps65913_read(TPS65913_RTC_CTRL_REG);
+
+ control &= ~bit;
+ tps65913_write(TPS65913_RTC_CTRL_REG, control);
+}
+
+static void tps65913_rtc_ctrl_set(uint8_t bit)
+{
+ uint8_t control = tps65913_read(TPS65913_RTC_CTRL_REG);
+
+ control |= TPS65913_RTC_CTRL_GET_TIME;
+ tps65913_write(TPS65913_RTC_CTRL_REG, control);
+}
+
+static int tps65913_is_rtc_running(void)
+{
+ uint8_t status = tps65913_read(TPS65913_RTC_STATUS_REG);
+ return ((status & TPS65913_RTC_STATUS_RUN) == TPS65913_RTC_RUNNING);
+}
+
+/*
+ * This function ensures that current time is copied to shadow registers. Then a
+ * normal read on TC registers reads from the shadow instead of current TC
+ * registers. This helps prevent the accidental change in counters while
+ * reading. In order to ensure that the current TC registers are copied into
+ * shadow registers, GET_TIME bit needs to be set to 0 and then to 1.
+ */
+static void tps65913_rtc_shadow(void)
+{
+ tps65913_rtc_ctrl_clear(TPS65913_RTC_CTRL_GET_TIME);
+ tps65913_rtc_ctrl_set(TPS65913_RTC_CTRL_GET_TIME);
+}
+
+static int tps65913_rtc_stop(void)
+{
+ /* Clearing stop bit freezes RTC */
+ tps65913_rtc_ctrl_clear(TPS65913_RTC_CTRL_STOP);
+
+ if (tps65913_is_rtc_running()) {
+ printk(BIOS_ERR, "Could not stop RTC\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static int tps65913_rtc_start(void)
+{
+ /* Setting stop bit starts RTC */
+ tps65913_rtc_ctrl_set(TPS65913_RTC_CTRL_STOP);
+
+ if (!tps65913_is_rtc_running()) {
+ printk(BIOS_ERR, "Could not start RTC\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+int rtc_set(const struct rtc_time *time)
+{
+ /* Before setting the time, ensure that rtc is stopped */
+ if (tps65913_rtc_stop())
+ return 1;
+
+ tps65913_write(TPS65913_SECONDS_REG, bin2bcd(time->sec));
+ tps65913_write(TPS65913_MINUTES_REG, bin2bcd(time->min));
+ tps65913_write(TPS65913_HOURS_REG, bin2bcd(time->hour));
+ tps65913_write(TPS65913_DAYS_REG, bin2bcd(time->mday));
+ tps65913_write(TPS65913_MONTHS_REG, bin2bcd(time->mon));
+ tps65913_write(TPS65913_YEARS_REG, bin2bcd(time->year));
+
+ /* Re-start rtc */
+ if (tps65913_rtc_start())
+ return 1;
+
+ return 0;
+}
+
+int rtc_get(struct rtc_time *time)
+{
+ tps65913_rtc_shadow();
+
+ time->sec = bcd2bin(tps65913_read(TPS65913_SECONDS_REG) & 0x7f);
+ time->min = bcd2bin(tps65913_read(TPS65913_MINUTES_REG) & 0x7f);
+ time->hour = bcd2bin(tps65913_read(TPS65913_HOURS_REG) & 0x3f);
+ time->mday = bcd2bin(tps65913_read(TPS65913_DAYS_REG) & 0x3f);
+ time->mon = bcd2bin(tps65913_read(TPS65913_MONTHS_REG) & 0x1f);
+ time->year = bcd2bin(tps65913_read(TPS65913_YEARS_REG) & 0xff);
+
+ return 0;
+}