the following patch was just integrated into master:
commit 6dc94c068217f9ea55f84b60725fd4bbc258f7cb
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Wed Nov 12 14:01:23 2014 -0800
vboot: fix invalid check for the returned value from spi_flash->write
spi_flash->write returns non-zero on error and zero on success, not the
number of bytes written.
BUG=none
BRANCH=ToT
TEST=Booted storm. Verified successfully nvdata was saved.
Original-Change-Id: If50cc1a62a4f06398d1830cca60085b6f925fff3
Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229389
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org>
(cherry picked from commit 1e8cdbdb07e99c3f72c35f76d68144f46107acd9)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I216e97f734da8d4b52c2da8329f4143b7b0656cd
Reviewed-on: http://review.coreboot.org/9439
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/9439 for details.
-gerrit
the following patch was just integrated into master:
commit 627b3bd2b09e4daf40001f2a7833df3ef2a257b2
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Mon Nov 3 17:42:09 2014 -0800
cbtables: Add RAM config information
This adds the RAM config code to the coreboot tables. The purpose is
to expose this information to software running at higher levels, e.g.
to print the RAM config coreboot is using as part of factory tests.
The prototype for ram_code() is in boardid.h since they are closely
related and will likely have common code.
BUG=chrome-os-partner:31728
BRANCH=none
TEST=tested w/ follow-up CLs on pinky
Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Original-Change-Id: Idd38ec5b6af16e87dfff2e3750c18fdaea604400
Original-Reviewed-on: https://chromium-review.googlesource.com/227248
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
(cherry picked from commit 77dd5fb9347b53bb8a64ad22341257fb3be0c106)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: Ibe7044cafe0a61214ac2d7fea5f7255b2c11829b
Reviewed-on: http://review.coreboot.org/9438
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/9438 for details.
-gerrit
the following patch was just integrated into master:
commit ceaabc94efec339f75732dd7bf72c51f8dc52941
Author: Gediminas Ramanauskas <gedis(a)google.com>
Date: Tue Nov 4 20:07:09 2014 -0800
vboot: adding VBSD_BOOT_FIRMWARE_WP_ENABLED logic
BUG=chrome-os-partner:33395
BRANCH=none
TEST=emerge and test using crossystem
Original-Change-Id: I0d49f85219d45c837a7100e0195bef86da2c6cdd
Original-Signed-off-by: Gediminas Ramanauskas <gedis(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227546
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 5a2868e04140973691136adfd7d9e6d1aa1f6dae)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I93c1ea9ce1270c2c143fd44ead2291dfbc114c00
Reviewed-on: http://review.coreboot.org/9437
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/9437 for details.
-gerrit
the following patch was just integrated into master:
commit 2ab9f0825fec5007e0a7168f4d432fd86b20aaf2
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Tue Oct 28 18:26:12 2014 -0700
fmap: use CBFS for all other than x86 platforms
The architectiure check in fmap.c is in fact used to delineate between
platforms where SPI flash is mapped to memory address space and where
it needs to be accessed through CBFS.
In fact cosmos board uses an ARM SOC which also maps SPI flash to
processor address space, this will have to be addressed when that
SOC's support is introduced, for now let's just presume that all but
X86 platforms require CBFS layer to access fmap.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=none
Original-Change-Id: Id135dc63278555a7fc5039a568fb28864f7cb8d1
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226180
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit b3c04f84504380066c54a6dec93781a4f25a5fc6)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I3a0a70fe583b69b1c9cd8729817bd7062126e1a9
Reviewed-on: http://review.coreboot.org/9436
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/9436 for details.
-gerrit
the following patch was just integrated into master:
commit 318708ddce2f3322e451bd066c88f5ca04ab179a
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Thu Oct 23 16:02:51 2014 -0700
chromeos: Add a function to copy VPD WiFi calibration data to CBMEM
This patch adds functions looking in the VPD for WiFi calibration
data, and if found, copying the calibration blobs into CBMEM.
Two possible key names templates are used: wifi_base64_calibrationX
and wifi_calibrationX, where X is replaced by the WiFi interface
number. Up to four interfaces can be provisioned.
The calibration data will be retrieved from CBMEM by the bootloader
and placed into the device tree before starting the kernel.
The structure of the WiFi calibration data CBMEM entry is defined
locally: it is a concatenation of the blob names and their contents.
Each blob is padded as necessary to make sure that the size divisible
by four.
To make sure that the exactly required amount of memory is allocated
for the CBMEM entry, the function first scans the VPD, caching the
information about the available blobs and calculating their combined
size.
Then the required size CBMEM entry is allocates and the blobs are
copied into it.
BRANCH=storm
BUG=chrome-os-partner:32611
TEST=when this function is called, and the VPD includes calibration
data blobs, the WIFI entry shows up in the list of CBMEM entries
reported by coreboot.
Original-Change-Id: Ibe02dc36ff6254e3b9ad0a5bd2696ca29e1b2be3
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225271
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 9fe185ae5fdc1a896bf892b498bff27a3462caeb)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: Ia60f0c5c84decf9854426c4f0cb88f8ccee69046
Reviewed-on: http://review.coreboot.org/9435
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9435 for details.
-gerrit
the following patch was just integrated into master:
commit b952f6b68b025bbb9d13deffd3bd621a236537c7
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Apr 8 11:05:37 2015 +0200
build system: Fix SeaBIOS integration with multilib compilers
SeaBIOS doesn't like CC and LD to contain arguments, so split
those out.
Change-Id: Id651719d529adfa8602a3e4f6685228330f36432
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9378
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-by: Kevin O'Connor <kevin(a)koconnor.net>
See http://review.coreboot.org/9378 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9480
-gerrit
commit 32dd9dbbc64ae5980b76b54842ac42e8da08bac3
Author: Kevin L Lee <kevin.l.lee(a)intel.com>
Date: Fri Dec 12 14:02:43 2014 +0800
baytrail: fix the coding error on PCIe L1 exit latency
The original code uses L1EXIT_MASK to shift the bit for
PCIe L1 exit latency, the code should use L1EXIT_SHIFT
for bit shifting.
BUG=chrome-os-partner:34037
BRANCH=None
TEST=build and boot on candy, verify B0:D28:F0 + 4Ch [17:15]
set to 010b. Correspond WIFI device performance got improvement.
Signed-off-by: Kevin L Lee <kevin.l.lee(a)intel.com>
Change-Id: I3ac5b6319b726aa16cdb9678face89022d979517
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 381827e3d92c9e786cd8ebe412586968662fb4be
Original-Change-Id: I8171f80720830cfa76f26778ae31c7590a723b92
Original-Reviewed-on: https://chromium-review.googlesource.com/234673
Original-Reviewed-by: Kenji Chen <kenji.chen(a)intel.com>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com>
Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com>
---
src/soc/intel/baytrail/pcie.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index 1870158..e44ebc6 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -95,7 +95,7 @@ static void byt_pcie_init(device_t dev)
/* Exit latency configuration based on
* PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/
REG_PCI_RMW32(LCAP, ~L1EXIT_MASK,
- 2 << (L1EXIT_MASK + pll_en_off)),
+ 2 << (L1EXIT_SHIFT + pll_en_off)),
REG_SCRIPT_NEXT(init_static_after_exit_latency),
/* Disable hot plug, set power to 10W, set slot number. */
REG_PCI_RMW32(SLCAP, ~(HPC | HPS),
the following patch was just integrated into master:
commit d777c780660bc8e5b4e531b5335e12bb56d8c700
Author: Sergej Ivanov <getinaks(a)gmail.com>
Date: Fri Apr 3 18:10:27 2015 +0300
mainboard/biostar: Add support for Biostar AM1ML ver7.x
Adds AM1ML board. This board has AM1 Socket and supports all
new AM1 APUs from AMD. Based on asrock/imb-a180 board.
Successfully tested with SeaBIOS and Linux 3.8.x and Windows XP.
Successfully tested audio, video, network, PS/2 keyboard and mouse,
PCIe x16, COM port, SATA and USB.
LPT port is not tested yet and it’s unknown if it’s work.
Change-Id: I9ebb9acc590d38e47579adc263f45ae3f607684e
Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com>
Reviewed-on: http://review.coreboot.org/9293
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com>
See http://review.coreboot.org/9293 for details.
-gerrit
the following patch was just integrated into master:
commit c294d702dc74cac6ac9fae8d05f1c1fc036f0b79
Author: Sergej Ivanov <getinaks(a)gmail.com>
Date: Fri Apr 3 16:53:49 2015 +0300
vendorcode/amd/agesa/f16kb: Enable support for AM1 socket
Adds option FORCE_AM1_SOCKET_SUPPORT to disable
package type mismatch check between cpu and northbridge.
Default agesa for kabini doesn't know about AM1 socket
so it returns FALSE, that stops memory config code.
With this hack current agesa version supports the AM1 socket.
Change-Id: I99e9cec5cd558087092cf195094df20489f6d3b5
Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com>
Reviewed-on: http://review.coreboot.org/9291
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com>
See http://review.coreboot.org/9291 for details.
-gerrit