the following patch was just integrated into master:
commit f687c92c9b86b8f1e2a48d2cdf16383587d33e68
Author: Sergej Ivanov <getinaks(a)gmail.com>
Date: Fri Apr 3 16:58:19 2015 +0300
southbridge/amd/agesa/hudson: Fix LPC_DEV definition
In agesa code for hudson southbridge LPC_DEV is not defined,
but used. Define LPC_DEV as done in southbridge/amd/cimx/sb800.
This fixes it.
Change-Id: Ie7db791e9eb607008e70e446fc6fd28114742750
Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com>
Reviewed-on: http://review.coreboot.org/9292
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com>
See http://review.coreboot.org/9292 for details.
-gerrit
Sergej Ivanov (getinaks(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9291
-gerrit
commit 3b3ba6ab2fabe406d0db7d798a78cdf4562b8d44
Author: Sergej Ivanov <getinaks(a)gmail.com>
Date: Fri Apr 3 16:53:49 2015 +0300
vendorcode/amd/agesa/f16kb: Enable support for AM1 socket
Adds option FORCE_AM1_SOCKET_SUPPORT to disable
package type mismatch check between cpu and northbridge.
Default agesa for kabini doesn't know about AM1 socket
so it returns FALSE, that stops memory config code.
With this hack current agesa version supports the AM1 socket.
Change-Id: I99e9cec5cd558087092cf195094df20489f6d3b5
Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com>
---
src/cpu/amd/agesa/family16kb/Kconfig | 11 +++++++++++
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c | 5 ++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig
index d36652b..d22a09d 100644
--- a/src/cpu/amd/agesa/family16kb/Kconfig
+++ b/src/cpu/amd/agesa/family16kb/Kconfig
@@ -62,4 +62,15 @@ config HIGH_SCRATCH_MEMORY_SIZE
# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
default 0xA1000
+config FORCE_AM1_SOCKET_SUPPORT
+ bool
+ default n
+ help
+ Force AGESA to ignore package type mismatch between CPU and northbridge
+ in memory code. This enables Socket AM1 support with current AGESA
+ version for Kabini platform.
+ Enable this option only if you have Socket AM1 board.
+ Note that the AGESA release shipped with coreboot does not officially
+ support the AM1 socket. Selecting this option might damage your hardware.
+
endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
index 348f704..b4a60a1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
@@ -489,7 +489,10 @@ MemPIsIdSupported (
return TRUE;
}
}
- return FALSE;
+ if (IS_ENABLED(CONFIG_FORCE_AM1_SOCKET_SUPPORT))
+ return TRUE;
+ else
+ return FALSE;
}
/* -----------------------------------------------------------------------------*/
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9538
-gerrit
commit 8830008e09a0bf7a4b0a1a2c3bed80115b198bc6
Author: Furquan Shaikh <furquan(a)google.com>
Date: Fri Nov 21 15:35:17 2014 -0800
arm64: Add conditional read/write from/to EL3 assembly macros.
Some registers are available only at EL3. Add conditional read/write functions
that perform operations only if currently we are in EL3.
BUG=chrome-os-partner:33962
BRANCH=None
TEST=Compiles and boots to kernel prompt.
Change-Id: Ic95838d10e18f58867b6b77aee937bdacae50597
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 62a0e324a00248dba92cb3e2ac2f4072d0e4e2a7
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Change-Id: Ia170d94adb9ecc141ff86e4a3041ddbf9045bc89
Original-Reviewed-on: https://chromium-review.googlesource.com/231549
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
---
src/arch/arm64/include/armv8/arch/lib_helpers.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h
index a804747..422b81a 100644
--- a/src/arch/arm64/include/armv8/arch/lib_helpers.h
+++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h
@@ -214,6 +214,31 @@
104:
.endm
+/* Macro to read from a register at EL3 only if we are currently at that
+ level. This is required to ensure that we do not attempt to read registers
+ from a level lower than el3. e.g. SCR is available for read only at EL3.
+ IMPORTANT: if EL != EL3, macro silently doesn't perform the read.
+*/
+.macro read_el3 xreg sysreg
+ switch_el \xreg, 402f, 402f, 401f
+401:
+ mrs \xreg, \sysreg\()_el3
+402:
+.endm
+
+/* Macro to write to a register at EL3 only if we are currently at that
+ level. This is required to ensure that we do not attempt to write to
+ registers from a level lower than el3. e.g. SCR is available to write only at
+ EL3.
+ IMPORTANT: if EL != EL3, macro silently doesn't perform the write.
+*/
+.macro write_el3 sysreg xreg temp
+ switch_el \temp, 402f, 402f, 401f
+401:
+ msr \sysreg\()_el3, \xreg
+402:
+.endm
+
#else
#include <stdint.h>
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9536
-gerrit
commit 410cf26a4e16b091c6cde962204d6ff38480320f
Author: Furquan Shaikh <furquan(a)google.com>
Date: Fri Nov 21 17:07:16 2014 -0800
tegra132: Make non-vboot2 memlayout more useful
Update non-vboot2 memlayout:
1) Add timestamp region
2) Increase ramstage size
3) Change name from memlayout_vboot.ld to memlayout.ld so that any non-vboot
upstream board can also use this layout.
BUG=None
BRANCH=None
TEST=Compiles and boots to kernel prompt on ryu with vboot selected instead of
vboot2.
Change-Id: Idced98f9df7cdbab5f62cd1e382c6046ade1d867
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 20fffa282b20fb32ce2ff687f4479be630f90fcf
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Change-Id: I91accd54efc53ab563a2063b9c6e9390f5dd527f
Original-Reviewed-on: https://chromium-review.googlesource.com/231547
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
---
src/mainboard/google/rush/memlayout.ld | 2 +-
src/mainboard/google/rush_ryu/memlayout.ld | 2 +-
src/soc/nvidia/tegra132/include/soc/memlayout.ld | 44 ++++++++++++++++++++++
.../nvidia/tegra132/include/soc/memlayout_vboot.ld | 43 ---------------------
4 files changed, 46 insertions(+), 45 deletions(-)
diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld
index 5bd72e5..d8fdb9a 100644
--- a/src/mainboard/google/rush/memlayout.ld
+++ b/src/mainboard/google/rush/memlayout.ld
@@ -1,5 +1,5 @@
#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
#include <soc/memlayout_vboot2.ld>
#else
-#include <soc/memlayout_vboot.ld>
+#include <soc/memlayout.ld>
#endif
diff --git a/src/mainboard/google/rush_ryu/memlayout.ld b/src/mainboard/google/rush_ryu/memlayout.ld
index 5bd72e5..d8fdb9a 100644
--- a/src/mainboard/google/rush_ryu/memlayout.ld
+++ b/src/mainboard/google/rush_ryu/memlayout.ld
@@ -1,5 +1,5 @@
#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
#include <soc/memlayout_vboot2.ld>
#else
-#include <soc/memlayout_vboot.ld>
+#include <soc/memlayout.ld>
#endif
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
new file mode 100644
index 0000000..a7e3635
--- /dev/null
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
+ * so the bootblock loading address must be placed after that. After the
+ * handoff that area may be reclaimed for other uses, e.g. CBFS cache.
+ * TODO: Did this change on Tegra132? What's the new valid range?
+ */
+
+SECTIONS
+{
+ SRAM_START(0x40000000)
+ PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
+ PRERAM_CBFS_CACHE(0x40002000, 84K)
+ STACK(0x40017000, 16K)
+ BOOTBLOCK(0x4001B800, 22K)
+ ROMSTAGE(0x40021000, 124K)
+ SRAM_END(0x40040000)
+
+ DRAM_START(0x80000000)
+ POSTRAM_CBFS_CACHE(0x80100000, 1M)
+ RAMSTAGE(0x80200000, 256K)
+}
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld
deleted file mode 100644
index c097c3c..0000000
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
- * so the bootblock loading address must be placed after that. After the
- * handoff that area may be reclaimed for other uses, e.g. CBFS cache.
- * TODO: Did this change on Tegra132? What's the new valid range?
- */
-
-SECTIONS
-{
- SRAM_START(0x40000000)
- PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
- CBFS_CACHE(0x40002000, 88K)
- STACK(0x40018000, 16K)
- BOOTBLOCK(0x4001C000, 20K)
- ROMSTAGE(0x40021000, 124K)
- SRAM_END(0x40040000)
-
- DRAM_START(0x80000000)
- RAMSTAGE(0x80200000, 192K)
-}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9542
-gerrit
commit 92ee859f080874f0e6734525ce4f9b034f484a9c
Author: Joseph Lo <josephl(a)nvidia.com>
Date: Fri Nov 21 08:54:15 2014 +0800
tegra132: psci: add cpu_on/off support
The CPU on/off functions are the method for the Kernel to support CPU
hot-plug function in PSCI. To support this, we still need flow controller
support to capture the WFI from the CPU and inform PMC to power gate the
CPU core. On the other path, we turn on the CPU by toggling the PMC and
use flow controller to let go when the power is steady.
BUG=chrome-os-partner:32136
BRANCH=None
TEST=built the kernel with PSCI enabled,
check both of the CPUs are coming up,
test the CPU hot-plug is working on Ryu
Change-Id: If2c529b6719c5747d5aea95fb5049b2d7353ff17
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 0f078e89daad1c4d8b342a395f36b3e922af66f5
Original-Change-Id: Ie49940adb2966dcc9967d2fcc9b1e0dcd6d98743
Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/231267
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/nvidia/tegra132/Makefile.inc | 2 +
src/soc/nvidia/tegra132/flow_ctrl.c | 96 +++++++++++++++++++++++++
src/soc/nvidia/tegra132/include/soc/flow_ctrl.h | 26 +++++++
src/soc/nvidia/tegra132/psci.c | 75 ++++++++++++++++++-
4 files changed, 197 insertions(+), 2 deletions(-)
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index a46a2e5..fc22b2a 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -97,6 +97,8 @@ ramstage-$(CONFIG_ARCH_USE_SECURE_MONITOR) += secmon.c
secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += 32bit_reset.S
secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += cpu.c
secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += cpu_lib.S
+secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += flow_ctrl.c
+secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += power.c
secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += psci.c
secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += uart.c
diff --git a/src/soc/nvidia/tegra132/flow_ctrl.c b/src/soc/nvidia/tegra132/flow_ctrl.c
new file mode 100644
index 0000000..4da54b1
--- /dev/null
+++ b/src/soc/nvidia/tegra132/flow_ctrl.c
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <soc/addressmap.h>
+#include <soc/flow_ctrl.h>
+
+#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
+#define FLOW_CTRL_WAITEVENT (2 << 29)
+#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
+#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11)
+#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10)
+#define FLOW_CTRL_CPU0_CSR 0x8
+#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
+#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
+#define FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
+#define FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
+#define FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
+#define FLOW_CTRL_CSR_ENABLE (1 << 0)
+#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
+#define FLOW_CTRL_CPU1_CSR 0x18
+
+#define HALT_REG_CORE0 (\
+ FLOW_CTRL_WAIT_FOR_INTERRUPT | \
+ FLOW_CTRL_HALT_LIC_IRQ | \
+ FLOW_CTRL_HALT_LIC_FIQ)
+
+#define HALT_REG_CORE1 FLOW_CTRL_WAITEVENT
+
+static void *tegra_flowctrl_base = (void*)TEGRA_FLOW_BASE;
+
+static const uint8_t flowctrl_offset_halt_cpu[] = {
+ FLOW_CTRL_HALT_CPU0_EVENTS,
+ FLOW_CTRL_HALT_CPU1_EVENTS
+};
+
+static const uint8_t flowctrl_offset_cpu_csr[] = {
+ FLOW_CTRL_CPU0_CSR,
+ FLOW_CTRL_CPU1_CSR
+};
+
+static uint32_t flowctrl_read_cpu_csr(int cpu)
+{
+ return read32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
+}
+
+static void flowctrl_write_cpu_csr(int cpu, uint32_t val)
+{
+ write32(val, tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
+ val = readl(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
+}
+
+void flowctrl_write_cpu_halt(int cpu, uint32_t val)
+{
+ writel(val, tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]);
+ val = readl(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]);
+}
+
+static void flowctrl_prepare_cpu_off(int cpu)
+{
+ uint32_t reg;
+
+ reg = flowctrl_read_cpu_csr(cpu);
+ reg &= ~FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */
+ reg &= ~FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */
+ reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
+ reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
+ reg |= FLOW_CTRL_CSR_WFI_CPU0 << cpu; /* power gating on wfi */
+ reg |= FLOW_CTRL_CSR_ENABLE; /* enable power gating */
+ flowctrl_write_cpu_csr(cpu, reg);
+}
+
+void flowctrl_cpu_off(int cpu)
+{
+ uint32_t reg;
+
+ reg = cpu ? HALT_REG_CORE1 : HALT_REG_CORE0;
+ flowctrl_prepare_cpu_off(cpu);
+ flowctrl_write_cpu_halt(cpu, reg);
+}
diff --git a/src/soc/nvidia/tegra132/include/soc/flow_ctrl.h b/src/soc/nvidia/tegra132/include/soc/flow_ctrl.h
new file mode 100644
index 0000000..28fe846
--- /dev/null
+++ b/src/soc/nvidia/tegra132/include/soc/flow_ctrl.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _TEGRA132_FLOW_CTRL_H_
+#define _TEGRA132_FLOW_CTRL_H_
+
+void flowctrl_cpu_off(int cpu);
+void flowctrl_write_cpu_halt(int cpu, uint32_t val);
+
+#endif
diff --git a/src/soc/nvidia/tegra132/psci.c b/src/soc/nvidia/tegra132/psci.c
index b075ffc..4525f98 100644
--- a/src/soc/nvidia/tegra132/psci.c
+++ b/src/soc/nvidia/tegra132/psci.c
@@ -17,8 +17,16 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
*/
+#include <arch/cpu.h>
+#include <arch/io.h>
#include <arch/psci.h>
+#include <soc/addressmap.h>
+#include <soc/clk_rst.h>
#include <soc/cpu.h>
+#include <soc/flow_ctrl.h>
+#include <soc/power.h>
+
+#include <console/console.h>
static void *cpu_on_entry_point;
@@ -57,14 +65,77 @@ static size_t children_at_level(int parent_level, uint64_t mpidr)
}
}
+#define TEGRA132_PM_CORE_C7 0x3
+
+static inline void tegra132_enter_sleep(unsigned long pmstate)
+{
+ asm volatile(
+ " isb\n"
+ " msr actlr_el1, %0\n"
+ " wfi\n"
+ :
+ : "r" (pmstate));
+}
+
+static void prepare_cpu_on(int cpu)
+{
+ uint32_t partid;
+
+ partid = cpu ? POWER_PARTID_CE1 : POWER_PARTID_CE0;
+
+ power_ungate_partition(partid);
+ flowctrl_write_cpu_halt(cpu, 0);
+}
+
static int cmd_prepare(struct psci_cmd *cmd)
{
- return PSCI_RET_NOT_SUPPORTED;
+ int ret;
+
+ switch (cmd->type) {
+ case PSCI_CMD_ON:
+ prepare_cpu_on(cmd->target->cpu_state.ci->id);
+ ret = PSCI_RET_SUCCESS;
+ break;
+ case PSCI_CMD_OFF:
+ if (cmd->state_id != -1) {
+ ret = PSCI_RET_INVALID_PARAMETERS;
+ break;
+ }
+ cmd->state_id = TEGRA132_PM_CORE_C7;
+ ret = PSCI_RET_SUCCESS;
+ break;
+ default:
+ ret = PSCI_RET_NOT_SUPPORTED;
+ break;
+ }
+ return ret;
}
static int cmd_commit(struct psci_cmd *cmd)
{
- return PSCI_RET_NOT_SUPPORTED;
+ int ret;
+ struct cpu_info *ci;
+
+ ci = cmd->target->cpu_state.ci;
+
+ switch (cmd->type) {
+ case PSCI_CMD_ON:
+ /* Take CPU out of reset */
+ start_cpu_silent(ci->id, cpu_on_entry_point);
+ ret = PSCI_RET_SUCCESS;
+ break;
+ case PSCI_CMD_OFF:
+ flowctrl_cpu_off(ci->id);
+ tegra132_enter_sleep(cmd->state_id);
+ /* Never reach here */
+ ret = PSCI_RET_NOT_SUPPORTED;
+ printk(BIOS_ERR, "t132 CPU%d PSCI_CMD_OFF fail\n", ci->id);
+ break;
+ default:
+ ret = PSCI_RET_NOT_SUPPORTED;
+ break;
+ }
+ return ret;
}
struct psci_soc_ops soc_psci_ops = {
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9541
-gerrit
commit 583d6c25726b640a9a64ba31012742a19b018bc8
Author: Furquan Shaikh <furquan(a)google.com>
Date: Fri Nov 21 15:54:39 2014 -0800
arm64: No need of invalidating cache line for secondary CPU stack
With support for initializing registers based on values saved by primary CPU, we
no longer need to invalidate secondary CPU stack cache lines. Before jumping to
C environment, we enable caching and update the required registers.
BUG=chrome-os-partner:33962
BRANCH=None
TEST=Compiles and boots both CPU0 and CPU1 on ryu.
Change-Id: Ifee36302b5de25b909b4570a30ada8ecd742ab82
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 0a0403d06b89dae30b7520747501b0521d16a6db
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Change-Id: I738250f948e912725264cba3e389602af7510e3e
Original-Reviewed-on: https://chromium-review.googlesource.com/231563
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
---
src/arch/arm64/cpu_ramstage.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c
index e6d0e8c..466ca01 100644
--- a/src/arch/arm64/cpu_ramstage.c
+++ b/src/arch/arm64/cpu_ramstage.c
@@ -151,13 +151,6 @@ static void init_cpu_info(struct bus *bus)
}
}
-static void invalidate_cpu_stack_top(unsigned int id)
-{
- const size_t size = 128;
- char *stack = cpu_get_stack(id);
- dcache_invalidate_by_mva(stack - size, size);
-}
-
void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops)
{
size_t max_cpus;
@@ -221,9 +214,6 @@ void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops)
/* Start the CPU. */
printk(BIOS_DEBUG, "Starting CPU%x\n", ci->id);
- /* Ensure CPU's top of stack is not in the cache. */
- invalidate_cpu_stack_top(ci->id);
-
if (cntrl_ops->start_cpu(ci->id, entry)) {
printk(BIOS_ERR,
"Failed to start CPU%x\n", ci->id);