coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: a5f5aee libpayload: move MRC processing to x86 path and remove ACPI_GNVS duplication
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8752 -gerrit commit a5f5aee1e1c69a8fa3eab78f8b469dd5c7a0c084 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Oct 24 13:29:43 2014 -0700 libpayload: move MRC processing to x86 path and remove ACPI_GNVS duplication It turns out that CB_TAG_ACPI_GNVS is handled in both x86 specific and common coreboot table parsing code. The MRC cache case used only by x86 is handled in the common code. This patch restores sanity and moves processing to where it belongs. BRANCH=none BUG=none TEST=verified that arm and x86 targets build. Change-Id: Iaddaa3380725be6d08a51a96c68b70522531bafe Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0afae893d5027026cb666cd46e054aeae4e71f83 Original-Change-Id: I2c114a8469455002c51593cb8be80585925969a7 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225457 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/x86/coreboot.c | 18 +++++++++--------- payloads/libpayload/libc/coreboot.c | 9 --------- 2 files changed, 9 insertions(+), 18 deletions(-) diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index 1f37b80..3a9eb1a 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -42,27 +42,27 @@ /* === Parsing code === */ /* This is the generic parsing code. */ -static void cb_parse_acpi_gnvs(void *ptr, struct sysinfo_t *info) -{ - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->acpi_gnvs = phys_to_virt(cbmem->cbmem_tab); -} - static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info) { struct cb_x86_rom_mtrr *rom_mtrr = ptr; info->x86_rom_var_mtrr_index = rom_mtrr->index; } +static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info) +{ + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; + info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); +} + int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) { switch(rec->tag) { - case CB_TAG_ACPI_GNVS: - cb_parse_acpi_gnvs(rec, info); - break; case CB_TAG_X86_ROM_MTRR: cb_parse_x86_rom_var_mtrr(rec, info); break; + case CB_TAG_MRC_CACHE: + cb_parse_mrc_cache(rec, info); + break; default: return 0; } diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 8bd118e..5da6cb8 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -142,12 +142,6 @@ static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) info->cbmem_cons = phys_to_virt(cbmem->cbmem_tab); } -static void cb_parse_mrc_cache(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); -} - static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) { struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; @@ -315,9 +309,6 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_CBMEM_CONSOLE: cb_parse_cbmem_cons(ptr, info); break; - case CB_TAG_MRC_CACHE: - cb_parse_mrc_cache(ptr, info); - break; case CB_TAG_ACPI_GNVS: cb_parse_acpi_gnvs(ptr, info); break;

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Patch set updated for coreboot: 04c1c2e libpayload: make wifi calibration table available through sysinfo
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8753 -gerrit commit 04c1c2ec19b8ca6ff61c97b4f30f61e8fd3dcb26 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Oct 24 15:14:55 2014 -0700 libpayload: make wifi calibration table available through sysinfo The WiFi calibration blob saved in the CBMEM by coreboot needs to be visible by depthcharge to supply it to the kernel. BRANCH=storm BUG=chrome-os-partner:32611 TEST=none yet Change-Id: I43a857f073a47ca315d400df4c53d5eb38e91601 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 46a649608e6740e07c562c722fadd8c64e264b5f Original-Change-Id: Iecd8739c9269b58064b3c3275f5376cebcd6804b Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225506 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/include/coreboot_tables.h | 1 + payloads/libpayload/include/sysinfo.h | 1 + payloads/libpayload/libc/coreboot.c | 9 +++++++++ 3 files changed, 11 insertions(+) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 13a9978..72c2ad8 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -199,6 +199,7 @@ struct lb_range { #define CB_TAG_CBMEM_CONSOLE 0x0017 #define CB_TAG_MRC_CACHE 0x0018 #define CB_TAG_ACPI_GNVS 0x0024 +#define CB_TAG_WIFI_CALIBRATION 0x0027 struct cb_cbmem_tab { uint32_t tag; uint32_t size; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index b90a8bd..5ad839b 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -114,6 +114,7 @@ struct sysinfo_t { void *mrc_cache; void *acpi_gnvs; u32 board_id; + void *wifi_calibration; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 5da6cb8..f9b03c2 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -183,6 +183,12 @@ static void cb_parse_string(unsigned char *ptr, char **info) *info = (char *)((struct cb_string *)ptr)->string; } +static void cb_parse_wifi_calibration(void *ptr, struct sysinfo_t *info) +{ + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; + info->wifi_calibration = phys_to_virt(cbmem->cbmem_tab); +} + int cb_parse_header(void *addr, int len, struct sysinfo_t *info) { struct cb_header *header; @@ -315,6 +321,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_BOARD_ID: cb_parse_board_id(ptr, info); break; + case CB_TAG_WIFI_CALIBRATION: + cb_parse_wifi_calibration(ptr, info); + break; default: cb_parse_arch_specific(rec, info); break;

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New patch to review for coreboot: da85051 libpayload: make wifi calibration table available through sysinfo
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8753 -gerrit commit da8505119ef1f664703ce83c0cbcbaa0187d5a32 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Oct 24 15:14:55 2014 -0700 libpayload: make wifi calibration table available through sysinfo The WiFi calibration blob saved in the CBMEM by coreboot needs to be visible by depthcharge to supply it to the kernel. BRANCH=storm BUG=chrome-os-partner:32611 TEST=none yet Change-Id: I43a857f073a47ca315d400df4c53d5eb38e91601 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 46a649608e6740e07c562c722fadd8c64e264b5f Original-Change-Id: Iecd8739c9269b58064b3c3275f5376cebcd6804b Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225506 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/include/coreboot_tables.h | 1 + payloads/libpayload/include/sysinfo.h | 1 + payloads/libpayload/libc/coreboot.c | 9 +++++++++ 3 files changed, 11 insertions(+) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 13a9978..72c2ad8 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -199,6 +199,7 @@ struct lb_range { #define CB_TAG_CBMEM_CONSOLE 0x0017 #define CB_TAG_MRC_CACHE 0x0018 #define CB_TAG_ACPI_GNVS 0x0024 +#define CB_TAG_WIFI_CALIBRATION 0x0027 struct cb_cbmem_tab { uint32_t tag; uint32_t size; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index b90a8bd..5ad839b 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -114,6 +114,7 @@ struct sysinfo_t { void *mrc_cache; void *acpi_gnvs; u32 board_id; + void *wifi_calibration; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 5da6cb8..f9b03c2 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -183,6 +183,12 @@ static void cb_parse_string(unsigned char *ptr, char **info) *info = (char *)((struct cb_string *)ptr)->string; } +static void cb_parse_wifi_calibration(void *ptr, struct sysinfo_t *info) +{ + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; + info->wifi_calibration = phys_to_virt(cbmem->cbmem_tab); +} + int cb_parse_header(void *addr, int len, struct sysinfo_t *info) { struct cb_header *header; @@ -315,6 +321,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_BOARD_ID: cb_parse_board_id(ptr, info); break; + case CB_TAG_WIFI_CALIBRATION: + cb_parse_wifi_calibration(ptr, info); + break; default: cb_parse_arch_specific(rec, info); break;

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New patch to review for coreboot: 5797220 libpayload: move MRC processing to x86 path and remove ACPI_GNVS duplication
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8752 -gerrit commit 5797220a34d168d731f852a0bfa1ca988463d87e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Oct 24 13:29:43 2014 -0700 libpayload: move MRC processing to x86 path and remove ACPI_GNVS duplication It turns out that CB_TAG_ACPI_GNVS is handled in both x86 specific and common coreboot table parsing code. The MRC cache case used only by x86 is handled in the common code. This patch restores sanity and moves processing to where it belongs. BRANCH=none BUG=none TEST=verified that arm and x86 targets build. Change-Id: Iaddaa3380725be6d08a51a96c68b70522531bafe Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0afae893d5027026cb666cd46e054aeae4e71f83 Original-Change-Id: I2c114a8469455002c51593cb8be80585925969a7 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225457 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/x86/coreboot.c | 18 +++++++++--------- payloads/libpayload/libc/coreboot.c | 9 --------- 2 files changed, 9 insertions(+), 18 deletions(-) diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index 1f37b80..3a9eb1a 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -42,27 +42,27 @@ /* === Parsing code === */ /* This is the generic parsing code. */ -static void cb_parse_acpi_gnvs(void *ptr, struct sysinfo_t *info) -{ - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->acpi_gnvs = phys_to_virt(cbmem->cbmem_tab); -} - static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info) { struct cb_x86_rom_mtrr *rom_mtrr = ptr; info->x86_rom_var_mtrr_index = rom_mtrr->index; } +static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info) +{ + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; + info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); +} + int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) { switch(rec->tag) { - case CB_TAG_ACPI_GNVS: - cb_parse_acpi_gnvs(rec, info); - break; case CB_TAG_X86_ROM_MTRR: cb_parse_x86_rom_var_mtrr(rec, info); break; + case CB_TAG_MRC_CACHE: + cb_parse_mrc_cache(rec, info); + break; default: return 0; } diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 8bd118e..5da6cb8 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -142,12 +142,6 @@ static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) info->cbmem_cons = phys_to_virt(cbmem->cbmem_tab); } -static void cb_parse_mrc_cache(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); -} - static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) { struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; @@ -315,9 +309,6 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_CBMEM_CONSOLE: cb_parse_cbmem_cons(ptr, info); break; - case CB_TAG_MRC_CACHE: - cb_parse_mrc_cache(ptr, info); - break; case CB_TAG_ACPI_GNVS: cb_parse_acpi_gnvs(ptr, info); break;

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New patch to review for coreboot: 557a208 libpayload: cros: include mac addresses in coreboot table
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8751 -gerrit commit 557a20873b9e4929b315e043b04d3610c6ccbca5 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Sep 22 19:36:28 2014 -0700 libpayload: cros: include mac addresses in coreboot table Pass MAC addresses found in coreboot table into lib_sysinfo. BUG=chrome-os-partner:32152 TEST=with all changes in place MAC addresses are properly inserted into the kernel device tree. Change-Id: I6b13c1c2c246362256abce3efa4a97b355647ef8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e2fe74f86b4ed43eb8a3c9d99055afc5d6fb7b78 Original-Change-Id: I1d0bd437fb27fabd14b9ba1fb5415586cd8847bb Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219444 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/include/coreboot_tables.h | 12 ++++++++++++ payloads/libpayload/include/sysinfo.h | 5 +++++ payloads/libpayload/libc/coreboot.c | 17 +++++++++++++++++ 3 files changed, 34 insertions(+) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 53b5890..13a9978 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -224,6 +224,18 @@ struct cb_x86_rom_mtrr { uint32_t index; }; +#define CB_TAG_MAC_ADDRS 0x0026 +struct mac_address { + uint8_t mac_addr[6]; + uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */ +}; + +struct cb_macs { + uint32_t tag; + uint32_t size; + uint32_t count; + struct mac_address mac_addrs[0]; +}; #define CB_TAG_CMOS_OPTION_TABLE 0x00c8 struct cb_cmos_option_table { diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index f4f47b7..b90a8bd 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -35,6 +35,9 @@ /* Allow a maximum of 8 GPIOs */ #define SYSINFO_MAX_GPIOS 8 +/* Up to 10 MAC addresses */ +#define SYSINFO_MAX_MACS 10 + #include <coreboot_tables.h> struct cb_serial; @@ -86,6 +89,8 @@ struct sysinfo_t { #ifdef CONFIG_LP_CHROMEOS int num_gpios; struct cb_gpio gpios[SYSINFO_MAX_GPIOS]; + int num_macs; + struct mac_address macs[SYSINFO_MAX_MACS]; #endif unsigned long *mbtable; /** Pointer to the multiboot table */ diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 1563d4a..8bd118e 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -114,6 +114,20 @@ static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info) info->vdat_addr = phys_to_virt(vdat->range_start); info->vdat_size = vdat->range_size; } + +static void cb_parse_mac_addresses(unsigned char *ptr, + struct sysinfo_t *info) +{ + struct cb_macs *macs = (struct cb_macs *)ptr; + int i; + + info->num_macs = (macs->count < ARRAY_SIZE(info->macs)) ? + macs->count : ARRAY_SIZE(info->macs); + + for (i = 0; i < info->num_macs; i++) + info->macs[i] = macs->mac_addrs[i]; +} + #endif static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) @@ -291,6 +305,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_VBOOT_HANDOFF: cb_parse_vboot_handoff(ptr, info); break; + case CB_TAG_MAC_ADDRS: + cb_parse_mac_addresses(ptr, info); + break; #endif case CB_TAG_TIMESTAMPS: cb_parse_tstamp(ptr, info);

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New patch to review for coreboot: e2f762f Consolidate coreboot table parsing
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8750 -gerrit commit e2f762f05d97f8f8088c95f796558ba05509b0f5 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Jul 31 21:02:57 2014 -0700 Consolidate coreboot table parsing There are three instances of coreboot.c in libpayload. for x86, arm and arm64 architectures. The arm and arm64 instances are exactly the same. The differences with the x86 instance are as follows: - a very slightly different set of coreboot table tags is parsed (one tag added and two removed) - instead of checking a fixed address if it contains the coreboot table, the x86 version iterates over two address ranges. This patch refactors the module, leaving architecture specific processing in arch subdirectories and moving the common code into libc. BUG=none TEST=none yet Change-Id: I1c7ad6f74e3498e93df78086ba0ff708c08e0a5c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3df209d58ebd5c5b1cf0168f6466e065d1ef3598 Original-Change-Id: I6dfed73f6ba5939f692d0f98d2774c0e0312a25f Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210770 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/arm/coreboot.c | 276 +------------------------- payloads/libpayload/arch/arm64/coreboot.c | 276 +------------------------- payloads/libpayload/arch/x86/coreboot.c | 281 ++------------------------ payloads/libpayload/include/sysinfo.h | 14 ++ payloads/libpayload/libc/Makefile.inc | 1 + payloads/libpayload/libc/coreboot.c | 319 ++++++++++++++++++++++++++++++ 6 files changed, 362 insertions(+), 805 deletions(-) diff --git a/payloads/libpayload/arch/arm/coreboot.c b/payloads/libpayload/arch/arm/coreboot.c index a1c3675..056d63e 100644 --- a/payloads/libpayload/arch/arm/coreboot.c +++ b/payloads/libpayload/arch/arm/coreboot.c @@ -35,279 +35,21 @@ /* This pointer gets set in head.S and is passed in from coreboot. */ void *cb_header_ptr; -/* - * Some of this is x86 specific, and the rest of it is generic. Right now, - * since we only support x86, we'll avoid trying to make lots of infrastructure - * we don't need. If in the future, we want to use coreboot on some other - * architecture, then take out the generic parsing code and move it elsewhere. - */ - -/* === Parsing code === */ -/* This is the generic parsing code. */ - -static void cb_parse_memory(void *ptr, struct sysinfo_t *info) -{ - struct cb_memory *mem = ptr; - int count = MEM_RANGE_COUNT(mem); - int i; - - if (count > SYSINFO_MAX_MEM_RANGES) - count = SYSINFO_MAX_MEM_RANGES; - - info->n_memranges = 0; - - for (i = 0; i < count; i++) { - struct cb_memory_range *range = MEM_RANGE_PTR(mem, i); - -#ifdef CONFIG_LP_MEMMAP_RAM_ONLY - if (range->type != CB_MEM_RAM) - continue; -#endif - - info->memrange[info->n_memranges].base = - cb_unpack64(range->start); - - info->memrange[info->n_memranges].size = - cb_unpack64(range->size); - - info->memrange[info->n_memranges].type = range->type; - - info->n_memranges++; - } -} - -static void cb_parse_serial(void *ptr, struct sysinfo_t *info) -{ - info->serial = ((struct cb_serial *)ptr); -} - -#ifdef CONFIG_LP_CHROMEOS -static void cb_parse_vboot_handoff(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_range *vbho = (struct cb_range *)ptr; - - info->vboot_handoff = (void *)(uintptr_t)vbho->range_start; - info->vboot_handoff_size = vbho->range_size; -} - -static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) -{ - struct lb_range *vbnv = (struct lb_range *)ptr; - - info->vbnv_start = vbnv->range_start; - info->vbnv_size = vbnv->range_size; -} - -static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info) -{ - int i; - struct cb_gpios *gpios = (struct cb_gpios *)ptr; - - info->num_gpios = (gpios->count < SYSINFO_MAX_GPIOS) ? - (gpios->count) : SYSINFO_MAX_GPIOS; - - for (i = 0; i < info->num_gpios; i++) - info->gpios[i] = gpios->gpios[i]; -} - -static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info) -{ - struct lb_range *vdat = (struct lb_range *)ptr; - - info->vdat_addr = phys_to_virt(vdat->range_start); - info->vdat_size = vdat->range_size; -} -#endif - -static void cb_parse_dma(unsigned char *ptr) +static void cb_parse_dma(void *ptr) { struct lb_range *dma = (struct lb_range *)ptr; init_dma_memory(phys_to_virt(dma->range_start), dma->range_size); } -static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) +int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->tstamp_table = phys_to_virt(cbmem->cbmem_tab); -} - -static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->cbmem_cons = phys_to_virt(cbmem->cbmem_tab); -} - -static void cb_parse_mrc_cache(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); -} - -static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_board_id *const cbbid = (struct cb_board_id *)ptr; - info->board_id = cbbid->board_id; -} - -#ifdef CONFIG_LP_NVRAM -static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) -{ - /* ptr points to a coreboot table entry and is already virtual */ - info->option_table = ptr; -} - -static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) -{ - struct cb_cmos_checksum *cmos_cksum = ptr; - info->cmos_range_start = cmos_cksum->range_start; - info->cmos_range_end = cmos_cksum->range_end; - info->cmos_checksum_location = cmos_cksum->location; -} -#endif - -#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE -static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) -{ - /* ptr points to a coreboot table entry and is already virtual */ - info->framebuffer = ptr; -} -#endif - -static void cb_parse_string(unsigned char *ptr, char **info) -{ - *info = (char *)((struct cb_string *)ptr)->string; -} - -static int cb_parse_header(void *addr, struct sysinfo_t *info) -{ - struct cb_header *header = addr; - unsigned char *ptr = addr; - void *forward; - int i; - - /* No signature found. */ - if (strncmp((const char *)header->signature, "LBIO", 4)) - return -1; - - if (!header->table_bytes) + switch(rec->tag) { + case CB_TAG_DMA: + cb_parse_dma(rec); + break; + default: return 0; - - /* Make sure the checksums match. */ - if (ipchksum((u16 *) header, sizeof(*header)) != 0) - return -1; - - if (ipchksum((u16 *) (ptr + sizeof(*header)), - header->table_bytes) != header->table_checksum) - return -1; - - info->header = header; - - /* - * Valid board IDs are small numbers, preset this to an invalid value - * for the case when firmware does not supply the board ID. - */ - info->board_id = ~0; - - /* Now, walk the tables. */ - ptr += header->header_bytes; - - for (i = 0; i < header->table_entries; i++) { - struct cb_record *rec = (struct cb_record *)ptr; - - /* We only care about a few tags here (maybe more later). */ - switch (rec->tag) { - case CB_TAG_FORWARD: - forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward); - return cb_parse_header(forward, info); - continue; - case CB_TAG_MEMORY: - cb_parse_memory(ptr, info); - break; - case CB_TAG_SERIAL: - cb_parse_serial(ptr, info); - break; - case CB_TAG_VERSION: - cb_parse_string(ptr, &info->cb_version); - break; - case CB_TAG_EXTRA_VERSION: - cb_parse_string(ptr, &info->extra_version); - break; - case CB_TAG_BUILD: - cb_parse_string(ptr, &info->build); - break; - case CB_TAG_COMPILE_TIME: - cb_parse_string(ptr, &info->compile_time); - break; - case CB_TAG_COMPILE_BY: - cb_parse_string(ptr, &info->compile_by); - break; - case CB_TAG_COMPILE_HOST: - cb_parse_string(ptr, &info->compile_host); - break; - case CB_TAG_COMPILE_DOMAIN: - cb_parse_string(ptr, &info->compile_domain); - break; - case CB_TAG_COMPILER: - cb_parse_string(ptr, &info->compiler); - break; - case CB_TAG_LINKER: - cb_parse_string(ptr, &info->linker); - break; - case CB_TAG_ASSEMBLER: - cb_parse_string(ptr, &info->assembler); - break; -#ifdef CONFIG_LP_NVRAM - case CB_TAG_CMOS_OPTION_TABLE: - cb_parse_optiontable(ptr, info); - break; - case CB_TAG_OPTION_CHECKSUM: - cb_parse_checksum(ptr, info); - break; -#endif -#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE - // FIXME we should warn on serial if coreboot set up a - // framebuffer buf the payload does not know about it. - case CB_TAG_FRAMEBUFFER: - cb_parse_framebuffer(ptr, info); - break; -#endif - case CB_TAG_MAINBOARD: - info->mainboard = (struct cb_mainboard *)ptr; - break; -#ifdef CONFIG_LP_CHROMEOS - case CB_TAG_GPIO: - cb_parse_gpios(ptr, info); - break; - case CB_TAG_VDAT: - cb_parse_vdat(ptr, info); - break; - case CB_TAG_VBNV: - cb_parse_vbnv(ptr, info); - break; - case CB_TAG_VBOOT_HANDOFF: - cb_parse_vboot_handoff(ptr, info); - break; -#endif - case CB_TAG_DMA: - cb_parse_dma(ptr); - break; - case CB_TAG_TIMESTAMPS: - cb_parse_tstamp(ptr, info); - break; - case CB_TAG_CBMEM_CONSOLE: - cb_parse_cbmem_cons(ptr, info); - break; - case CB_TAG_MRC_CACHE: - cb_parse_mrc_cache(ptr, info); - break; - case CB_TAG_BOARD_ID: - cb_parse_board_id(ptr, info); - break; - } - - ptr += rec->size; } - return 1; } @@ -316,7 +58,5 @@ static int cb_parse_header(void *addr, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(cb_header_ptr, info); - - return (ret == 1) ? 0 : -1; + return cb_parse_header(cb_header_ptr, 1, info); } diff --git a/payloads/libpayload/arch/arm64/coreboot.c b/payloads/libpayload/arch/arm64/coreboot.c index 6d7c955..056d63e 100644 --- a/payloads/libpayload/arch/arm64/coreboot.c +++ b/payloads/libpayload/arch/arm64/coreboot.c @@ -35,279 +35,21 @@ /* This pointer gets set in head.S and is passed in from coreboot. */ void *cb_header_ptr; -/* - * Some of this is x86 specific, and the rest of it is generic. Right now, - * since we only support x86, we'll avoid trying to make lots of infrastructure - * we don't need. If in the future, we want to use coreboot on some other - * architecture, then take out the generic parsing code and move it elsewhere. - */ - -/* === Parsing code === */ -/* This is the generic parsing code. */ - -static void cb_parse_memory(void *ptr, struct sysinfo_t *info) -{ - struct cb_memory *mem = ptr; - int count = MEM_RANGE_COUNT(mem); - int i; - - if (count > SYSINFO_MAX_MEM_RANGES) - count = SYSINFO_MAX_MEM_RANGES; - - info->n_memranges = 0; - - for (i = 0; i < count; i++) { - struct cb_memory_range *range = MEM_RANGE_PTR(mem, i); - -#ifdef CONFIG_LP_MEMMAP_RAM_ONLY - if (range->type != CB_MEM_RAM) - continue; -#endif - - info->memrange[info->n_memranges].base = - cb_unpack64(range->start); - - info->memrange[info->n_memranges].size = - cb_unpack64(range->size); - - info->memrange[info->n_memranges].type = range->type; - - info->n_memranges++; - } -} - -static void cb_parse_serial(void *ptr, struct sysinfo_t *info) -{ - info->serial = ((struct cb_serial *)ptr); -} - -#ifdef CONFIG_LP_CHROMEOS -static void cb_parse_vboot_handoff(unsigned char *ptr, struct sysinfo_t *info) -{ - struct lb_range *vbho = (struct lb_range *)ptr; - - info->vboot_handoff = (void *)(uintptr_t)vbho->range_start; - info->vboot_handoff_size = vbho->range_size; -} - -static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) -{ - struct lb_range *vbnv = (struct lb_range *)ptr; - - info->vbnv_start = vbnv->range_start; - info->vbnv_size = vbnv->range_size; -} - -static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info) -{ - int i; - struct cb_gpios *gpios = (struct cb_gpios *)ptr; - - info->num_gpios = (gpios->count < SYSINFO_MAX_GPIOS) ? - (gpios->count) : SYSINFO_MAX_GPIOS; - - for (i = 0; i < info->num_gpios; i++) - info->gpios[i] = gpios->gpios[i]; -} - -static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info) -{ - struct lb_range *vdat = (struct lb_range *)ptr; - - info->vdat_addr = phys_to_virt(vdat->range_start); - info->vdat_size = vdat->range_size; -} -#endif - -static void cb_parse_dma(unsigned char *ptr) +static void cb_parse_dma(void *ptr) { struct lb_range *dma = (struct lb_range *)ptr; init_dma_memory(phys_to_virt(dma->range_start), dma->range_size); } -static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) +int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->tstamp_table = phys_to_virt(cbmem->cbmem_tab); -} - -static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->cbmem_cons = phys_to_virt(cbmem->cbmem_tab); -} - -static void cb_parse_mrc_cache(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); -} - -static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_board_id *const cbbid = (struct cb_board_id *)ptr; - info->board_id = cbbid->board_id; -} - -#ifdef CONFIG_LP_NVRAM -static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) -{ - /* ptr points to a coreboot table entry and is already virtual */ - info->option_table = ptr; -} - -static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) -{ - struct cb_cmos_checksum *cmos_cksum = ptr; - info->cmos_range_start = cmos_cksum->range_start; - info->cmos_range_end = cmos_cksum->range_end; - info->cmos_checksum_location = cmos_cksum->location; -} -#endif - -#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE -static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) -{ - /* ptr points to a coreboot table entry and is already virtual */ - info->framebuffer = ptr; -} -#endif - -static void cb_parse_string(unsigned char *ptr, char **info) -{ - *info = (char *)((struct cb_string *)ptr)->string; -} - -static int cb_parse_header(void *addr, struct sysinfo_t *info) -{ - struct cb_header *header = addr; - unsigned char *ptr = addr; - void *forward; - int i; - - /* No signature found. */ - if (strncmp((const char *)header->signature, "LBIO", 4)) - return -1; - - if (!header->table_bytes) + switch(rec->tag) { + case CB_TAG_DMA: + cb_parse_dma(rec); + break; + default: return 0; - - /* Make sure the checksums match. */ - if (ipchksum((u16 *) header, sizeof(*header)) != 0) - return -1; - - if (ipchksum((u16 *) (ptr + sizeof(*header)), - header->table_bytes) != header->table_checksum) - return -1; - - info->header = header; - - /* - * Valid board IDs are small numbers, preset this to an invalid value - * for the case when firmware does not supply the board ID. - */ - info->board_id = ~0; - - /* Now, walk the tables. */ - ptr += header->header_bytes; - - for (i = 0; i < header->table_entries; i++) { - struct cb_record *rec = (struct cb_record *)ptr; - - /* We only care about a few tags here (maybe more later). */ - switch (rec->tag) { - case CB_TAG_FORWARD: - forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward); - return cb_parse_header(forward, info); - continue; - case CB_TAG_MEMORY: - cb_parse_memory(ptr, info); - break; - case CB_TAG_SERIAL: - cb_parse_serial(ptr, info); - break; - case CB_TAG_VERSION: - cb_parse_string(ptr, &info->cb_version); - break; - case CB_TAG_EXTRA_VERSION: - cb_parse_string(ptr, &info->extra_version); - break; - case CB_TAG_BUILD: - cb_parse_string(ptr, &info->build); - break; - case CB_TAG_COMPILE_TIME: - cb_parse_string(ptr, &info->compile_time); - break; - case CB_TAG_COMPILE_BY: - cb_parse_string(ptr, &info->compile_by); - break; - case CB_TAG_COMPILE_HOST: - cb_parse_string(ptr, &info->compile_host); - break; - case CB_TAG_COMPILE_DOMAIN: - cb_parse_string(ptr, &info->compile_domain); - break; - case CB_TAG_COMPILER: - cb_parse_string(ptr, &info->compiler); - break; - case CB_TAG_LINKER: - cb_parse_string(ptr, &info->linker); - break; - case CB_TAG_ASSEMBLER: - cb_parse_string(ptr, &info->assembler); - break; -#ifdef CONFIG_LP_NVRAM - case CB_TAG_CMOS_OPTION_TABLE: - cb_parse_optiontable(ptr, info); - break; - case CB_TAG_OPTION_CHECKSUM: - cb_parse_checksum(ptr, info); - break; -#endif -#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE - // FIXME we should warn on serial if coreboot set up a - // framebuffer buf the payload does not know about it. - case CB_TAG_FRAMEBUFFER: - cb_parse_framebuffer(ptr, info); - break; -#endif - case CB_TAG_MAINBOARD: - info->mainboard = (struct cb_mainboard *)ptr; - break; -#ifdef CONFIG_LP_CHROMEOS - case CB_TAG_GPIO: - cb_parse_gpios(ptr, info); - break; - case CB_TAG_VDAT: - cb_parse_vdat(ptr, info); - break; - case CB_TAG_VBNV: - cb_parse_vbnv(ptr, info); - break; - case CB_TAG_VBOOT_HANDOFF: - cb_parse_vboot_handoff(ptr, info); - break; -#endif - case CB_TAG_DMA: - cb_parse_dma(ptr); - break; - case CB_TAG_TIMESTAMPS: - cb_parse_tstamp(ptr, info); - break; - case CB_TAG_CBMEM_CONSOLE: - cb_parse_cbmem_cons(ptr, info); - break; - case CB_TAG_MRC_CACHE: - cb_parse_mrc_cache(ptr, info); - break; - case CB_TAG_BOARD_ID: - cb_parse_board_id(ptr, info); - break; - } - - ptr += rec->size; } - return 1; } @@ -316,7 +58,5 @@ static int cb_parse_header(void *addr, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(cb_header_ptr, info); - - return (ret == 1) ? 0 : -1; + return cb_parse_header(cb_header_ptr, 1, info); } diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index 43fde9f..1f37b80 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -31,7 +31,6 @@ #include <libpayload-config.h> #include <libpayload.h> #include <coreboot_tables.h> -#include <stdint.h> /* * Some of this is x86 specific, and the rest of it is generic. Right now, @@ -43,289 +42,33 @@ /* === Parsing code === */ /* This is the generic parsing code. */ -static void cb_parse_memory(void *ptr, struct sysinfo_t *info) -{ - struct cb_memory *mem = ptr; - int count = MEM_RANGE_COUNT(mem); - int i; - - if (count > SYSINFO_MAX_MEM_RANGES) - count = SYSINFO_MAX_MEM_RANGES; - - info->n_memranges = 0; - - for (i = 0; i < count; i++) { - struct cb_memory_range *range = MEM_RANGE_PTR(mem, i); - -#ifdef CONFIG_LP_MEMMAP_RAM_ONLY - if (range->type != CB_MEM_RAM) - continue; -#endif - - info->memrange[info->n_memranges].base = - cb_unpack64(range->start); - - info->memrange[info->n_memranges].size = - cb_unpack64(range->size); - - info->memrange[info->n_memranges].type = range->type; - - info->n_memranges++; - } -} - -static void cb_parse_serial(void *ptr, struct sysinfo_t *info) -{ - info->serial = ((struct cb_serial *)ptr); -} - -#ifdef CONFIG_LP_CHROMEOS -static void cb_parse_vboot_handoff(unsigned char *ptr, struct sysinfo_t *info) -{ - struct lb_range *vbho = (struct lb_range *)ptr; - - info->vboot_handoff = (void *)(uintptr_t)vbho->range_start; - info->vboot_handoff_size = vbho->range_size; -} - -static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) -{ - struct lb_range *vbnv = (struct lb_range *)ptr; - - info->vbnv_start = vbnv->range_start; - info->vbnv_size = vbnv->range_size; -} - -static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info) -{ - int i; - struct cb_gpios *gpios = (struct cb_gpios *)ptr; - - info->num_gpios = (gpios->count < SYSINFO_MAX_GPIOS) ? - (gpios->count) : SYSINFO_MAX_GPIOS; - - for (i = 0; i < info->num_gpios; i++) - info->gpios[i] = gpios->gpios[i]; -} - -static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info) -{ - struct lb_range *vdat = (struct lb_range *) ptr; - - info->vdat_addr = phys_to_virt(vdat->range_start); - info->vdat_size = vdat->range_size; -} -#endif - -static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->tstamp_table = phys_to_virt(cbmem->cbmem_tab); -} - -static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->cbmem_cons = phys_to_virt(cbmem->cbmem_tab); -} - -static void cb_parse_mrc_cache(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); -} - -static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_acpi_gnvs(void *ptr, struct sysinfo_t *info) { struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; info->acpi_gnvs = phys_to_virt(cbmem->cbmem_tab); } -static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_board_id *const cbbid = (struct cb_board_id *)ptr; - info->board_id = cbbid->board_id; -} - -#ifdef CONFIG_LP_NVRAM -static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) -{ - /* ptr points to a coreboot table entry and is already virtual */ - info->option_table = ptr; -} - -static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) -{ - struct cb_cmos_checksum *cmos_cksum = ptr; - info->cmos_range_start = cmos_cksum->range_start; - info->cmos_range_end = cmos_cksum->range_end; - info->cmos_checksum_location = cmos_cksum->location; -} -#endif - -#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE -static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) -{ - /* ptr points to a coreboot table entry and is already virtual */ - info->framebuffer = ptr; -} -#endif - static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info) { struct cb_x86_rom_mtrr *rom_mtrr = ptr; info->x86_rom_var_mtrr_index = rom_mtrr->index; } -static void cb_parse_string(unsigned char *ptr, char **info) +int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) { - *info = (char *)((struct cb_string *)ptr)->string; -} - -static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) -{ - struct cb_header *header; - unsigned char *ptr = addr; - void *forward; - int i; - - for (i = 0; i < len; i += 16, ptr += 16) { - header = (struct cb_header *)ptr; - if (!strncmp((const char *)header->signature, "LBIO", 4)) - break; - } - - /* We walked the entire space and didn't find anything. */ - if (i >= len) - return -1; - - if (!header->table_bytes) + switch(rec->tag) { + case CB_TAG_ACPI_GNVS: + cb_parse_acpi_gnvs(rec, info); + break; + case CB_TAG_X86_ROM_MTRR: + cb_parse_x86_rom_var_mtrr(rec, info); + break; + default: return 0; - - /* Make sure the checksums match. */ - if (ipchksum((u16 *) header, sizeof(*header)) != 0) - return -1; - - if (ipchksum((u16 *) (ptr + sizeof(*header)), - header->table_bytes) != header->table_checksum) - return -1; - - info->header = header; - - /* - * Valid board IDs are small numbers, preset this to an invalid value - * for the case when firmware does not supply the board ID. - */ - info->board_id = ~0; - - /* Now, walk the tables. */ - ptr += header->header_bytes; - - for (i = 0; i < header->table_entries; i++) { - struct cb_record *rec = (struct cb_record *)ptr; - - /* We only care about a few tags here (maybe more later). */ - switch (rec->tag) { - case CB_TAG_FORWARD: - forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward); - return cb_parse_header(forward, len, info); - case CB_TAG_MEMORY: - cb_parse_memory(ptr, info); - break; - case CB_TAG_SERIAL: - cb_parse_serial(ptr, info); - break; - case CB_TAG_VERSION: - cb_parse_string(ptr, &info->cb_version); - break; - case CB_TAG_EXTRA_VERSION: - cb_parse_string(ptr, &info->extra_version); - break; - case CB_TAG_BUILD: - cb_parse_string(ptr, &info->build); - break; - case CB_TAG_COMPILE_TIME: - cb_parse_string(ptr, &info->compile_time); - break; - case CB_TAG_COMPILE_BY: - cb_parse_string(ptr, &info->compile_by); - break; - case CB_TAG_COMPILE_HOST: - cb_parse_string(ptr, &info->compile_host); - break; - case CB_TAG_COMPILE_DOMAIN: - cb_parse_string(ptr, &info->compile_domain); - break; - case CB_TAG_COMPILER: - cb_parse_string(ptr, &info->compiler); - break; - case CB_TAG_LINKER: - cb_parse_string(ptr, &info->linker); - break; - case CB_TAG_ASSEMBLER: - cb_parse_string(ptr, &info->assembler); - break; -#ifdef CONFIG_LP_NVRAM - case CB_TAG_CMOS_OPTION_TABLE: - cb_parse_optiontable(ptr, info); - break; - case CB_TAG_OPTION_CHECKSUM: - cb_parse_checksum(ptr, info); - break; -#endif -#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE - // FIXME we should warn on serial if coreboot set up a - // framebuffer buf the payload does not know about it. - case CB_TAG_FRAMEBUFFER: - cb_parse_framebuffer(ptr, info); - break; -#endif - case CB_TAG_MAINBOARD: - info->mainboard = (struct cb_mainboard *)ptr; - break; -#ifdef CONFIG_LP_CHROMEOS - case CB_TAG_GPIO: - cb_parse_gpios(ptr, info); - break; - case CB_TAG_VDAT: - cb_parse_vdat(ptr, info); - break; - case CB_TAG_VBNV: - cb_parse_vbnv(ptr, info); - break; - case CB_TAG_VBOOT_HANDOFF: - cb_parse_vboot_handoff(ptr, info); - break; -#endif - case CB_TAG_TIMESTAMPS: - cb_parse_tstamp(ptr, info); - break; - case CB_TAG_CBMEM_CONSOLE: - cb_parse_cbmem_cons(ptr, info); - break; - case CB_TAG_MRC_CACHE: - cb_parse_mrc_cache(ptr, info); - break; - case CB_TAG_ACPI_GNVS: - cb_parse_acpi_gnvs(ptr, info); - break; - case CB_TAG_X86_ROM_MTRR: - cb_parse_x86_rom_var_mtrr(ptr, info); - break; - case CB_TAG_BOARD_ID: - cb_parse_board_id(ptr, info); - break; - } - - ptr += rec->size; } - return 1; } -/* == Architecture specific == */ -/* This is the x86 specific stuff. */ - int get_coreboot_info(struct sysinfo_t *info) { int ret; @@ -336,8 +79,8 @@ int get_coreboot_info(struct sysinfo_t *info) ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); - if (ret != 1) + if (ret) ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info); - return (ret == 1) ? 0 : -1; + return ret; } diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index e8a5858..f4f47b7 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -113,5 +113,19 @@ struct sysinfo_t { extern struct sysinfo_t lib_sysinfo; +/* + * Check if this is an architecture specific coreboot table record and process + * it, if it is. Returns 1 if record type was recognized, 0 otherwise. + */ +int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info); + +/* + * Check if the region in range addr..addr+len contains a 16 byte aligned + * coreboot table. If it does - process the table filling up the sysinfo + * structure with information from the table. Return 0 on success and -1 on + * failure. + */ +int cb_parse_header(void *addr, int len, struct sysinfo_t *info); + #endif diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc index e2eee15..bd2a6f7 100644 --- a/payloads/libpayload/libc/Makefile.inc +++ b/payloads/libpayload/libc/Makefile.inc @@ -37,6 +37,7 @@ libc-$(CONFIG_LP_LIBC) += strlcpy.c libc-$(CONFIG_LP_LIBC) += qsort.c libc-$(CONFIG_LP_LIBC) += hexdump.c libc-$(CONFIG_LP_LIBC) += die.c +libc-$(CONFIG_LP_LIBC) += coreboot.c # should be moved to coreboot directory libc-$(CONFIG_LP_LAR) += lar.c diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c new file mode 100644 index 0000000..1563d4a --- /dev/null +++ b/payloads/libpayload/libc/coreboot.c @@ -0,0 +1,319 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2009 coresystems GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload-config.h> +#include <libpayload.h> +#include <coreboot_tables.h> +#include <stdint.h> + +/* + * The code in this file applies to all coreboot architectures. Some coreboot + * table tags are architecture specific, they are handled by their respective + * cb_parse_arch_specific() functions. + */ + +/* === Parsing code === */ +/* This is the generic parsing code. */ + +static void cb_parse_memory(void *ptr, struct sysinfo_t *info) +{ + struct cb_memory *mem = ptr; + int count = MEM_RANGE_COUNT(mem); + int i; + + if (count > SYSINFO_MAX_MEM_RANGES) + count = SYSINFO_MAX_MEM_RANGES; + + info->n_memranges = 0; + + for (i = 0; i < count; i++) { + struct cb_memory_range *range = MEM_RANGE_PTR(mem, i); + +#ifdef CONFIG_LP_MEMMAP_RAM_ONLY + if (range->type != CB_MEM_RAM) + continue; +#endif + + info->memrange[info->n_memranges].base = + cb_unpack64(range->start); + + info->memrange[info->n_memranges].size = + cb_unpack64(range->size); + + info->memrange[info->n_memranges].type = range->type; + + info->n_memranges++; + } +} + +static void cb_parse_serial(void *ptr, struct sysinfo_t *info) +{ + info->serial = ((struct cb_serial *)ptr); +} + +#ifdef CONFIG_LP_CHROMEOS +static void cb_parse_vboot_handoff(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_range *vbho = (struct cb_range *)ptr; + + info->vboot_handoff = (void *)(uintptr_t)vbho->range_start; + info->vboot_handoff_size = vbho->range_size; +} + +static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_range *vbnv = (struct cb_range *)ptr; + + info->vbnv_start = vbnv->range_start; + info->vbnv_size = vbnv->range_size; +} + +static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info) +{ + int i; + struct cb_gpios *gpios = (struct cb_gpios *)ptr; + + info->num_gpios = (gpios->count < SYSINFO_MAX_GPIOS) ? + (gpios->count) : SYSINFO_MAX_GPIOS; + + for (i = 0; i < info->num_gpios; i++) + info->gpios[i] = gpios->gpios[i]; +} + +static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_range *vdat = (struct cb_range *) ptr; + + info->vdat_addr = phys_to_virt(vdat->range_start); + info->vdat_size = vdat->range_size; +} +#endif + +static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; + info->tstamp_table = phys_to_virt(cbmem->cbmem_tab); +} + +static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; + info->cbmem_cons = phys_to_virt(cbmem->cbmem_tab); +} + +static void cb_parse_mrc_cache(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; + info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); +} + +static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; + info->acpi_gnvs = phys_to_virt(cbmem->cbmem_tab); +} + +static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_board_id *const cbbid = (struct cb_board_id *)ptr; + info->board_id = cbbid->board_id; +} + +#ifdef CONFIG_LP_NVRAM +static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) +{ + /* ptr points to a coreboot table entry and is already virtual */ + info->option_table = ptr; +} + +static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) +{ + struct cb_cmos_checksum *cmos_cksum = ptr; + info->cmos_range_start = cmos_cksum->range_start; + info->cmos_range_end = cmos_cksum->range_end; + info->cmos_checksum_location = cmos_cksum->location; +} +#endif + +#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE +static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) +{ + /* ptr points to a coreboot table entry and is already virtual */ + info->framebuffer = ptr; +} +#endif + +static void cb_parse_string(unsigned char *ptr, char **info) +{ + *info = (char *)((struct cb_string *)ptr)->string; +} + +int cb_parse_header(void *addr, int len, struct sysinfo_t *info) +{ + struct cb_header *header; + unsigned char *ptr = addr; + void *forward; + int i; + + for (i = 0; i < len; i += 16, ptr += 16) { + header = (struct cb_header *)ptr; + if (!strncmp((const char *)header->signature, "LBIO", 4)) + break; + } + + /* We walked the entire space and didn't find anything. */ + if (i >= len) + return -1; + + /* Make sure the checksums match. */ + if (ipchksum((u16 *) header, sizeof(*header)) != 0) + return -1; + + if (!header->table_bytes) + return 0; + + if (ipchksum((u16 *) (ptr + sizeof(*header)), + header->table_bytes) != header->table_checksum) + return -1; + + info->header = header; + + /* + * Valid board IDs are small numbers, preset this to an invalid value + * for the case when firmware does not supply the board ID. + */ + info->board_id = ~0; + + /* Now, walk the tables. */ + ptr += header->header_bytes; + + for (i = 0; i < header->table_entries; i++) { + struct cb_record *rec = (struct cb_record *)ptr; + + /* We only care about a few tags here (maybe more later). */ + switch (rec->tag) { + case CB_TAG_FORWARD: + forward = phys_to_virt((void *)(unsigned long) + ((struct cb_forward *)rec)->forward); + return cb_parse_header(forward, len, info); + continue; + case CB_TAG_MEMORY: + cb_parse_memory(ptr, info); + break; + case CB_TAG_SERIAL: + cb_parse_serial(ptr, info); + break; + case CB_TAG_VERSION: + cb_parse_string(ptr, &info->cb_version); + break; + case CB_TAG_EXTRA_VERSION: + cb_parse_string(ptr, &info->extra_version); + break; + case CB_TAG_BUILD: + cb_parse_string(ptr, &info->build); + break; + case CB_TAG_COMPILE_TIME: + cb_parse_string(ptr, &info->compile_time); + break; + case CB_TAG_COMPILE_BY: + cb_parse_string(ptr, &info->compile_by); + break; + case CB_TAG_COMPILE_HOST: + cb_parse_string(ptr, &info->compile_host); + break; + case CB_TAG_COMPILE_DOMAIN: + cb_parse_string(ptr, &info->compile_domain); + break; + case CB_TAG_COMPILER: + cb_parse_string(ptr, &info->compiler); + break; + case CB_TAG_LINKER: + cb_parse_string(ptr, &info->linker); + break; + case CB_TAG_ASSEMBLER: + cb_parse_string(ptr, &info->assembler); + break; +#ifdef CONFIG_LP_NVRAM + case CB_TAG_CMOS_OPTION_TABLE: + cb_parse_optiontable(ptr, info); + break; + case CB_TAG_OPTION_CHECKSUM: + cb_parse_checksum(ptr, info); + break; +#endif +#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE + // FIXME we should warn on serial if coreboot set up a + // framebuffer buf the payload does not know about it. + case CB_TAG_FRAMEBUFFER: + cb_parse_framebuffer(ptr, info); + break; +#endif + case CB_TAG_MAINBOARD: + info->mainboard = (struct cb_mainboard *)ptr; + break; +#ifdef CONFIG_LP_CHROMEOS + case CB_TAG_GPIO: + cb_parse_gpios(ptr, info); + break; + case CB_TAG_VDAT: + cb_parse_vdat(ptr, info); + break; + case CB_TAG_VBNV: + cb_parse_vbnv(ptr, info); + break; + case CB_TAG_VBOOT_HANDOFF: + cb_parse_vboot_handoff(ptr, info); + break; +#endif + case CB_TAG_TIMESTAMPS: + cb_parse_tstamp(ptr, info); + break; + case CB_TAG_CBMEM_CONSOLE: + cb_parse_cbmem_cons(ptr, info); + break; + case CB_TAG_MRC_CACHE: + cb_parse_mrc_cache(ptr, info); + break; + case CB_TAG_ACPI_GNVS: + cb_parse_acpi_gnvs(ptr, info); + break; + case CB_TAG_BOARD_ID: + cb_parse_board_id(ptr, info); + break; + default: + cb_parse_arch_specific(rec, info); + break; + } + + ptr += rec->size; + } + + return 0; +}

1 0

Patch merged into coreboot/master: 86f4ca5 cpu/amd/model_10xxx: Add support for early cbmem
by gerrit＠coreboot.org 19 Mar '15

19 Mar '15

the following patch was just integrated into master: commit 86f4ca5b4b99a799b403e61a90aa24d103fb7f2f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 13:27:58 2015 -0500 cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE When GFXUMA is disabled, CBMEM is placed at TOM This matches the behaviour present before conversion to early CBMEM. The CBMEM location code implicitly assumes TOM does not change between romstage and ramstage. TOM is set by romstage raminit, and is never changed by romstage or ramstage afterward. As the CBMEM location is positioned at a specific offset from TOM that is known to both romstage and ramstage early CBMEM is safe on Fam10h systems. TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp tables from romstage and cbmem log tables from ramstage. Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8489 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> See http://review.coreboot.org/8489 for details. -gerrit

1 0

Patch merged into coreboot/master: e24f7d3 cpu/amd/model_10xxx: Fix UMA memory sizes
by gerrit＠coreboot.org 19 Mar '15

19 Mar '15

the following patch was just integrated into master: commit e24f7d37cef5acb71c070f934a74286efb6ee32e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Mar 19 00:03:59 2015 -0500 cpu/amd/model_10xxx: Fix UMA memory sizes Fix up commit 4916880 (cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function) unintentionally changing behavior when converting the switch statement to an if-else statement. Change-Id: I8d126aaec1b324face6407a2b451e603e61db0e5 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8748 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8748 for details. -gerrit

1 0

Patch set updated for coreboot: 791d1ea cpu/amd/model_10xxx: Add support for early cbmem
by Timothy Pearson 19 Mar '15

19 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8489 -gerrit commit 791d1eae438d85ef4d668ad356339bb2dabc92e7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 13:27:58 2015 -0500 cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE When GFXUMA is disabled, CBMEM is placed at TOM This matches the behaviour present before conversion to early CBMEM. The CBMEM location code implicitly assumes TOM does not change between romstage and ramstage. TOM is set by romstage raminit, and is never changed by romstage or ramstage afterward. As the CBMEM location is positioned at a specific offset from TOM that is known to both romstage and ramstage early CBMEM is safe on Fam10h systems. TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp tables from romstage and cbmem log tables from ramstage. Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/ram_calc.c | 9 +++++++++ src/mainboard/advansus/a785e-i/romstage.c | 1 + src/mainboard/amd/bimini_fam10/romstage.c | 1 + src/mainboard/amd/mahogany_fam10/romstage.c | 1 + src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 1 + src/mainboard/amd/tilapia_fam10/romstage.c | 1 + src/mainboard/asus/kfsn4-dre/romstage.c | 1 + src/mainboard/asus/m4a78-em/romstage.c | 1 + src/mainboard/asus/m4a785-m/romstage.c | 1 + src/mainboard/asus/m5a88-v/romstage.c | 1 + src/mainboard/avalue/eax-785e/romstage.c | 1 + src/mainboard/gigabyte/ma785gm/romstage.c | 1 + src/mainboard/gigabyte/ma785gmt/romstage.c | 1 + src/mainboard/gigabyte/ma78gm/romstage.c | 1 + src/mainboard/hp/dl165_g6_fam10/romstage.c | 1 + src/mainboard/iei/kino-780am2-fam10/romstage.c | 1 + src/mainboard/jetway/pa78vm5/romstage.c | 1 + src/mainboard/msi/ms9652_fam10/romstage.c | 1 + src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 + src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 + src/mainboard/supermicro/h8scm_fam10/romstage.c | 1 + src/mainboard/tyan/s2912_fam10/romstage.c | 1 + src/northbridge/amd/amdfam10/Kconfig | 1 - src/northbridge/amd/amdfam10/northbridge.c | 3 --- 24 files changed, 30 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c index c37c0ce..c17b85a 100644 --- a/src/cpu/amd/model_10xxx/ram_calc.c +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -22,6 +22,8 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#include <cbmem.h> + #include "ram_calc.h" uint64_t get_uma_memory_size(uint64_t topmem) @@ -41,3 +43,10 @@ uint64_t get_uma_memory_size(uint64_t topmem) return uma_size; } + +void *cbmem_top(void) +{ + uint32_t topmem = rdmsr(TOP_MEM).lo; + + return (void *) topmem - get_uma_memory_size(topmem); +} diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 19ce53e..c1c9a1b 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index d8a38d7..6d03685 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -198,6 +198,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index e6d7f2e..e53c64d 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 76bc73f..ef15e83 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -312,6 +312,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index b7f6869..7d2f272 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 0dab8e8..44864f6 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -343,6 +343,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); printk(BIOS_DEBUG, "disable_spd()\n"); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 7c93767..47b9c83 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 328955a..7ebec29 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index baa38ac..2339478 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index b586198..c1dbaa7 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -201,6 +201,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 4ad3d2c..7b0168d 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 590bb93..d0d6c94 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index a7b6b1b..8861ab6 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index d7e8447..4aefcd2 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -204,6 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); bcm5785_early_setup(); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index b88baa3..991cd55 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 08b6398..df30a69 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -205,6 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 45f05a5..0bdcd38 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -231,6 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index bc1ca24..4615465 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -228,6 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 2be09bc..c8ed2df 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -292,6 +292,7 @@ post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index eb38a29..4c6292f 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -212,6 +212,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 74c0aaa..7dcca17 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -227,6 +227,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index ff7fb9c..37993aa 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES - select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDFAM10 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 68c6e35..9206de7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -897,10 +897,7 @@ static void amdfam10_domain_set_resources(device_t dev) } #if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(bsp_topmem()); #endif for(link = dev->link_list; link; link = link->next) {

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Patch set updated for coreboot: f3e9227 cpu/amd/model_10xxx: Fix UMA memory sizes
by Timothy Pearson 19 Mar '15

19 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8748 -gerrit commit f3e922799a70819b1d564c33dafc432f3924cdb0 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Mar 19 00:03:59 2015 -0500 cpu/amd/model_10xxx: Fix UMA memory sizes Fix up commit 4916880 (cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function) unintentionally changing behavior when converting the switch statement to an if-else statement. Change-Id: I8d126aaec1b324face6407a2b451e603e61db0e5 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/ram_calc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c index 98b80e9..c37c0ce 100644 --- a/src/cpu/amd/model_10xxx/ram_calc.c +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -29,13 +29,13 @@ uint64_t get_uma_memory_size(uint64_t topmem) uint64_t uma_size = 0; if (IS_ENABLED(CONFIG_GFXUMA)) { /* refer to UMA Size Consideration in 780 BDG. */ - if (topmem > 0x40000000) /* 1GB and above system memory */ + if (topmem >= 0x40000000) /* 1GB and above system memory */ uma_size = 0x10000000; /* 256M recommended UMA */ - else if (topmem > 0x20000000) /* 512M - 1023M system memory */ + else if (topmem >= 0x20000000) /* 512M - 1023M system memory */ uma_size = 0x8000000; /* 128M recommended UMA */ - else if (topmem > 0x10000000) /* 256M - 511M system memory */ + else if (topmem >= 0x10000000) /* 256M - 511M system memory */ uma_size = 0x4000000; /* 64M recommended UMA */ }

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coreboot-gerrit March 2015