coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 6b36d6f vboot2: translate shared data to hand off to depthcharge
by Aaron Durbin 19 Mar '15

19 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8655 -gerrit commit 6b36d6f53a66596ec0123fb088fc012626e400ee Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Mon Jun 30 08:51:39 2014 -0700 vboot2: translate shared data to hand off to depthcharge TEST=Built Blaze with USE=+/-vboot2. Ran faft: CorruptBothFwAB, CorruptBothFWSigAB, CorruptFwBodyA/B, CoccurptFwSigA/B, DevBootUSB, DevMode, TryFwB, UserRequestRecovery, SelfSignedBoot, RollbackFirmware. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: I45a1efd4d55fde37cc67fc02642fed0bc9366469 Original-Reviewed-on: https://chromium-review.googlesource.com/205236 Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> (cherry picked from commit 0a9e7f099251c33ce286fa8d704a3e021eac4d3e) Change-Id: I5f61c03c66ca83a5837c14378905ba178aba5300 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/coreboot_table.c | 2 +- src/mainboard/google/nyan_blaze/romstage.c | 2 +- src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/chromeos.h | 1 + src/vendorcode/google/chromeos/vboot_handoff.c | 142 +++++++++++++++++++++++++ src/vendorcode/google/chromeos/vboot_handoff.h | 1 + 6 files changed, 147 insertions(+), 2 deletions(-) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index abcb0ed..9112cd1 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -191,7 +191,7 @@ static void lb_vbnv(struct lb_header *header) #endif } -#if CONFIG_VBOOT_VERIFY_FIRMWARE +#if CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE static void lb_vboot_handoff(struct lb_header *header) { void *addr; diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 522ee91..1817715 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -200,7 +200,7 @@ static void __attribute__((noinline)) romstage(void) configure_tpm_i2c_bus(); #if CONFIG_VBOOT2_VERIFY_FIRMWARE - // vboot_create_handoff((void *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS); + vboot_create_handoff((void *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS); #else vboot_verify_firmware(romstage_handoff_find_or_add()); #endif diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index c8781dd..1fcb42e 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -102,6 +102,7 @@ INCLUDES += -I$(VB_SOURCE)/firmware/2lib/include INCLUDES += -I$(VB_SOURCE)/firmware/include verstage-y += vboot_main.c fmap.c chromeos.c verstage-y += antirollback.c vbnv_ec.c +romstage-y += vboot_handoff.c VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-VERSTAGE-y)) VB2_LIB = $(obj)/external/vboot_reference/vboot_fw2.a diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index a799528..724ff57 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -88,6 +88,7 @@ static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} #if CONFIG_VBOOT2_VERIFY_FIRMWARE void select_firmware(void); +void vboot_create_handoff(void * vboot_workbuf); #endif #endif diff --git a/src/vendorcode/google/chromeos/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot_handoff.c new file mode 100644 index 0000000..3b276aa --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot_handoff.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <2recovery_reasons.h> +#include <2struct.h> +#include <stdint.h> +#include <stddef.h> +#include <string.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <console/vtxprintf.h> +#include <stdlib.h> +#include <timestamp.h> +#include "chromeos.h" +#include "fmap.h" +#include "vboot_handoff.h" +#include <vboot_struct.h> + +/** + * Sets vboot_handoff based on the information in vb2_shared_data + * + * TODO: Read wp switch to set VBSD_BOOT_FIRMWARE_WP_ENABLED + */ +static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, + struct vb2_shared_data *vb2_sd) +{ + VbSharedDataHeader *vb_sd = + (VbSharedDataHeader *)vboot_handoff->shared_data; + uint32_t *oflags = &vboot_handoff->init_params.out_flags; + + vb_sd->flags |= VBSD_BOOT_FIRMWARE_VBOOT2; + + vboot_handoff->selected_firmware = vb2_sd->fw_slot; + + /* TODO: fw_slot is never 0xff while firmware_index can. */ + vb_sd->firmware_index = vb2_sd->fw_slot; + + vb_sd->magic = VB_SHARED_DATA_MAGIC; + vb_sd->struct_version = VB_SHARED_DATA_VERSION; + vb_sd->struct_size = sizeof(VbSharedDataHeader); + vb_sd->data_size = VB_SHARED_DATA_MIN_SIZE; + vb_sd->data_used = sizeof(VbSharedDataHeader); + + if (vb2_sd->recovery_reason) { + vb_sd->firmware_index = 0xFF; + if (vb2_sd->recovery_reason == VB2_RECOVERY_RO_MANUAL) + vb_sd->flags |= VBSD_BOOT_REC_SWITCH_ON; + *oflags |= VB_INIT_OUT_ENABLE_RECOVERY; + *oflags |= VB_INIT_OUT_CLEAR_RAM; + *oflags |= VB_INIT_OUT_ENABLE_DISPLAY; + *oflags |= VB_INIT_OUT_ENABLE_USB_STORAGE; + } + if (vb2_sd->flags & VB2_SD_DEV_MODE_ENABLED) { + *oflags |= VB_INIT_OUT_ENABLE_DEVELOPER; + *oflags |= VB_INIT_OUT_CLEAR_RAM; + *oflags |= VB_INIT_OUT_ENABLE_DISPLAY; + *oflags |= VB_INIT_OUT_ENABLE_USB_STORAGE; + vb_sd->flags |= VBSD_BOOT_DEV_SWITCH_ON; + vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; + } + if (CONFIG_VIRTUAL_DEV_SWITCH) + vb_sd->flags |= VBSD_HONOR_VIRT_DEV_SWITCH; + if (CONFIG_EC_SOFTWARE_SYNC) { + vb_sd->flags |= VBSD_EC_SOFTWARE_SYNC; + vb_sd->flags |= VBSD_BOOT_REC_SWITCH_VIRTUAL; + } + /* In vboot1, VBSD_FWB_TRIED is + * set only if B is booted as explicitly requested. Therefore, if B is + * booted because A was found bad, the flag should not be set. It's + * better not to touch it if we can only ambiguously control it. */ + /* if (vb2_sd->fw_slot) + vb_sd->flags |= VBSD_FWB_TRIED; */ + + /* copy kernel subkey if it's found */ + if (vb2_sd->workbuf_preamble_size) { + struct vb2_fw_preamble *fp; + uintptr_t dst, src; + printk(BIOS_ERR, "Copying FW preamble\n"); + fp = (struct vb2_fw_preamble *)( (uintptr_t)vb2_sd + + vb2_sd->workbuf_preamble_offset); + src = (uintptr_t)&fp->kernel_subkey + fp->kernel_subkey.key_offset; + dst = (uintptr_t)vb_sd + sizeof(VbSharedDataHeader); + memcpy((void *)dst, (void *)src, fp->kernel_subkey.key_size); + vb_sd->data_used += fp->kernel_subkey.key_size; + vb_sd->kernel_subkey.key_offset = + dst - (uintptr_t)&vb_sd->kernel_subkey; + vb_sd->kernel_subkey.key_size = fp->kernel_subkey.key_size; + vb_sd->kernel_subkey.algorithm = fp->kernel_subkey.algorithm; + vb_sd->kernel_subkey.key_version = fp->kernel_subkey.key_version; + } + + vb_sd->recovery_reason = vb2_sd->recovery_reason; +} + +/** + * Create vboot handoff struct + * + * struct vboot_handoff { + * VbInitParams init_params; + * uint32_t selected_firmware; + * struct firmware_component components[MAX_PARSED_FW_COMPONENTS]; + * char shared_data[VB_SHARED_DATA_MIN_SIZE]; + * } __attribute__((packed)); + */ +void vboot_create_handoff(void *vboot_workbuf) +{ + struct vboot_handoff *vh; + struct vb2_shared_data *sd; + + sd = (struct vb2_shared_data *)vboot_workbuf; + sd->workbuf_hash_offset = 0; + sd->workbuf_hash_size = 0; + + printk(BIOS_INFO, "Creating vboot_handoff structure\n"); + vh = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, sizeof(*vh)); + + if (vh == NULL) { + printk(BIOS_ERR, "Could not add vboot_handoff structure\n"); + return; + } + + memset(vh, 0, sizeof(*vh)); + + fill_vboot_handoff(vh, sd); +} diff --git a/src/vendorcode/google/chromeos/vboot_handoff.h b/src/vendorcode/google/chromeos/vboot_handoff.h index 09c7897..e1e519f 100644 --- a/src/vendorcode/google/chromeos/vboot_handoff.h +++ b/src/vendorcode/google/chromeos/vboot_handoff.h @@ -20,6 +20,7 @@ #define VBOOT_HANDOFF_H #include <vboot_api.h> +#include <vboot_struct.h> /* * The vboot handoff structure keeps track of a maximum number of firmware

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Patch merged into coreboot/master: b0f8326 uio_usbdebug: User-space-i/o framework for usbdebug
by gerrit＠coreboot.org 19 Mar '15

19 Mar '15

the following patch was just integrated into master: commit b0f8326ac264a9eee748623720dacda0def9cceb Author: Nico Huber <nico.h(a)gmx.de> Date: Wed Jan 1 20:47:55 2014 +0100 uio_usbdebug: User-space-i/o framework for usbdebug uio_usbdebug enables you to debug coreboot's usbdebug driver inside a running operating system (only Linux at this time). This comes very handy if you're hacking the usbdebug driver and don't have any other debug output from coreboot itself. Currently, only Intel chipsets are supported. Change-Id: Iaf0bcd4b4c01ae0b099d1206d553344054a62f31 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/4695 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/4695 for details. -gerrit

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Patch set updated for coreboot: c66ba69 libpayload: Add USB device mode driver
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8756 -gerrit commit c66ba695d8acc3c8ab8cd4c3fcd98f89f8703906 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Jan 26 20:17:49 2015 +0100 libpayload: Add USB device mode driver Add a framework for USB device mode controllers and a driver for the ChipIdea controller which is part of the tegra platform. TODO: - fix USB detach/attach - implement zero length packet handling properly BUG=chrome-os-partner:35861 TEST=none BRANCH=none Change-Id: I8defeea78b5a3bdbf9c1b1222c2702eaf3256b81 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 542332291880c4026a05a960ceb91d37891ee018 Original-Change-Id: Ib4068d201dd63ebeda80157bd3130f3059919cdd Original-Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243272 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/Config.in | 15 + payloads/libpayload/drivers/Makefile.inc | 4 + payloads/libpayload/drivers/udc/chipidea.c | 472 ++++++++++++++++++++++++ payloads/libpayload/drivers/udc/chipidea_priv.h | 168 +++++++++ payloads/libpayload/drivers/udc/udc.c | 327 ++++++++++++++++ payloads/libpayload/include/udc/chipidea.h | 37 ++ payloads/libpayload/include/udc/udc.h | 141 +++++++ 7 files changed, 1164 insertions(+) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index 6c95bfa..7b86816 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -495,6 +495,21 @@ config USB_PCI default y if ARCH_X86 default n +config UDC + bool "USB device mode support" + default n + help + Select this option to add support for running as + a USB device. + +config UDC_CI + bool "ChipIdea driver for USB device mode" + depends on UDC + default n + help + Select this option to add the driver for ChipIdea + USB device controller. + endmenu menu "Debugging" diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 0fc2faa..6f4e73d 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -99,5 +99,9 @@ libc-$(CONFIG_LP_USB_XHCI) += usb/xhci_rh.c libc-$(CONFIG_LP_USB_HID) += usb/usbhid.c libc-$(CONFIG_LP_USB_MSC) += usb/usbmsc.c +# USB device stack +libc-$(CONFIG_LP_UDC) += udc/udc.c +libc-$(CONFIG_LP_UDC_CI) += udc/chipidea.c + # used by both USB HID and keyboard libc-y += hid.c diff --git a/payloads/libpayload/drivers/udc/chipidea.c b/payloads/libpayload/drivers/udc/chipidea.c new file mode 100644 index 0000000..e06f0d2 --- /dev/null +++ b/payloads/libpayload/drivers/udc/chipidea.c @@ -0,0 +1,472 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2015 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> +#include <arch/cache.h> +#include <assert.h> +#include <endian.h> +#include <queue.h> +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <usb/usb.h> + +#include <udc/udc.h> +#include <udc/chipidea.h> +#include "chipidea_priv.h" + +#ifdef DEBUG +#define debug(x...) printf(x) +#else +#define debug(x...) do {} while (0) +#endif + +#define min(a, b) (((a) < (b)) ? (a) : (b)) + +static struct qh *get_qh(struct chipidea_pdata *p, int endpoint, int in_dir) +{ + assert(in_dir <= 1); + return &p->qhlist[2 * endpoint + in_dir]; +} + +static unsigned int ep_to_bits(int ep, int in_dir) +{ + return ep + (in_dir ? 16 : 0); +} + +static void clear_setup_ep(struct chipidea_pdata *p, int endpoint) +{ + writel(1 << endpoint, &p->opreg->epsetupstat); +} + +static void clear_ep(struct chipidea_pdata *p, int endpoint, int in_dir) +{ + writel(1 << ep_to_bits(endpoint, in_dir), &p->opreg->epcomplete); +} + +static int chipidea_hw_init(struct usbdev_ctrl *this, void *_opreg, + const device_descriptor_t *dd) +{ + struct chipidea_opreg *opreg = _opreg; + struct chipidea_pdata *p = CI_PDATA(this); + + p->opreg = phys_to_virt(opreg); + p->qhlist = dma_memalign(4096, sizeof(struct qh) * CI_QHELEMENTS); + memcpy(&this->device_descriptor, dd, sizeof(*dd)); + + if (p->qhlist == NULL) + die("failed to allocate memory for usb device mode"); + + memset(p->qhlist, 0, sizeof(struct qh) * CI_QHELEMENTS); + + SLIST_INIT(&this->configs); + + int i; + for (i = 0; i < 16; i++) { + SIMPLEQ_INIT(&p->job_queue[i][0]); + SIMPLEQ_INIT(&p->job_queue[i][1]); + } + + for (i = 0; i < CI_QHELEMENTS; i++) { + p->qhlist[i].config = QH_MPS(512) | QH_NO_AUTO_ZLT | QH_IOS; + p->qhlist[i].td.next = TD_TERMINATE; + } + /* EP0 in/out are hardwired for SETUP */ + p->qhlist[0].config = QH_MPS(64) | QH_NO_AUTO_ZLT | QH_IOS; + p->qhlist[1].config = QH_MPS(64) | QH_NO_AUTO_ZLT | QH_IOS; + + do { + debug("waiting for usb phy clk valid: %x\n", + readl(&p->opreg->susp_ctrl)); + mdelay(1); + } while ((readl(&p->opreg->susp_ctrl) & (1 << 7)) == 0); + + writel(USBCMD_8MICRO | USBCMD_RST, &p->opreg->usbcmd); + mdelay(1); + + /* enable device mode */ + writel(2, &p->opreg->usbmode); + + dcache_clean_by_mva(p->qhlist, sizeof(struct qh) * CI_QHELEMENTS); + + writel(virt_to_phys(p->qhlist), &p->opreg->epbase); + writel(0xffffffff, &p->opreg->epflush); + + /* enable EP0 */ + writel((1 << 23) | (1 << 22) | (1 << 7) | (1 << 6), + &p->opreg->epctrl[0]); + + /* clear status register */ + writel(readl(&p->opreg->usbsts), &p->opreg->usbsts); + + debug("taking controller out of reset\n"); + writel(USBCMD_8MICRO | USBCMD_RUN, &p->opreg->usbcmd); + + return 1; +} + +static void chipidea_halt_ep(struct usbdev_ctrl *this, int ep, int in_dir) +{ + struct chipidea_pdata *p = CI_PDATA(this); + writel(1 << ep_to_bits(ep, in_dir), &p->opreg->epflush); + while (readl(&p->opreg->epflush)) + ; + clrbits_le32(&p->opreg->epctrl[ep], 1 << (7 + (in_dir ? 16 : 0))); +} + +static void chipidea_start_ep(struct usbdev_ctrl *this, + int ep, int in_dir, int ep_type, int mps) +{ + struct chipidea_pdata *p = CI_PDATA(this); + struct qh *qh = get_qh(p, ep, in_dir); + qh->config = (mps << 16) | QH_NO_AUTO_ZLT | QH_IOS; + dcache_clean_by_mva(qh, sizeof(*qh)); + in_dir = in_dir ? 1 : 0; + debug("enabling %d-%d (type %d)\n", ep, in_dir, ep_type); + /* enable endpoint, reset data toggle */ + setbits_le32(&p->opreg->epctrl[ep], + ((1 << 7) | (1 << 6) | (ep_type << 2)) << (in_dir*16)); + p->ep_busy[ep][in_dir] = 0; +} + +static void advance_endpoint(struct chipidea_pdata *p, int endpoint, int in_dir) +{ + if (p->ep_busy[endpoint][in_dir]) + return; + if (SIMPLEQ_EMPTY(&p->job_queue[endpoint][in_dir])) + return; + + struct job *job = SIMPLEQ_FIRST(&p->job_queue[endpoint][in_dir]); + struct qh *qh = get_qh(p, endpoint, in_dir); + + uint32_t start = (uint32_t)(uintptr_t)job->data; + uint32_t offset = (start & 0xfff); + /* unlike with typical EHCI controllers, + * a full TD transfers either 0x5000 bytes if + * page aligned or 0x4000 bytes if not. + */ + int maxsize = 0x5000; + if (offset > 0) + maxsize = 0x4000; + uint32_t td_count = (job->length + maxsize - 1) / maxsize; + + /* special case for zero length packets */ + if (td_count == 0) + td_count = 1; + + if (job->zlp) + td_count++; + + struct td *tds = dma_memalign(32, sizeof(struct td) * td_count); + memset(tds, 0, sizeof(struct td) * td_count); + + int i; + int remaining = job->length; + for (i = 0; i < td_count; i++) { + int datacount = min(maxsize, remaining); + + debug("td %d, %d bytes\n", i, datacount); + tds[i].next = (uint32_t)virt_to_phys(&tds[i+1]); + tds[i].info = TD_INFO_LEN(datacount) | TD_INFO_ACTIVE; + tds[i].page0 = start; + tds[i].page1 = (start & 0xfffff000) + 0x1000; + tds[i].page2 = (start & 0xfffff000) + 0x2000; + tds[i].page3 = (start & 0xfffff000) + 0x3000; + tds[i].page4 = (start & 0xfffff000) + 0x4000; + remaining -= datacount; + start = start + datacount; + } + tds[td_count - 1].next = TD_TERMINATE; + tds[td_count - 1].info |= TD_INFO_IOC; + + qh->td.next = (uint32_t)virt_to_phys(tds); + qh->td.info = 0; + + job->tds = tds; + job->td_count = td_count; + + dcache_clean_by_mva(tds, sizeof(struct td) * td_count); + dcache_clean_by_mva(job->data, job->length); + dcache_clean_by_mva(qh, sizeof(*qh)); + + debug("priming EP %d-%d with %zx bytes starting at %x (%p)\n", endpoint, + in_dir, job->length, tds[0].page0, job->data); + writel(1 << ep_to_bits(endpoint, in_dir), &p->opreg->epprime); + while (readl(&p->opreg->epprime)) + ; + p->ep_busy[endpoint][in_dir] = 1; +} + +static void handle_endpoint(struct usbdev_ctrl *this, int endpoint, int in_dir) +{ + struct chipidea_pdata *p = CI_PDATA(this); + struct job *job = SIMPLEQ_FIRST(&p->job_queue[endpoint][in_dir]); + SIMPLEQ_REMOVE_HEAD(&p->job_queue[endpoint][in_dir], queue); + + if (in_dir) + dcache_invalidate_by_mva(job->data, job->length); + + int length = job->length; + + int i = 0; + do { + int active; + do { + dcache_invalidate_by_mva(&job->tds[i], + sizeof(struct td)); + active = job->tds[i].info & TD_INFO_ACTIVE; + debug("%d-%d: info %08x, page0 %x, next %x\n", + endpoint, in_dir, job->tds[i].info, + job->tds[i].page0, job->tds[i].next); + } while (active); + /* + * The controller writes back the length field in info + * with the number of bytes it did _not_ process. + * Hence, take the originally scheduled length and + * subtract whatever lengths we still find - that gives + * us the data that the controller did transfer. + */ + int remaining = job->tds[i].info >> 16; + length -= remaining; + } while (job->tds[i++].next != TD_TERMINATE); + debug("%d-%d: scheduled %zd, now %d bytes\n", endpoint, in_dir, + job->length, length); + + if (this->current_config && + this->current_config->interfaces[0].handle_packet) + this->current_config->interfaces[0].handle_packet(this, + endpoint, in_dir, job->data, length); + + free(job->tds); + if (job->autofree) + free(job->data); + free(job); + p->ep_busy[endpoint][in_dir] = 0; + + advance_endpoint(p, endpoint, in_dir); +} + +static void start_setup(struct usbdev_ctrl *this, int ep) +{ + dev_req_t dr; + struct chipidea_pdata *p = CI_PDATA(this); + struct qh *qh = get_qh(p, ep, 0); + + dcache_invalidate_by_mva(qh, sizeof(*qh)); + memcpy(&dr, qh->setup_data, sizeof(qh->setup_data)); + clear_setup_ep(p, ep); + +#ifdef DEBUG + hexdump((unsigned long)&dr, sizeof(dr)); +#endif + + udc_handle_setup(this, ep, &dr); +} + + +static void chipidea_enqueue_packet(struct usbdev_ctrl *this, int endpoint, + int in_dir, void *data, int len, int zlp, int autofree) +{ + struct chipidea_pdata *p = CI_PDATA(this); + struct job *job = malloc(sizeof(*job)); + + job->data = data; + job->length = len; + job->zlp = zlp; + job->autofree = autofree; + + debug("adding job of %d bytes to EP %d-%d\n", len, endpoint, in_dir); + SIMPLEQ_INSERT_TAIL(&p->job_queue[endpoint][in_dir], job, queue); + + if ((endpoint == 0) || (this->initialized)) + advance_endpoint(p, endpoint, in_dir); +} + +static int chipidea_poll(struct usbdev_ctrl *this) +{ + struct chipidea_pdata *p = CI_PDATA(this); + uint32_t sts = readl(&p->opreg->usbsts); + writel(sts, &p->opreg->usbsts); /* clear */ + + /* new information if the bus is high speed or not */ + if (sts & USBSTS_PCI) { + debug("USB speed negotiation: "); + if ((readl(&p->opreg->devlc) & DEVLC_HOSTSPEED_MASK) + == DEVLC_HOSTSPEED(2)) { + debug("high speed\n"); + // TODO: implement + } else { + debug("full speed\n"); + // TODO: implement + } + } + + /* reset requested. stop all activities */ + if (sts & USBSTS_URI) { + int i; + debug("USB reset requested\n"); + if (this->initialized) { + writel(readl(&p->opreg->epstat), &p->opreg->epstat); + writel(readl(&p->opreg->epsetupstat), + &p->opreg->epsetupstat); + writel(0xffffffff, &p->opreg->epflush); + for (i = 1; i < 16; i++) + writel(0, &p->opreg->epctrl[i]); + this->initialized = 0; + } + writel((1 << 22) | (1 << 6), &p->opreg->epctrl[0]); + p->qhlist[0].config = QH_MPS(64) | QH_NO_AUTO_ZLT | QH_IOS; + p->qhlist[1].config = QH_MPS(64) | QH_NO_AUTO_ZLT | QH_IOS; + dcache_clean_by_mva(p->qhlist, 2 * sizeof(struct qh)); + } + + if (sts & (USBSTS_UEI | USBSTS_UI)) { + uint32_t bitmap = readl(&p->opreg->epsetupstat); + int ep = 0; + while (bitmap) { + if (bitmap & 1) { + debug("incoming packet on EP %d (setup)\n", ep); + start_setup(this, ep); + } + bitmap >>= 1; + ep++; + } + bitmap = readl(&p->opreg->epcomplete); + ep = 0; + int dir_in = 0; + while (bitmap) { + if (bitmap & 1) { + debug("incoming packet on EP %d (%s)\n", + ep, dir_in ? "intr/in" : "out"); + handle_endpoint(this, ep & 0xf, dir_in); + clear_ep(p, ep & 0xf, dir_in); + } + bitmap >>= 1; + ep++; + if (ep == 16) + dir_in = 1; + } + } + + return 1; +} + +static void chipidea_shutdown(struct usbdev_ctrl *this) +{ + struct chipidea_pdata *p = CI_PDATA(this); + int i, j; + int is_empty = 0; + while (!is_empty) { + is_empty = 1; + this->poll(this); + for (i = 0; i < 16; i++) + for (j = 0; j < 2; j++) + if (!SIMPLEQ_EMPTY(&p->job_queue[i][j])) + is_empty = 0; + } + writel(0xffffffff, &p->opreg->epflush); + writel(USBCMD_8MICRO | USBCMD_RST, &p->opreg->usbcmd); + writel(0, &p->opreg->usbmode); + writel(USBCMD_8MICRO, &p->opreg->usbcmd); + free(p->qhlist); + free(p); + free(this); +} + +static void chipidea_set_address(struct usbdev_ctrl *this, int address) +{ + struct chipidea_pdata *p = CI_PDATA(this); + writel((address << 25) | (1 << 24), &p->opreg->usbadr); +} + +static void chipidea_stall(struct usbdev_ctrl *this, + uint8_t ep, int in_dir, int set) +{ + struct chipidea_pdata *p = CI_PDATA(this); + assert(ep < 16); + uint32_t *ctrl = &p->opreg->epctrl[ep]; + in_dir = in_dir ? 1 : 0; + if (set) { + if (in_dir) + setbits_le32(ctrl, 1 << 16); + else + setbits_le32(ctrl, 1 << 0); + } else { + /* reset STALL bit, reset data toggle */ + if (in_dir) { + setbits_le32(ctrl, 1 << 22); + clrbits_le32(ctrl, 1 << 16); + } else { + setbits_le32(ctrl, 1 << 6); + setbits_le32(ctrl, 1 << 0); + } + } + this->ep_halted[ep][in_dir] = set; +} + +static void *chipidea_malloc(size_t size) +{ + return dma_malloc(size); +} + +static void chipidea_free(void *ptr) +{ + free(ptr); +} + +struct usbdev_ctrl *chipidea_init(device_descriptor_t *dd) +{ + struct usbdev_ctrl *ctrl = calloc(1, sizeof(*ctrl)); + if (ctrl == NULL) + return NULL; + ctrl->pdata = calloc(1, sizeof(struct chipidea_pdata)); + if (ctrl->pdata == NULL) { + free(ctrl); + return NULL; + } + + ctrl->poll = chipidea_poll; + ctrl->add_gadget = udc_add_gadget; + ctrl->enqueue_packet = chipidea_enqueue_packet; + ctrl->shutdown = chipidea_shutdown; + ctrl->set_address = chipidea_set_address; + ctrl->stall = chipidea_stall; + ctrl->halt_ep = chipidea_halt_ep; + ctrl->start_ep = chipidea_start_ep; + ctrl->alloc_data = chipidea_malloc; + ctrl->free_data = chipidea_free; + ctrl->initialized = 0; + + if (!chipidea_hw_init(ctrl, (void *)0x7d000000, dd)) { + free(ctrl->pdata); + free(ctrl); + return NULL; + } + return ctrl; +} diff --git a/payloads/libpayload/drivers/udc/chipidea_priv.h b/payloads/libpayload/drivers/udc/chipidea_priv.h new file mode 100644 index 0000000..ede97ab --- /dev/null +++ b/payloads/libpayload/drivers/udc/chipidea_priv.h @@ -0,0 +1,168 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2015 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __CHIPIDEA_PRIV_H__ +#define __CHIPIDEA_PRIV_H__ + +#include <queue.h> + +struct chipidea_opreg { + uint8_t pad0[0x130]; + uint32_t usbcmd; // 0x130 + uint32_t usbsts; // 0x134 + uint32_t pad138[3]; + uint32_t usbadr; // 0x144 + /* 31:25: address + * 24: staging: 1 -> commit new address after + * next ctrl-in on ep0 + */ + uint32_t epbase; // 0x148 + uint32_t pad14c[10]; + uint32_t portsc; // 0x174 + uint32_t pad178[15]; + uint32_t devlc; // 0x1b4 + /* 25:26: host-desired usb version + * 23: force full speed */ + uint32_t pad1b8[16]; + uint32_t usbmode; // 0x1f8 + /* 0:1: 2 -> device mode */ + uint32_t pad1fc[3]; + uint32_t epsetupstat; // 0x208 + /* 0:15: 1 -> epX received setup packet */ + uint32_t epprime; // 0x20c + /* 0:15: 1 -> rx buffer for epX (OUT) is primed + * (ie. ready for controller-side processing) + * 16:31: 1 -> tx buffer for ep(X-16) (IN/INTR) is primed + * (ie. ready for controller-side processing) + * + * controller will read new td from qh and process it, + * then set the bit to 0 + */ + uint32_t epflush; // 0x210 + /* 0:31: 1 -> flush buffer (as defined in epprime), + * so it's uninitialized again. + * controller resets to 0 when done + */ + uint32_t epstat; // 0x214 + /* 0:31: 1 -> command in epprime is done, EP is ready + * (which may be later than epprime reset) + */ + uint32_t epcomplete; // 0x218 + /* 0:15: 1 -> incoming out/setup packet for epX was handled. + * software should check QH state + * 16:31: 1 -> incoming intr/in packet for ep(X-16) was + * handled. software should check QH state + */ + uint32_t epctrl[16]; // 0x21c + /* epctrl[0] is hardcoded as enabled control endpoint. + * TXS/RXS for stalling can be written. + * + * 23: TXE tx endpoint enable + * 22: TXR reset tx data toggle (for every configuration event) + * 18:19: 0=ctrl, 1=isoc, 2=bulk, 3=intr endpoint + * 16: TXS stall tx + * + * 7: RXE rx endpoint enable + * 6: RXR reset rx data toggle (for every configuration event) + * 2:3: endpoint type (like 18:19) + * 0: RXS stall rx + */ + uint32_t pad25c[0x69]; // 0x25c + uint32_t susp_ctrl; // 0x400 +}; + +#define CI_PDATA(ctrl) ((struct chipidea_pdata *)((ctrl)->pdata)) +#define CI_QHELEMENTS 32 + +#define QH_NO_AUTO_ZLT (1 << 29) /* no automatic ZLT handling by chipset */ +#define QH_MPS(x) ((x) << 16) +#define QH_IOS (1 << 15) /* IRQ on setup */ + +#define TD_INFO_LEN(x) ((x) << 16) +#define TD_INFO_IOC (1 << 15) +#define TD_INFO_ACTIVE (1 << 7) +#define TD_TERMINATE 1 + +#define USBCMD_8MICRO (8 << 16) +#define USBCMD_RST 2 +#define USBCMD_RUN 1 + +#define USBSTS_SLI (1 << 8) +#define USBSTS_URI (1 << 6) +#define USBSTS_PCI (1 << 2) +#define USBSTS_UEI (1 << 1) +#define USBSTS_UI (1 << 0) + +#define DEVLC_HOSTSPEED(x) (x << 25) +#define DEVLC_HOSTSPEED_MASK DEVLC_HOSTSPEED(3) + +struct td { + /* points to next td */ + uint32_t next; + uint32_t info; + /* page0..4 are like EHCI pages: up to 4k each + * page0 from addr to page end, page4 to its length + */ + uint32_t page0; + uint32_t page1; + uint32_t page2; + uint32_t page3; + uint32_t page4; + uint32_t res; +}; + +struct qh { + uint32_t config; + uint32_t current; + struct td td; + /* contains the data of a setup request */ + uint8_t setup_data[8]; + uint32_t res[4]; +}; + +struct job { + SIMPLEQ_ENTRY(job) queue; // linkage + struct td *tds; // for later free()ing + int td_count; + void *data; + size_t length; + int zlp; // append zero length packet? + int autofree; // free after processing? +}; + +SIMPLEQ_HEAD(job_queue, job); + +struct chipidea_pdata { + struct chipidea_opreg *opreg; + struct qh *qhlist; + struct job_queue job_queue[16][2]; + int ep_busy[16][2]; +}; + +#endif diff --git a/payloads/libpayload/drivers/udc/udc.c b/payloads/libpayload/drivers/udc/udc.c new file mode 100644 index 0000000..cdc2b29 --- /dev/null +++ b/payloads/libpayload/drivers/udc/udc.c @@ -0,0 +1,327 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2015 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> +#include <arch/cache.h> +#include <assert.h> +#include <endian.h> +#include <queue.h> +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <usb/usb.h> + +#include <udc/udc.h> + +#ifdef DEBUG +#define debug(x...) printf(x) +#else +#define debug(x...) do {} while (0) +#endif + +#define min(a, b) (((a) < (b)) ? (a) : (b)) + +// TODO: make this right +#define ZLP(len, explen) 0 + +static struct usbdev_configuration *fetch_config(struct usbdev_ctrl *this, + int id) +{ + struct usbdev_configuration *config; + SLIST_FOREACH(config, &this->configs, list) { + debug("checking descriptor %d\n", + config->descriptor.bConfigurationValue); + if (config->descriptor.bConfigurationValue == id) + return config; + } + return NULL; +} + +static void enable_interface(struct usbdev_ctrl *this, int iface_num) +{ + struct usbdev_configuration *config = this->current_config; + struct usbdev_interface *iface = &config->interfaces[iface_num]; + + /* first: shut down all endpoints except EP0 */ + int i; + for (i = 1; i < 16; i++) { + /* disable endpoints */ + this->halt_ep(this, i, 0); + this->halt_ep(this, i, 1); + } + + /* now enable all configured endpoints */ + int epcount = iface->descriptor.bNumEndpoints; + for (i = 0; i < epcount; i++) { + int ep = iface->eps[i].bEndpointAddress; + int mps = iface->eps[i].wMaxPacketSize; + int in_dir = 0; + if (ep & 0x80) { + in_dir = 1; + ep &= 0x7f; + } + int ep_type = iface->eps[i].bmAttributes & 0x3; + this->start_ep(this, ep, in_dir, ep_type, mps); + } + + // gadget specific configuration + if (iface->init) + iface->init(this); +} + +/** + * handle default control transfers on EP 0 + * + * returns 1 if transfer was handled + */ +static int setup_ep0(struct usbdev_ctrl *this, dev_req_t *dr) +{ + if ((dr->bmRequestType == 0x00) && + (dr->bRequest == SET_ADDRESS)) { + this->set_address(this, dr->wValue & 0x7f); + + /* status phase IN */ + this->enqueue_packet(this, 0, 1, NULL, 0, 0, 0); + return 1; + } else + if ((dr->bmRequestType == 0x00) && + (dr->bRequest == SET_CONFIGURATION)) { + struct usbdev_configuration *config = + fetch_config(this, dr->wValue); + + this->current_config = config; + this->current_config_id = dr->wValue; + + if (dr->wValue == 0) + // TODO: reset device + return 1; + + if (config == NULL) { + this->stall(this, 0, 0, 1); + this->stall(this, 0, 1, 1); + return 1; + } + + /* status phase IN */ + this->enqueue_packet(this, 0, 1, NULL, 0, 0, 0); + + /* automatically configure endpoints in interface 0 */ + enable_interface(this, 0); + this->initialized = 1; + return 1; + } else + if ((dr->bmRequestType == 0x80) && + (dr->bRequest == GET_CONFIGURATION)) { + unsigned char *res = dma_malloc(1); + res[0] = this->current_config_id; + + /* data phase IN */ + this->enqueue_packet(this, 0, 1, res, 1, 0, 1); + + // status phase OUT + this->enqueue_packet(this, 0, 0, NULL, 0, 0, 0); + return 1; + } else + // ENDPOINT_HALT + if ((dr->bmRequestType == 0x02) && // endpoint + (dr->bRequest == CLEAR_FEATURE) && + (dr->wValue == 0)) { + int ep = dr->wIndex; + /* clear STALL */ + this->stall(this, ep & 0xf, ep & 0x80, 0); + + /* status phase IN */ + this->enqueue_packet(this, 0, 1, NULL, 0, 0, 0); + return 1; + } else + // ENDPOINT_HALT + if ((dr->bmRequestType == 0x02) && // endpoint + (dr->bRequest == SET_FEATURE) && + (dr->wValue == 0)) { + int ep = dr->wIndex; + /* set STALL */ + this->stall(this, ep & 0xf, ep & 0x80, 1); + + /* status phase IN */ + this->enqueue_packet(this, 0, 1, NULL, 0, 0, 0); + return 1; + } else + // DEVICE_REMOTE_WAKEUP + if ((dr->bmRequestType == 0x00) && + (dr->bRequest == CLEAR_FEATURE) && + (dr->wValue == 1)) { + this->remote_wakeup = 0; + + /* status phase IN */ + this->enqueue_packet(this, 0, 1, NULL, 0, 0, 0); + return 1; + } else + // DEVICE_REMOTE_WAKEUP + if ((dr->bmRequestType == 0x00) && + (dr->bRequest == SET_FEATURE) && + (dr->wValue == 1)) { + this->remote_wakeup = 1; + + /* status phase IN */ + this->enqueue_packet(this, 0, 1, NULL, 0, 0, 0); + return 1; + } else + if ((dr->bmRequestType == 0x82) && // endpoint + (dr->bRequest == GET_STATUS)) { + unsigned char *res = dma_malloc(2); + int ep = dr->wIndex; + /* is EP halted? */ + res[0] = this->ep_halted[ep & 0xf][(ep & 0x80) ? 1 : 0]; + res[1] = 0; + + /* data phase IN */ + this->enqueue_packet(this, 0, 1, res, + min(2, dr->wLength), 0, 1); + + // status phase OUT + this->enqueue_packet(this, 0, 0, NULL, 0, 0, 0); + return 1; + } else + if ((dr->bmRequestType == 0x80) && + (dr->bRequest == GET_STATUS)) { + unsigned char *res = dma_malloc(2); + res[0] = 1; // self powered + if (this->remote_wakeup) + res[0] |= 2; + + res[1] = 0; + + /* data phase IN */ + this->enqueue_packet(this, 0, 1, res, + min(2, dr->wLength), 0, 1); + + // status phase OUT + this->enqueue_packet(this, 0, 0, NULL, 0, 0, 0); + return 1; + } else + if ((dr->bmRequestType == 0x80) && + (dr->bRequest == GET_DESCRIPTOR) && + ((dr->wValue & 0xff00) == 0x0200)) { + int i, j; + /* config descriptor #id + * since config = 0 is undefined, but descriptors + * should start at 0, add 1 to have them match up. + */ + int id = (dr->wValue & 0xff) + 1; + struct usbdev_configuration *config = fetch_config(this, id); + if (config == NULL) { + this->stall(this, 0, 0, 1); + this->stall(this, 0, 1, 1); + return 1; + } + debug("descriptor found, should be %d bytes\n", + config->descriptor.wTotalLength); + + uint8_t *data = dma_malloc(config->descriptor.wTotalLength); + uint8_t *head = data; + + memcpy(head, &config->descriptor, + sizeof(configuration_descriptor_t)); + head += sizeof(configuration_descriptor_t); + + for (i = 0; i < config->descriptor.bNumInterfaces; i++) { + memcpy(head, &config->interfaces[i].descriptor, + sizeof(interface_descriptor_t)); + head += sizeof(interface_descriptor_t); + for (j = 0; + j < config->interfaces[i].descriptor.bNumEndpoints; + j++) { + memcpy(head, &config->interfaces[i].eps[j], + sizeof(endpoint_descriptor_t)); + head += sizeof(endpoint_descriptor_t); + } + } + int size = config->descriptor.wTotalLength; + assert((head - data) == config->descriptor.wTotalLength); + + /* data phase IN */ + this->enqueue_packet(this, 0, 1, data, + min(size, dr->wLength), + ZLP(size, dr->wLength), 1); + + /* status phase OUT */ + this->enqueue_packet(this, 0, 0, NULL, 0, 0, 0); + return 1; + } else + if ((dr->bmRequestType == 0x80) && + (dr->bRequest == GET_DESCRIPTOR) && + ((dr->wValue & 0xff00) == 0x0100)) { + device_descriptor_t *dd = dma_malloc(sizeof(*dd)); + memcpy(dd, &this->device_descriptor, sizeof(*dd)); + dd->bNumConfigurations = this->config_count; + + /* data phase IN */ + this->enqueue_packet(this, 0, 1, (void *)dd, + min(sizeof(*dd), dr->wLength), + ZLP(sizeof(*dd), dr->wLength), 1); + + /* status phase OUT */ + this->enqueue_packet(this, 0, 0, NULL, 0, 0, 0); + return 1; + } + return 0; +} + +void udc_add_gadget(struct usbdev_ctrl *this, + struct usbdev_configuration *config) +{ + int i, size; + SLIST_INSERT_HEAD(&this->configs, config, list); + + size = sizeof(configuration_descriptor_t); + + for (i = 0; i < config->descriptor.bNumInterfaces; i++) { + size += sizeof(config->interfaces[i].descriptor); + size += config->interfaces[i].descriptor.bNumEndpoints * + sizeof(endpoint_descriptor_t); + } + config->descriptor.wTotalLength = size; + config->descriptor.bConfigurationValue = ++this->config_count; +} + +void udc_handle_setup(struct usbdev_ctrl *this, int ep, dev_req_t *dr) +{ + if ((ep == 0) && setup_ep0(this, dr)) + return; + + if (this->current_config && + this->current_config->interfaces[0].handle_setup && + this->current_config->interfaces[0].handle_setup(this, ep, dr)) + return; + + /* no successful SETUP transfer should end up here, report error */ + this->halt_ep(this, ep, 0); + this->halt_ep(this, ep, 1); +} + diff --git a/payloads/libpayload/include/udc/chipidea.h b/payloads/libpayload/include/udc/chipidea.h new file mode 100644 index 0000000..41b8385 --- /dev/null +++ b/payloads/libpayload/include/udc/chipidea.h @@ -0,0 +1,37 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2015 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __CHIPIDEA_H__ +#define __CHIPIDEA_H__ + +#include "udc.h" + +struct usbdev_ctrl *chipidea_init(device_descriptor_t *dd); + +#endif diff --git a/payloads/libpayload/include/udc/udc.h b/payloads/libpayload/include/udc/udc.h new file mode 100644 index 0000000..48e73f4 --- /dev/null +++ b/payloads/libpayload/include/udc/udc.h @@ -0,0 +1,141 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2015 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __UDC_H__ +#define __UDC_H__ + +#include <queue.h> +#include <usb/usb.h> + +struct usbdev_ctrl; + +struct usbdev_interface { + interface_descriptor_t descriptor; + void (*init)(struct usbdev_ctrl *); + + /** + * handle_packet: called by the controller driver for incoming packets + * + * @param ep endpoint the packet is for + * + * @param in_dir 1, if it's an IN or INTR transfer. + * 0 for OUT, SETUP is handled in handle_setup + * + * @param len Actual transfer length in bytes. Can differ from the + * scheduled length if the host requested a smaller + * transfer than we prepared for. + */ + void (*handle_packet)(struct usbdev_ctrl *, int ep, int in_dir, + void *data, int len); + + /** + * handle_setup: called by the controller driver for setup packets + * + * @param ep endpoint the SETUP request came up on + * @param dr SETUP request data + */ + int (*handle_setup)(struct usbdev_ctrl *, int ep, dev_req_t *dr); + endpoint_descriptor_t *eps; +}; + +struct usbdev_configuration { + configuration_descriptor_t descriptor; + SLIST_ENTRY(usbdev_configuration) list; + struct usbdev_interface interfaces[]; +}; + +SLIST_HEAD(configuration_list, usbdev_configuration); + +struct usbdev_ctrl { + /* private data */ + void *pdata; + + int initialized; + int remote_wakeup; + + struct usbdev_configuration *current_config; + int current_config_id; + + struct configuration_list configs; + int config_count; + device_descriptor_t device_descriptor; + + int ep_halted[16][2]; + + /** returns 0 if an error occurred */ + int (*poll)(struct usbdev_ctrl *); + + /** + * Add a gadget driver that exposes properties described in config. + * + * Each gadget driver is registered and exposed as separate USB + * "configuration", so the host can choose between them. + */ + void (*add_gadget)(struct usbdev_ctrl *, + struct usbdev_configuration *config); + + /** + * Add packet to process by the controller. + * zlp: zero length packet, if such a termination is necessary + * autofree: free data after use + */ + void (*enqueue_packet)(struct usbdev_ctrl *this, int endpoint, + int in_dir, void *data, int len, int zlp, int autofree); + + /** + * Tell the hardware that it should listen to a new address + */ + void (*set_address)(struct usbdev_ctrl *, int address); + + void (*halt_ep)(struct usbdev_ctrl *this, int ep, int in_dir); + void (*start_ep)(struct usbdev_ctrl *this, + int ep, int in_dir, int ep_type, int mps); + + /** + * Set or clear endpoint ep's STALL state + */ + void (*stall)(struct usbdev_ctrl *, uint8_t ep, int in_dir, int set); + + void (*shutdown)(struct usbdev_ctrl *this); + + /** + * Allocate n bytes for use as data + */ + void *(*alloc_data)(size_t n); + /** + * Free memory object allocated with alloc_data() + */ + void (*free_data)(void *); +}; + +void udc_add_gadget(struct usbdev_ctrl *this, + struct usbdev_configuration *config); +void udc_handle_setup(struct usbdev_ctrl *this, int ep, dev_req_t *dr); + +#endif

1 0

New patch to review for coreboot: b6b4847 spi: do not use malloc in Gigadevice driver
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8774 -gerrit commit b6b4847feaeee8b89efa2a1791dd8133651c8e5d Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Dec 12 14:07:08 2014 -0800 spi: do not use malloc in Gigadevice driver This allows us to use the driver before ramstage. BRANCH=none BUG=none TEST=built and booted on Pinky Change-Id: I0700388b0e4e0562e3c0a52863c8357097bfd8d6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: cd57587dab74de509d5c50cfc1ad337d765af6c8 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I0ce901331e401274254b8889484ffb41359119fa Original-Reviewed-on: https://chromium-review.googlesource.com/235864 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/drivers/spi/gigadevice.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 15b73b9..9d163f8 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -197,11 +197,12 @@ static int gigadevice_erase(struct spi_flash *flash, u32 offset, size_t len) return spi_flash_cmd_erase(flash, CMD_GD25_SE, offset, len); } +static struct gigadevice_spi_flash stm; + struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode) { const struct gigadevice_spi_flash_params *params; unsigned page_size; - struct gigadevice_spi_flash *stm; unsigned int i; for (i = 0; i < ARRAY_SIZE(gigadevice_spi_flash_table); i++) { @@ -217,32 +218,25 @@ struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode) return NULL; } - stm = malloc(sizeof(struct gigadevice_spi_flash)); - if (!stm) { - printk(BIOS_WARNING, - "SF gigadevice.c: Failed to allocate memory\n"); - return NULL; - } - - stm->params = params; - stm->flash.spi = spi; - stm->flash.name = params->name; + stm.params = params; + stm.flash.spi = spi; + stm.flash.name = params->name; /* Assuming power-of-two page size initially. */ page_size = 1 << params->l2_page_size; - stm->flash.write = gigadevice_write; - stm->flash.erase = gigadevice_erase; + stm.flash.write = gigadevice_write; + stm.flash.erase = gigadevice_erase; #if CONFIG_SPI_FLASH_NO_FAST_READ - stm->flash.read = spi_flash_cmd_read_slow; + stm.flash.read = spi_flash_cmd_read_slow; #else - stm->flash.read = spi_flash_cmd_read_fast; + stm.flash.read = spi_flash_cmd_read_fast; #endif - stm->flash.sector_size = (1 << stm->params->l2_page_size) * - stm->params->pages_per_sector; - stm->flash.size = page_size * params->pages_per_sector + stm.flash.sector_size = (1 << stm.params->l2_page_size) * + stm.params->pages_per_sector; + stm.flash.size = page_size * params->pages_per_sector * params->sectors_per_block * params->nr_blocks; - return &stm->flash; + return &stm.flash; }

1 0

New patch to review for coreboot: 2183e58 spi_flash: add support for S25FL116K
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8773 -gerrit commit 2183e58f1e4efaa2053ee850f3d2d63a6636d6b4 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Dec 10 11:37:05 2014 -0800 spi_flash: add support for S25FL116K S25FL116K family use the first 3 bytes in response to a regacy identification command (9f) while previously supported models use the last 4 bytes. This change defines identify functions to allow both types to be handled correctly. BUG=none BRANCH=tot TEST=verified romstage is loaded on cosmos development board. Change-Id: I1970a9af17e81299fada5029724d405de4022156 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 65ff436db2355cb68a766a3dedbcd7e2f765e6db Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: Icdd2645e356652672c4482e7b805da1bc0f21e71 Original-Reviewed-on: https://chromium-review.googlesource.com/234431 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/drivers/spi/spansion.c | 70 ++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 61 insertions(+), 9 deletions(-) diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index d8a1754..d7cca3f 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -44,20 +44,25 @@ #define CMD_S25FLXX_DP 0xb9 /* Deep Power-down */ #define CMD_S25FLXX_RES 0xab /* Release from DP, and Read Signature */ +#define SPSN_MANUFACTURER_ID_S25FL116K 0x01 #define SPSN_ID_S25FL008A 0x0213 #define SPSN_ID_S25FL016A 0x0214 #define SPSN_ID_S25FL032A 0x0215 #define SPSN_ID_S25FL064A 0x0216 #define SPSN_ID_S25FL128S 0x0219 #define SPSN_ID_S25FL128P 0x2018 +#define SPSN_ID_S25FL116K 0x4015 #define SPSN_EXT_ID_S25FL128P_256KB 0x0300 #define SPSN_EXT_ID_S25FL128P_64KB 0x0301 #define SPSN_EXT_ID_S25FL032P 0x4d00 #define SPSN_EXT_ID_S25FLXXS_64KB 0x4d01 struct spansion_spi_flash_params { + u8 idcode0; u16 idcode1; u16 idcode2; + int (*identify) (const struct spansion_spi_flash_params *params, + u8 *idcode); u16 page_size; u16 pages_per_sector; u16 nr_sectors; @@ -75,79 +80,130 @@ static inline struct spansion_spi_flash *to_spansion_spi_flash(struct spi_flash return container_of(flash, struct spansion_spi_flash, flash); } +/* + * returns non-zero if the given idcode matches the ID of the chip. this is for + * chips which use 2nd, 3rd, 4th, and 5th byte. + */ +static int identify_2345(const struct spansion_spi_flash_params *params, + u8 *idcode) +{ + u16 jedec = idcode[1] << 8 | idcode[2]; + u16 ext_jedec = idcode[3] << 8 | idcode[4]; + return (params->idcode1 == jedec) && (params->idcode2 == ext_jedec); +} + +/* + * returns non-zero if the given idcode matches the ID of the chip. this is for + * chips which use 1st, 2nd, and 3rd byte. + */ +static int identify_123(const struct spansion_spi_flash_params *params, + u8 *idcode) +{ + u16 jedec = idcode[1] << 8 | idcode[2]; + return (params->idcode0 == idcode[0]) && (params->idcode1 == jedec); +} + static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { { + .idcode0 = 0, .idcode1 = SPSN_ID_S25FL008A, .idcode2 = 0, + .identify = identify_2345, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 16, .name = "S25FL008A", }, { + .idcode0 = 0, .idcode1 = SPSN_ID_S25FL016A, .idcode2 = 0, + .identify = identify_2345, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 32, .name = "S25FL016A", }, { + .idcode0 = 0, .idcode1 = SPSN_ID_S25FL032A, .idcode2 = 0, + .identify = identify_2345, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 64, .name = "S25FL032A", }, { + .idcode0 = 0, .idcode1 = SPSN_ID_S25FL064A, .idcode2 = 0, + .identify = identify_2345, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 128, .name = "S25FL064A", }, { + .idcode0 = 0, .idcode1 = SPSN_ID_S25FL128P, .idcode2 = SPSN_EXT_ID_S25FL128P_64KB, + .identify = identify_2345, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 256, .name = "S25FL128P_64K", }, { + .idcode0 = 0, .idcode1 = SPSN_ID_S25FL128P, .idcode2 = SPSN_EXT_ID_S25FL128P_256KB, + .identify = identify_2345, .page_size = 256, .pages_per_sector = 1024, .nr_sectors = 64, .name = "S25FL128P_256K", }, { + .idcode0 = 0, .idcode1 = SPSN_ID_S25FL128S, .idcode2 = SPSN_EXT_ID_S25FLXXS_64KB, + .identify = identify_2345, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 512, .name = "S25FL128S_256K", }, { + .idcode0 = 0, .idcode1 = SPSN_ID_S25FL032A, .idcode2 = SPSN_EXT_ID_S25FL032P, + .identify = identify_2345, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 64, .name = "S25FL032P", }, { + .idcode0 = 0, .idcode1 = SPSN_ID_S25FL128P, .idcode2 = SPSN_EXT_ID_S25FLXXS_64KB, + .identify = identify_2345, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 256, .name = "25FS128S", }, + { + .idcode0 = SPSN_MANUFACTURER_ID_S25FL116K, + .idcode1 = SPSN_ID_S25FL116K, + .idcode2 = 0, + .identify = identify_123, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 32, + .name = "S25FL116K_16M", + }, }; static int spansion_write(struct spi_flash *flash, @@ -223,21 +279,17 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) const struct spansion_spi_flash_params *params; struct spansion_spi_flash *spsn; unsigned int i; - unsigned short jedec, ext_jedec; - - jedec = idcode[1] << 8 | idcode[2]; - ext_jedec = idcode[3] << 8 | idcode[4]; for (i = 0; i < ARRAY_SIZE(spansion_spi_flash_table); i++) { params = &spansion_spi_flash_table[i]; - if (params->idcode1 == jedec) { - if (params->idcode2 == ext_jedec) - break; - } + if (params->identify(params, idcode)) + break; } if (i == ARRAY_SIZE(spansion_spi_flash_table)) { - printk(BIOS_WARNING, "SF: Unsupported SPANSION ID %04x %04x\n", jedec, ext_jedec); + printk(BIOS_WARNING, + "SF: Unsupported SPANSION ID %02x %02x %02x %02x %02x\n", + idcode[0], idcode[1], idcode[2], idcode[3], idcode[4]); return NULL; }

1 0

New patch to review for coreboot: 2fe6007 verstage should include the CBFS SPI wrapper, when configured
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8772 -gerrit commit 2fe6007e605410fbd4dd88bbb72573ea45512db9 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Oct 16 11:24:12 2014 -0700 verstage should include the CBFS SPI wrapper, when configured Vboot2 targets so far did not have COMMON_CBFS_SPI_WRAPPER configuration option enabled, so the verstage is missing the relevant files in some Makefiles. This patch fixes the problem. BRANCH=none BUG=none TEST=with the rest of the patches applied cosmos target builds fine with COMMON_CBFS_SPI_WRAPPER enabled Change-Id: I3ce78c8afc5f7d8ce822bbf8dd789c0c2ba4b99c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b72693c96f7d8ce94ce6fe12b316d5b88fded579 Original-Change-Id: Iab813b9f5b0156c45b007fe175500ef0de50e65c Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223751 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/spi/Makefile.inc | 11 +++++++++++ src/lib/Makefile.inc | 3 +++ 2 files changed, 14 insertions(+) diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 1bada79..ade34a2 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -20,6 +20,17 @@ romstage-$(CONFIG_SPI_FLASH_SST) += sst.c romstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c romstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c romstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c + +verstage-$(CONFIG_SPI_FLASH) += spi_flash.c +verstage-$(CONFIG_SPI_FLASH_EON) += eon.c +verstage-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c +verstage-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c +verstage-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c +verstage-$(CONFIG_SPI_FLASH_SST) += sst.c +verstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c +verstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c +verstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c + endif ramstage-$(CONFIG_SPI_FLASH) += spi_flash.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e599066..d1e3a92 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -29,6 +29,9 @@ verstage-y += delay.c verstage-y += cbfs.c verstage-y += memcmp.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c +verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c +verstage-y += tlcl.c +verstage-$(CONFIG_GENERIC_UDELAY) += timer.c romstage-y += memchr.c

1 0

New patch to review for coreboot: b7c93f9 spi: do not use malloc in Winbond driver
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8771 -gerrit commit b7c93f9fca29cd0e27d23b38a5dcfed3ebefc01a Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Nov 11 07:17:24 2014 -0800 spi: do not use malloc in Winbond driver When the driver is included in bootblock, malloc() is not available. Come to think of it, it is perfectly fine to use a statically allocated structure for the SPI device descriptor - coreboot is unlikely to require concurrent support of multiple SPI devices of the same kind. BRANCH=none BUG=chrome-os-partner:31438 TEST=bootblock on the FPGA board recognizes the installed Winbond device: coreboot-4.0 bootblock Tue Nov 11 07:27:24 PST 2014 starting... SF: Detected W25Q16 with page size 1000, total 200000 Change-Id: Iea1936a219d38848580a10f75eb8bbcab17e6507 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0b4082442aa526d387a80cb5872d78670e6b468b Original-Change-Id: Iaa69d610ef18e69b1ae5ade2d958f9fe1595a723 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228959 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/spi/winbond.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 4c4150f..5fc7b42 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -194,11 +194,12 @@ static int winbond_erase(struct spi_flash *flash, u32 offset, size_t len) return spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len); } +static struct winbond_spi_flash stm; + struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) { const struct winbond_spi_flash_params *params; unsigned page_size; - struct winbond_spi_flash *stm; unsigned int i; for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) { @@ -213,31 +214,25 @@ struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) return NULL; } - stm = malloc(sizeof(struct winbond_spi_flash)); - if (!stm) { - printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); - return NULL; - } - - stm->params = params; - stm->flash.spi = spi; - stm->flash.name = params->name; + stm.params = params; + stm.flash.spi = spi; + stm.flash.name = params->name; /* Assuming power-of-two page size initially. */ page_size = 1 << params->l2_page_size; - stm->flash.write = winbond_write; - stm->flash.erase = winbond_erase; + stm.flash.write = winbond_write; + stm.flash.erase = winbond_erase; #if CONFIG_SPI_FLASH_NO_FAST_READ - stm->flash.read = spi_flash_cmd_read_slow; + stm.flash.read = spi_flash_cmd_read_slow; #else - stm->flash.read = spi_flash_cmd_read_fast; + stm.flash.read = spi_flash_cmd_read_fast; #endif - stm->flash.sector_size = (1 << stm->params->l2_page_size) * - stm->params->pages_per_sector; - stm->flash.size = page_size * params->pages_per_sector + stm.flash.sector_size = (1 << stm.params->l2_page_size) * + stm.params->pages_per_sector; + stm.flash.size = page_size * params->pages_per_sector * params->sectors_per_block * params->nr_blocks; - return &stm->flash; + return &stm.flash; }

1 0

New patch to review for coreboot: b86efe2 Add support for GigaDevice GD25LQ64C/GD25LB64C SPI ROM.
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8770 -gerrit commit b86efe229bacd98767af171af61e16e11d792628 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Thu Apr 3 16:37:06 2014 -0600 Add support for GigaDevice GD25LQ64C/GD25LB64C SPI ROM. GD25LQ64C and GD25LB64C have the same ID and settings. BUG=chrome-os-partner:25907 BRANCH=baytrail TEST=Boot with GD25LQ64 and check MRC data save/restore works. Change-Id: I8a4aa7cabd9a7657c2f0bae255a87341db3f1061 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 20b5896adbbbdedcb1b7de435466dcc6bfa703cb Original-Change-Id: I86d1e69552b6000faa9e0523356e27d7e2a6a6db Original-Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193238 Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/drivers/spi/gigadevice.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 68b487e..15b73b9 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -106,7 +106,15 @@ static const struct gigadevice_spi_flash_params gigadevice_spi_flash_table[] = { .pages_per_sector = 16, .sectors_per_block = 16, .nr_blocks = 128, - .name = "GD25Q64(B)", + .name = "GD25Q64B/GD25B64C", + }, + { + .id = 0x6017, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "GD25LQ64C/GD25LB64C", }, { .id = 0x4018,

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New patch to review for coreboot: 479fd18 console: Allow bootblock console on MIPS
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8769 -gerrit commit 479fd18740102893eedc3b6c2f162b1f94a3bc09 Author: Paul Burton <paul.burton(a)imgtec.com> Date: Sat Jun 14 00:04:33 2014 +0100 console: Allow bootblock console on MIPS In addition to ARM based systems, allow MIPS based systems to select bootblock console support. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: I40e5d8b651102709118878a317f7e983a617f433 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1a41853273ef9ae716d5645379fcef79c5771b87 Original-Change-Id: I41f03ea8c8104ba2dd9f532b084696385d29636c Original-Signed-off-by: Paul Burton <paul.burton(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207973 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> --- src/console/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index e686506..0a0e069 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -2,7 +2,7 @@ menu "Console" config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." - depends on ARCH_ARM || ARCH_RISCV + depends on ARCH_ARM || ARCH_RISCV || ARCH_MIPS default n help Use console during the bootblock if supported

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New patch to review for coreboot: 79077de imgtec/danube: Build BIMG boot images
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8768 -gerrit commit 79077def638457511b7961d9f4e10323c4accbc9 Author: Paul Burton <paul.burton(a)imgtec.com> Date: Sat Jun 14 00:09:49 2014 +0100 imgtec/danube: Build BIMG boot images Add a new utility named bimgtool, a simple tool which generates boot images in the BIMG format. This is the format the Danube boot ROM expects the user supplied code to be wrapped in, it is described by struct bimg_header in the code. This utility will be used to wrap the coreboot bootblock when building Danube targets. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: I08ddb1b70d0b1feb1ffb3d62c4e5e6f07f4acdb7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7fe6a9f383b79120f9ae231453d4b3a0f85b4fa7 Original-Change-Id: I63b9f5e09cd1f12765317b38e2a0dd033cdd6d39 Original-Signed-off-by: Paul Burton <paul.burton(a)imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207975 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 8 +- util/bimgtool/Makefile | 17 ++++ util/bimgtool/bimgtool.c | 222 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 245 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 41c5778..bf1b95a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -265,10 +265,9 @@ else CFLAGS_common += -Os endif - additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ $(objutil)/ifdfake $(objutil)/options $(objutil)/fletcher \ - $(objutil)/cbootimage + $(objutil)/cbootimage $(objutil)/bimgtool ####################################################################### # generate build support files @@ -333,6 +332,11 @@ CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage subdirs-y += util/nvidia +BIMGTOOL:=$(objutil)/bimgtool/bimgtool +$(BIMGTOOL): $(top)/util/bimgtool/bimgtool.c + @printf " HOSTCC $(subst $(obj)/,,$(@))\n" + $(HOSTCC) $(HOSTCFLAGS) -o $@ $< + ####################################################################### # needed objects that every mainboard uses # Creation of these is architecture and mainboard independent diff --git a/util/bimgtool/Makefile b/util/bimgtool/Makefile new file mode 100644 index 0000000..3bd0f07 --- /dev/null +++ b/util/bimgtool/Makefile @@ -0,0 +1,17 @@ +obj ?= $(shell pwd) + +HOSTCC ?= gcc +CFLAGS ?= -g +CFLAGS += -D_7ZIP_ST +CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes +CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs +CFLAGS += -Wstrict-aliasing -Wshadow -Werror +LDFLAGS += -g + +all: dep $(obj)/bimgtool + +clean: + rm -f $(obj)/bimgtool + +$(obj)/bimgtool: bimgtool.c + $(HOSTCC) $(CFLAGS) -o $@ $^ diff --git a/util/bimgtool/bimgtool.c b/util/bimgtool/bimgtool.c new file mode 100644 index 0000000..eed9248 --- /dev/null +++ b/util/bimgtool/bimgtool.c @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Imagination Technologies Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <errno.h> +#include <stdint.h> +#include <stdio.h> +#include <stdlib.h> +#include <sys/stat.h> +#include <sys/types.h> + +struct bimg_header { + uint32_t magic; + uint16_t ver_major; + uint16_t ver_minor; + uint32_t data_size; + uint32_t entry_addr; + uint32_t flags; + uint32_t data_crc; + uint32_t crc; +} __attribute__((packed)); + +struct bimg_data_header { + uint32_t size; + uint32_t dest_addr; + uint16_t crc; +} __attribute__((packed)); + +#define BIMG_MAGIC /* y */ 0xabbadaba /* doo! */ + +#define BIMG_OP_MASK (0xf << 0) +#define BIMG_OP_EXEC_RETURN (0x1 << 0) +#define BIMG_OP_EXEC_NO_RETURN (0x2 << 0) +#define BIMG_DATA_CHECKSUM (0x1 << 4) + +#define MAX_RECORD_BYTES 0x8000 + +#define CRC_INIT 0xffff + +#define error(msg...) fprintf(stderr, "ERROR: " msg) + +#define error_ret(ret, msg...) { \ + error(msg); \ + return ret; \ +} + +static uint16_t crc_x25(uint16_t crc, void *void_buf, size_t size) +{ + static const uint16_t crc_table[16] = { + 0x0000, 0x1021, 0x2042, 0x3063, + 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, + 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + }; + uint8_t *buf, data; + + for (buf = void_buf; size; size--) { + data = *buf++; + crc = (crc << 4) ^ crc_table[((crc >> 12) ^ (data >> 4)) & 0xf]; + crc = (crc << 4) ^ crc_table[((crc >> 12) ^ (data >> 0)) & 0xf]; + } + + return crc; +} + +static int write_binary(FILE *out, FILE *in, struct bimg_header *hdr) +{ + static uint8_t file_buf[MAX_RECORD_BYTES]; + struct bimg_data_header data_hdr; + size_t n_written; + + data_hdr.dest_addr = hdr->entry_addr; + + while ((data_hdr.size = fread(file_buf, 1, sizeof(file_buf), in))) { + data_hdr.crc = crc_x25(CRC_INIT, &data_hdr, + sizeof(data_hdr) - sizeof(data_hdr.crc)); + + if (fwrite(&data_hdr, sizeof(data_hdr), 1, out) != 1) + error_ret(-EIO, "Failed to write data header: %d\n", + errno); + + n_written = fwrite(file_buf, 1, data_hdr.size, out); + if (n_written != data_hdr.size) + error_ret(-EIO, "Failed to write to output file: %d\n", + errno); + + data_hdr.dest_addr += n_written; + hdr->data_size += sizeof(data_hdr) + n_written; + hdr->data_crc = crc_x25(hdr->data_crc, file_buf, n_written); + } + + if (ferror(in)) + error_ret(-EIO, "Failed to read input file\n"); + + return 0; +} + +static int write_final(FILE *out, struct bimg_header *hdr) +{ + struct bimg_data_header data_hdr = { + .size = 0, + .dest_addr = ~0, + }; + + data_hdr.crc = crc_x25(CRC_INIT, &data_hdr, + sizeof(data_hdr) - sizeof(data_hdr.crc)); + + if (fwrite(&data_hdr, sizeof(data_hdr), 1, out) != 1) + error_ret(-EIO, "Failed to write data header: %d\n", errno); + + hdr->data_size += sizeof(data_hdr); + + return 0; +} + +static void usage(FILE *f) +{ + fprintf(f, + "Usage: bimgtool <input> <output> <base-address>\n" + "\n" + "bimgtool is a simple tool which generates boot images in the " + "BIMG format used in systems designed by Imagination " + "Technologies, for example the Danube SoC. This version of the " + "tool generates BIMG version 1.0 images.\n" + "\n" + " input: The binary file to be converted to a BIMG\n" + " output: The name of the output BIMG file\n" + " base-address: The address in memory at which you wish the " + "input binary to be loaded.\n"); +} + +int main(int argc, char *argv[]) +{ + const char *in_filename, *out_filename; + FILE *in_file, *out_file; + int err; + struct bimg_header hdr = { + .magic = BIMG_MAGIC, + .ver_major = 1, + .ver_minor = 0, + .flags = BIMG_OP_EXEC_NO_RETURN | BIMG_DATA_CHECKSUM, + .data_crc = CRC_INIT, + }; + + if (argc != 4) { + usage(stderr); + goto out_err; + } + + in_filename = argv[1]; + out_filename = argv[2]; + hdr.entry_addr = strtoul(argv[3], NULL, 16); + + in_file = fopen(in_filename, "r"); + if (!in_file) { + error("Failed to open input file '%s'\n", in_filename); + goto out_err; + } + + out_file = fopen(out_filename, "w"); + if (!out_file) { + error("Failed to open output file '%s'\n", out_filename); + goto out_err_close_in; + } + + if (fseek(out_file, sizeof(hdr), SEEK_SET)) { + error("Failed to seek past header: %d\n", errno); + goto out_err_close_out; + } + + err = write_binary(out_file, in_file, &hdr); + if (err) { + error("Failed to write binary: %d\n", err); + goto out_err_close_out; + } + + err = write_final(out_file, &hdr); + if (err) { + error("Failed to write final record: %d\n", err); + goto out_err_close_out; + } + + hdr.crc = crc_x25(CRC_INIT, &hdr, sizeof(hdr) - sizeof(hdr.crc)); + + if (fseek(out_file, 0, SEEK_SET)) { + error("Failed to seek to header: %d\n", errno); + goto out_err_close_out; + } + + if (fwrite(&hdr, sizeof(hdr), 1, out_file) != 1) { + error("Failed to write header: %d\n", errno); + goto out_err_close_out; + } + + fclose(in_file); + fclose(out_file); + return EXIT_SUCCESS; + +out_err_close_out: + fclose(out_file); +out_err_close_in: + fclose(in_file); +out_err: + return EXIT_FAILURE; +}

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coreboot-gerrit March 2015