coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 6968c00 mips: fix bootblock stack definitions
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8767 -gerrit commit 6968c0091c0e27c2d2b1680181244ef578e73c83 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 17 16:29:15 2014 -0700 mips: fix bootblock stack definitions Bootblock stack on Danube should be SRAM and defined separately from the rest of the coreboot stack. The actual coreboot stack will be defined later. The top of the stack should be above the bottom, as the stack grows towards lower addresses. BUG=chrome-os-partner:31438 TEST=ran bootblock on simulator under codescape, observed stack properly initialized. Change-Id: I43d2bae5f85a09a95ca0103b253399bd92555aef Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e02724cb4b30990ebaa631dabb45917af29d6437 Original-Change-Id: I3c37c8b5a1c0e7fd19411558a8f6d899fc283191 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218732 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/mips/bootblock.inc | 6 +++--- src/soc/imgtec/danube/Kconfig | 16 +++++++++------- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/src/arch/mips/bootblock.inc b/src/arch/mips/bootblock.inc index 76a10cf..dbde803 100644 --- a/src/arch/mips/bootblock.inc +++ b/src/arch/mips/bootblock.inc @@ -23,18 +23,18 @@ .globl _start _start: /* Set the stack pointer */ - li $sp, CONFIG_STACK_TOP + li $sp, CONFIG_BOOTBLOCK_STACK_TOP /* * Initialise the stack to a known value, used later to check for * overflow. */ - li $t0, CONFIG_STACK_BOTTOM + li $t0, CONFIG_BOOTBLOCK_STACK_BOTTOM addi $t1, $sp, -4 li $t2, 0xdeadbeef 1: sw $t2, 0($t0) bne $t0, $t1, 1b - addi $t0, $t0, 4 + addi $t0, $t0, 4 /* Run main */ b main diff --git a/src/soc/imgtec/danube/Kconfig b/src/soc/imgtec/danube/Kconfig index ba04146..b2e7a5d 100644 --- a/src/soc/imgtec/danube/Kconfig +++ b/src/soc/imgtec/danube/Kconfig @@ -57,15 +57,17 @@ config CBMEM_CONSOLE_PRERAM_BASE Allocate 4KB to the pre-ram console buffer, we should be able to use GRAM eventually and have a much larger buffer. -config STACK_TOP +config BOOTBLOCK_STACK_BOTTOM hex - default CBMEM_CONSOLE_PRERAM_BASE + default 0x9b00e000 + help + This allocates 6KB of stack space. One needs to verify that this is + sufficient. -config STACK_BOTTOM +config BOOTBLOCK_STACK_TOP hex - default 0x9b00f000 + default CBMEM_CONSOLE_PRERAM_BASE help - Allocating 12KB for the stack, should be able to have more once GRAM - is available. - + Bootblock stack starts immediately under the CBMEM console buffer, + stack location might be changed by ro stage. endif

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New patch to review for coreboot: 8d2ffc6 imgvp-danube: Support for the ImgTec Danube Virtual Platform
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8766 -gerrit commit 8d2ffc6dd63e87247fe3e8f1d4cd2ce6dc20fc60 Author: Paul Burton <paul.burton(a)imgtec.com> Date: Sat Jun 14 00:13:28 2014 +0100 imgvp-danube: Support for the ImgTec Danube Virtual Platform Add basic board support for the ImgTec Danube Virtual Platform, which emulates a system built around the Danube SoC. Run this by loading coreboot.bimg into a flash device connected to SPFI1 chip select 0 & then executing the Danube boot ROM. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: Ia62af62804bab261f3cabf7c2e62f5bb08a4a1a4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6cb1017f5e2fec85f7f5c60cd2cfec63cc886b49 Original-Change-Id: I7a2b52f304bcb4b614440ec38975e05f38b0e590 Original-Signed-off-by: Paul Burton <paul.burton(a)imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207976 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/emulation/Kconfig | 4 ++ src/mainboard/emulation/imgvp-danube/Kconfig | 53 ++++++++++++++++++++++ src/mainboard/emulation/imgvp-danube/Makefile.inc | 22 +++++++++ src/mainboard/emulation/imgvp-danube/bootblock.c | 24 ++++++++++ src/mainboard/emulation/imgvp-danube/devicetree.cb | 26 +++++++++++ src/mainboard/emulation/imgvp-danube/mainboard.c | 33 ++++++++++++++ src/mainboard/emulation/imgvp-danube/romstage.c | 38 ++++++++++++++++ 7 files changed, 200 insertions(+) diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index a1ee02d..2ddb846 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -15,6 +15,9 @@ config BOARD_EMULATION_QEMU_ARMV7 config BOARD_EMULATION_QEMU_UCB_RISCV bool "QEMU ucb riscv" +config BOARD_EMULATION_IMGVP_DANUBE + bool "ImgTec Danube Virtual Platform" + endchoice config BOARD_EMULATION_QEMU_X86 @@ -26,6 +29,7 @@ source "src/mainboard/emulation/qemu-i440fx/Kconfig" source "src/mainboard/emulation/qemu-q35/Kconfig" source "src/mainboard/emulation/qemu-armv7/Kconfig" source "src/mainboard/emulation/qemu-riscv/Kconfig" +source "src/mainboard/emulation/imgvp-danube/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/emulation/imgvp-danube/Kconfig b/src/mainboard/emulation/imgvp-danube/Kconfig new file mode 100644 index 0000000..07897f7 --- /dev/null +++ b/src/mainboard/emulation/imgvp-danube/Kconfig @@ -0,0 +1,53 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Imagination Technologies +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +if BOARD_EMULATION_IMGVP_DANUBE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOOTBLOCK_CONSOLE + select CPU_IMGTEC_DANUBE + +config MAINBOARD_DIR + string + default emulation/imgvp-danube + +config MAINBOARD_PART_NUMBER + string + default "ImgTec Danube Virtual Platform" + +config BOOTBLOCK_MAINBOARD_INIT + string + default "mainboard/emulation/imgvp-danube/bootblock.c" + +config SYS_SDRAM_BASE + hex "SDRAM base address" + default 0x80000000 + +config DRAM_SIZE_MB + int + default 256 + +config HEAP_SIZE + hex + default 0x08000000 + +endif diff --git a/src/mainboard/emulation/imgvp-danube/Makefile.inc b/src/mainboard/emulation/imgvp-danube/Makefile.inc new file mode 100644 index 0000000..8be1b22 --- /dev/null +++ b/src/mainboard/emulation/imgvp-danube/Makefile.inc @@ -0,0 +1,22 @@ +# +# This file is part of the coreboot project. +# +# Copyright 2014 Imagination Technologies Ltd. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +romstage-y += romstage.c diff --git a/src/mainboard/emulation/imgvp-danube/bootblock.c b/src/mainboard/emulation/imgvp-danube/bootblock.c new file mode 100644 index 0000000..1784a02 --- /dev/null +++ b/src/mainboard/emulation/imgvp-danube/bootblock.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/emulation/imgvp-danube/devicetree.cb b/src/mainboard/emulation/imgvp-danube/devicetree.cb new file mode 100644 index 0000000..6e9849e --- /dev/null +++ b/src/mainboard/emulation/imgvp-danube/devicetree.cb @@ -0,0 +1,26 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Imagination Technologies +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +chip soc/imgtec/danube + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/emulation/imgvp-danube/mainboard.c b/src/mainboard/emulation/imgvp-danube/mainboard.c new file mode 100644 index 0000000..a3e2703 --- /dev/null +++ b/src/mainboard/emulation/imgvp-danube/mainboard.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> + +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Enable imgvp-danube device...\n"); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/emulation/imgvp-danube/romstage.c b/src/mainboard/emulation/imgvp-danube/romstage.c new file mode 100644 index 0000000..ac0ea5f --- /dev/null +++ b/src/mainboard/emulation/imgvp-danube/romstage.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/hlt.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <console/console.h> + +void main(void) +{ + void *entry; + + console_init(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + if (entry != (void *)-1) + stage_exit(entry); + + hlt(); +}

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New patch to review for coreboot: c9e8f27 danube: modify to use the generic timer interface
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8765 -gerrit commit c9e8f270acbe38c9412d8276972dbf8726c7640e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Sep 29 13:08:24 2014 -0700 danube: modify to use the generic timer interface Actual timer support is not yet available for Danube, it will be added soon. For now, just to make the target build, modify it to use GENERIC_UDELAY and HAVE_MONOTONIC_TIMER configuration option. BUG=none TEST=the target builds again Change-Id: Iad1ceb966d5dbc8687b966be4d2506c8f92eba5a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 261837539fb5a31f96e682edbcbbbc0e588f2750 Original-Change-Id: Ie3289eace9d2baadd01bd641b5dffc635ac80c0f Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220395 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/danube/Kconfig | 2 ++ src/soc/imgtec/danube/Makefile.inc | 2 ++ src/soc/imgtec/danube/monotonic_timer.c | 25 +++++++++++++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/src/soc/imgtec/danube/Kconfig b/src/soc/imgtec/danube/Kconfig index 0e3c629..ba04146 100644 --- a/src/soc/imgtec/danube/Kconfig +++ b/src/soc/imgtec/danube/Kconfig @@ -22,6 +22,8 @@ config CPU_IMGTEC_DANUBE select CPU_MIPS select DYNAMIC_CBMEM + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL bool diff --git a/src/soc/imgtec/danube/Makefile.inc b/src/soc/imgtec/danube/Makefile.inc index 6a2ba4f..2660848 100644 --- a/src/soc/imgtec/danube/Makefile.inc +++ b/src/soc/imgtec/danube/Makefile.inc @@ -30,9 +30,11 @@ romstage-y += uart.c ramstage-y += uart.c endif +bootblock-y += monotonic_timer.c bootblock-y += timestamp.c ramstage-y += cbmem.c +ramstage-y += monotonic_timer.c ramstage-y += timestamp.c romstage-y += cbmem.c diff --git a/src/soc/imgtec/danube/monotonic_timer.c b/src/soc/imgtec/danube/monotonic_timer.c new file mode 100644 index 0000000..a8fe27c --- /dev/null +++ b/src/soc/imgtec/danube/monotonic_timer.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <timer.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + /* to be defined */ +}

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New patch to review for coreboot: 05746c2 danube: use SOC specific rom stage code
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8764 -gerrit commit 05746c258e1398d9ff560f4332ee6a31d4d8ce4b Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 2 13:20:47 2014 -0700 danube: use SOC specific rom stage code Romstage initialization code does not need to be board specific, keep it in the SOC directory. Should there be a need for the board specific code, it can be added later. BUG=chrome-os-partner:31438 TEST=with upcoming patches, the urara board coreboot builds fine Change-Id: Ib619fa9313d463ded13e9259e50bb5aeaab4fb05 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2c08977aaa5e9b5da29359d1920d7d8b61ce86d3 Original-Change-Id: I27e2d225bd36c42ccd29128d0ea9a970566c02af Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215992 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/danube/Makefile.inc | 1 + src/soc/imgtec/danube/romstage.c | 39 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/src/soc/imgtec/danube/Makefile.inc b/src/soc/imgtec/danube/Makefile.inc index d7628ed..6a2ba4f 100644 --- a/src/soc/imgtec/danube/Makefile.inc +++ b/src/soc/imgtec/danube/Makefile.inc @@ -36,6 +36,7 @@ ramstage-y += cbmem.c ramstage-y += timestamp.c romstage-y += cbmem.c +romstage-y += romstage.c romstage-y += timestamp.c # Generate the actual coreboot bootblock code diff --git a/src/soc/imgtec/danube/romstage.c b/src/soc/imgtec/danube/romstage.c new file mode 100644 index 0000000..53ca898 --- /dev/null +++ b/src/soc/imgtec/danube/romstage.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/hlt.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <console/console.h> + +void main(void) +{ + void *entry; + + console_init(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, + CONFIG_CBFS_PREFIX "/ramstage"); + if (entry != (void *)-1) + stage_exit(entry); + + hlt(); +}

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New patch to review for coreboot: 8b01000 danube: prepare SOC directory for urara
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8763 -gerrit commit 8b01000bd9b5598373dd9d67953e7bf264fa7b12 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Aug 29 16:34:46 2014 -0700 danube: prepare SOC directory for urara These modules are necessary to resolve external names when building the board image. These are just skeletons for now which will be filled later. BUG=chrome-os-partner:31438 TEST=when config is enabled, emerge-urara coreboot succeeds. more extensive testing to come later Change-Id: I0fcb5d33187172ecac77041425402b33e89e8944 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 94ec79b0ab872f5c5fe7db5bef5fdabf77d6b3b6 Original-Change-Id: I69cc178976a910ebf8031ed9ac9ad67b4cc0878a Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215678 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/danube/Kconfig | 2 +- src/soc/imgtec/danube/Makefile.inc | 13 ++++++++++++- src/soc/imgtec/danube/spi.c | 35 +++++++++++++++++++++++++++++++++++ src/soc/imgtec/danube/timestamp.c | 19 +++++++++++++++++++ 4 files changed, 67 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/danube/Kconfig b/src/soc/imgtec/danube/Kconfig index df2b685..0e3c629 100644 --- a/src/soc/imgtec/danube/Kconfig +++ b/src/soc/imgtec/danube/Kconfig @@ -20,7 +20,7 @@ # config CPU_IMGTEC_DANUBE - select CPU_MIPS32R2 + select CPU_MIPS select DYNAMIC_CBMEM select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL diff --git a/src/soc/imgtec/danube/Makefile.inc b/src/soc/imgtec/danube/Makefile.inc index 74822de..d7628ed 100644 --- a/src/soc/imgtec/danube/Makefile.inc +++ b/src/soc/imgtec/danube/Makefile.inc @@ -19,14 +19,24 @@ # MA 02110-1301 USA # +# We enable CBFS_SPI_WRAPPER for Danuibe targets. +bootblock-y += spi.c +romstage-y += spi.c +ramstage-y += spi.c + ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c romstage-y += uart.c ramstage-y += uart.c endif -romstage-y += cbmem.c +bootblock-y += timestamp.c + ramstage-y += cbmem.c +ramstage-y += timestamp.c + +romstage-y += cbmem.c +romstage-y += timestamp.c # Generate the actual coreboot bootblock code $(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf @@ -38,3 +48,4 @@ $(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL) @printf " BIMGTOOL $(subst $(obj)/,,$(@))\n" $(BIMGTOOL) $< $@ $(CONFIG_BOOTBLOCK_BASE) + diff --git a/src/soc/imgtec/danube/spi.c b/src/soc/imgtec/danube/spi.c new file mode 100644 index 0000000..95bf827 --- /dev/null +++ b/src/soc/imgtec/danube/spi.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2014 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <spi-generic.h> + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +{ + return NULL; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned out_bytes, void *din, unsigned in_bytes) +{ + return 0; +} diff --git a/src/soc/imgtec/danube/timestamp.c b/src/soc/imgtec/danube/timestamp.c new file mode 100644 index 0000000..f0dc5ad --- /dev/null +++ b/src/soc/imgtec/danube/timestamp.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2014 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <timestamp.h> + +uint64_t timestamp_get(void) +{ + return 0; +}

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New patch to review for coreboot: 0998227 imgtec/danube: Add support for ImgTec Danube SoC
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8762 -gerrit commit 09982278145f2da06abeb7868be58c18523106c3 Author: Paul Burton <paul.burton(a)imgtec.com> Date: Sat Jun 14 00:08:02 2014 +0100 imgtec/danube: Add support for ImgTec Danube SoC Add build infrastructure and basic support code for the ImgTec Danube SoC. This support is sufficient to run on a simulator. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: I59e36589765bf06b075fd4850215a0ef71246bb1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 881278d7fbb8e6803bc8f6f9e84c64640b097401 Original-Change-Id: Ia7ed7288b13085db7ff37b5ad75d978b6137f958 Original-Signed-off-by: Paul Burton <paul.burton(a)imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207974 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/Makefile.inc | 1 + src/soc/Kconfig | 1 + src/soc/Makefile.inc | 1 + src/soc/imgtec/Kconfig | 1 + src/soc/imgtec/Makefile.inc | 1 + src/soc/imgtec/danube/Kconfig | 69 ++++++++++++ src/soc/imgtec/danube/Makefile.inc | 40 +++++++ src/soc/imgtec/danube/bootblock.c | 24 ++++ src/soc/imgtec/danube/cbmem.c | 30 +++++ src/soc/imgtec/danube/uart.c | 217 +++++++++++++++++++++++++++++++++++++ 10 files changed, 385 insertions(+) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 2411aeb..da0e76f 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -5,6 +5,7 @@ subdirs-y += allwinner subdirs-y += amd subdirs-y += dmp subdirs-y += armltd +subdirs-y += imgtec subdirs-y += intel subdirs-y += ti subdirs-y += via diff --git a/src/soc/Kconfig b/src/soc/Kconfig index a36bedd..43c2010 100644 --- a/src/soc/Kconfig +++ b/src/soc/Kconfig @@ -1,3 +1,4 @@ +source src/soc/imgtec/Kconfig source src/soc/intel/Kconfig source src/soc/nvidia/Kconfig source src/soc/qualcomm/Kconfig diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc index 80dd109..543e155 100644 --- a/src/soc/Makefile.inc +++ b/src/soc/Makefile.inc @@ -1,6 +1,7 @@ ################################################################################ ## Subdirectories ################################################################################ +subdirs-y += imgtec subdirs-y += intel subdirs-y += nvidia subdirs-y += qualcomm diff --git a/src/soc/imgtec/Kconfig b/src/soc/imgtec/Kconfig new file mode 100644 index 0000000..4364a94 --- /dev/null +++ b/src/soc/imgtec/Kconfig @@ -0,0 +1 @@ +source src/soc/imgtec/danube/Kconfig diff --git a/src/soc/imgtec/Makefile.inc b/src/soc/imgtec/Makefile.inc new file mode 100644 index 0000000..06ce1d2 --- /dev/null +++ b/src/soc/imgtec/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_CPU_IMGTEC_DANUBE) += danube diff --git a/src/soc/imgtec/danube/Kconfig b/src/soc/imgtec/danube/Kconfig new file mode 100644 index 0000000..df2b685 --- /dev/null +++ b/src/soc/imgtec/danube/Kconfig @@ -0,0 +1,69 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Imagination Technologies +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +config CPU_IMGTEC_DANUBE + select CPU_MIPS32R2 + select DYNAMIC_CBMEM + select HAVE_UART_MEMORY_MAPPED + select HAVE_UART_SPECIAL + bool + +if CPU_IMGTEC_DANUBE + +config BOOTBLOCK_CPU_INIT + string + default "soc/imgtec/danube/bootblock.c" + +config BOOTBLOCK_BASE + hex + default 0x9b000000 + +config CBFS_ROM_OFFSET + # Effectively the maximum size of the bootblock + hex + default 0x4000 + +config ROMSTAGE_BASE + hex + default 0x9b004000 + help + The address where romstage is supposed to be loaded, right above the + bootblock. + +config CBMEM_CONSOLE_PRERAM_BASE + hex "memory address of the CBMEM console buffer" + default 0x9b00f800 + help + Allocate 4KB to the pre-ram console buffer, we should be able to use + GRAM eventually and have a much larger buffer. + +config STACK_TOP + hex + default CBMEM_CONSOLE_PRERAM_BASE + +config STACK_BOTTOM + hex + default 0x9b00f000 + help + Allocating 12KB for the stack, should be able to have more once GRAM + is available. + +endif diff --git a/src/soc/imgtec/danube/Makefile.inc b/src/soc/imgtec/danube/Makefile.inc new file mode 100644 index 0000000..74822de --- /dev/null +++ b/src/soc/imgtec/danube/Makefile.inc @@ -0,0 +1,40 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Imagination Technologies +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +romstage-y += uart.c +ramstage-y += uart.c +endif + +romstage-y += cbmem.c +ramstage-y += cbmem.c + +# Generate the actual coreboot bootblock code +$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY_bootblock) -O binary $< $@.tmp + @mv $@.tmp $@ + +# Create a complete bootblock which will start up the system +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL) + @printf " BIMGTOOL $(subst $(obj)/,,$(@))\n" + $(BIMGTOOL) $< $@ $(CONFIG_BOOTBLOCK_BASE) diff --git a/src/soc/imgtec/danube/bootblock.c b/src/soc/imgtec/danube/bootblock.c new file mode 100644 index 0000000..f6cc76b --- /dev/null +++ b/src/soc/imgtec/danube/bootblock.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +static void bootblock_cpu_init(void) +{ +} diff --git a/src/soc/imgtec/danube/cbmem.c b/src/soc/imgtec/danube/cbmem.c new file mode 100644 index 0000000..062f560 --- /dev/null +++ b/src/soc/imgtec/danube/cbmem.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <stdlib.h> + +void *cbmem_top(void) +{ + uintptr_t top = MIN(CONFIG_DRAM_SIZE_MB, 256) << 20; + return (void *)(top + CONFIG_SYS_SDRAM_BASE); +} + diff --git a/src/soc/imgtec/danube/uart.c b/src/soc/imgtec/danube/uart.c new file mode 100644 index 0000000..855fce5 --- /dev/null +++ b/src/soc/imgtec/danube/uart.c @@ -0,0 +1,217 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <delay.h> +#include <uart.h> +#include <uart8250.h> + +/* Should support 8250, 16450, 16550, 16550A type UARTs */ + +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) +#define UART_SHIFT 2 + +#define GEN_ACCESSOR(name, idx) \ +static inline uint8_t read_##name(unsigned base_port) \ +{ \ + return read8(base_port + (idx << UART_SHIFT)); \ +} \ + \ +static inline void write_##name(unsigned base_port, uint8_t val) \ +{ \ + write8(base_port + (idx << UART_SHIFT), val); \ +} + +GEN_ACCESSOR(rbr, UART8250_RBR) +GEN_ACCESSOR(tbr, UART8250_TBR) +GEN_ACCESSOR(ier, UART8250_IER) +GEN_ACCESSOR(fcr, UART8250_FCR) +GEN_ACCESSOR(lcr, UART8250_LCR) +GEN_ACCESSOR(mcr, UART8250_MCR) +GEN_ACCESSOR(lsr, UART8250_LSR) +GEN_ACCESSOR(dll, UART8250_DLL) +GEN_ACCESSOR(dlm, UART8250_DLM) + +static int uart8250_mem_can_tx_byte(unsigned base_port) +{ + return read_lsr(base_port) & UART8250_LSR_THRE; +} + +static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_mem_can_tx_byte(base_port)) + udelay(1); + write_tbr(base_port, data); +} + +static void uart8250_mem_tx_flush(unsigned base_port) +{ + unsigned long int i = FIFO_TIMEOUT; + while (i-- && !(read_lsr(base_port) & UART8250_LSR_TEMT)) + udelay(1); +} + +static int uart8250_mem_can_rx_byte(unsigned base_port) +{ + return read_lsr(base_port) & UART8250_LSR_DR; +} + +static unsigned char uart8250_mem_rx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_mem_can_rx_byte(base_port)) + udelay(1); + if (i) + return read_rbr(base_port); + else + return 0x0; +} + +static void uart8250_mem_init(unsigned base_port, unsigned divisor) +{ + /* Disable interrupts */ + write_ier(base_port, 0x0); + /* Enable FIFOs */ + write_fcr(base_port, UART8250_FCR_FIFO_EN); + + /* Assert DTR and RTS so the other end is happy */ + write_mcr(base_port, UART8250_MCR_DTR | UART8250_MCR_RTS); + + /* DLAB on */ + write_lcr(base_port, UART8250_LCR_DLAB | CONFIG_TTYS0_LCS); + + write_dll(base_port, divisor & 0xFF); + write_dlm(base_port, (divisor >> 8) & 0xFF); + + /* Set to 3 for 8N1 */ + write_lcr(base_port, CONFIG_TTYS0_LCS); +} + +static unsigned int uart_platform_refclk(void) +{ + /* TODO: this is entirely arbitrary */ + return 1000000; +} + +static unsigned int uart_platform_base(int idx) +{ + switch (idx) { + case 0: + return 0xb8101400; + + case 1: + return 0xb8101500; + + default: + return 0x0; + } +} + +/* Calculate divisor. Do not floor but round to nearest integer. */ +static unsigned int uart_baudrate_divisor(unsigned int baudrate, + unsigned int refclk, unsigned int oversample) +{ + return (1 + (2 * refclk) / (baudrate * oversample)) / 2; +} + +static void danube_uart_init(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + + unsigned int div; + div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD, + uart_platform_refclk(), 16); + uart8250_mem_init(base, div); +} + +static void danube_uart_tx_byte(unsigned char data) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_byte(base, data); +} + +static unsigned char danube_uart_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0xff; + return uart8250_mem_rx_byte(base); +} + +static void danube_uart_tx_flush(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_flush(base); +} + +#if !defined(__PRE_RAM__) + +static const struct console_driver danube_uart_console __console = { + .init = danube_uart_init, + .tx_byte = danube_uart_tx_byte, + .tx_flush = danube_uart_tx_flush, + .rx_byte = danube_uart_rx_byte, +}; + +uint32_t uartmem_getbaseaddr(void) +{ + return uart_platform_base(0); +} + +#else /* __PRE_RAM__ */ + +void uart_init(void) +{ + danube_uart_init(); +} + +void uart_tx_byte(unsigned char data) +{ + danube_uart_tx_byte(data); +} + +unsigned char uart_rx_byte(void) +{ + return danube_uart_rx_byte(); +} + +void uart_tx_flush(void) +{ + danube_uart_tx_flush(); +} + +#endif /* __PRE_RAM__ */

1 0

New patch to review for coreboot: e351353 mips: no need in architecture specific implementation of do_printk
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8761 -gerrit commit e351353122462031eac52cc58d339f2b87ee7b9a Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 2 10:13:15 2014 -0700 mips: no need in architecture specific implementation of do_printk With the proper configuration flags enabled, do_printk is available from src/console, no need to define it elsewhere. BUG=chrome-os-partner:31438 TEST=with upcoming patches, the urara board coreboot builds fine Change-Id: I82071b4ca1686639c0bd39c63a06b61cb5bf5571 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 69c655537c50274a61cf123b7fc387ec60dd29c7 Original-Change-Id: Ib1e3e5750cdc1adc509b4580a4f24d3ff3b105ee Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215862 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/mips/early_console.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/src/arch/mips/early_console.c b/src/arch/mips/early_console.c index 8f3d907..c699abc 100644 --- a/src/arch/mips/early_console.c +++ b/src/arch/mips/early_console.c @@ -36,20 +36,3 @@ void console_tx_flush(void) uart_tx_flush(); #endif } - -int do_printk(int msg_level, const char *fmt, ...) -{ - va_list args; - int i; - - if (msg_level > console_loglevel) - return 0; - - va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); - va_end(args); - - console_tx_flush(); - - return i; -}

1 0

New patch to review for coreboot: f7278f3 arch/mips: Add base MIPS architecture support
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8760 -gerrit commit f7278f3841cc1a33b5563bb7f57bdb2c3dc7f37d Author: Paul Burton <paul.burton(a)imgtec.com> Date: Sat Jun 14 00:00:10 2014 +0100 arch/mips: Add base MIPS architecture support Add the build infrastructure and basic architectural support required to build for targets using the MIPS architecture. This is sufficient to run on a simulator, but will require the addition of some cache maintenance and timer setup in order to run on real hardware. BUG=chrome-os-partner:31438, chromium:409082 TEST=none yet Change-Id: I027902d8408e419b626d0aab7768bc564bd49047 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fcc0d934d7223922c878b1f87021cb5c2d7e6f21 Original-Change-Id: If4f99554463bd3760fc142477440326fd16c67cc Original-Signed-off-by: Paul Burton <paul.burton(a)imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207972 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 3 +- src/Kconfig | 5 + src/arch/mips/Kconfig | 37 +++++++ src/arch/mips/Makefile.inc | 148 +++++++++++++++++++++++++++ src/arch/mips/boot.c | 27 +++++ src/arch/mips/bootblock.inc | 44 ++++++++ src/arch/mips/bootblock.ld | 57 +++++++++++ src/arch/mips/bootblock_simple.c | 45 ++++++++ src/arch/mips/early_console.c | 55 ++++++++++ src/arch/mips/include/arch/byteorder.h | 48 +++++++++ src/arch/mips/include/arch/cache.h | 23 +++++ src/arch/mips/include/arch/cpu.h | 43 ++++++++ src/arch/mips/include/arch/early_variables.h | 30 ++++++ src/arch/mips/include/arch/exception.h | 25 +++++ src/arch/mips/include/arch/hlt.h | 29 ++++++ src/arch/mips/include/arch/io.h | 125 ++++++++++++++++++++++ src/arch/mips/include/arch/pci_ops.h | 30 ++++++ src/arch/mips/include/arch/stages.h | 29 ++++++ src/arch/mips/include/arch/types.h | 67 ++++++++++++ src/arch/mips/include/bootblock_common.h | 30 ++++++ src/arch/mips/include/stdint.h | 99 ++++++++++++++++++ src/arch/mips/ramstage.ld | 121 ++++++++++++++++++++++ src/arch/mips/romstage.ld | 72 +++++++++++++ src/arch/mips/stages.c | 35 +++++++ src/arch/mips/tables.c | 67 ++++++++++++ src/arch/mips/timer.c | 31 ++++++ src/cpu/Kconfig | 1 + src/cpu/mips/Kconfig | 36 +++++++ toolchain.inc | 2 +- 29 files changed, 1362 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index cc696e4..41c5778 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -70,7 +70,8 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs subdirs-y := src/lib src/console src/device src/ec src/southbridge src/soc subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool -subdirs-y += src/arch/arm src/arch/arm64 src/arch/x86 src/arch/riscv +subdirs-y += src/arch/arm src/arch/arm64 src/arch/mips src/arch/riscv +subdirs-y += src/arch/x86 subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += site-local diff --git a/src/Kconfig b/src/Kconfig index 6cabc70..d0db5e7 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -277,10 +277,15 @@ config ARCH_RISCV default n select ANY_TOOLCHAIN +config ARCH_MIPS + bool + default n + source src/arch/x86/Kconfig source src/arch/arm/Kconfig source src/arch/arm64/Kconfig source src/arch/riscv/Kconfig +source src/arch/mips/Kconfig source src/vendorcode/Kconfig diff --git a/src/arch/mips/Kconfig b/src/arch/mips/Kconfig new file mode 100644 index 0000000..3d8e2c6 --- /dev/null +++ b/src/arch/mips/Kconfig @@ -0,0 +1,37 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Imagination Technologies +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +menu "Architecture (mips)" + +config ARCH_BOOTBLOCK_MIPS + bool + default n + select ARCH_MIPS + +config ARCH_ROMSTAGE_MIPS + bool + default n + +config ARCH_RAMSTAGE_MIPS + bool + default n + +endmenu diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc new file mode 100644 index 0000000..956f2d5 --- /dev/null +++ b/src/arch/mips/Makefile.inc @@ -0,0 +1,148 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Imagination Technologies +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +############################################################################### +# MIPS specific options +############################################################################### + +ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y) +CBFSTOOL_PRE1_OPTS = -m mips -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET) +CBFSTOOL_PRE_OPTS = -b 0 +endif + +############################################################################### +# bootblock +############################################################################### + +ifeq ($(CONFIG_ARCH_BOOTBLOCK_MIPS),y) + +bootblock-y += boot.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c +bootblock-y += stages.c +bootblock-y += timer.c +bootblock-y += ../../lib/memcpy.c +bootblock-y += ../../lib/memmove.c +bootblock-y += ../../lib/memset.c + +bootblock_lds = $(src)/arch/mips/bootblock.ld + +bootblock_inc += $(src)/arch/mips/bootblock.inc +bootblock_inc += $(objgenerated)/bootblock.inc + +# Much of the assembly code is generated by the compiler, and may contain +# terms which the preprocessor will happily go on to replace. For example +# "mips" would be replaced with "1". Clear all the built in definitions to +# prevent that. +bootblock-S-ccopts += -undef + +$(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions + @printf " GEN $(subst $(obj)/,,$(@))\n" + printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ + +$(objgenerated)/bootblock_inc.S: $$(bootblock_inc) + @printf " GEN $(subst $(obj)/,,$(@))\n" + printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ + +$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_bootblock) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm + +$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_bootblock) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E \ + -I$(src)/include -I$(src)/arch/mips/include -I$(obj) \ + -include $(obj)/build.h -include $(obj)/config.h -I. \ + -I$(src) $< -o $@ + +$(objgenerated)/bootblock.inc: $(src)/arch/mips/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(obj)/config.h + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_bootblock) $(bootblock-c-ccopts) $(CFLAGS_bootblock) -MM \ + -MT$(objgenerated)/bootblock.inc \ + $< > $(objgenerated)/bootblock.inc.d + $(CC_bootblock) $(bootblock-c-ccopts) -c -S $(CFLAGS_bootblock) -I. $< -o $@ + +$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(obj)/config.h + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(CC_bootblock) $(CFLAGS_bootblock) -nostdlib -Wl,--gc-sections -nostartfiles -include $(obj)/config.h -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(objgenerated)/bootblock.o $(bootblock-objs) -Wl,--end-group + +endif # CONFIG_ARCH_BOOTBLOCK_MIPS + +############################################################################### +# romstage +############################################################################### + +ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y) + +romstage-y += boot.c +romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c +romstage-y += stages.c +romstage-y += timer.c +romstage-y += ../../lib/memcpy.c +romstage-y += ../../lib/memmove.c +romstage-y += ../../lib/memset.c + +romstage-lds = $(src)/arch/mips/romstage.ld + +$(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(CC_romstage) -nostdlib -Wl,--gc-sections -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage.ld -Wl,--start-group $(romstage-objs) -Wl,--end-group + +$(objgenerated)/romstage.ld: $$(romstage-lds) $(obj)/ldoptions + @printf " GEN $(subst $(obj)/,,$(@))\n" + rm -f $@ + printf '$(foreach ldscript,ldoptions $(romstage-lds),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp + mv $@.tmp $@ + +endif # CONFIG_ARCH_ROMSTAGE_MIPS + +############################################################################### +# ramstage +############################################################################### + +ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPS),y) + +ramstage-y += ashldi3.c +ramstage-y += boot.c +ramstage-y += stages.c +ramstage-y += tables.c +ramstage-y += timer.c +ramstage-y += ../../lib/memcpy.c +ramstage-y += ../../lib/memmove.c +ramstage-y += ../../lib/memset.c +ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) + +ramstage-lds = $(src)/arch/mips/ramstage.ld + +$(objgenerated)/ramstage.ld: $$(ramstage-lds) $(obj)/ldoptions + @printf " GEN $(subst $(obj)/,,$(@))\n" + rm -f $@ + printf '$(foreach ldscript,ldoptions $(ramstage-lds),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp + mv $@.tmp $@ + +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(objgenerated)/ramstage.ld + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_ramstage) -nostdlib -Wl,--gc-sections -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/ramstage.ld $< + +$(objgenerated)/ramstage.o: $$(ramstage-objs) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--start-group $(ramstage-objs) -Wl,--end-group + +endif # CONFIG_ARCH_RAMSTAGE_MIPS diff --git a/src/arch/mips/boot.c b/src/arch/mips/boot.c new file mode 100644 index 0000000..d322e99 --- /dev/null +++ b/src/arch/mips/boot.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/stages.h> + +void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) +{ + printk(BIOS_SPEW, "entry = %p\n", entry); + stage_exit(entry); +} diff --git a/src/arch/mips/bootblock.inc b/src/arch/mips/bootblock.inc new file mode 100644 index 0000000..76a10cf --- /dev/null +++ b/src/arch/mips/bootblock.inc @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +.set noreorder /* Prevent assembler from "optimizing" this code. */ + +.section ".start", "ax", %progbits +.globl _start +_start: + /* Set the stack pointer */ + li $sp, CONFIG_STACK_TOP + + /* + * Initialise the stack to a known value, used later to check for + * overflow. + */ + li $t0, CONFIG_STACK_BOTTOM + addi $t1, $sp, -4 + li $t2, 0xdeadbeef +1: sw $t2, 0($t0) + bne $t0, $t1, 1b + addi $t0, $t0, 4 + + /* Run main */ + b main + + /* Should never return from main. */ +2: + b 2b diff --git a/src/arch/mips/bootblock.ld b/src/arch/mips/bootblock.ld new file mode 100644 index 0000000..3721f85 --- /dev/null +++ b/src/arch/mips/bootblock.ld @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +OUTPUT_ARCH(mips) + +ENTRY(_start) + +PHDRS +{ + to_load PT_LOAD; +} + +preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + +SECTIONS +{ + . = CONFIG_BOOTBLOCK_BASE; + + /* This section might be better named .setup */ + .rom : { + _rom = .; + *(.start); + *(.id); + *(.text); + *(.text.*); + *(.rom.text); + *(.rom.data); + *(.rom.data.*); + *(.rodata.*); + _erom = .; + } : to_load = 0xff + + /DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + } +} diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c new file mode 100644 index 0000000..49ea24d --- /dev/null +++ b/src/arch/mips/bootblock_simple.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/hlt.h> +#include <arch/stages.h> +#include <bootblock_common.h> +#include <cbfs.h> +#include <console/console.h> + +void main(void) +{ + const char *stage_name = "fallback/romstage"; + void *entry; + + bootblock_cpu_init(); + bootblock_mainboard_init(); + +#if CONFIG_BOOTBLOCK_CONSOLE + console_init(); +#endif + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); + if (entry != (void *)-1) + stage_exit(entry); + + hlt(); +} diff --git a/src/arch/mips/early_console.c b/src/arch/mips/early_console.c new file mode 100644 index 0000000..8f3d907 --- /dev/null +++ b/src/arch/mips/early_console.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/vtxprintf.h> + +void console_tx_byte(unsigned char byte) +{ + if (byte == '\n') + console_tx_byte('\r'); + +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_byte(byte); +#endif +} + +void console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_flush(); +#endif +} + +int do_printk(int msg_level, const char *fmt, ...) +{ + va_list args; + int i; + + if (msg_level > console_loglevel) + return 0; + + va_start(args, fmt); + i = vtxprintf(console_tx_byte, fmt, args); + va_end(args); + + console_tx_flush(); + + return i; +} diff --git a/src/arch/mips/include/arch/byteorder.h b/src/arch/mips/include/arch/byteorder.h new file mode 100644 index 0000000..90c375e --- /dev/null +++ b/src/arch/mips/include/arch/byteorder.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MIPS_ARCH_BYTEORDER_H +#define __MIPS_ARCH_BYTEORDER_H + +#include <stdint.h> +#include <swab.h> + +#ifndef __ORDER_LITTLE_ENDIAN__ +#errror "What endian are you!?" +#endif + +#define cpu_to_le64(x) ((uint64_t)(x)) +#define le64_to_cpu(x) ((uint64_t)(x)) +#define cpu_to_le32(x) ((uint32_t)(x)) +#define le32_to_cpu(x) ((uint32_t)(x)) +#define cpu_to_le16(x) ((uint16_t)(x)) +#define le16_to_cpu(x) ((uint16_t)(x)) +#define cpu_to_be64(x) swab64(x) +#define be64_to_cpu(x) swab64(x) +#define cpu_to_be32(x) swab32((x)) +#define be32_to_cpu(x) swab32((x)) +#define cpu_to_be16(x) swab16((x)) +#define be16_to_cpu(x) swab16((x)) + +#define ntohll(x) be64_to_cpu(x) +#define htonll(x) cpu_to_be64(x) +#define ntohl(x) be32_to_cpu(x) +#define htonl(x) cpu_to_be32(x) + +#endif /* __MIPS_ARCH_BYTEORDER_H */ diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h new file mode 100644 index 0000000..a985741 --- /dev/null +++ b/src/arch/mips/include/arch/cache.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MIPS_ARCH_CACHE_H +#define __MIPS_ARCH_CACHE_H + +#endif /* __MIPS_ARCH_CACHE_H */ diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h new file mode 100644 index 0000000..0ac9f31 --- /dev/null +++ b/src/arch/mips/include/arch/cpu.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MIPS_ARCH_CPU_H +#define __MIPS_ARCH_CPU_H + +#define asmlinkage + +#ifndef __PRE_RAM__ + +#include <device/device.h> + +struct cpu_driver { + struct device_operations *ops; + struct cpu_device_id *id_table; +}; + +struct thread; + +struct cpu_info { + device_t cpu; + unsigned long index; +}; + +#endif /* !__PRE_RAM__ */ + +#endif /* __MIPS_ARCH_CPU_H */ diff --git a/src/arch/mips/include/arch/early_variables.h b/src/arch/mips/include/arch/early_variables.h new file mode 100644 index 0000000..a81a6b4 --- /dev/null +++ b/src/arch/mips/include/arch/early_variables.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MIPS_ARCH_EARLY_VARIABLES_H +#define __MIPS_ARCH_EARLY_VARIABLES_H + +#define CAR_GLOBAL +#define CAR_MIGRATE(migrate_fn_) + +static inline void car_migrate_variables(void) {} +#define car_get_var(var) (var) +#define car_set_var(var, val) { (var) = (val); } + +#endif /* __MIPS_ARCH_EARLY_VARIABLES_H */ diff --git a/src/arch/mips/include/arch/exception.h b/src/arch/mips/include/arch/exception.h new file mode 100644 index 0000000..ff92728 --- /dev/null +++ b/src/arch/mips/include/arch/exception.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MIPS_ARCH_EXCEPTION_H +#define __MIPS_ARCH_EXCEPTION_H + +static inline void exception_init(void) {} + +#endif /* __MIPS_ARCH_EXCEPTION_H */ diff --git a/src/arch/mips/include/arch/hlt.h b/src/arch/mips/include/arch/hlt.h new file mode 100644 index 0000000..851de56 --- /dev/null +++ b/src/arch/mips/include/arch/hlt.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MIPS_ARCH_HLT_H +#define __MIPS_ARCH_HLT_H + +static inline __attribute__((always_inline)) void hlt(void) +{ + for (;;) + ; +} + +#endif /* __MIPS_ARCH_HLT_H */ diff --git a/src/arch/mips/include/arch/io.h b/src/arch/mips/include/arch/io.h new file mode 100644 index 0000000..d034b09 --- /dev/null +++ b/src/arch/mips/include/arch/io.h @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * Based on arch/armv7/include/arch/io.h: + * Copyright 2013 Google Inc. + * Copyright (C) 1996-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MIPS_ARCH_IO_H +#define __MIPS_ARCH_IO_H + +#include <types.h> +#include <arch/cache.h> +#include <arch/byteorder.h> + +static inline uint8_t read8(unsigned long addr) +{ + asm("sync"); + return *(volatile uint8_t *)addr; +} + +static inline uint16_t read16(unsigned long addr) +{ + asm("sync"); + return *(volatile uint16_t *)addr; +} + +static inline uint32_t read32(unsigned long addr) +{ + asm("sync"); + return *(volatile uint32_t *)addr; +} + +static inline void write8(unsigned long addr, uint8_t val) +{ + asm("sync"); + *(volatile uint8_t *)addr = val; + asm("sync"); +} + +static inline void write16(unsigned long addr, uint16_t val) +{ + asm("sync"); + *(volatile uint16_t *)addr = val; + asm("sync"); +} + +static inline void write32(unsigned long addr, uint32_t val) +{ + asm("sync"); + *(volatile uint32_t *)addr = val; + asm("sync"); +} + +/* + * Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define out_arch(type, endian, a, v) write##type(cpu_to_##endian(v), a) +#define in_arch(type, endian, a) endian##_to_cpu(read##type(a)) + +#define out_le32(a, v) out_arch(l, le32, a, v) +#define out_le16(a, v) out_arch(w, le16, a, v) + +#define in_le32(a) in_arch(l, le32, a) +#define in_le16(a) in_arch(w, le16, a) + +#define out_be32(a, v) out_arch(l, be32, a, v) +#define out_be16(a, v) out_arch(w, be16, a, v) + +#define in_be32(a) in_arch(l, be32, a) +#define in_be16(a) in_arch(w, be16, a) + +#define out_8(a, v) writeb(v, a) +#define in_8(a) readb(a) + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + +#endif /* __MIPS_ARCH_IO_H */ diff --git a/src/arch/mips/include/arch/pci_ops.h b/src/arch/mips/include/arch/pci_ops.h new file mode 100644 index 0000000..1b3f074 --- /dev/null +++ b/src/arch/mips/include/arch/pci_ops.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ARCH_MIPS_PCI_OPS_H +#define ARCH_MIPS_PCI_OPS_H + +#include <stddef.h> + +static inline const struct pci_bus_operations *pci_config_default(void) +{ + return NULL; +} + +#endif diff --git a/src/arch/mips/include/arch/stages.h b/src/arch/mips/include/arch/stages.h new file mode 100644 index 0000000..b95ad1d --- /dev/null +++ b/src/arch/mips/include/arch/stages.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MIPS_ARCH_STAGES_H +#define __MIPS_ARCH_STAGES_H + +extern void main(void); + +void stage_entry(void); +void stage_exit(void *); +void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); + +#endif /* __MIPS_ARCH_STAGES_H */ diff --git a/src/arch/mips/include/arch/types.h b/src/arch/mips/include/arch/types.h new file mode 100644 index 0000000..c3eae24 --- /dev/null +++ b/src/arch/mips/include/arch/types.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * Based on src/arch/armv7/include/arch/types.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MIPS_ARCH_TYPES_H +#define __MIPS_ARCH_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + +#endif /* __MIPS_ARCH_TYPES_H */ diff --git a/src/arch/mips/include/bootblock_common.h b/src/arch/mips/include/bootblock_common.h new file mode 100644 index 0000000..e1960ba --- /dev/null +++ b/src/arch/mips/include/bootblock_common.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifdef CONFIG_BOOTBLOCK_CPU_INIT +#include CONFIG_BOOTBLOCK_CPU_INIT +#endif + +#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT +#include CONFIG_BOOTBLOCK_MAINBOARD_INIT +#else +static void bootblock_mainboard_init(void) +{ +} +#endif diff --git a/src/arch/mips/include/stdint.h b/src/arch/mips/include/stdint.h new file mode 100644 index 0000000..5c21fe6 --- /dev/null +++ b/src/arch/mips/include/stdint.h @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Based on src/arch/armv7/include/stdint.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MIPS_STDINT_H +#define __MIPS_STDINT_H + +#if defined(__GNUC__) +#define __HAVE_LONG_LONG__ 1 +#else +#define __HAVE_LONG_LONG__ 0 +#endif + +/* Exact integral types */ +typedef unsigned char uint8_t; +typedef signed char int8_t; + +typedef unsigned short uint16_t; +typedef signed short int16_t; + +typedef unsigned int uint32_t; +typedef signed int int32_t; + +#if __HAVE_LONG_LONG__ +typedef unsigned long long uint64_t; +typedef signed long long int64_t; +#endif + +/* Small types */ +typedef unsigned char uint_least8_t; +typedef signed char int_least8_t; + +typedef unsigned short uint_least16_t; +typedef signed short int_least16_t; + +typedef unsigned int uint_least32_t; +typedef signed int int_least32_t; + +#if __HAVE_LONG_LONG__ +typedef unsigned long long uint_least64_t; +typedef signed long long int_least64_t; +#endif + +/* Fast Types */ +typedef unsigned char uint_fast8_t; +typedef signed char int_fast8_t; + +typedef unsigned int uint_fast16_t; +typedef signed int int_fast16_t; + +typedef unsigned int uint_fast32_t; +typedef signed int int_fast32_t; + +#if __HAVE_LONG_LONG__ +typedef unsigned long long uint_fast64_t; +typedef signed long long int_fast64_t; +#endif + +/* Types for `void *' pointers. */ +typedef int intptr_t; +typedef unsigned int uintptr_t; + +/* Largest integral types */ +#if __HAVE_LONG_LONG__ +typedef long long int intmax_t; +typedef unsigned long long uintmax_t; +#else +typedef long int intmax_t; +typedef unsigned long int uintmax_t; +#endif + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +#if __HAVE_LONG_LONG__ +typedef uint64_t u64; +#endif +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; + +#undef __HAVE_LONG_LONG__ + +#endif /* __MIPS_STDINT_H */ diff --git a/src/arch/mips/ramstage.ld b/src/arch/mips/ramstage.ld new file mode 100644 index 0000000..4052444 --- /dev/null +++ b/src/arch/mips/ramstage.ld @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * Based on src/arch/arm/ramstage.ld: + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +OUTPUT_ARCH(mips) + +ENTRY(stage_entry) + +PHDRS +{ + to_load PT_LOAD; +} + +SECTIONS +{ + . = CONFIG_SYS_SDRAM_BASE; + + .text : { + _text = .; + _start = .; + *(.text.stage_entry.mips); + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; + } : to_load + + .ctors : { + . = ALIGN(0x100); + __CTOR_LIST__ = .; + *(.ctors); + LONG(0); + __CTOR_END__ = .; + } + + .rodata : { + _rodata = .; + . = ALIGN(4); + console_drivers = .; + KEEP(*(.rodata.console_drivers)); + econsole_drivers = . ; + . = ALIGN(4); + pci_drivers = . ; + KEEP(*(.rodata.pci_driver)); + epci_drivers = . ; + cpu_drivers = . ; + KEEP(*(.rodata.cpu_driver)); + ecpu_drivers = . ; + _bs_init_begin = .; + KEEP(*(.bs_init)); + _bs_init_end = .; + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + _erodata = .; + } + + .data : { + _data = .; + *(.data) + _edata = .; + } + + /* bss will be cleared by cbfs_load_stage */ + _bss = .; + .bss . : { + *(.bss) + *(.sbss) + *(COMMON) + } + _ebss = .; + _end = .; + + /* + * coreboot from the perspective of the loader really "ends" + * here. Only symbols are placed after this. + */ + + _heap = .; + _eheap = . + CONFIG_HEAP_SIZE; + + _stack = CONFIG_STACK_BOTTOM; + _estack = CONFIG_STACK_TOP; + + /* + * The ram segment. This includes all memory used by the memory + * resident copy of coreboot, except the tables that are produced on + * the fly, but including stack and heap. + */ + _ram_seg = _text; + _eram_seg = _eheap; + + /* Discard the sections we don't need/want */ + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} diff --git a/src/arch/mips/romstage.ld b/src/arch/mips/romstage.ld new file mode 100644 index 0000000..8964285 --- /dev/null +++ b/src/arch/mips/romstage.ld @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +OUTPUT_ARCH(mips) + +ENTRY(stage_entry) + +PHDRS +{ + to_load PT_LOAD; +} + +preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + +SECTIONS +{ + . = CONFIG_ROMSTAGE_BASE; + + .romtext . : { + _rom = .; + _start = .; + *(.text.stage_entry.mips); + *(.text.startup); + *(.text); + } : to_load + + .romdata . : { + *(.rodata); + *(.data); + . = ALIGN(16); + _erom = .; + } + + /* bss will be cleared by cbfs_load_stage */ + .bss . : { + . = ALIGN(8); + _bss = .; + *(.bss) + *(.sbss) + *(COMMON) + } + + _ebss = .; + _end = .; + + /* Discard the sections we don't need/want */ + /DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.eh_frame); + } +} diff --git a/src/arch/mips/stages.c b/src/arch/mips/stages.c new file mode 100644 index 0000000..ae10594 --- /dev/null +++ b/src/arch/mips/stages.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/stages.h> +#include <arch/cache.h> + + __attribute__((section(".text.stage_entry.mips"))) void stage_entry(void) +{ + main(); +} + +void stage_exit(void *addr) +{ + void (*doit)(void) = addr; + + /* TODO: synci */ + + doit(); +} diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c new file mode 100644 index 0000000..858fa79 --- /dev/null +++ b/src/arch/mips/tables.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Based on src/arch/armv7/tables.c: + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2005 Steve Magnani + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <boot/tables.h> +#include <boot/coreboot_tables.h> +#include <string.h> +#include <cbmem.h> +#include <lib.h> + +#define MAX_COREBOOT_TABLE_SIZE (8 * 1024) + +void cbmem_arch_init(void) +{ +} + +struct lb_memory *write_tables(void) +{ + unsigned long table_pointer, new_table_pointer; + + post_code(0x9d); + + table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, + MAX_COREBOOT_TABLE_SIZE); + if (!table_pointer) { + printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); + return NULL; + } + + new_table_pointer = write_coreboot_table(0UL, 0UL, table_pointer, + table_pointer); + + if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) + printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", + new_table_pointer - table_pointer, + MAX_COREBOOT_TABLE_SIZE); + + printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", + new_table_pointer - table_pointer); + + post_code(0x9e); + + /* Print CBMEM sections */ + cbmem_list(); + + return get_lb_mem(); +} diff --git a/src/arch/mips/timer.c b/src/arch/mips/timer.c new file mode 100644 index 0000000..c38601d --- /dev/null +++ b/src/arch/mips/timer.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <timer.h> + +void init_timer(void) +{ + /* TODO */ +} + +void udelay(unsigned usec) +{ + /* TODO */ +} diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 8a6e9d8..f6f0647 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -9,6 +9,7 @@ source src/cpu/ti/Kconfig source src/cpu/amd/Kconfig source src/cpu/dmp/Kconfig source src/cpu/intel/Kconfig +source src/cpu/mips/Kconfig source src/cpu/via/Kconfig source src/cpu/qemu-x86/Kconfig source src/cpu/x86/Kconfig diff --git a/src/cpu/mips/Kconfig b/src/cpu/mips/Kconfig new file mode 100644 index 0000000..4507977 --- /dev/null +++ b/src/cpu/mips/Kconfig @@ -0,0 +1,36 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Imagination Technologies +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +config CPU_MIPS + bool + select ARCH_BOOTBLOCK_MIPS + select ARCH_ROMSTAGE_MIPS + select ARCH_RAMSTAGE_MIPS + +config BOOTBLOCK_ROM_OFFSET + hex + depends on CPU_MIPS + default 0x00 + +config CBFS_HEADER_ROM_OFFSET + hex + depends on CPU_MIPS + default 0x10 diff --git a/toolchain.inc b/toolchain.inc index 8241e25..83f478b 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -64,7 +64,7 @@ CFLAGS_arm := -mno-unaligned-access -ffunction-sections -fdata-sections CFLAGS_arm64 := -ffunction-sections -fdata-sections -CFLAGS_mipsel := -mips32r2 -G 0 +CFLAGS_mipsel := -mips32r2 -G 0 -ffunction-sections -fdata-sections CFLAGS_x86_32 := -ffunction-sections -fdata-sections

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New patch to review for coreboot: adace79 Linux copy of mips/ashldi3.c
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8759 -gerrit commit adace79fac25e1276fb340916d56cd44d00757ef Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Aug 25 17:45:57 2014 -0700 Linux copy of mips/ashldi3.c As MIPS toolchain does not provide adequate support for 64 bit division and shift operations, the missing functions are required to be provided by the user. This patch brings in the Linux implementation of the 64 bit arithmetic shift borrowed from arch/mips/lib/ashldi3.c. BUG=chromium:406038 TEST=With the upcoming patches coreboot successfully builds for MIPS targets in chroot (coming later). Change-Id: I2168f69352a9b9e3c5d197489f701a442e65703c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8ec616161be8ad3aeb6494e7121615e3329b414d Original-Change-Id: Ia1ccb29d4c9f3c95e04e06f6af7ce8a00e2e7455 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214156 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/mips/ashldi3.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/src/arch/mips/ashldi3.c b/src/arch/mips/ashldi3.c new file mode 100644 index 0000000..caa69fa --- /dev/null +++ b/src/arch/mips/ashldi3.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google, Inc. + * + * Based on linux arch/mips/lib/ashldi3.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ORDER_LITTLE_ENDIAN__ +#errror "What endian are you!?" +#endif + +typedef unsigned word_type; +long long __ashldi3(long long u, word_type b); + +struct DWstruct { + int low, high; +}; +typedef union { + struct DWstruct s; + long long ll; +} DWunion; + +long long __ashldi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.low = 0; + w.s.high = (unsigned int) uu.s.low << -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.low >> bm; + + w.s.low = (unsigned int) uu.s.low << b; + w.s.high = ((unsigned int) uu.s.high << b) | carries; + } + + return w.ll; +} +

1 0

New patch to review for coreboot: 9fe6f67 libpayload: cbfs: Fix ram_media map() error return value
by Patrick Georgi 19 Mar '15

19 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8758 -gerrit commit 9fe6f672b4d89774ac6fb5d31b375f0a45bafbe3 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Jan 6 21:34:19 2015 -0800 libpayload: cbfs: Fix ram_media map() error return value The correct return value for errors on a cbfs_media->map() call is CBFS_MEDIA_INVALID_MAP_ADDRESS, not NULL. Not sure if that's the best choice (since 0xffffffff is probably a more likely valid address than 0 there), but that's what the upper layers expect right now. BRANCH=veyron BUG=None TEST=Press CTRL+L with an RW_LEGACY section filled with 0xff. Observe how cbfs_get_header() returns failure without doing a bunch of NULL pointer accesses first (not that those have any visible effect on Veyron, but that's another problem...) Change-Id: I3d012fc9af9da6e01159990a6bdd62c38fc22329 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3a609e17bb9b0ef4d3a833f72fa4fbfd8e8cb0ab Original-Change-Id: I0793434116a8c568e19fe0dee24f13942fc50f25 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238991 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- payloads/libpayload/libcbfs/ram_media.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/libcbfs/ram_media.c b/payloads/libpayload/libcbfs/ram_media.c index 3d9abf0..d5469f6 100644 --- a/payloads/libpayload/libcbfs/ram_media.c +++ b/payloads/libpayload/libcbfs/ram_media.c @@ -51,7 +51,7 @@ static void *ram_map(struct cbfs_media *media, size_t offset, size_t count) { if (offset + count > m->size) { printf("ERROR: ram_map: request out of range (0x%zx+0x%zx)\n", offset, count); - return NULL; + return CBFS_MEDIA_INVALID_MAP_ADDRESS; } return (void*)(m->start + offset); } @@ -63,6 +63,8 @@ static void *ram_unmap(struct cbfs_media *media, const void *address) { static size_t ram_read(struct cbfs_media *media, void *dest, size_t offset, size_t count) { void *ptr = ram_map(media, offset, count); + if (ptr == CBFS_MEDIA_INVALID_MAP_ADDRESS) + return 0; memcpy(dest, ptr, count); ram_unmap(media, ptr); return count;

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coreboot-gerrit March 2015