coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 355a7d8 libpayload: special case large memalign() requests
by Patrick Georgi 18 Mar '15

18 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8729 -gerrit commit 355a7d8029c563fe1f410e167df883a002adedce Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 22 08:59:03 2015 -0600 libpayload: special case large memalign() requests For memalign() requests the current allocator keeps metadata about each chunk of aligned memory that copmrises the size requested. For large allocations relative to the alignment this can cause significant metadata overhead. Instead, consider all memalign() requests whose size meets or exceeds 1KiB or alignment that meets or exceeds 1KiB large requests. These requests are handled specially to only allocate the amount of memory required for the size and alignment constraints by not allocating any metadata as the whole region would be consumed by the request. BUG=None BRANCH=None TEST=Built and tested various scenarios. Noted the ability to free() and properly coalesce the heap as expected. Change-Id: Ia9cf5529ca859e490617af296cffd2705c2c6fd8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4e32fc57626dac6194c9fd0141df680b4a5417e8 Original-Change-Id: Icdf022831b733e3bb84a2d2f3b499f4e25d89128 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242456 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/libc/malloc.c | 140 +++++++++++++++++++++++++++++--------- 1 file changed, 109 insertions(+), 31 deletions(-) diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index edda0b4..3c35793 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -318,6 +318,8 @@ void *realloc(void *ptr, size_t size) struct align_region_t { + /* If alignment is 0 then the region reqpresents a large region which + * has no metadata for tracking subelements. */ int alignment; /* start in memory, and size in bytes */ void* start; @@ -336,58 +338,126 @@ struct align_region_t struct align_region_t *next; }; -static struct align_region_t *allocate_region(int alignment, int num_elements, struct memory_type *type) +static inline int region_is_large(const struct align_region_t *r) { - struct align_region_t *new_region; + return r->alignment == 0; +} + +static inline int addr_in_region(const struct align_region_t *r, void *addr) +{ + return ((addr >= r->start_data) && (addr < r->start_data + r->size)); +} + +/* num_elements == 0 indicates a large aligned region instead of a smaller + * region comprised of alignment-sized chunks. */ +static struct align_region_t *allocate_region(int alignment, int num_elements, + size_t size, struct memory_type *type) +{ + struct align_region_t *r; + size_t extra_space; + #ifdef CONFIG_LP_DEBUG_MALLOC - printf("%s(old align_regions=%p, alignment=%u, num_elements=%u)\n", - __func__, type->align_regions, alignment, num_elements); + printf("%s(old align_regions=%p, alignment=%u, num_elements=%u, size=%zu)\n", + __func__, type->align_regions, alignment, num_elements, size); #endif - new_region = malloc(sizeof(struct align_region_t)); + r = malloc(sizeof(*r)); - if (!new_region) + if (r == NULL) return NULL; - new_region->alignment = alignment; - new_region->start = alloc((num_elements+1) * alignment + num_elements, type); - if (!new_region->start) { - free(new_region); + + memset(r, 0, sizeof(r)); + + if (num_elements != 0) { + r->alignment = alignment; + r->size = num_elements * alignment; + r->free = num_elements; + /* Allocate enough memory for alignment requirements and + * metadata for each chunk. */ + extra_space = num_elements; + } else { + /* Large aligned allocation. Set alignment = 0. */ + r->alignment = 0; + r->size = size; + extra_space = 0; + } + + r->start = alloc(r->size + alignment + extra_space, type); + + if (r->start == NULL) { + free(r); return NULL; } - new_region->start_data = (void*)((uintptr_t)(new_region->start + num_elements + alignment - 1) & (~(alignment-1))); - new_region->size = num_elements * alignment; - new_region->free = num_elements; - new_region->next = type->align_regions; - memset(new_region->start, 0, num_elements); - type->align_regions = new_region; - return new_region; + + r->start_data = (void *)ALIGN_UP((uintptr_t)r->start + extra_space, + alignment); + + /* Clear any (if requested) metadata. */ + memset(r->start, 0, extra_space); + + /* Link the region with the rest. */ + r->next = type->align_regions; + type->align_regions = r; + + return r; } +static void try_free_region(struct align_region_t **prev_link) +{ + struct align_region_t *r = *prev_link; + + /* All large regions are immediately free-able. Non-large regions + * need to be checked for the fully freed state. */ + if (!region_is_large(r)) { + if (r->free != r->size / r->alignment) + return; + } + + /* Unlink region from link list. */ + *prev_link = r->next; + + /* Free the data and metadata. */ + free(r->start); + free(r); +} static int free_aligned(void* addr, struct memory_type *type) { - struct align_region_t *reg = type->align_regions; - while (reg != 0) + struct align_region_t **prev_link = &type->align_regions; + + while (*prev_link != NULL) { - if ((addr >= reg->start_data) && (addr < reg->start_data + reg->size)) - { - int i = (addr-reg->start_data)/reg->alignment; - while (((u8*)reg->start)[i]==2) - { - ((u8*)reg->start)[i++]=0; - reg->free++; - } - ((u8*)reg->start)[i]=0; - reg->free++; + if (!addr_in_region(*prev_link, addr)) { + prev_link = &((*prev_link)->next); + continue; + } + + if (region_is_large(*prev_link)) { + try_free_region(prev_link); return 1; } - reg = reg->next; + + int i = (addr-(*prev_link)->start_data)/(*prev_link)->alignment; + u8 *meta = (*prev_link)->start; + while (meta[i] == 2) + { + meta[i++] = 0; + (*prev_link)->free++; + } + meta[i] = 0; + (*prev_link)->free++; + try_free_region(prev_link); + return 1; } return 0; } static void *alloc_aligned(size_t align, size_t size, struct memory_type *type) { + /* Define a large request to be 1024 bytes for either alignment or + * size of allocation. */ + const size_t large_request = 1024; + if (size == 0) return 0; if (type->align_regions == 0) { type->align_regions = malloc(sizeof(struct align_region_t)); @@ -396,6 +466,14 @@ static void *alloc_aligned(size_t align, size_t size, struct memory_type *type) memset(type->align_regions, 0, sizeof(struct align_region_t)); } struct align_region_t *reg = type->align_regions; + + if (size >= large_request || align >= large_request) { + reg = allocate_region(align, 0, size, type); + if (reg == NULL) + return NULL; + return reg->start_data; + } + look_further: while (reg != 0) { @@ -414,7 +492,7 @@ look_further: printf(" need to allocate a new memalign region\n"); #endif /* get align regions */ - reg = allocate_region(align, (size<1024)?(1024/align):(((size-1)/align)+1), type); + reg = allocate_region(align, large_request/align, size, type); #ifdef CONFIG_LP_DEBUG_MALLOC printf(" ... returned %p\n", reg); #endif

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Patch set updated for coreboot: e7086bb libpayload: Add board id parsing
by Patrick Georgi 18 Mar '15

18 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8730 -gerrit commit e7086bb596c73fb7505c01f6d85c52f2c1f98dc5 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jul 29 17:51:29 2014 -0700 libpayload: Add board id parsing Make board ID value supplied in the coreboot table available to the bootloader on all three architectures. BUG=chrome-os-partner:30489 TEST=none yet Change-Id: I6c2d39e94212b55650929d7d99896581d23f789d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 723e4a600a5d3a03e960169b04f8322f6dd2486b Original-Change-Id: I7847bd9fe2d000a29c7ae95144f4868d926fb198 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210430 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/arch/arm/coreboot.c | 15 +++++++++++++++ payloads/libpayload/arch/arm64/coreboot.c | 15 +++++++++++++++ payloads/libpayload/arch/x86/coreboot.c | 15 +++++++++++++++ payloads/libpayload/include/coreboot_tables.h | 8 ++++++++ payloads/libpayload/include/sysinfo.h | 1 + 5 files changed, 54 insertions(+) diff --git a/payloads/libpayload/arch/arm/coreboot.c b/payloads/libpayload/arch/arm/coreboot.c index c7f371e..a1c3675 100644 --- a/payloads/libpayload/arch/arm/coreboot.c +++ b/payloads/libpayload/arch/arm/coreboot.c @@ -143,6 +143,12 @@ static void cb_parse_mrc_cache(unsigned char *ptr, struct sysinfo_t *info) info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); } +static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_board_id *const cbbid = (struct cb_board_id *)ptr; + info->board_id = cbbid->board_id; +} + #ifdef CONFIG_LP_NVRAM static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { @@ -196,6 +202,12 @@ static int cb_parse_header(void *addr, struct sysinfo_t *info) info->header = header; + /* + * Valid board IDs are small numbers, preset this to an invalid value + * for the case when firmware does not supply the board ID. + */ + info->board_id = ~0; + /* Now, walk the tables. */ ptr += header->header_bytes; @@ -288,6 +300,9 @@ static int cb_parse_header(void *addr, struct sysinfo_t *info) case CB_TAG_MRC_CACHE: cb_parse_mrc_cache(ptr, info); break; + case CB_TAG_BOARD_ID: + cb_parse_board_id(ptr, info); + break; } ptr += rec->size; diff --git a/payloads/libpayload/arch/arm64/coreboot.c b/payloads/libpayload/arch/arm64/coreboot.c index 6c671c8..6d7c955 100644 --- a/payloads/libpayload/arch/arm64/coreboot.c +++ b/payloads/libpayload/arch/arm64/coreboot.c @@ -143,6 +143,12 @@ static void cb_parse_mrc_cache(unsigned char *ptr, struct sysinfo_t *info) info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); } +static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_board_id *const cbbid = (struct cb_board_id *)ptr; + info->board_id = cbbid->board_id; +} + #ifdef CONFIG_LP_NVRAM static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { @@ -196,6 +202,12 @@ static int cb_parse_header(void *addr, struct sysinfo_t *info) info->header = header; + /* + * Valid board IDs are small numbers, preset this to an invalid value + * for the case when firmware does not supply the board ID. + */ + info->board_id = ~0; + /* Now, walk the tables. */ ptr += header->header_bytes; @@ -288,6 +300,9 @@ static int cb_parse_header(void *addr, struct sysinfo_t *info) case CB_TAG_MRC_CACHE: cb_parse_mrc_cache(ptr, info); break; + case CB_TAG_BOARD_ID: + cb_parse_board_id(ptr, info); + break; } ptr += rec->size; diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index a463557..43fde9f 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -141,6 +141,12 @@ static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) info->acpi_gnvs = phys_to_virt(cbmem->cbmem_tab); } +static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_board_id *const cbbid = (struct cb_board_id *)ptr; + info->board_id = cbbid->board_id; +} + #ifdef CONFIG_LP_NVRAM static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { @@ -206,6 +212,12 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) info->header = header; + /* + * Valid board IDs are small numbers, preset this to an invalid value + * for the case when firmware does not supply the board ID. + */ + info->board_id = ~0; + /* Now, walk the tables. */ ptr += header->header_bytes; @@ -300,6 +312,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_X86_ROM_MTRR: cb_parse_x86_rom_var_mtrr(ptr, info); break; + case CB_TAG_BOARD_ID: + cb_parse_board_id(ptr, info); + break; } ptr += rec->size; diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index e20249d..53b5890 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -205,6 +205,14 @@ struct cb_cbmem_tab { uint64_t cbmem_tab; }; +#define CB_TAG_BOARD_ID 0x0025 +struct cb_board_id { + uint32_t tag; + uint32_t size; + /* Board ID as retrieved from the board revision GPIOs. */ + uint32_t board_id; +}; + #define CB_TAG_X86_ROM_MTRR 0x0021 struct cb_x86_rom_mtrr { uint32_t tag; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 92b8dca..e8a5858 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -108,6 +108,7 @@ struct sysinfo_t { void *cbmem_cons; void *mrc_cache; void *acpi_gnvs; + u32 board_id; }; extern struct sysinfo_t lib_sysinfo;

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Patch set updated for coreboot: 1c1dd56 libpayload: Add support for memory barriers
by Patrick Georgi 18 Mar '15

18 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8731 -gerrit commit 1c1dd56ac5c89f0bc7a3966bac06ee39a84f3155 Author: Furquan Shaikh <furquan(a)google.com> Date: Sun Aug 24 22:47:20 2014 -0700 libpayload: Add support for memory barriers Add support for memory barriers in arch {arm,arm64,x86}. This is required to force strict CPU ordering. Definitions are based on FREEBSD atomic.h definitions. BUG=chrome-os-partner:31533 BRANCH=None TEST=Memory barriers tested with ehci driver on arm64 Change-Id: I50060b0f33a6bd6cb95e829df079df379b2ff2a5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 937d66cdab92a8521ede8307f5af8f5c20d3e552 Original-Change-Id: Ie51e3452f7a254b24111000da5dbe8714ac22223 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213916 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- payloads/libpayload/include/arm/arch/barrier.h | 66 ++++++++++++++++++++++ payloads/libpayload/include/arm/arch/cache.h | 18 +----- payloads/libpayload/include/arm64/arch/barrier.h | 70 ++++++++++++++++++++++++ payloads/libpayload/include/arm64/arch/cache.h | 22 +++----- payloads/libpayload/include/x86/arch/barrier.h | 38 +++++++++++++ 5 files changed, 184 insertions(+), 30 deletions(-) diff --git a/payloads/libpayload/include/arm/arch/barrier.h b/payloads/libpayload/include/arm/arch/barrier.h new file mode 100644 index 0000000..fde55fa --- /dev/null +++ b/payloads/libpayload/include/arm/arch/barrier.h @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * Copyright (C) 2003-2004 Olivier Houchard + * Copyright (C) 1994-1997 Mark Brinicombe + * Copyright (C) 1994 Brini + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef __ARCH_BARRIER_H_ +#define __ARCH_BARRIER_H__ + +#include <arch/cache.h> + +/* + * Description of different memory barriers introduced: + * + * Memory barrier(mb) - Guarantees that all memory accesses specified before the + * barrier will happen before all memory accesses specified after the barrier + * + * Read memory barrier (rmb) - Guarantees that all read memory accesses + * specified before the barrier will happen before all read memory accesses + * specified after the barrier + * + * Write memory barrier (wmb) - Guarantees that all write memory accesses + * specified before the barrier will happen before all write memory accesses + * specified after the barrier + */ + +/* + * According to ARM Reference Manual (ARMv7-A), by default dmb ensures: + * Full system is the required shareability domain + * Reads and writes are the required access types. + */ +#define mb() dmb() +#define rmb() dmb() +#define wmb() dmb() + +#endif /* __ARCH_BARRIER_H__ */ diff --git a/payloads/libpayload/include/arm/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h index 647ec42..67f6fd4 100644 --- a/payloads/libpayload/include/arm/arch/cache.h +++ b/payloads/libpayload/include/arm/arch/cache.h @@ -70,24 +70,12 @@ /* * Sync primitives */ - /* data memory barrier */ -static inline void dmb(void) -{ - asm volatile ("dmb" : : : "memory"); -} - +#define dmb() asm volatile ("dmb" : : : "memory") /* data sync barrier */ -static inline void dsb(void) -{ - asm volatile ("dsb" : : : "memory"); -} - +#define dsb() asm volatile ("dsb" : : : "memory") /* instruction sync barrier */ -static inline void isb(void) -{ - asm volatile ("isb" : : : "memory"); -} +#define isb() asm volatile ("isb" : : : "memory") /* * Low-level TLB maintenance operations diff --git a/payloads/libpayload/include/arm64/arch/barrier.h b/payloads/libpayload/include/arm64/arch/barrier.h new file mode 100644 index 0000000..de1b165 --- /dev/null +++ b/payloads/libpayload/include/arm64/arch/barrier.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * Copyright (C) 2003-2004 Olivier Houchard + * Copyright (C) 1994-1997 Mark Brinicombe + * Copyright (C) 1994 Brini + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef __ARCH_BARRIER_H_ +#define __ARCH_BARRIER_H__ + +#include <arch/cache.h> + +/* + * Description of different memory barriers introduced: + * + * Memory barrier(mb) - Guarantees that all memory accesses specified before the + * barrier will happen before all memory accesses specified after the barrier + * + * Read memory barrier (rmb) - Guarantees that all read memory accesses + * specified before the barrier will happen before all read memory accesses + * specified after the barrier + * + * Write memory barrier (wmb) - Guarantees that all write memory accesses + * specified before the barrier will happen before all write memory accesses + * specified after the barrier + */ + +/* + * According to ARMv8 Instruction Set Overview: + * Options specified to dmb instruction have the following meaning: + * Option Ordered accesses + * sy any-any + * ld load-load, load-store + * st store-store + */ + +#define mb() dmb_opt(sy) +#define rmb() dmb_opt(ld) +#define wmb() dmb_opt(st) + +#endif /* __ARCH_BARRIER_H__ */ diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h index 2d3175e..f03d09b 100644 --- a/payloads/libpayload/include/arm64/arch/cache.h +++ b/payloads/libpayload/include/arm64/arch/cache.h @@ -70,24 +70,16 @@ /* * Sync primitives */ - /* data memory barrier */ -static inline void dmb(void) -{ - asm volatile ("dmb sy" : : : "memory"); -} - +#define dmb_opt(opt) asm volatile ("dmb " #opt : : : "memory") /* data sync barrier */ -static inline void dsb(void) -{ - asm volatile ("dsb sy" : : : "memory"); -} - +#define dsb_opt(opt) asm volatile ("dsb " #opt : : : "memory") /* instruction sync barrier */ -static inline void isb(void) -{ - asm volatile ("isb" : : : "memory"); -} +#define isb_opt(opt) asm volatile ("isb " #opt : : : "memory") + +#define dmb() dmb_opt(sy) +#define dsb() dsb_opt(sy) +#define isb() isb_opt() /* * Low-level TLB maintenance operations diff --git a/payloads/libpayload/include/x86/arch/barrier.h b/payloads/libpayload/include/x86/arch/barrier.h new file mode 100644 index 0000000..5e2cfec --- /dev/null +++ b/payloads/libpayload/include/x86/arch/barrier.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef __ARCH_BARRIER_H_ +#define __ARCH_BARRIER_H__ + +#define mb() +#define rmb() +#define wmb() + +#endif /* __ARCH_BARRIER_H__ */

1 0

Patch set updated for coreboot: 678469b libpayload EHCI: Add memory barrier to EHCI driver
by Patrick Georgi 18 Mar '15

18 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8732 -gerrit commit 678469bcfb13d8153de00f815bc518976fcf7847 Author: Furquan Shaikh <furquan(a)google.com> Date: Sun Aug 24 23:07:43 2014 -0700 libpayload EHCI: Add memory barrier to EHCI driver EHCI driver accesses mmio space using regular struct pointers. In order to avoid any CPU re-ordering, memory barrier is required in async_set_schedule, especially for arm64. Without the memory barrier, there seems to be re-ordering taking place which leads to USB errors with some flash drives as well as transfer errors in netboot. BUG=chrome-os-partner:31533 BRANCH=None TEST=With the memory barrier introduced, netboot for ryu completes transfer without any error and finishes within 6-7 seconds. Change-Id: Ib6d29dc79fd5722c27284478e8da316929e86bff Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 561bdd746c4d4446ce0a6d21337d354625d85ddc Original-Change-Id: Ic05d47422312a1cddbebe3180f4f159853604440 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213917 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- payloads/libpayload/drivers/usb/ehci.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index b83712c..7002623 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -30,6 +30,7 @@ //#define USB_DEBUG #include <libpayload.h> +#include <arch/barrier.h> #include <arch/cache.h> #include "ehci.h" #include "ehci_private.h" @@ -317,6 +318,14 @@ static int wait_for_tds(qtd_t *head) static int ehci_set_async_schedule(ehci_t *ehcic, int enable) { + + /* Memory barrier to ensure that all memory accesses before we set the + * async schedule are complete. It was observed especially in the case of + * arm64, that netboot and usb stuff resulted in lots of errors possibly + * due to CPU reordering. Hence, enforcing strict CPU ordering. + */ + mb(); + /* Set async schedule status. */ if (enable) ehcic->operation->usbcmd |= HC_OP_ASYNC_SCHED_EN;

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Patch set updated for coreboot: e945691 libpayload: UTF-16LE to ASCII conversion
by Patrick Georgi 18 Mar '15

18 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8733 -gerrit commit e945691aabc7ef8fbf85ebfe66e629f31515b037 Author: Dan Ehrenberg <dehrenberg(a)chromium.org> Date: Fri Nov 21 15:50:27 2014 -0800 libpayload: UTF-16LE to ASCII conversion This patch adds a simple function to convert a string in UTF-16LE to ASCII. TEST=Ran against a string found in a GPT with the intended outcome BRANCH=none BUG=none Change-Id: I94ec0a32f5712259d3d0caec2233c992330228e3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1104db8328a197c7ccf6959a238277f416a2113a Original-Signed-off-by: Dan Ehrenberg <dehrenberg(a)chromium.org> Original-Change-Id: I50ca5bfdfbef9e084321b2beb1b8d4194ca5af9c Original-Reviewed-on: https://chromium-review.googlesource.com/231456 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/include/string.h | 7 +++++++ payloads/libpayload/libc/string.c | 19 +++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/payloads/libpayload/include/string.h b/payloads/libpayload/include/string.h index 952261f..ca5d513 100644 --- a/payloads/libpayload/include/string.h +++ b/payloads/libpayload/include/string.h @@ -69,6 +69,13 @@ char *strerror(int errnum); /** @} */ /** + * @defgroup string Unicode functions + * @{ + */ +char *utf16le_to_ascii(uint16_t *utf16_string, int maxlen); +/** @} */ + +/** * @defgroup string OpenBSD based safe string functions * @{ */ diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index 71dd1a6..9985749 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -653,3 +653,22 @@ char *strerror(int errnum) snprintf(errstr, sizeof(errstr), "Unknown error %d", errnum); return errstr; } + +/* + * Simple routine to convert UTF-16 to ASCII, giving up with ? if too high. + * A single code point may convert to ?? if not in the BMP. + * @param utf16_string A string encoded in UTF-16LE + * @param maxlen Maximum possible length of the string in code points + * @return Newly allocated ASCII string + */ +char *utf16le_to_ascii(uint16_t *utf16_string, int maxlen) +{ + char *ascii_string = xmalloc(maxlen + 1); /* +1 for trailing \0 */ + ascii_string[maxlen] = '\0'; + int i; + for (i = 0; i < maxlen; i++) { + uint16_t wchar = utf16_string[i]; + ascii_string[i] = wchar > 0x7f ? '?' : (char)wchar; + } + return ascii_string; +}

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Patch set updated for coreboot: c591ec7 libpayload: PCI bus scan - Eliminate endless loop
by Patrick Georgi 18 Mar '15

18 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8734 -gerrit commit c591ec7fb88ebc1ea3bd30921c4b86c05228a31e Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Dec 17 13:05:26 2014 -0800 libpayload: PCI bus scan - Eliminate endless loop Don't attempt to scan the PCI bus if the bridge is disabled. When the PCI bridge is not setup and enabled, it is possible for the secondary bus register to contain the value zero (0). In this case the usb_scan_pci_bus routine gets into an infinite recursive loop which ends only when the heap or stack is exhausted. This patch verifies that the PCI bridge is enabled by verifying that it is enabled for either memory or I/O operations. When enabled, the secondary bus is scanned. BRANCH=none BUG=None TEST=Build and run on Samus Change-Id: I6826dc1d73b7c24729de5ac7c4d3534922ca73c5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 63d04b47934761351b54c847a2692bdef81ce54f Original-Change-Id: I855240c52fa3eba841e6754816ebbcb824abc4cd Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/236382 Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Giri P Mudusuru <giri.p.mudusuru(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- payloads/libpayload/drivers/usb/usbinit.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index 6fb7d4b..4225c3f 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -146,9 +146,13 @@ static void usb_scan_pci_bus(int bus) header_type = pci_read_config8(pci_device, REG_HEADER_TYPE); /* If this is a bridge, scan the other side. */ if ((header_type & ~HEADER_TYPE_MULTIFUNCTION) == - HEADER_TYPE_BRIDGE) - usb_scan_pci_bus(pci_read_config8(pci_device, - REG_SECONDARY_BUS)); + HEADER_TYPE_BRIDGE) { + /* Verify that the bridge is enabled */ + if ((pci_read_config16(pci_device, REG_COMMAND) + & 3) != 0) + usb_scan_pci_bus(pci_read_config8( + pci_device, REG_SECONDARY_BUS)); + } else usb_controller_initialize(bus, dev, func); }

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Patch set updated for coreboot: 0197193 libpayload console: Add check for already existing driver
by Patrick Georgi 18 Mar '15

18 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8739 -gerrit commit 01971934af2194b819d7667072a192b577232c12 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Aug 25 15:06:18 2014 -0700 libpayload console: Add check for already existing driver Add support to check if the driver for console_out or console_in is already present in the list. If console_init is called twice, then the driver might get added twice leading to a loop. BUG=None BRANCH=None TEST=With console_init in libpayload and depthcharge both, there are no console loops seen anymore Change-Id: I9103230dfe88added28c51bff33ea4fa1ab034c1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6931236ba2cfa71849973fe41cc340b7d70656ad Original-Change-Id: If9a927318b850ec59619d92b1da4dddd0aa09cd1 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214072 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- payloads/libpayload/libc/console.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/payloads/libpayload/libc/console.c b/payloads/libpayload/libc/console.c index 827da79..7717daf 100644 --- a/payloads/libpayload/libc/console.c +++ b/payloads/libpayload/libc/console.c @@ -35,15 +35,47 @@ struct console_output_driver *console_out; struct console_input_driver *console_in; static console_input_type last_getchar_input_type; +static int output_driver_exists(struct console_output_driver *out) +{ + struct console_output_driver *head = console_out; + + while (head) { + if (head == out) + return 1; + head = head->next; + } + + return 0; +} + +static int input_driver_exists(struct console_input_driver *in) +{ + struct console_input_driver *head = console_in; + + while (head) { + if (head == in) + return 1; + head = head->next; + } + + return 0; +} + void console_add_output_driver(struct console_output_driver *out) { die_if(!out->putchar && !out->write, "Need at least one output func\n"); + /* Check if this driver was already added to the console list */ + if (output_driver_exists(out)) + return; out->next = console_out; console_out = out; } void console_add_input_driver(struct console_input_driver *in) { + /* Check if this driver was already added to the console list */ + if (input_driver_exists(in)) + return; in->next = console_in; console_in = in; }

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Patch merged into coreboot/master: 9ef9d85 bootstate: use structure pointers for scheduling callbacks
by gerrit＠coreboot.org 18 Mar '15

18 Mar '15

the following patch was just integrated into master: commit 9ef9d85976fcfc5f4c8c273eaf3377fdd6e5c24d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 16 17:30:09 2015 -0500 bootstate: use structure pointers for scheduling callbacks The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/8699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8699 for details. -gerrit

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Patch set updated for coreboot: 6ce7d93 libpayload: arch/mips: add virt/bus/phy_to_bus/phy/virt operations
by Patrick Georgi 18 Mar '15

18 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8746 -gerrit commit 6ce7d937a0c623426453098d19646e78d3d780ea Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Mon Feb 2 14:48:12 2015 +0000 libpayload: arch/mips: add virt/bus/phy_to_bus/phy/virt operations BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA and bring up board; works as expected BRANCH=none Change-Id: I368494f388b82969dda0ce73a38824791efce616 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e4c2bbcbdbcf706062724cffe2d5f15953468ace Original-Change-Id: Id5c9b1d65c6ec87f2aba06995dc940c50afb041f Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245386 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- payloads/libpayload/arch/mips/virtual.c | 3 ++- payloads/libpayload/include/mips/arch/virtual.h | 13 ++++++++----- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/arch/mips/virtual.c b/payloads/libpayload/arch/mips/virtual.c index 9d22649..5c110d0 100644 --- a/payloads/libpayload/arch/mips/virtual.c +++ b/payloads/libpayload/arch/mips/virtual.c @@ -19,7 +19,8 @@ #include <unistd.h> -unsigned long virtual_offset = 0; +unsigned long virt_to_phys_offset = 0; +unsigned long virt_to_bus_offset = 0x60000000; int getpagesize(void) { diff --git a/payloads/libpayload/include/mips/arch/virtual.h b/payloads/libpayload/include/mips/arch/virtual.h index 70aea20..f470393 100644 --- a/payloads/libpayload/include/mips/arch/virtual.h +++ b/payloads/libpayload/include/mips/arch/virtual.h @@ -20,12 +20,15 @@ #ifndef __MIPS_ARCH_VIRTUAL_H #define __MIPS_ARCH_VIRTUAL_H -extern unsigned long virtual_offset; +extern unsigned long virt_to_phys_offset; +extern unsigned long virt_to_bus_offset; -#define virt_to_phys(virt) ((unsigned long) (virt) + virtual_offset) -#define phys_to_virt(phys) ((void *) ((unsigned long) (phys) - virtual_offset)) +#define virt_to_phys(virt) ((unsigned long) (virt) + virt_to_phys_offset) +#define phys_to_virt(phys) ((void *) ((unsigned long) (phys) - \ + virt_to_phys_offset)) -#define virt_to_bus(addr) virt_to_phys(addr) -#define bus_to_virt(addr) phys_to_virt(addr) +#define virt_to_bus(virt) ((unsigned long) (virt) + virt_to_bus_offset) +#define bus_to_virt(phys) ((void *) ((unsigned long) (phys) - \ + virt_to_bus_offset)) #endif

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Patch set updated for coreboot: 475913b libpayload: mips: add SOC CPU frequency; correct platform ID
by Patrick Georgi 18 Mar '15

18 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8745 -gerrit commit 475913b2539fd0477a76c7e1398764bea1ebe06f Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Mon Jan 19 02:41:49 2015 +0000 libpayload: mips: add SOC CPU frequency; correct platform ID Add CPU frequency corrsponding to SOC. Corrected platform ID. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: I8e5ac80e95b5169102eaa075bc22045c0789d486 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604 Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241427 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- payloads/libpayload/arch/mips/timer.c | 21 +++++++++++++++++---- payloads/libpayload/include/mips/arch/cpu.h | 11 +++++++++-- 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/arch/mips/timer.c b/payloads/libpayload/arch/mips/timer.c index 1710a32..782959b 100644 --- a/payloads/libpayload/arch/mips/timer.c +++ b/payloads/libpayload/arch/mips/timer.c @@ -19,6 +19,10 @@ #include <libpayload.h> #include <arch/cpu.h> +#include <arch/io.h> + +#define PISTACHIO_CLOCK_SWITCH 0xB8144200 +#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 /** * @ingroup arch @@ -34,10 +38,19 @@ u32 cpu_khz; unsigned int get_cpu_speed(void) { if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) - cpu_khz = 50000U; /* FPGA board */ - /* else { - * TODO find CPU frequency on the real SOC - } */ + cpu_khz = 50000; /* FPGA board */ + else { + /* If MIPS PLL external bypass bit is set, it means + * that the MIPS PLL is already set up to work at a + * frequency of 550 MHz; otherwise, the crystal is + * used with a frequency of 52 MHz + */ + if (read32(PISTACHIO_CLOCK_SWITCH) & + MIPS_EXTERN_PLL_BYPASS_MASK) + cpu_khz = 550000; + else + cpu_khz = 52000; + } return cpu_khz; } diff --git a/payloads/libpayload/include/mips/arch/cpu.h b/payloads/libpayload/include/mips/arch/cpu.h index 952ec7c..93e42ea 100644 --- a/payloads/libpayload/include/mips/arch/cpu.h +++ b/payloads/libpayload/include/mips/arch/cpu.h @@ -22,8 +22,15 @@ * Reading at this address allows to identify the platform the code is running * on */ -#define IMG_PLATFORM_ID() (*((unsigned *)0xB8149060)) -#define IMG_PLATFORM_ID_SILICON 0xF00D0006 + +/* + * This register holds the FPGA image version + * If we're not working on the FPGA this will be 0 + */ +#define PRIMARY_FPGA_VERSION 0xB8149060 +#define IMG_PLATFORM_ID() read32(PRIMARY_FPGA_VERSION) +#define IMG_PLATFORM_ID_FPGA 0xD1400003 /* Last FPGA image */ +#define IMG_PLATFORM_ID_SILICON 0 #define CP0_COUNT 9 #define CP0_COMPARE 11

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coreboot-gerrit March 2015