coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

1 participants
509 discussions

New patch to review for coreboot: 0f61690 lint: exclude nvidia submodule from file list
by Patrick Georgi 05 Feb '15

05 Feb '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8372 -gerrit commit 0f616900740ede9104dd35635de9b2096a094868 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 5 23:38:45 2015 +0100 lint: exclude nvidia submodule from file list From git's point of view submodules are a weird third thing between file and directory. Avoid trying to apply file handling on a directory. Change-Id: Ibbc9c28e1657d96413c5fb08705d30e25171254d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/lint/lint-stable-003-whitespace | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 22c5c3c..47853ba 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -19,6 +19,6 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch|\.bin$)"` | \ +grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch|\.bin$)"` | \ sed -e "s,^.*$,File & has lines ending with whitespace.,"

1 0

New patch to review for coreboot: 2814089 documentation: begin documenting our use of git submodules
by Patrick Georgi 05 Feb '15

05 Feb '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8371 -gerrit commit 2814089fbbb41847aa41d2b768e3819632bba019 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 5 23:36:32 2015 +0100 documentation: begin documenting our use of git submodules git submodules have some surprising behaviour, and we make full of it. Start building a canonical resource for that so developers can spend their time on better things than on fighting git. Change-Id: I5aa721e9b0acb2912a057858fd23a1d59d845ed1 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- documentation/submodules.txt | 46 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/documentation/submodules.txt b/documentation/submodules.txt new file mode 100644 index 0000000..07c3598 --- /dev/null +++ b/documentation/submodules.txt @@ -0,0 +1,46 @@ +Use of git submodules in coreboot +================================= +coreboot uses git submodules to keep certain parts of the tree separate, +with two major use cases: + +First, we use a vendor tool by nvidia for systems based on their SoC +and since they publish it through git, we can just import it into our +tree using submodules. + +Second, lots of boards these days require binaries and we want to keep +them separate from coreboot proper to clearly delineate shiny Open Source +from ugly blobs. +Since we don't want to impose blobs on users who really don't need them, +that repository is only downloaded and checked out on explicit request. + +Handling submodules +------------------- +For the most part, submodules should be automatically checked out on the +first execution of the coreboot Makefile. + +To manually fetch all repositories (eg. when you want to prepare the tree +for archiving, or to use it without network access), run + + $ git submodule update --init --checkout + +This also checks out the binaries below `3rdparty/` + +Mirroring coreboot +------------------ +When running a coreboot mirror to checkout from, for full operating, you +should also mirror the blobs and nvidia-cbootimage repository, and place +them in the same directory as the coreboot repository mirror. + +That is, when residing in coreboot's repository, `cd ../blobs.git` +should move you to the blobs repository. + +With that, no matter what the URL of your coreboot repository is, the +git client (of a sufficiently new version) is able to pick up the other +repositories transparently. + +Minimum requirements +-------------------- +git needs to be able to handle relative paths to submodule repositories, +and it needs to know about non-automatic submodules. + +For these features, we require git version 1.7.6.1 or newer.

1 0

New patch to review for coreboot: bdd9576 src/lib/tpm_error_messages.h: convert CRLF to LF
by Patrick Georgi 05 Feb '15

05 Feb '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8370 -gerrit commit bdd9576b0c315fbd39a0233e85f578a375e9c4cc Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 5 23:35:41 2015 +0100 src/lib/tpm_error_messages.h: convert CRLF to LF This matches the rest of the tree. Change-Id: I94cb64709eca85fb327513a496f6a2dc560e5495 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/lib/tpm_error_messages.h | 500 +++++++++++++++++++++---------------------- 1 file changed, 250 insertions(+), 250 deletions(-) diff --git a/src/lib/tpm_error_messages.h b/src/lib/tpm_error_messages.h index 14cb86b..3b0f48c 100644 --- a/src/lib/tpm_error_messages.h +++ b/src/lib/tpm_error_messages.h @@ -1,250 +1,250 @@ -/* Copyright (c) 2010 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* TPM error codes. - * - * Copy-pasted and lightly edited from TCG TPM Main Part 2 TPM Structures - * Version 1.2 Level 2 Revision 103 26 October 2006 Draft. - */ - -#ifndef TPM_ERROR_MESSAGES_H -#define TPM_ERROR_MESSAGES_H - -#define TPM_E_BASE 0x0 -#define TPM_E_NON_FATAL 0x800 - -typedef struct tpm_error_info { - const char* name; - uint32_t code; - const char* description; -} tpm_error_info; - -tpm_error_info tpm_error_table[] = { -{ "TPM_AUTHFAIL", TPM_E_BASE + 1, -"Authentication failed" }, -{ "TPM_BADINDEX", TPM_E_BASE + 2, -"The index to a PCR, DIR or other register is incorrect" }, -{ "TPM_BAD_PARAMETER", TPM_E_BASE + 3, -"One or more parameter is bad" }, -{ "TPM_AUDITFAILURE", TPM_E_BASE + 4, -"An operation completed successfully\n\ -but the auditing of that operation failed" }, -{ "TPM_CLEAR_DISABLED", TPM_E_BASE + 5, -"The clear disable flag is set and all clear operations now require\n\ -physical access" }, -{ "TPM_DEACTIVATED", TPM_E_BASE + 6, -"The TPM is deactivated" }, -{ "TPM_DISABLED", TPM_E_BASE + 7, -"The TPM is disabled" }, -{ "TPM_DISABLED_CMD", TPM_E_BASE + 8, -"The target command has been disabled" }, -{ "TPM_FAIL", TPM_E_BASE + 9, -"The operation failed" }, -{ "TPM_BAD_ORDINAL", TPM_E_BASE + 10, -"The ordinal was unknown or inconsistent" }, -{ "TPM_INSTALL_DISABLED", TPM_E_BASE + 11, -"The ability to install an owner is disabled" }, -{ "TPM_INVALID_KEYHANDLE", TPM_E_BASE + 12, -"The key handle can not be interpreted" }, -{ "TPM_KEYNOTFOUND", TPM_E_BASE + 13, -"The key handle points to an invalid key" }, -{ "TPM_INAPPROPRIATE_ENC", TPM_E_BASE + 14, -"Unacceptable encryption scheme" }, -{ "TPM_MIGRATEFAIL", TPM_E_BASE + 15, -"Migration authorization failed" }, -{ "TPM_INVALID_PCR_INFO", TPM_E_BASE + 16, -"PCR information could not be interpreted" }, -{ "TPM_NOSPACE", TPM_E_BASE + 17, -"No room to load key" }, -{ "TPM_NOSRK", TPM_E_BASE + 18, -"There is no SRK set" }, -{ "TPM_NOTSEALED_BLOB", TPM_E_BASE + 19, -"An encrypted blob is invalid or was not created by this TPM" }, -{ "TPM_OWNER_SET", TPM_E_BASE + 20, -"There is already an Owner" }, -{ "TPM_RESOURCES", TPM_E_BASE + 21, -"The TPM has insufficient internal resources to perform the requested action" }, -{ "TPM_SHORTRANDOM", TPM_E_BASE + 22, -"A random string was too short" }, -{ "TPM_SIZE", TPM_E_BASE + 23, -"The TPM does not have the space to perform the operation" }, -{ "TPM_WRONGPCRVAL", TPM_E_BASE + 24, -"The named PCR value does not match the current PCR value" }, -{ "TPM_BAD_PARAM_SIZE", TPM_E_BASE + 25, -"The paramSize argument to the command has the incorrect value" }, -{ "TPM_SHA_THREAD", TPM_E_BASE + 26, -"There is no existing SHA-1 thread" }, -{ "TPM_SHA_ERROR", TPM_E_BASE + 27, -"The calculation is unable to proceed because the existing SHA-1\n\ -thread has already encountered an error" }, -{ "TPM_FAILEDSELFTEST", TPM_E_BASE + 28, -"Self-test has failed and the TPM has shutdown" }, -{ "TPM_AUTH2FAIL", TPM_E_BASE + 29, -"The authorization for the second key in a 2 key function\n\ -failed authorization" }, -{ "TPM_BADTAG", TPM_E_BASE + 30, -"The tag value sent to for a command is invalid" }, -{ "TPM_IOERROR", TPM_E_BASE + 31, -"An IO error occurred transmitting information to the TPM" }, -{ "TPM_ENCRYPT_ERROR", TPM_E_BASE + 32, -"The encryption process had a problem" }, -{ "TPM_DECRYPT_ERROR", TPM_E_BASE + 33, -"The decryption process did not complete" }, -{ "TPM_INVALID_AUTHHANDLE", TPM_E_BASE + 34, -"An invalid handle was used" }, -{ "TPM_NO_ENDORSEMENT", TPM_E_BASE + 35, -"The TPM does not a EK installed" }, -{ "TPM_INVALID_KEYUSAGE", TPM_E_BASE + 36, -"The usage of a key is not allowed" }, -{ "TPM_WRONG_ENTITYTYPE", TPM_E_BASE + 37, -"The submitted entity type is not allowed" }, -{ "TPM_INVALID_POSTINIT", TPM_E_BASE + 38, -"The command was received in the wrong sequence relative to TPM_Init\n\ -and a subsequent TPM_Startup" }, -{ "TPM_INAPPROPRIATE_SIG", TPM_E_BASE + 39, -"Signed data cannot include additional DER information" }, -{ "TPM_BAD_KEY_PROPERTY", TPM_E_BASE + 40, -"The key properties in TPM_KEY_PARMs are not supported by this TPM" }, -{ "TPM_BAD_MIGRATION", TPM_E_BASE + 41, -"The migration properties of this key are incorrect" }, -{ "TPM_BAD_SCHEME", TPM_E_BASE + 42, -"The signature or encryption scheme for this key is incorrect or not\n\ -permitted in this situation" }, -{ "TPM_BAD_DATASIZE", TPM_E_BASE + 43, -"The size of the data (or blob) parameter is bad or inconsistent\n\ -with the referenced key" }, -{ "TPM_BAD_MODE", TPM_E_BASE + 44, -"A mode parameter is bad, such as capArea or subCapArea for\n\ -TPM_GetCapability, physicalPresence parameter for TPM_PhysicalPresence,\n\ -or migrationType for, TPM_CreateMigrationBlob" }, -{ "TPM_BAD_PRESENCE", TPM_E_BASE + 45, -"Either the physicalPresence or physicalPresenceLock bits\n\ -have the wrong value" }, -{ "TPM_BAD_VERSION", TPM_E_BASE + 46, -"The TPM cannot perform this version of the capability" }, -{ "TPM_NO_WRAP_TRANSPORT", TPM_E_BASE + 47, -"The TPM does not allow for wrapped transport sessions" }, -{ "TPM_AUDITFAIL_UNSUCCESSFUL", TPM_E_BASE + 48, -"TPM audit construction failed and the underlying command\n\ -was returning a failure code also" }, -{ "TPM_AUDITFAIL_SUCCESSFUL", TPM_E_BASE + 49, -"TPM audit construction failed and the underlying command\n\ -was returning success" }, -{ "TPM_NOTRESETABLE", TPM_E_BASE + 50, -"Attempt to reset a PCR register that does not have the resettable attribute" }, -{ "TPM_NOTLOCAL", TPM_E_BASE + 51, -"Attempt to reset a PCR register that requires locality\n\ -and locality modifier not part of command transport" }, -{ "TPM_BAD_TYPE", TPM_E_BASE + 52, -"Make identity blob not properly typed" }, -{ "TPM_INVALID_RESOURCE", TPM_E_BASE + 53, -"When saving context identified resource type does not match actual resource" }, -{ "TPM_NOTFIPS", TPM_E_BASE + 54, -"The TPM is attempting to execute a command only available when in FIPS mode" }, -{ "TPM_INVALID_FAMILY", TPM_E_BASE + 55, -"The command is attempting to use an invalid family ID" }, -{ "TPM_NO_NV_PERMISSION", TPM_E_BASE + 56, -"The permission to manipulate the NV storage is not available" }, -{ "TPM_REQUIRES_SIGN", TPM_E_BASE + 57, -"The operation requires a signed command" }, -{ "TPM_KEY_NOTSUPPORTED", TPM_E_BASE + 58, -"Wrong operation to load an NV key" }, -{ "TPM_AUTH_CONFLICT", TPM_E_BASE + 59, -"NV_LoadKey blob requires both owner and blob authorization" }, -{ "TPM_AREA_LOCKED", TPM_E_BASE + 60, -"The NV area is locked and not writable" }, -{ "TPM_BAD_LOCALITY", TPM_E_BASE + 61, -"The locality is incorrect for the attempted operation" }, -{ "TPM_READ_ONLY", TPM_E_BASE + 62, -"The NV area is read only and canât be written to" }, -{ "TPM_PER_NOWRITE", TPM_E_BASE + 63, -"There is no protection on the write to the NV area" }, -{ "TPM_FAMILYCOUNT", TPM_E_BASE + 64, -"The family count value does not match" }, -{ "TPM_WRITE_LOCKED", TPM_E_BASE + 65, -"The NV area has already been written to" }, -{ "TPM_BAD_ATTRIBUTES", TPM_E_BASE + 66, -"The NV area attributes conflict" }, -{ "TPM_INVALID_STRUCTURE", TPM_E_BASE + 67, -"The structure tag and version are invalid or inconsistent" }, -{ "TPM_KEY_OWNER_CONTROL", TPM_E_BASE + 68, -"The key is under control of the TPM Owner and can only be evicted\n\ -by the TPM Owner" }, -{ "TPM_BAD_COUNTER", TPM_E_BASE + 69, -"The counter handle is incorrect" }, -{ "TPM_NOT_FULLWRITE", TPM_E_BASE + 70, -"The write is not a complete write of the area" }, -{ "TPM_CONTEXT_GAP", TPM_E_BASE + 71, -"The gap between saved context counts is too large" }, -{ "TPM_MAXNVWRITES", TPM_E_BASE + 72, -"The maximum number of NV writes without an owner has been exceeded" }, -{ "TPM_NOOPERATOR", TPM_E_BASE + 73, -"No operator AuthData value is set" }, -{ "TPM_RESOURCEMISSING", TPM_E_BASE + 74, -"The resource pointed to by context is not loaded" }, -{ "TPM_DELEGATE_LOCK", TPM_E_BASE + 75, -"The delegate administration is locked" }, -{ "TPM_DELEGATE_FAMILY", TPM_E_BASE + 76, -"Attempt to manage a family other then the delegated family" }, -{ "TPM_DELEGATE_ADMIN", TPM_E_BASE + 77, -"Delegation table management not enabled" }, -{ "TPM_TRANSPORT_NOTEXCLUSIVE", TPM_E_BASE + 78, -"There was a command executed outside of an exclusive transport session" }, -{ "TPM_OWNER_CONTROL", TPM_E_BASE + 79, -"Attempt to context save a owner evict controlled key" }, -{ "TPM_DAA_RESOURCES", TPM_E_BASE + 80, -"The DAA command has no resources available to execute the command" }, -{ "TPM_DAA_INPUT_DATA0", TPM_E_BASE + 81, -"The consistency check on DAA parameter inputData0 has failed" }, -{ "TPM_DAA_INPUT_DATA1", TPM_E_BASE + 82, -"The consistency check on DAA parameter inputData1 has failed" }, -{ "TPM_DAA_ISSUER_SETTINGS", TPM_E_BASE + 83, -"The consistency check on DAA_issuerSettings has failed" }, -{ "TPM_DAA_TPM_SETTINGS", TPM_E_BASE + 84, -"The consistency check on DAA_tpmSpecific has failed" }, -{ "TPM_DAA_STAGE", TPM_E_BASE + 85, -"The atomic process indicated by the submitted DAA command is not\n\ -the expected process" }, -{ "TPM_DAA_ISSUER_VALIDITY", TPM_E_BASE + 86, -"The issuerâs validity check has detected an inconsistency" }, -{ "TPM_DAA_WRONG_W", TPM_E_BASE + 87, -"The consistency check on w has failed" }, -{ "TPM_BAD_HANDLE", TPM_E_BASE + 88, -"The handle is incorrect" }, -{ "TPM_BAD_DELEGATE", TPM_E_BASE + 89, -"Delegation is not correct" }, -{ "TPM_BADCONTEXT", TPM_E_BASE + 90, -"The context blob is invalid" }, -{ "TPM_TOOMANYCONTEXTS", TPM_E_BASE + 91, -"Too many contexts held by the TPM" }, -{ "TPM_MA_TICKET_SIGNATURE", TPM_E_BASE + 92, -"Migration authority signature validation failure" }, -{ "TPM_MA_DESTINATION", TPM_E_BASE + 93, -"Migration destination not authenticated" }, -{ "TPM_MA_SOURCE", TPM_E_BASE + 94, -"Migration source incorrect" }, -{ "TPM_MA_AUTHORITY", TPM_E_BASE + 95, -"Incorrect migration authority" }, -{ "TPM_PERMANENTEK", TPM_E_BASE + 97, -"Attempt to revoke the EK and the EK is not revocable" }, -{ "TPM_BAD_SIGNATURE", TPM_E_BASE + 98, -"Bad signature of CMK ticket" }, -{ "TPM_NOCONTEXTSPACE", TPM_E_BASE + 99, -"There is no room in the context list for additional contexts" }, -{ "TPM_RETRY", TPM_E_BASE + TPM_E_NON_FATAL, -"The TPM is too busy to respond to the command immediately, but\n\ -the command could be resubmitted at a later time. The TPM MAY\n\ -return TPM_RETRY for any command at any time" }, -{ "TPM_NEEDS_SELFTEST", TPM_E_BASE + TPM_E_NON_FATAL + 1, -"TPM_ContinueSelfTest has not been run" }, -{ "TPM_DOING_SELFTEST", TPM_E_BASE + TPM_E_NON_FATAL + 2, -"The TPM is currently executing the actions of TPM_ContinueSelfTest\n\ -because the ordinal required resources that have not been tested" }, -{ "TPM_DEFEND_LOCK_RUNNING", TPM_E_BASE + TPM_E_NON_FATAL + 3, -"The TPM is defending against dictionary attacks and is in some\n\ -time-out period" }, - }; - -#endif /* TPM_ERROR_MESSAGES_H */ +/* Copyright (c) 2010 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* TPM error codes. + * + * Copy-pasted and lightly edited from TCG TPM Main Part 2 TPM Structures + * Version 1.2 Level 2 Revision 103 26 October 2006 Draft. + */ + +#ifndef TPM_ERROR_MESSAGES_H +#define TPM_ERROR_MESSAGES_H + +#define TPM_E_BASE 0x0 +#define TPM_E_NON_FATAL 0x800 + +typedef struct tpm_error_info { + const char* name; + uint32_t code; + const char* description; +} tpm_error_info; + +tpm_error_info tpm_error_table[] = { +{ "TPM_AUTHFAIL", TPM_E_BASE + 1, +"Authentication failed" }, +{ "TPM_BADINDEX", TPM_E_BASE + 2, +"The index to a PCR, DIR or other register is incorrect" }, +{ "TPM_BAD_PARAMETER", TPM_E_BASE + 3, +"One or more parameter is bad" }, +{ "TPM_AUDITFAILURE", TPM_E_BASE + 4, +"An operation completed successfully\n\ +but the auditing of that operation failed" }, +{ "TPM_CLEAR_DISABLED", TPM_E_BASE + 5, +"The clear disable flag is set and all clear operations now require\n\ +physical access" }, +{ "TPM_DEACTIVATED", TPM_E_BASE + 6, +"The TPM is deactivated" }, +{ "TPM_DISABLED", TPM_E_BASE + 7, +"The TPM is disabled" }, +{ "TPM_DISABLED_CMD", TPM_E_BASE + 8, +"The target command has been disabled" }, +{ "TPM_FAIL", TPM_E_BASE + 9, +"The operation failed" }, +{ "TPM_BAD_ORDINAL", TPM_E_BASE + 10, +"The ordinal was unknown or inconsistent" }, +{ "TPM_INSTALL_DISABLED", TPM_E_BASE + 11, +"The ability to install an owner is disabled" }, +{ "TPM_INVALID_KEYHANDLE", TPM_E_BASE + 12, +"The key handle can not be interpreted" }, +{ "TPM_KEYNOTFOUND", TPM_E_BASE + 13, +"The key handle points to an invalid key" }, +{ "TPM_INAPPROPRIATE_ENC", TPM_E_BASE + 14, +"Unacceptable encryption scheme" }, +{ "TPM_MIGRATEFAIL", TPM_E_BASE + 15, +"Migration authorization failed" }, +{ "TPM_INVALID_PCR_INFO", TPM_E_BASE + 16, +"PCR information could not be interpreted" }, +{ "TPM_NOSPACE", TPM_E_BASE + 17, +"No room to load key" }, +{ "TPM_NOSRK", TPM_E_BASE + 18, +"There is no SRK set" }, +{ "TPM_NOTSEALED_BLOB", TPM_E_BASE + 19, +"An encrypted blob is invalid or was not created by this TPM" }, +{ "TPM_OWNER_SET", TPM_E_BASE + 20, +"There is already an Owner" }, +{ "TPM_RESOURCES", TPM_E_BASE + 21, +"The TPM has insufficient internal resources to perform the requested action" }, +{ "TPM_SHORTRANDOM", TPM_E_BASE + 22, +"A random string was too short" }, +{ "TPM_SIZE", TPM_E_BASE + 23, +"The TPM does not have the space to perform the operation" }, +{ "TPM_WRONGPCRVAL", TPM_E_BASE + 24, +"The named PCR value does not match the current PCR value" }, +{ "TPM_BAD_PARAM_SIZE", TPM_E_BASE + 25, +"The paramSize argument to the command has the incorrect value" }, +{ "TPM_SHA_THREAD", TPM_E_BASE + 26, +"There is no existing SHA-1 thread" }, +{ "TPM_SHA_ERROR", TPM_E_BASE + 27, +"The calculation is unable to proceed because the existing SHA-1\n\ +thread has already encountered an error" }, +{ "TPM_FAILEDSELFTEST", TPM_E_BASE + 28, +"Self-test has failed and the TPM has shutdown" }, +{ "TPM_AUTH2FAIL", TPM_E_BASE + 29, +"The authorization for the second key in a 2 key function\n\ +failed authorization" }, +{ "TPM_BADTAG", TPM_E_BASE + 30, +"The tag value sent to for a command is invalid" }, +{ "TPM_IOERROR", TPM_E_BASE + 31, +"An IO error occurred transmitting information to the TPM" }, +{ "TPM_ENCRYPT_ERROR", TPM_E_BASE + 32, +"The encryption process had a problem" }, +{ "TPM_DECRYPT_ERROR", TPM_E_BASE + 33, +"The decryption process did not complete" }, +{ "TPM_INVALID_AUTHHANDLE", TPM_E_BASE + 34, +"An invalid handle was used" }, +{ "TPM_NO_ENDORSEMENT", TPM_E_BASE + 35, +"The TPM does not a EK installed" }, +{ "TPM_INVALID_KEYUSAGE", TPM_E_BASE + 36, +"The usage of a key is not allowed" }, +{ "TPM_WRONG_ENTITYTYPE", TPM_E_BASE + 37, +"The submitted entity type is not allowed" }, +{ "TPM_INVALID_POSTINIT", TPM_E_BASE + 38, +"The command was received in the wrong sequence relative to TPM_Init\n\ +and a subsequent TPM_Startup" }, +{ "TPM_INAPPROPRIATE_SIG", TPM_E_BASE + 39, +"Signed data cannot include additional DER information" }, +{ "TPM_BAD_KEY_PROPERTY", TPM_E_BASE + 40, +"The key properties in TPM_KEY_PARMs are not supported by this TPM" }, +{ "TPM_BAD_MIGRATION", TPM_E_BASE + 41, +"The migration properties of this key are incorrect" }, +{ "TPM_BAD_SCHEME", TPM_E_BASE + 42, +"The signature or encryption scheme for this key is incorrect or not\n\ +permitted in this situation" }, +{ "TPM_BAD_DATASIZE", TPM_E_BASE + 43, +"The size of the data (or blob) parameter is bad or inconsistent\n\ +with the referenced key" }, +{ "TPM_BAD_MODE", TPM_E_BASE + 44, +"A mode parameter is bad, such as capArea or subCapArea for\n\ +TPM_GetCapability, physicalPresence parameter for TPM_PhysicalPresence,\n\ +or migrationType for, TPM_CreateMigrationBlob" }, +{ "TPM_BAD_PRESENCE", TPM_E_BASE + 45, +"Either the physicalPresence or physicalPresenceLock bits\n\ +have the wrong value" }, +{ "TPM_BAD_VERSION", TPM_E_BASE + 46, +"The TPM cannot perform this version of the capability" }, +{ "TPM_NO_WRAP_TRANSPORT", TPM_E_BASE + 47, +"The TPM does not allow for wrapped transport sessions" }, +{ "TPM_AUDITFAIL_UNSUCCESSFUL", TPM_E_BASE + 48, +"TPM audit construction failed and the underlying command\n\ +was returning a failure code also" }, +{ "TPM_AUDITFAIL_SUCCESSFUL", TPM_E_BASE + 49, +"TPM audit construction failed and the underlying command\n\ +was returning success" }, +{ "TPM_NOTRESETABLE", TPM_E_BASE + 50, +"Attempt to reset a PCR register that does not have the resettable attribute" }, +{ "TPM_NOTLOCAL", TPM_E_BASE + 51, +"Attempt to reset a PCR register that requires locality\n\ +and locality modifier not part of command transport" }, +{ "TPM_BAD_TYPE", TPM_E_BASE + 52, +"Make identity blob not properly typed" }, +{ "TPM_INVALID_RESOURCE", TPM_E_BASE + 53, +"When saving context identified resource type does not match actual resource" }, +{ "TPM_NOTFIPS", TPM_E_BASE + 54, +"The TPM is attempting to execute a command only available when in FIPS mode" }, +{ "TPM_INVALID_FAMILY", TPM_E_BASE + 55, +"The command is attempting to use an invalid family ID" }, +{ "TPM_NO_NV_PERMISSION", TPM_E_BASE + 56, +"The permission to manipulate the NV storage is not available" }, +{ "TPM_REQUIRES_SIGN", TPM_E_BASE + 57, +"The operation requires a signed command" }, +{ "TPM_KEY_NOTSUPPORTED", TPM_E_BASE + 58, +"Wrong operation to load an NV key" }, +{ "TPM_AUTH_CONFLICT", TPM_E_BASE + 59, +"NV_LoadKey blob requires both owner and blob authorization" }, +{ "TPM_AREA_LOCKED", TPM_E_BASE + 60, +"The NV area is locked and not writable" }, +{ "TPM_BAD_LOCALITY", TPM_E_BASE + 61, +"The locality is incorrect for the attempted operation" }, +{ "TPM_READ_ONLY", TPM_E_BASE + 62, +"The NV area is read only and canât be written to" }, +{ "TPM_PER_NOWRITE", TPM_E_BASE + 63, +"There is no protection on the write to the NV area" }, +{ "TPM_FAMILYCOUNT", TPM_E_BASE + 64, +"The family count value does not match" }, +{ "TPM_WRITE_LOCKED", TPM_E_BASE + 65, +"The NV area has already been written to" }, +{ "TPM_BAD_ATTRIBUTES", TPM_E_BASE + 66, +"The NV area attributes conflict" }, +{ "TPM_INVALID_STRUCTURE", TPM_E_BASE + 67, +"The structure tag and version are invalid or inconsistent" }, +{ "TPM_KEY_OWNER_CONTROL", TPM_E_BASE + 68, +"The key is under control of the TPM Owner and can only be evicted\n\ +by the TPM Owner" }, +{ "TPM_BAD_COUNTER", TPM_E_BASE + 69, +"The counter handle is incorrect" }, +{ "TPM_NOT_FULLWRITE", TPM_E_BASE + 70, +"The write is not a complete write of the area" }, +{ "TPM_CONTEXT_GAP", TPM_E_BASE + 71, +"The gap between saved context counts is too large" }, +{ "TPM_MAXNVWRITES", TPM_E_BASE + 72, +"The maximum number of NV writes without an owner has been exceeded" }, +{ "TPM_NOOPERATOR", TPM_E_BASE + 73, +"No operator AuthData value is set" }, +{ "TPM_RESOURCEMISSING", TPM_E_BASE + 74, +"The resource pointed to by context is not loaded" }, +{ "TPM_DELEGATE_LOCK", TPM_E_BASE + 75, +"The delegate administration is locked" }, +{ "TPM_DELEGATE_FAMILY", TPM_E_BASE + 76, +"Attempt to manage a family other then the delegated family" }, +{ "TPM_DELEGATE_ADMIN", TPM_E_BASE + 77, +"Delegation table management not enabled" }, +{ "TPM_TRANSPORT_NOTEXCLUSIVE", TPM_E_BASE + 78, +"There was a command executed outside of an exclusive transport session" }, +{ "TPM_OWNER_CONTROL", TPM_E_BASE + 79, +"Attempt to context save a owner evict controlled key" }, +{ "TPM_DAA_RESOURCES", TPM_E_BASE + 80, +"The DAA command has no resources available to execute the command" }, +{ "TPM_DAA_INPUT_DATA0", TPM_E_BASE + 81, +"The consistency check on DAA parameter inputData0 has failed" }, +{ "TPM_DAA_INPUT_DATA1", TPM_E_BASE + 82, +"The consistency check on DAA parameter inputData1 has failed" }, +{ "TPM_DAA_ISSUER_SETTINGS", TPM_E_BASE + 83, +"The consistency check on DAA_issuerSettings has failed" }, +{ "TPM_DAA_TPM_SETTINGS", TPM_E_BASE + 84, +"The consistency check on DAA_tpmSpecific has failed" }, +{ "TPM_DAA_STAGE", TPM_E_BASE + 85, +"The atomic process indicated by the submitted DAA command is not\n\ +the expected process" }, +{ "TPM_DAA_ISSUER_VALIDITY", TPM_E_BASE + 86, +"The issuerâs validity check has detected an inconsistency" }, +{ "TPM_DAA_WRONG_W", TPM_E_BASE + 87, +"The consistency check on w has failed" }, +{ "TPM_BAD_HANDLE", TPM_E_BASE + 88, +"The handle is incorrect" }, +{ "TPM_BAD_DELEGATE", TPM_E_BASE + 89, +"Delegation is not correct" }, +{ "TPM_BADCONTEXT", TPM_E_BASE + 90, +"The context blob is invalid" }, +{ "TPM_TOOMANYCONTEXTS", TPM_E_BASE + 91, +"Too many contexts held by the TPM" }, +{ "TPM_MA_TICKET_SIGNATURE", TPM_E_BASE + 92, +"Migration authority signature validation failure" }, +{ "TPM_MA_DESTINATION", TPM_E_BASE + 93, +"Migration destination not authenticated" }, +{ "TPM_MA_SOURCE", TPM_E_BASE + 94, +"Migration source incorrect" }, +{ "TPM_MA_AUTHORITY", TPM_E_BASE + 95, +"Incorrect migration authority" }, +{ "TPM_PERMANENTEK", TPM_E_BASE + 97, +"Attempt to revoke the EK and the EK is not revocable" }, +{ "TPM_BAD_SIGNATURE", TPM_E_BASE + 98, +"Bad signature of CMK ticket" }, +{ "TPM_NOCONTEXTSPACE", TPM_E_BASE + 99, +"There is no room in the context list for additional contexts" }, +{ "TPM_RETRY", TPM_E_BASE + TPM_E_NON_FATAL, +"The TPM is too busy to respond to the command immediately, but\n\ +the command could be resubmitted at a later time. The TPM MAY\n\ +return TPM_RETRY for any command at any time" }, +{ "TPM_NEEDS_SELFTEST", TPM_E_BASE + TPM_E_NON_FATAL + 1, +"TPM_ContinueSelfTest has not been run" }, +{ "TPM_DOING_SELFTEST", TPM_E_BASE + TPM_E_NON_FATAL + 2, +"The TPM is currently executing the actions of TPM_ContinueSelfTest\n\ +because the ordinal required resources that have not been tested" }, +{ "TPM_DEFEND_LOCK_RUNNING", TPM_E_BASE + TPM_E_NON_FATAL + 3, +"The TPM is defending against dictionary attacks and is in some\n\ +time-out period" }, + }; + +#endif /* TPM_ERROR_MESSAGES_H */

1 0

Patch set updated for coreboot: d999087 lenovo/t430s: Add new port.
by Nicolas Reinecke 05 Feb '15

05 Feb '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8359 -gerrit commit d999087b5f6141eec78bf29950d2d3c3dfeba40b Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sat Jan 31 19:20:50 2015 +0100 lenovo/t430s: Add new port. The port is based on the x230 / t530. Tested - is in active use. Change-Id: Ic5ccfe70343e8aef3465690edce9cdebf153a44d Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/lenovo/Kconfig | 6 + src/mainboard/lenovo/t430s/Kconfig | 72 +++++++ src/mainboard/lenovo/t430s/Makefile.inc | 21 ++ src/mainboard/lenovo/t430s/acpi/ec.asl | 26 +++ src/mainboard/lenovo/t430s/acpi/platform.asl | 77 +++++++ src/mainboard/lenovo/t430s/acpi/superio.asl | 1 + src/mainboard/lenovo/t430s/acpi_tables.c | 64 ++++++ src/mainboard/lenovo/t430s/board_info.txt | 5 + src/mainboard/lenovo/t430s/cmos.default | 18 ++ src/mainboard/lenovo/t430s/cmos.layout | 167 +++++++++++++++ src/mainboard/lenovo/t430s/devicetree.cb | 172 ++++++++++++++++ src/mainboard/lenovo/t430s/dsdt.asl | 56 ++++++ src/mainboard/lenovo/t430s/gpio.c | 290 +++++++++++++++++++++++++++ src/mainboard/lenovo/t430s/hda_verb.c | 131 ++++++++++++ src/mainboard/lenovo/t430s/mainboard.c | 82 ++++++++ src/mainboard/lenovo/t430s/romstage.c | 73 +++++++ src/mainboard/lenovo/t430s/smihandler.c | 195 ++++++++++++++++++ src/mainboard/lenovo/t430s/thermal.h | 30 +++ 18 files changed, 1486 insertions(+) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index 30b1d36..95f7cfd 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -37,6 +37,11 @@ config BOARD_LENOVO_T420S help Lenovo T420s laptop. Consult wiki for details. +config BOARD_LENOVO_T430S + bool "ThinkPad T430s" + help + Lenovo T430s laptop. Consult wiki for details. + config BOARD_LENOVO_T520 bool "ThinkPad T520" help @@ -68,6 +73,7 @@ source "src/mainboard/lenovo/x201/Kconfig" source "src/mainboard/lenovo/x220/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t420s/Kconfig" +source "src/mainboard/lenovo/t430s/Kconfig" source "src/mainboard/lenovo/t520/Kconfig" source "src/mainboard/lenovo/t530/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig new file mode 100644 index 0000000..dbe08b5 --- /dev/null +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -0,0 +1,72 @@ +if BOARD_LENOVO_T430S + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SYSTEM_TYPE_LAPTOP + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + select SOUTHBRIDGE_INTEL_C216 + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select INTEL_INT15 + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select IVYBRIDGE_LVDS + select ENABLE_VMX + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default lenovo/t430s + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T430s" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x17aa + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x21fb + +endif # BOARD_LENOVO_T430S diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc new file mode 100644 index 0000000..265059a --- /dev/null +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +romstage-y += gpio.c diff --git a/src/mainboard/lenovo/t430s/acpi/ec.asl b/src/mainboard/lenovo/t430s/acpi/ec.asl new file mode 100644 index 0000000..4b3e72c --- /dev/null +++ b/src/mainboard/lenovo/t430s/acpi/ec.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +Scope(\_SB.PCI0.LPCB.EC) +{ +} diff --git a/src/mainboard/lenovo/t430s/acpi/platform.asl b/src/mainboard/lenovo/t430s/acpi/platform.asl new file mode 100644 index 0000000..f937dc5 --- /dev/null +++ b/src/mainboard/lenovo/t430s/acpi/platform.asl @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + + /* Not implemented. */ + Return(Package(){0,0}) +} diff --git a/src/mainboard/lenovo/t430s/acpi/superio.asl b/src/mainboard/lenovo/t430s/acpi/superio.asl new file mode 100644 index 0000000..03b65bc --- /dev/null +++ b/src/mainboard/lenovo/t430s/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t430s/acpi_tables.c b/src/mainboard/lenovo/t430s/acpi_tables.c new file mode 100644 index 0000000..407c8f9 --- /dev/null +++ b/src/mainboard/lenovo/t430s/acpi_tables.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpigen.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} diff --git a/src/mainboard/lenovo/t430s/board_info.txt b/src/mainboard/lenovo/t430s/board_info.txt new file mode 100644 index 0000000..2d10440 --- /dev/null +++ b/src/mainboard/lenovo/t430s/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM package: SOIC-8 / WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default new file mode 100644 index 0000000..137f482 --- /dev/null +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +hyper_threading=Enable +backlight=Both \ No newline at end of file diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout new file mode 100644 index 0000000..696c338 --- /dev/null +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -0,0 +1,167 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +#419 2 r 0 unused +421 1 e 9 sata_mode +422 2 e 10 backlight + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb new file mode 100644 index 0000000..e2ae392 --- /dev/null +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -0,0 +1,172 @@ +chip northbridge/intel/sandybridge + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms + register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms + register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms + register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "1" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x11551155" + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + # Coordinate with HW_ALL + register "pstate_coord_type" = "0xfe" + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device domain 0 on + device pci 00.0 on + subsystemid 0x17aa 0x21fb + end # host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on + subsystemid 0x17aa 0x21fb + end # Integrated Graphics Controller + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "alt_gp_smi_en" = "0x0000" + register "gpi1_routing" = "2" + register "gpi13_routing" = "2" + + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) + register "sata_port_map" = "0x17" + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen4_dec" = "0x0c06a1" + + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported + register "p_cnt_throttling_supported" = "1" + + device pci 14.0 on + subsystemid 0x17aa 0x21fb + end # USB 3.0 Controller + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on + subsystemid 0x17aa 0x21f3 + end # Intel Gigabit Ethernet + device pci 1a.0 on + subsystemid 0x17aa 0x21fb + end # USB Enhanced Host Controller #2 + device pci 1b.0 on + subsystemid 0x17aa 0x21fb + end # High Definition Audio Controller + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 on + subsystemid 0x17aa 0x21fb + end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.2 on + subsystemid 0x17aa 0x21fb + end # PCIe Port #3 ExpressCard + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on + subsystemid 0x17aa 0x21fb + end # USB Enhanced Host Controller #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + subsystemid 0x17aa 0x21fb + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa7" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0xe2" + + register "has_keyboard_backlight" = "1" + + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "has_power_management_beeps" = "0" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0x3c" + register "event6_enable" = "0x00" + register "event7_enable" = "0x01" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x00" + register "eventb_enable" = "0x00" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + end + end # LPC Controller + device pci 1f.2 on + subsystemid 0x17aa 0x21fb + end # 6 port SATA AHCI Controller + device pci 1f.3 on + subsystemid 0x17aa 0x21fb + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end # SMBus Controller + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on + subsystemid 0x17aa 0x21fb + end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl new file mode 100644 index 0000000..85e2b4f --- /dev/null +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define HAVE_LCD_SCREEN 1 + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/t430s/gpio.c b/src/mainboard/lenovo/t430s/gpio.c new file mode 100644 index 0000000..a1c345c --- /dev/null +++ b/src/mainboard/lenovo/t430s/gpio.c @@ -0,0 +1,290 @@ +#include "southbridge/intel/bd82x6x/gpio.h" +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, // OC5 - -USB_PORT9_OC5 - input + .gpio10 = GPIO_MODE_GPIO, // DRAMRST_GATE_ON - output + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, // -EC_WAKE - input + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, // OC1 -USB_PORT1_OC1 - input + .gpio41 = GPIO_MODE_NATIVE, // OC2 - pullup + .gpio42 = GPIO_MODE_NATIVE, // OC3 -USB_PORT2_OC3 - input + .gpio43 = GPIO_MODE_GPIO, // SMB_3B_EN - output + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, // OC0 -USB_PORT0_OC0 - input + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + .blink = &pch_gpio_set1_blink, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/lenovo/t430s/hda_verb.c b/src/mainboard/lenovo/t430s/hda_verb.c new file mode 100644 index 0000000..232b9c2 --- /dev/null +++ b/src/mainboard/lenovo/t430s/hda_verb.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Vendor Name : Realtek + * Vendor ID : 0x10ec0269 + * Subsystem ID : 0x17aa21fb + * Revision ID : 0x100203 + */ + + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC + 0x17aa21fb, // Subsystem ID + 0x00000013, // Number of 4 dword sets + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +/* NID 0x01 - NodeInfo */ + AZALIA_SUBVENDOR(0x0, 0x17AA21FB), + +/* NID 0x0A - External Microphone Connector + * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020), + +/* NID 0x0B - Headphone Connector + * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F), + +/* NID 0x0C - Not connected + * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0), + +/* NID 0x0D - Internal Speakers + * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110), + +/* NID 0x0F - Not connected + * Config=0x40F000F0 + */ + AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0), + +/* NID 0x11 - Internal Microphone + * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111F0), + AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830), + AZALIA_PIN_CFG(0x0, 0x19, 0x411111F0), + + 0x01970804, + 0x01870803, + 0x01470740, + 0x00970600, + + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111F0), + AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205), + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0), + + /* Misc entries */ + 0x00370600, + 0x00270600, + 0x00B707C0, /* Enable PortB as Output with HP amp */ + 0x00D70740, /* Enable PortD as Output */ + 0x0017A200, /* Disable ClkEn of PortSenseTst */ + 0x0017C621, /* Slave Port - Port A used as microphone input for + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ + 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x00170500, /* Set power state to D0 */ + + /* --- Next Codec --- */ + +/* Vendor Name : Intel + * Vendor ID : 0x80862806 + * Subsystem ID : 0x80860101 + * Revision ID : 0x100000 + */ + /* coreboot specific header */ + 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of IDs + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) +}; + +const u32 pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t430s/mainboard.c b/src/mainboard/lenovo/t430s/mainboard.c new file mode 100644 index 0000000..359de8c --- /dev/null +++ b/src/mainboard/lenovo/t430s/mainboard.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <drivers/intel/gma/int15.h> +#include <arch/acpi.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <pc80/keyboard.h> +#include <ec/lenovo/h8/h8.h> +#include <version.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +const char *smbios_mainboard_bios_version(void) +{ + static char *s = NULL; + + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + + if (s != NULL) + return s; + s = strconcat("CBET4000 ", coreboot_version); + return s; +} + +static void mainboard_init(device_t dev) +{ + /* init spi */ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + + pc_keyboard_init(); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +void h8_mainboard_init_dock(void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c new file mode 100644 index 0000000..d518fb4 --- /dev/null +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +void pch_enable_lpc(void) +{ + /* EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000); +} + +void rcba_config(void) +{ + /* Disable unused devices (board specific) */ + RCBA32(FD) = 0x17e81fe3; + RCBA32(BUC) = 0; +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, /* P0: , OC 0 */ + { 1, 1, 1 }, /* P1: (EHCI debug), OC 1 */ + { 1, 1, 3 }, /* P2: OC 3 */ + { 1, 0, -1 }, /* P3: no OC */ + { 1, 2, -1 }, /* P4: no OC */ + { 1, 1, -1 }, /* P5: no OC */ + { 1, 1, -1 }, /* P6: no OC */ + { 0, 1, -1 }, /* P7: empty, no OC */ + { 1, 1, -1 }, /* P8: smart card reader, no OC */ + { 1, 0, 5 }, /* P9: (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 0, 0, -1 }, /* P12: wlan, no OC */ + { 1, 1, -1 }, /* P13: camera, no OC */ +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x51); +} diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c new file mode 100644 index 0000000..b384a73 --- /dev/null +++ b/src/mainboard/lenovo/t430s/smihandler.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> + +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +static void mainboard_smi_brightness_up(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); +} + +static void mainboard_smi_brightness_down(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, + (value - 0x10) & 0xf0); +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); + + switch (event) { + case 0x14: + /* brightness up */ + mainboard_smi_brightness_up(); + break; + case 0x15: + /* brightness down */ + mainboard_smi_brightness_down(); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, + data); + + if (!pmbase) + return 0; + + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI), + pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + u32 gpe_rout; + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + /* Enable EC WAKE GPE. */ + outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN); + gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + /* Redirect EC WAKE GPE to SCI. */ + gpe_rout &= ~(3 << (GPE_EC_WAKE * 2)); + gpe_rout |= (2 << (GPE_EC_WAKE * 2)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + } + } +} diff --git a/src/mainboard/lenovo/t430s/thermal.h b/src/mainboard/lenovo/t430s/thermal.h new file mode 100644 index 0000000..11d3917 --- /dev/null +++ b/src/mainboard/lenovo/t430s/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef T430S_THERMAL_H +#define T430S_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* T430S_THERMAL_H */

1 0

New patch to review for coreboot: 73604a4 mainboards/asus/kfsn4-dre: Indicate native text mode init support
by Timothy Pearson 05 Feb '15

05 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8369 -gerrit commit 73604a46a176e4fea0437db95998d039eb1ab8cc Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 11:03:36 2015 -0600 mainboards/asus/kfsn4-dre: Indicate native text mode init support Change-Id: Ib00ecdcad17fa5c0300d22378837e36d0918f9db Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index c16440d..f2530e5 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT_DEFAULT select DRIVERS_XGI_Z9S select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG config MAINBOARD_DIR string

1 0

Patch set updated for coreboot: 005f378 payloads/seabios: Enable SeaVGABIOS option if native text init supported
by Timothy Pearson 05 Feb '15

05 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8368 -gerrit commit 005f3788913d03060f67851ab3b94f330498ca0c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 10:47:40 2015 -0600 payloads/seabios: Enable SeaVGABIOS option if native text init supported SeaVGABIOS supports both the coreboot linear framebuffer and native EGA text mode. To use SeaBIOS interactively on standard VGA hardware a VBIOS is needed; SeaVGABIOS is one such option. TEST: Booted KFSN4-DRE with XGI Volari Z9s and SeaVGABIOS. Was able to interact with SeaBIOS and comboot menu, then booted linux successfully. VGA display was continuously usable from power on to Linux login. Change-Id: Id4bd4cb5cece9114457633832c5f0e5280c02b47 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index e5dc26b..4c80f34 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -661,7 +661,7 @@ config SEABIOS_MALLOC_UPPERMEMORY config SEABIOS_VGA_COREBOOT prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS default n - depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT + depends on !VGA_BIOS && (MAINBOARD_DO_NATIVE_VGA_INIT || MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG) bool help Coreboot can initialize the GPU of some mainboards.

1 0

New patch to review for coreboot: 5e61d5d payloads/seabios: Enable SeaVGABIOS option if native text init supported
by Timothy Pearson 05 Feb '15

05 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8368 -gerrit commit 5e61d5dfeb5112e5338f580b01a92938f2bb065c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 10:47:40 2015 -0600 payloads/seabios: Enable SeaVGABIOS option if native text init supported SeaVGABIOS supports both the coreboot linear framebuffer and native EGA text mode. To use SeaBIOS interactively on standard VGA hardware a VBIOS is needed; SeaVGABIOS is one such option. TEST: Booted KFSN4-DRE with XGI Volari Z9s and SeaVGABIOS. Was able to interact with SeaBIOS and comboot menu, then booted linux successfully. VGA display was continuously usable from power on to Linux login. Change-Id: Id4bd4cb5cece9114457633832c5f0e5280c02b47 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/Kconfig | 2 +- src/mainboard/asus/kfsn4-dre/Kconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index e5dc26b..4c80f34 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -661,7 +661,7 @@ config SEABIOS_MALLOC_UPPERMEMORY config SEABIOS_VGA_COREBOOT prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS default n - depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT + depends on !VGA_BIOS && (MAINBOARD_DO_NATIVE_VGA_INIT || MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG) bool help Coreboot can initialize the GPU of some mainboards. diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index c16440d..f2530e5 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT_DEFAULT select DRIVERS_XGI_Z9S select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG config MAINBOARD_DIR string

1 0

Patch set updated for coreboot: 230cbf1 drivers/xgi: Fix legacy VGA text mode initialization
by Timothy Pearson 05 Feb '15

05 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8360 -gerrit commit 230cbf17e1f792cb9a27241ed20ff423db5e2ef8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 01:02:57 2015 -0600 drivers/xgi: Fix legacy VGA text mode initialization TEST: Booted KFSN4-DRE with on-board XGI Volari Z9s Initial text from coreboot appeared, and the Linux console was displayed immediately at the start of kernel initialization. After boot was complete the text mode console continued to behave normally. SeaBIOS does not currently make use of the legacy VGA text-mode display. Change-Id: I2177a1d00e6f07db661dd99fe0184e2c228404d1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/xgi/common/vb_init.c | 6 +++++- src/drivers/xgi/common/xgi_coreboot.c | 27 +++++++++++++++++++-------- src/drivers/xgi/common/xgi_coreboot.h | 2 ++ 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c index 2b81605..a2fbc80 100644 --- a/src/drivers/xgi/common/vb_init.c +++ b/src/drivers/xgi/common/vb_init.c @@ -1,8 +1,11 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * * File taken from the Linux xgifb driver (v3.18.5) * Coreboot-specific includes added at top + * XGINew_SetDRAMSize_340 slightly modified for coreboot text mode * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -854,7 +857,8 @@ static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info, pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress; - XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e); data = xgifb_reg_get(pVBInfo->P3c4, 0x21); /* disable read cache */ diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index 84ed81a..a4abe71 100755 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -123,12 +123,14 @@ int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) xgifb_info->video_size = video_size_max; } - /* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */ - xgifb_reg_or(XGISR, - IND_SIS_PCI_ADDRESS_SET, - (SIS_PCI_ADDR_ENABLE | SIS_MEM_MAP_IO_ENABLE)); - /* Enable 2D accelerator engine */ - xgifb_reg_or(XGISR, IND_SIS_MODULE_ENABLE, SIS_ENABLE_2D); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + /* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */ + xgifb_reg_or(XGISR, + IND_SIS_PCI_ADDRESS_SET, + (SIS_PCI_ADDR_ENABLE | SIS_MEM_MAP_IO_ENABLE)); + /* Enable 2D accelerator engine */ + xgifb_reg_or(XGISR, IND_SIS_MODULE_ENABLE, SIS_ENABLE_2D); + } hw_info->ulVideoMemorySize = xgifb_info->video_size; @@ -265,7 +267,10 @@ int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) xgifb_info->mode_idx = XGIfb_GetXG21DefaultLVDSModeIdx(xgifb_info); else - xgifb_info->mode_idx = DEFAULT_MODE; + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + xgifb_info->mode_idx = DEFAULT_MODE; + else + xgifb_info->mode_idx = DEFAULT_TEXT_MODE; } if (xgifb_info->mode_idx < 0) { @@ -406,10 +411,16 @@ int xgifb_modeset(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) } #else /* FIXME - * Text mode does not work + * Text mode is slightly unstable/jittery (bad/incomplete DDR init?) */ + + /* Initialize standard VGA text mode */ vga_io_init(); vga_textmode_init(); + printk(BIOS_INFO, "XGI VGA text mode initialized\n"); + + /* if we don't have console, at least print something... */ + vga_line_write(0, "XGI VGA text mode initialized"); #endif return 0; diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h index 524615c..b616751 100644 --- a/src/drivers/xgi/common/xgi_coreboot.h +++ b/src/drivers/xgi/common/xgi_coreboot.h @@ -208,6 +208,8 @@ enum _SIS_LCD_TYPE { /* End code taken from Linux kernel 3.18.5 */ +#define DEFAULT_TEXT_MODE 16 /* index for 800x600x8 */ + /* coreboot <--> kernel code interface */ #define __iomem #define SISIOMEMTYPE

1 0

Patch set updated for coreboot: e865a96 drivers/xgi: Fix user-visible typo in printk
by Timothy Pearson 05 Feb '15

05 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8361 -gerrit commit e865a96cf311ca3403b1d5ccf25fa6b66d5a44c5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 01:02:09 2015 -0600 drivers/xgi: Fix user-visible typo in printk Change-Id: I1e4c5c807d4a78844a40083178b6f96ffeb3659e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/xgi/common/XGI_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/xgi/common/XGI_main.c b/src/drivers/xgi/common/XGI_main.c index c76ebf7..6c832aa 100644 --- a/src/drivers/xgi/common/XGI_main.c +++ b/src/drivers/xgi/common/XGI_main.c @@ -115,7 +115,7 @@ static int XGIfb_get_dram_size(struct xgifb_video_info *xgifb_info) xgifb_info->video_size = xgifb_info->video_size * ChannelNum; - pr_info("SR14=%x DramSzie %x ChannelNum %x\n", + pr_info("SR14=%x DramSize %x ChannelNum %x\n", reg, xgifb_info->video_size, ChannelNum); return 0;

1 0

Patch merged into coreboot/master: 67085e0 mainboards/asus/kfsn4-dre: Enable native VGA initialization
by gerrit＠coreboot.org 05 Feb '15

05 Feb '15

the following patch was just integrated into master: commit 67085e0c09825ffabd208faf9e8e19abd0b702d9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 3 00:19:01 2015 -0600 mainboards/asus/kfsn4-dre: Enable native VGA initialization Change-Id: I953ced7d34af9ec0923fa6df93b9ad4270196c77 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8332 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8332 for details. -gerrit

1 0

← Newer
1
...
34
35
36
37
38
39
40
...
51
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2015