coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 870390b drivers/xgi: Fix legacy VGA text mode initialization
by Timothy Pearson 06 Feb '15

06 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8360 -gerrit commit 870390b59d7c977d33f2756c1198e4fb2b7b4442 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 01:02:57 2015 -0600 drivers/xgi: Fix legacy VGA text mode initialization TEST: Booted KFSN4-DRE with on-board XGI Volari Z9s Initial text from coreboot appeared, and the Linux console was displayed immediately at the start of kernel initialization. After boot was complete the text mode console continued to behave normally. SeaBIOS does not currently make use of the legacy VGA text-mode display. Change-Id: I2177a1d00e6f07db661dd99fe0184e2c228404d1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/xgi/common/vb_init.c | 6 +++++- src/drivers/xgi/common/xgi_coreboot.c | 27 +++++++++++++++++++-------- src/drivers/xgi/common/xgi_coreboot.h | 2 ++ src/drivers/xgi/z9s/z9s.c | 11 ++++++++++- 4 files changed, 36 insertions(+), 10 deletions(-) diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c index 2b81605..a2fbc80 100644 --- a/src/drivers/xgi/common/vb_init.c +++ b/src/drivers/xgi/common/vb_init.c @@ -1,8 +1,11 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * * File taken from the Linux xgifb driver (v3.18.5) * Coreboot-specific includes added at top + * XGINew_SetDRAMSize_340 slightly modified for coreboot text mode * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -854,7 +857,8 @@ static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info, pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress; - XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e); data = xgifb_reg_get(pVBInfo->P3c4, 0x21); /* disable read cache */ diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index 84ed81a..a4abe71 100755 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -123,12 +123,14 @@ int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) xgifb_info->video_size = video_size_max; } - /* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */ - xgifb_reg_or(XGISR, - IND_SIS_PCI_ADDRESS_SET, - (SIS_PCI_ADDR_ENABLE | SIS_MEM_MAP_IO_ENABLE)); - /* Enable 2D accelerator engine */ - xgifb_reg_or(XGISR, IND_SIS_MODULE_ENABLE, SIS_ENABLE_2D); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + /* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */ + xgifb_reg_or(XGISR, + IND_SIS_PCI_ADDRESS_SET, + (SIS_PCI_ADDR_ENABLE | SIS_MEM_MAP_IO_ENABLE)); + /* Enable 2D accelerator engine */ + xgifb_reg_or(XGISR, IND_SIS_MODULE_ENABLE, SIS_ENABLE_2D); + } hw_info->ulVideoMemorySize = xgifb_info->video_size; @@ -265,7 +267,10 @@ int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) xgifb_info->mode_idx = XGIfb_GetXG21DefaultLVDSModeIdx(xgifb_info); else - xgifb_info->mode_idx = DEFAULT_MODE; + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + xgifb_info->mode_idx = DEFAULT_MODE; + else + xgifb_info->mode_idx = DEFAULT_TEXT_MODE; } if (xgifb_info->mode_idx < 0) { @@ -406,10 +411,16 @@ int xgifb_modeset(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) } #else /* FIXME - * Text mode does not work + * Text mode is slightly unstable/jittery (bad/incomplete DDR init?) */ + + /* Initialize standard VGA text mode */ vga_io_init(); vga_textmode_init(); + printk(BIOS_INFO, "XGI VGA text mode initialized\n"); + + /* if we don't have console, at least print something... */ + vga_line_write(0, "XGI VGA text mode initialized"); #endif return 0; diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h index 524615c..b616751 100644 --- a/src/drivers/xgi/common/xgi_coreboot.h +++ b/src/drivers/xgi/common/xgi_coreboot.h @@ -208,6 +208,8 @@ enum _SIS_LCD_TYPE { /* End code taken from Linux kernel 3.18.5 */ +#define DEFAULT_TEXT_MODE 16 /* index for 800x600x8 */ + /* coreboot <--> kernel code interface */ #define __iomem #define SISIOMEMTYPE diff --git a/src/drivers/xgi/z9s/z9s.c b/src/drivers/xgi/z9s/z9s.c index 095489e..eaf04df 100644 --- a/src/drivers/xgi/z9s/z9s.c +++ b/src/drivers/xgi/z9s/z9s.c @@ -31,6 +31,15 @@ #include "../common/xgi_coreboot.h" #include "../common/XGIfb.h" +static void xgi_z9s_set_resources(device_t dev) +{ + /* Reserve VGA regions */ + mmio_resource(dev, 3, 0xa0000 >> 10, 0x1ffff >> 10); + + /* Run standard resource set routine */ + pci_dev_set_resources(dev); +} + static void xgi_z9s_init(struct device *dev) { u8 ret; @@ -46,7 +55,7 @@ static void xgi_z9s_init(struct device *dev) static struct device_operations xgi_z9s_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = xgi_z9s_set_resources, .enable_resources = pci_dev_enable_resources, .init = xgi_z9s_init, .scan_bus = 0,

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Patch set updated for coreboot: 393120b drivers/xgi: Fix user-visible typo in printk
by Timothy Pearson 06 Feb '15

06 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8361 -gerrit commit 393120bea89c11b0caa5971c3a1be9a6a59914f4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 01:02:09 2015 -0600 drivers/xgi: Fix user-visible typo in printk Change-Id: I1e4c5c807d4a78844a40083178b6f96ffeb3659e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/xgi/common/XGI_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/xgi/common/XGI_main.c b/src/drivers/xgi/common/XGI_main.c index c76ebf7..6c832aa 100644 --- a/src/drivers/xgi/common/XGI_main.c +++ b/src/drivers/xgi/common/XGI_main.c @@ -115,7 +115,7 @@ static int XGIfb_get_dram_size(struct xgifb_video_info *xgifb_info) xgifb_info->video_size = xgifb_info->video_size * ChannelNum; - pr_info("SR14=%x DramSzie %x ChannelNum %x\n", + pr_info("SR14=%x DramSize %x ChannelNum %x\n", reg, xgifb_info->video_size, ChannelNum); return 0;

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Patch set updated for coreboot: 6e21a71 mainboards/asus/kfsn4-dre: Indicate native text mode init support
by Timothy Pearson 06 Feb '15

06 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8369 -gerrit commit 6e21a716c2218bc947d0e7c56f6340956203529b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 11:03:36 2015 -0600 mainboards/asus/kfsn4-dre: Indicate native text mode init support Change-Id: Ib00ecdcad17fa5c0300d22378837e36d0918f9db Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index c16440d..f2530e5 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT_DEFAULT select DRIVERS_XGI_Z9S select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG config MAINBOARD_DIR string

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Patch set updated for coreboot: ff3312d payloads/seabios: Enable SeaVGABIOS option if native text init supported
by Timothy Pearson 06 Feb '15

06 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8368 -gerrit commit ff3312dc1b6a6cd834351deea24c6403b6e7ee83 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 10:47:40 2015 -0600 payloads/seabios: Enable SeaVGABIOS option if native text init supported SeaVGABIOS supports both the coreboot linear framebuffer and native EGA text mode. To use SeaBIOS interactively on standard VGA hardware a VBIOS is needed; SeaVGABIOS is one such option. TEST: Booted KFSN4-DRE with XGI Volari Z9s and SeaVGABIOS. Was able to interact with SeaBIOS and comboot menu, then booted Linux successfully. VGA display was continuously usable from power on to Linux login. Change-Id: Id4bd4cb5cece9114457633832c5f0e5280c02b47 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index e5dc26b..4c80f34 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -661,7 +661,7 @@ config SEABIOS_MALLOC_UPPERMEMORY config SEABIOS_VGA_COREBOOT prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS default n - depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT + depends on !VGA_BIOS && (MAINBOARD_DO_NATIVE_VGA_INIT || MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG) bool help Coreboot can initialize the GPU of some mainboards.

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Patch set updated for coreboot: 75aedec drivers/xgi: Fix legacy VGA text mode initialization
by Timothy Pearson 06 Feb '15

06 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8360 -gerrit commit 75aedeca4c1fafb0967ff08110351c83465f18bf Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 01:02:57 2015 -0600 drivers/xgi: Fix legacy VGA text mode initialization TEST: Booted KFSN4-DRE with on-board XGI Volari Z9s Initial text from coreboot appeared, and the Linux console was displayed immediately at the start of kernel initialization. After boot was complete the text mode console continued to behave normally. SeaBIOS does not currently make use of the legacy VGA text-mode display. Change-Id: I2177a1d00e6f07db661dd99fe0184e2c228404d1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/xgi/common/vb_init.c | 6 +++++- src/drivers/xgi/common/xgi_coreboot.c | 27 +++++++++++++++++++-------- src/drivers/xgi/common/xgi_coreboot.h | 2 ++ src/drivers/xgi/z9s/z9s.c | 15 ++++++++++++++- 4 files changed, 40 insertions(+), 10 deletions(-) diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c index 2b81605..a2fbc80 100644 --- a/src/drivers/xgi/common/vb_init.c +++ b/src/drivers/xgi/common/vb_init.c @@ -1,8 +1,11 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * * File taken from the Linux xgifb driver (v3.18.5) * Coreboot-specific includes added at top + * XGINew_SetDRAMSize_340 slightly modified for coreboot text mode * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -854,7 +857,8 @@ static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info, pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress; - XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e); data = xgifb_reg_get(pVBInfo->P3c4, 0x21); /* disable read cache */ diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index 84ed81a..a4abe71 100755 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -123,12 +123,14 @@ int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) xgifb_info->video_size = video_size_max; } - /* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */ - xgifb_reg_or(XGISR, - IND_SIS_PCI_ADDRESS_SET, - (SIS_PCI_ADDR_ENABLE | SIS_MEM_MAP_IO_ENABLE)); - /* Enable 2D accelerator engine */ - xgifb_reg_or(XGISR, IND_SIS_MODULE_ENABLE, SIS_ENABLE_2D); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + /* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */ + xgifb_reg_or(XGISR, + IND_SIS_PCI_ADDRESS_SET, + (SIS_PCI_ADDR_ENABLE | SIS_MEM_MAP_IO_ENABLE)); + /* Enable 2D accelerator engine */ + xgifb_reg_or(XGISR, IND_SIS_MODULE_ENABLE, SIS_ENABLE_2D); + } hw_info->ulVideoMemorySize = xgifb_info->video_size; @@ -265,7 +267,10 @@ int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) xgifb_info->mode_idx = XGIfb_GetXG21DefaultLVDSModeIdx(xgifb_info); else - xgifb_info->mode_idx = DEFAULT_MODE; + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + xgifb_info->mode_idx = DEFAULT_MODE; + else + xgifb_info->mode_idx = DEFAULT_TEXT_MODE; } if (xgifb_info->mode_idx < 0) { @@ -406,10 +411,16 @@ int xgifb_modeset(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) } #else /* FIXME - * Text mode does not work + * Text mode is slightly unstable/jittery (bad/incomplete DDR init?) */ + + /* Initialize standard VGA text mode */ vga_io_init(); vga_textmode_init(); + printk(BIOS_INFO, "XGI VGA text mode initialized\n"); + + /* if we don't have console, at least print something... */ + vga_line_write(0, "XGI VGA text mode initialized"); #endif return 0; diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h index 524615c..b616751 100644 --- a/src/drivers/xgi/common/xgi_coreboot.h +++ b/src/drivers/xgi/common/xgi_coreboot.h @@ -208,6 +208,8 @@ enum _SIS_LCD_TYPE { /* End code taken from Linux kernel 3.18.5 */ +#define DEFAULT_TEXT_MODE 16 /* index for 800x600x8 */ + /* coreboot <--> kernel code interface */ #define __iomem #define SISIOMEMTYPE diff --git a/src/drivers/xgi/z9s/z9s.c b/src/drivers/xgi/z9s/z9s.c index 095489e..04c4563 100644 --- a/src/drivers/xgi/z9s/z9s.c +++ b/src/drivers/xgi/z9s/z9s.c @@ -31,6 +31,19 @@ #include "../common/xgi_coreboot.h" #include "../common/XGIfb.h" +static void xgi_z9s_set_resources(device_t dev) +{ + /* Reserve standard VGA regions */ + mmio_resource(dev, 3, 0xa0000 >> 10, 0xffff >> 10); + mmio_resource(dev, 4, 0xb8000 >> 10, 0x7fff >> 10); + + /* Reserve non-standard VGA regions */ + mmio_resource(dev, 5, 0xb0000 >> 10, 0x7fff >> 10); + + /* Run standard resource set routine */ + pci_dev_set_resources(dev); +} + static void xgi_z9s_init(struct device *dev) { u8 ret; @@ -46,7 +59,7 @@ static void xgi_z9s_init(struct device *dev) static struct device_operations xgi_z9s_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = xgi_z9s_set_resources, .enable_resources = pci_dev_enable_resources, .init = xgi_z9s_init, .scan_bus = 0,

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Patch set updated for coreboot: f2326a1 drivers/xgi: Fix user-visible typo in printk
by Timothy Pearson 06 Feb '15

06 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8361 -gerrit commit f2326a1cbc9b6d64cfaabb78ce0d0ef2ea9bd9e9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 01:02:09 2015 -0600 drivers/xgi: Fix user-visible typo in printk Change-Id: I1e4c5c807d4a78844a40083178b6f96ffeb3659e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/xgi/common/XGI_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/xgi/common/XGI_main.c b/src/drivers/xgi/common/XGI_main.c index c76ebf7..6c832aa 100644 --- a/src/drivers/xgi/common/XGI_main.c +++ b/src/drivers/xgi/common/XGI_main.c @@ -115,7 +115,7 @@ static int XGIfb_get_dram_size(struct xgifb_video_info *xgifb_info) xgifb_info->video_size = xgifb_info->video_size * ChannelNum; - pr_info("SR14=%x DramSzie %x ChannelNum %x\n", + pr_info("SR14=%x DramSize %x ChannelNum %x\n", reg, xgifb_info->video_size, ChannelNum); return 0;

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Patch merged into coreboot/master: 114baa0 intel/fsp_rangeley: Indent '#define' consistently
by gerrit＠coreboot.org 06 Feb '15

06 Feb '15

the following patch was just integrated into master: commit 114baa0a0ad8132964d8c60bd9583c339b6fcc51 Author: York Yang <york.yang(a)intel.com> Date: Tue Feb 3 14:14:42 2015 -0700 intel/fsp_rangeley: Indent '#define' consistently The indentations of #define are not consistent in chip.h. Update to make all #define indentations being aligned and put them after the variable declaration. Change-Id: I37550acac18bac3efddb580ef6b956be0e2b357a Signed-off-by: York Yang <york.yang(a)intel.com> Reviewed-on: http://review.coreboot.org/8333 Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8333 for details. -gerrit

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Patch set updated for coreboot: bdb8287 fsp_baytrail: Get FSP reserved memory from the FSP HOB list
by Martin Roth 06 Feb '15

06 Feb '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8308 -gerrit commit bdb82874f0d8801c075c458ba0af8ef9f4008694 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jan 30 20:56:05 2015 -0700 fsp_baytrail: Get FSP reserved memory from the FSP HOB list Because the pointer to the FSP HOB list is now being saved, we can use that to find the top of usable memory. This eliminates the need to hardcode the size of the FSP reserved memory area. Tested on minnowboard max for baytrail. The HOB structure used does not seem to be present for the rangeley or ivybridge/pantherpoint FSPs. At the very least, the GUID is not documented in the integration guides. Change-Id: I643e57655f55bfada60075b55aad2ce010ec4f67 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/intel/fsp/fsp_util.c | 20 ++++++++++++++++++++ src/drivers/intel/fsp/fsp_util.h | 1 + src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 2 -- src/soc/intel/fsp_baytrail/memmap.c | 15 +++++++-------- src/soc/intel/fsp_baytrail/northcluster.c | 7 +------ 5 files changed, 29 insertions(+), 16 deletions(-) diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 0844b37..2a53c25 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -195,6 +195,26 @@ void * find_saved_temp_mem(void *hob_list_ptr) return (void *) ((char *) saved_mem_hob + sizeof(EFI_HOB_GUID_TYPE)); } +#ifndef FSP_RESERVE_MEMORY_SIZE +/** @brief locates the HOB containing the location of the fsp reserved mem area + * + * @param hob_list_ptr pointer to the start of the hob list + * @return pointer to the start of the FSP reserved memory or NULL if not found. + */ +void * find_fsp_reserved_mem(void *hob_list_ptr) +{ + EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; + EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem = + (EFI_HOB_RESOURCE_DESCRIPTOR *) find_hob_by_guid( + hob_list_ptr, &fsp_reserved_guid); + + if (fsp_reserved_mem == NULL) + return NULL; + + return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart); +} +#endif /* FSP_RESERVE_MEMORY_SIZE */ + #ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ void print_fsp_info(void) { diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h index a39f5a2..d65b842 100644 --- a/src/drivers/intel/fsp/fsp_util.h +++ b/src/drivers/intel/fsp/fsp_util.h @@ -38,6 +38,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, FSP_INFO_HEADER *fsp_ptr); void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr); void * find_saved_temp_mem(void *hob_list_ptr); +void * find_fsp_reserved_mem(void *hob_list_ptr); /* functions in hob.c */ void print_hob_mem_attributes(void *Hobptr); diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h index 1f4fa74..29309bf 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -32,8 +32,6 @@ #include <fspvpd.h> #include <azalia.h> -#define FSP_RESERVE_MEMORY_SIZE 0x200000 - #define FSP_INFO_HEADER_GUID \ { \ 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 615916b..8a10ac8 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -29,18 +29,17 @@ uintptr_t smm_region_start(void) return (iosf_bunit_read(BUNIT_SMRRL) << 20); } -/* - * Calculate the top of usable (low) DRAM. - * The FSP's reserved memory sits just below the SMM region, - * allowing calculation of the top of usable memory. +/** @brief get the top of usable low memory from the FSP's HOB list + * + * The FSP's reserved memory sits just below the SMM region. The memory + * region below it is usable memory. * * The entire memory map is shown in northcluster.c + * + * @return pointer to the first byte of reserved memory */ void *cbmem_top(void) { - uintptr_t tom = smm_region_start(); - if (!tom) - tom = iosf_bunit_read(BUNIT_BMBOUND); - return (void *) tom - FSP_RESERVE_MEMORY_SIZE; + return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..b288388 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -149,8 +149,7 @@ static void mc_add_dram_resources(device_t dev) uint32_t fsp_mem_base = 0; GetHighMemorySize(&highmem_size); - GetLowMemorySize(&fsp_mem_base); - + fsp_mem_base=(uint32_t)cbmem_top(); bmbound = iosf_bunit_read(BUNIT_BMBOUND); bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; @@ -162,10 +161,6 @@ static void mc_add_dram_resources(device_t dev) printk(BIOS_DEBUG, "FSP memory location: 0x%x\nFSP memory size: %dM\n", fsp_mem_base, (bsmmrrl - fsp_mem_base) >> 20); - - if ((bsmmrrl - fsp_mem_base ) != FSP_RESERVE_MEMORY_SIZE) - printk(BIOS_WARNING, "Warning: Fsp memory size does not match " - "expected memory size (%x).\n", FSP_RESERVE_MEMORY_SIZE); } printk(BIOS_INFO, "Available memory below 4GB: 0x%08x (%dM)\n",

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Patch merged into coreboot/master: 582b2ae FSP & CBMEM: Fix broken cbmem CAR transition.
by gerrit＠coreboot.org 06 Feb '15

06 Feb '15

the following patch was just integrated into master: commit 582b2aee0f5ac84339853551cca1f4d21e1e3fca Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:29:29 2015 -0700 FSP & CBMEM: Fix broken cbmem CAR transition. 1) Save the pointer to the FSP HOB list to low memory at address 0x614. This is the same location as CBMEM_RESUME_BACKUP - the two aren't used in the same platform, so overlapping should be OK. I didn't see any documentation that actually said that this location was free to use, and didn't need to be restored after use in S3 resume, but it looks like the DOS boot vector gets loaded juat above this location, so it SHOULD be ok. The alternative is to copy the memory out and store it in cbmem until we're ready to restore it. 2) When a request for the pointer to a CAR variable comes in, pass back the location inside the FSP hob structure. 3) Skip the memcopy of the CAR Data. The CAR variables do not get transitioned back into cbmem, but used out of the HOB structure. 4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform. Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/8196 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8196 for details. -gerrit

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Patch merged into coreboot/master: 0490f74 TPM: Fix whitespace
by gerrit＠coreboot.org 06 Feb '15

06 Feb '15

the following patch was just integrated into master: commit 0490f74d7808e96b079c83764d712f794ecb4198 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 4 15:55:06 2015 +0200 TPM: Fix whitespace Change-Id: I2d00a2964b16436356c5e02764897e37ef610efc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8343 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8343 for details. -gerrit

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coreboot-gerrit February 2015