coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

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509 discussions

Patch merged into coreboot/master: da8fcf0 mainboards/asus/kfsn4-dre: Indicate native text mode init support
by gerrit＠coreboot.org 06 Feb '15

06 Feb '15

the following patch was just integrated into master: commit da8fcf0afeb08d288171bda4022c25c3e5a6ecc4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 11:03:36 2015 -0600 mainboards/asus/kfsn4-dre: Indicate native text mode init support Change-Id: Ib00ecdcad17fa5c0300d22378837e36d0918f9db Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8369 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8369 for details. -gerrit

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Patch merged into coreboot/master: 08c15ed drivers/xgi: Fix legacy VGA text mode initialization
by gerrit＠coreboot.org 06 Feb '15

06 Feb '15

the following patch was just integrated into master: commit 08c15ed266d8dec11de9b2eed097678b454ea7fc Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 01:02:57 2015 -0600 drivers/xgi: Fix legacy VGA text mode initialization TEST: Booted KFSN4-DRE with on-board XGI Volari Z9s Initial text from coreboot appeared, and the Linux console was displayed immediately at the start of kernel initialization. After boot was complete the text mode console continued to behave normally. SeaBIOS does not currently make use of the legacy VGA text-mode display. Change-Id: I2177a1d00e6f07db661dd99fe0184e2c228404d1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8360 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8360 for details. -gerrit

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Patch set updated for coreboot: c86e729 southbridge/amd/pi: Combine and expand the IRQ text strings
by Dave Frodin 06 Feb '15

06 Feb '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8374 -gerrit commit c86e729824d50b612747c6db19f8ae0a84b256cf Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Feb 6 07:25:11 2015 -0700 southbridge/amd/pi: Combine and expand the IRQ text strings This expands the table of text descriptions of the IRQ assignments. It also combines the strings that are common to Avalon and Bolton. The range of values used by Bolton is also increased to 128 locations. Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 2 +- src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 24 +++++++++-------------- 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 78a40f0..ae3c88d 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -73,7 +73,7 @@ #endif #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) -#define FCH_INT_TABLE_SIZE 0x54 +#define FCH_INT_TABLE_SIZE 128 #define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */ #define PIRQ_GPP2 0x52 /* GPP INT 2 */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index 517c892..20e5faf 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -20,26 +20,20 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) const char * intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", - [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t\t", [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", - [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB","Dev20.5 INTC", + [0x7F] = "RSVD\t", +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) + [0x40] = "RSVD\t","SATA\t", + [0x62] = "GPIO\t", +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) [0x40] = "IDE\t", "SATA\t", - [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" -}; -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) -const char * intr_types[] = { - [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", - [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", - [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t", - [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", - [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", - [0x40] = "RSVD\t", "SATA\t", - [0x60] = "RSVD\t", "RSVD\t", "GPIO\t", -}; + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", #endif +}; #endif /* AMD_PCI_INT_TYPES_H */

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Patch set updated for coreboot: f411c27 drivers/pc80/mc146818rtc: Reduce superfluous preprocessor use
by Alexandru Gagniuc 06 Feb '15

06 Feb '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8306 -gerrit commit f411c27b2a84214fbdaa08a4aeeada37ee110053 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 30 00:07:12 2015 -0600 drivers/pc80/mc146818rtc: Reduce superfluous preprocessor use cmos_init() had layers of preprocessor directives, which resulted in a complete mess. Refactor it to make use of the IS_ENABLED() macro. This improves readability significantly. One of the changes is to remove in inline stub declaration of (get|set)_option. Although that provided the ability for the compiler to optimize out code when USE_OPTION_TABLE is not selected, there is no evidence that such savings are measureable. Change-Id: I07f00084d809adbb55031b2079f71136ade3028e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/pc80/Makefile.inc | 4 +- src/drivers/pc80/mc146818rtc.c | 99 ++++++++++++++++++++++-------------------- src/include/pc80/mc146818rtc.h | 14 ++---- 3 files changed, 57 insertions(+), 60 deletions(-) diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc index 1d28152..9715949 100644 --- a/src/drivers/pc80/Makefile.inc +++ b/src/drivers/pc80/Makefile.inc @@ -7,9 +7,7 @@ ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c ramstage-$(CONFIG_SPKMODEM) += spkmodem.c -ifeq ($(CONFIG_DRIVERS_MC146818),y) -romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c -endif +romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_early.c romstage-$(CONFIG_LPC_TPM) += tpm.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index fc3adf0..b18f22f 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -26,9 +26,15 @@ #include <boot/coreboot_tables.h> #include <rtc.h> #include <string.h> +#include <cbfs.h> + +/* There's no way around this include guard. option_table.h is autogenerated */ #if CONFIG_USE_OPTION_TABLE #include "option_table.h" -#include <cbfs.h> +#else +#define LB_CKS_RANGE_START 0 +#define LB_CKS_RANGE_END 0 +#define LB_CKS_LOC 0 #endif @@ -48,7 +54,6 @@ static void cmos_reset_date(void) rtc_set(&time); } -#if CONFIG_USE_OPTION_TABLE static int cmos_checksum_valid(int range_start, int range_end, int cks_loc) { int i; @@ -71,19 +76,18 @@ static void cmos_set_checksum(int range_start, int range_end, int cks_loc) cmos_write(((sum >> 8) & 0x0ff), cks_loc); cmos_write(((sum >> 0) & 0x0ff), cks_loc + 1); } -#endif #define RTC_CONTROL_DEFAULT (RTC_24H) #define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) #ifndef __SMM__ -void cmos_init(int invalid) +void cmos_init(bool invalid) { - int cmos_invalid = 0; - int checksum_invalid = 0; -#if CONFIG_USE_OPTION_TABLE - unsigned char x; -#endif + bool cmos_invalid = false; + bool checksum_invalid = false; + bool clear_cmos; + size_t i; + uint8_t x; #ifndef __PRE_RAM__ /* @@ -98,38 +102,37 @@ void cmos_init(int invalid) printk(BIOS_DEBUG, "RTC Init\n"); -#if CONFIG_USE_OPTION_TABLE - /* See if there has been a CMOS power problem. */ - x = cmos_read(RTC_VALID); - cmos_invalid = !(x & RTC_VRT); + if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { + /* See if there has been a CMOS power problem. */ + x = cmos_read(RTC_VALID); + cmos_invalid = !(x & RTC_VRT); - /* See if there is a CMOS checksum error */ - checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START, - PC_CKS_RANGE_END,PC_CKS_LOC); + /* See if there is a CMOS checksum error */ + checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START, + PC_CKS_RANGE_END, PC_CKS_LOC); -#define CLEAR_CMOS 0 -#else -#define CLEAR_CMOS 1 -#endif + clear_cmos = false; + } else { + clear_cmos = true; + } if (invalid || cmos_invalid || checksum_invalid) { -#if CLEAR_CMOS - int i; - - cmos_write(0, 0x01); - cmos_write(0, 0x03); - cmos_write(0, 0x05); - for (i = 10; i < 128; i++) - cmos_write(0, i); -#endif + if (clear_cmos) { + cmos_write(0, 0x01); + cmos_write(0, 0x03); + cmos_write(0, 0x05); + for (i = 10; i < 128; i++) + cmos_write(0, i); + } + if (cmos_invalid) cmos_reset_date(); printk(BIOS_WARNING, "RTC:%s%s%s%s\n", - invalid?" Clear requested":"", - cmos_invalid?" Power Problem":"", - checksum_invalid?" Checksum invalid":"", - CLEAR_CMOS?" zeroing cmos":""); + invalid ? " Clear requested":"", + cmos_invalid ? " Power Problem":"", + checksum_invalid ? " Checksum invalid":"", + clear_cmos ? " zeroing cmos":""); } /* Setup the real time clock */ @@ -139,24 +142,23 @@ void cmos_init(int invalid) /* Ensure all reserved bits are 0 in register D */ cmos_write(RTC_VRT, RTC_VALID); -#if CONFIG_USE_OPTION_TABLE - /* See if there is a LB CMOS checksum error */ - checksum_invalid = !cmos_checksum_valid(LB_CKS_RANGE_START, - LB_CKS_RANGE_END,LB_CKS_LOC); - if (checksum_invalid) - printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n"); - - /* Make certain we have a valid checksum */ - cmos_set_checksum(PC_CKS_RANGE_START, PC_CKS_RANGE_END, PC_CKS_LOC); -#endif + if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { + /* See if there is a LB CMOS checksum error */ + checksum_invalid = !cmos_checksum_valid(LB_CKS_RANGE_START, + LB_CKS_RANGE_END,LB_CKS_LOC); + if (checksum_invalid) + printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n"); + + /* Make certain we have a valid checksum */ + cmos_set_checksum(PC_CKS_RANGE_START, PC_CKS_RANGE_END, PC_CKS_LOC); + } /* Clear any pending interrupts */ cmos_read(RTC_INTR_FLAGS); } -#endif +#endif /* __SMM__ */ -#if CONFIG_USE_OPTION_TABLE /* * This routine returns the value of the requested bits. * input bit = bit count from the beginning of the cmos image @@ -200,6 +202,9 @@ enum cb_err get_option(void *dest, const char *name) size_t namelen; int found = 0; + if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) + return CB_CMOS_OTABLE_DISABLED; + /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); @@ -280,6 +285,9 @@ enum cb_err set_option(const char *name, void *value) size_t namelen; int found = 0; + if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) + return CB_CMOS_OTABLE_DISABLED; + /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); @@ -318,7 +326,6 @@ enum cb_err set_option(const char *name, void *value) return CB_SUCCESS; } -#endif /* CONFIG_USE_OPTION_TABLE */ /* * If the CMOS is cleared, the rtc_reg has the invalid date. That diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 90ae7ae..c74af66 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -169,21 +169,13 @@ static inline void cmos_write32(u8 offset, u32 value) #endif #if !defined(__ROMCC__) -void cmos_init(int invalid); +void cmos_init(bool invalid); void cmos_check_update_date(void); -#if CONFIG_USE_OPTION_TABLE + enum cb_err set_option(const char *name, void *val); enum cb_err get_option(void *dest, const char *name); unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def); -#else -static inline enum cb_err set_option(const char *name __attribute__((unused)), - void *val __attribute__((unused))) - { return CB_CMOS_OTABLE_DISABLED; }; -static inline enum cb_err get_option(void *dest __attribute__((unused)), - const char *name __attribute__((unused))) - { return CB_CMOS_OTABLE_DISABLED; } -#define read_option_lowlevel(start, size, def) def -#endif + #else /* defined(__ROMCC__) */ #include <drivers/pc80/mc146818rtc_early.c> #endif /* !defined(__ROMCC__) */

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New patch to review for coreboot: 4f66a17 superio/fintek/f81216h: Add the correct unlock key values
by Dave Frodin 06 Feb '15

06 Feb '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8375 -gerrit commit 4f66a17124a4ba7140d128e4fcbda369595c45da Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Feb 6 07:25:40 2015 -0700 superio/fintek/f81216h: Add the correct unlock key values Change-Id: I8f20e3d0ce83dd87b6c233ee98c3e77a6b7c1b03 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/superio/fintek/f81216h/superio.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c index 89204c4..84116a0 100644 --- a/src/superio/fintek/f81216h/superio.c +++ b/src/superio/fintek/f81216h/superio.c @@ -46,15 +46,21 @@ static void pnp_enter_ext_func_mode(struct device *dev) */ switch(conf->conf_key_mode) { case MODE_6767: + key = 0x67; + break; case MODE_7777: + key = 0x77; + break; case MODE_8787: + key = 0x87; + break; case MODE_A0A0: - key = conf->conf_key_mode; + key = 0xA0; break; default: printk(BIOS_WARNING, "Warning: Undefined F81216 unlock key assignment!\n"); printk(BIOS_WARNING, "Setting conf_key_mode to default\n"); - key = MODE_7777; /* try the hw default */ + key = 0x77; /* try the hw default */ break; }

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New patch to review for coreboot: e912f36 southbridge/amd/pi: Correct a text string description
by Dave Frodin 06 Feb '15

06 Feb '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8374 -gerrit commit e912f364647040427e59f53c49016ce206307dd1 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Feb 6 07:25:11 2015 -0700 southbridge/amd/pi: Correct a text string description Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index 517c892..94dbfa3 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -24,7 +24,7 @@ const char * intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", - [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t", [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", [0x40] = "IDE\t", "SATA\t",

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Patch set updated for coreboot: cc15c05 RTC: Enable RTC reset when power loss was detected.
by Werner Zeh 06 Feb '15

06 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8373 -gerrit commit cc15c0547927a34d0c663ee5b352aa3f3ee5af9f Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jan 29 13:25:59 2015 +0100 RTC: Enable RTC reset when power loss was detected. If function cmos_init() was called with parameter invalid set, this indicates, that the caller has found a power loss event in the RTC registers. In this case, we need to load the default date and time because it can be corrupted. Change-Id: Ib8d58a14da0182ceb8167e67440a0f1ea2a20eb7 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/pc80/mc146818rtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index fc3adf0..d0d906a 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -122,7 +122,7 @@ void cmos_init(int invalid) for (i = 10; i < 128; i++) cmos_write(0, i); #endif - if (cmos_invalid) + if (invalid || cmos_invalid) cmos_reset_date(); printk(BIOS_WARNING, "RTC:%s%s%s%s\n",

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New patch to review for coreboot: 9ed8352 RTC: Enable RTC reset when power loss was detected.
by Werner Zeh 06 Feb '15

06 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8373 -gerrit commit 9ed8352690ded93a3e276d8bf074d01be5e2fcde Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jan 29 13:25:59 2015 +0100 RTC: Enable RTC reset when power loss was detected. If function cmos_init() was called with parameter invalid set, this indicates, that the caller has found a power loss event in the RTC registers. In this case, we need to load the default date and time because it can be corrupted. Change-Id: Ib8d58a14da0182ceb8167e67440a0f1ea2a20eb7 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/pc80/mc146818rtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 014a8c9..747e446 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -106,7 +106,7 @@ void cmos_init(int invalid) for (i = 10; i < 128; i++) cmos_write(0, i); #endif - if (cmos_invalid) + if (invalid || cmos_invalid) cmos_update_date(RTC_HAS_NO_ALTCENTURY); printk(BIOS_WARNING, "RTC:%s%s%s%s\n",

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Patch set updated for coreboot: 51aeaac mainboards/asus/kfsn4-dre: Indicate native text mode init support
by Timothy Pearson 06 Feb '15

06 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8369 -gerrit commit 51aeaac2b8d038cfdbc14b1bc0d9253330f8db79 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 11:03:36 2015 -0600 mainboards/asus/kfsn4-dre: Indicate native text mode init support Change-Id: Ib00ecdcad17fa5c0300d22378837e36d0918f9db Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index c16440d..f2530e5 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT_DEFAULT select DRIVERS_XGI_Z9S select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG config MAINBOARD_DIR string

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Patch set updated for coreboot: 744fd13 payloads/seabios: Enable SeaVGABIOS option if native text init supported
by Timothy Pearson 06 Feb '15

06 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8368 -gerrit commit 744fd13f3cbbdbe85288238a79f1a3d2f87e425b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 5 10:47:40 2015 -0600 payloads/seabios: Enable SeaVGABIOS option if native text init supported SeaVGABIOS supports both the coreboot linear framebuffer and native EGA text mode. To use SeaBIOS interactively on standard VGA hardware a VBIOS is needed; SeaVGABIOS is one such option. TEST: Booted KFSN4-DRE with XGI Volari Z9s and SeaVGABIOS. Was able to interact with SeaBIOS and comboot menu, then booted Linux successfully. VGA display was continuously usable from power on to Linux login. Change-Id: Id4bd4cb5cece9114457633832c5f0e5280c02b47 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index e5dc26b..4c80f34 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -661,7 +661,7 @@ config SEABIOS_MALLOC_UPPERMEMORY config SEABIOS_VGA_COREBOOT prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS default n - depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT + depends on !VGA_BIOS && (MAINBOARD_DO_NATIVE_VGA_INIT || MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG) bool help Coreboot can initialize the GPU of some mainboards.

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coreboot-gerrit February 2015