coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

1 participants
509 discussions

Patch merged into coreboot/master: c522fc8 drivers/xgi/z9s: Port Linux framebuffer initialization to coreboot
by gerrit＠coreboot.org 05 Feb '15

05 Feb '15

the following patch was just integrated into master: commit c522fc8f3815ab33fe11ca58263d84bc8e98417d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Feb 2 18:25:34 2015 -0600 drivers/xgi/z9s: Port Linux framebuffer initialization to coreboot Add native XGI Z9s framebuffer support to coreboot XGI initialization code largely taken from Linux 3.18.5 TEST: Booted KFSN4-DRE with XGI Volari Z9s into SeaBIOS with SeaVGABIOS enabled. Text appeared correctly on screen and interaction with graphical comboot menu was successful. However, Linux cleared the framebuffer on boot, rendering the screen useless until Linux loaded its native xgifb driver. Change-Id: I606a3892849fc578b0c4d74536aec0a0adef3be3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8331 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8331 for details. -gerrit

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Patch merged into coreboot/master: 5c015f0 southbridge/amd/pi: write_hpet requires additional config option
by gerrit＠coreboot.org 05 Feb '15

05 Feb '15

the following patch was just integrated into master: commit 5c015f045ddd00d34e56ee407ed2596e97a1433a Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Jan 27 07:19:04 2015 -0700 southbridge/amd/pi: write_hpet requires additional config option This copies what was done in southbridge/amd/agesa in: commit 56f46d8 agesa/family15tn: Switch to per-device ACPI TEST: amd/lamar. Change-Id: Id8890ccd4a1ea783ad4740333ae6b061b6bbd7fc Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8288 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8288 for details. -gerrit

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Patch merged into coreboot/master: ef9a4e6 southbridge/amd/pi: Update Kconfig and makefiles for bolton
by gerrit＠coreboot.org 05 Feb '15

05 Feb '15

the following patch was just integrated into master: commit ef9a4e6aeca1305ca05c8946432f9baef050d136 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Jan 27 07:16:03 2015 -0700 southbridge/amd/pi: Update Kconfig and makefiles for bolton Change-Id: I208c931bdaee572c9df11b35c1e6e9f27609ea6c Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8287 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8287 for details. -gerrit

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Patch merged into coreboot/master: 9cfa742 southbridge/amd/pi: Add the bolton definitions
by gerrit＠coreboot.org 05 Feb '15

05 Feb '15

the following patch was just integrated into master: commit 9cfa742a264442a8796120964b06fcc8e03185bf Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Jan 27 07:19:48 2015 -0700 southbridge/amd/pi: Add the bolton definitions This adds the PCI and interrupt related definitions for the bolton specific features. Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8286 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/8286 for details. -gerrit

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New patch to review for coreboot: 09a34e5 PCI subsystem: Remove AGP bridge type
by Kyösti Mälkki 05 Feb '15

05 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8367 -gerrit commit 09a34e52c1a0b81a9519f183b4cc640679edbb06 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 2 15:56:27 2015 +0200 PCI subsystem: Remove AGP bridge type There is no auto-detection for AGP type and we have no hardware that selects this. Furthermore, we treat AGP bridges just like PCI bridges, there is no optimisation for higher bandwidth. Change-Id: I4fe87c83411643cb9b8d3216f2af07bf098174d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 5 ---- src/device/Makefile.inc | 1 - src/device/agp_device.c | 75 ------------------------------------------------ src/device/pci_device.c | 4 --- src/include/device/agp.h | 14 --------- 5 files changed, 99 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index dc00b75..b613a1e 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -219,11 +219,6 @@ config PCIEXP_PLUGIN_SUPPORT depends on PCI default y -config AGP_PLUGIN_SUPPORT - bool - depends on PCI - default y - config CARDBUS_PLUGIN_SUPPORT bool depends on PCI diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 7fdd9b5..8c9ba5d 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -6,7 +6,6 @@ ramstage-$(CONFIG_PCI) += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c -ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c diff --git a/src/device/agp_device.c b/src/device/agp_device.c deleted file mode 100644 index 550297a..0000000 --- a/src/device/agp_device.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Linux Networx - * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/agp.h> - -static void agp_tune_dev(device_t dev) -{ - unsigned int cap; - - cap = pci_find_capability(dev, PCI_CAP_ID_AGP); - if (!cap) - return; - - /* The OS is responsible for AGP tuning so do nothing here. */ -} - -unsigned int agp_scan_bus(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, unsigned int max) -{ - device_t child; - - max = pci_scan_bus(bus, min_devfn, max_devfn, max); - - for (child = bus->children; child; child = child->sibling) { - if ((child->path.pci.devfn < min_devfn) || - (child->path.pci.devfn > max_devfn)) { - continue; - } - agp_tune_dev(child); - } - - return max; -} - -unsigned int agp_scan_bridge(device_t dev, unsigned int max) -{ - return do_pci_scan_bridge(dev, max, agp_scan_bus); -} - -/** Default device operations for AGP bridges. */ -static struct pci_operations agp_bus_ops_pci = { - .set_subsystem = 0, -}; - -struct device_operations default_agp_ops_bus = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = agp_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &agp_bus_ops_pci, -}; diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 862ed0e..127ee32 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -32,7 +32,6 @@ #include <stdint.h> #include <string.h> #include <delay.h> -#include <device/agp.h> #include <device/cardbus.h> #include <device/device.h> #include <device/pci.h> @@ -771,9 +770,6 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) return &default_pcix_ops_bus; } #endif -#if CONFIG_AGP_PLUGIN_SUPPORT - /* How do I detect a PCI to AGP bridge? */ -#endif #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT unsigned int htpos = 0; while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) { diff --git a/src/include/device/agp.h b/src/include/device/agp.h deleted file mode 100644 index be2b833..0000000 --- a/src/include/device/agp.h +++ /dev/null @@ -1,14 +0,0 @@ -/* (c) 2005 Linux Networx GPL see COPYING for details */ - -#ifndef DEVICE_AGP_H -#define DEVICE_AGP_H - -#include <device/device.h> - -unsigned int agp_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max); -unsigned int agp_scan_bridge(device_t dev, unsigned int max); - -extern struct device_operations default_agp_ops_bus; - -#endif /* DEVICE_AGP_H */

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New patch to review for coreboot: 8653b4c AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki 05 Feb '15

05 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8366 -gerrit commit 8653b4cdd85f1b91842e0d9d49cb1550bcdee9c6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 15:48:38 2015 +0200 AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0 If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain on southbridge is the first to scan and it will be assigned with bus number 0. If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range of bus numbers instead of assigning consecutive numbers across all the links. All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge. Follow-up can easily drop this if we find this is dictated by architecture. Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/advansus/a785e-i/Kconfig | 4 ---- src/mainboard/amd/bimini_fam10/Kconfig | 4 ---- src/mainboard/amd/dbm690t/Kconfig | 5 +---- src/mainboard/amd/mahogany/Kconfig | 5 +---- src/mainboard/amd/mahogany_fam10/Kconfig | 4 ---- src/mainboard/amd/pistachio/Kconfig | 5 +---- src/mainboard/amd/serengeti_cheetah/Kconfig | 6 ++---- src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 5 +---- src/mainboard/amd/tilapia_fam10/Kconfig | 4 ---- src/mainboard/arima/hdama/Kconfig | 5 +---- src/mainboard/asrock/939a785gmh/Kconfig | 5 +---- src/mainboard/asus/a8n_e/Kconfig | 6 ++---- src/mainboard/asus/a8v-e_deluxe/Kconfig | 5 +---- src/mainboard/asus/a8v-e_se/Kconfig | 5 +---- src/mainboard/asus/k8v-x/Kconfig | 5 +---- src/mainboard/asus/kfsn4-dre/Kconfig | 4 ---- src/mainboard/asus/m2n-e/Kconfig | 6 ++---- src/mainboard/asus/m2v-mx_se/Kconfig | 5 +---- src/mainboard/asus/m2v/Kconfig | 5 +---- src/mainboard/asus/m4a78-em/Kconfig | 4 ---- src/mainboard/asus/m4a785-m/Kconfig | 4 ---- src/mainboard/asus/m4a785t-m/Kconfig | 4 ---- src/mainboard/asus/m5a88-v/Kconfig | 4 ---- src/mainboard/avalue/eax-785e/Kconfig | 4 ---- src/mainboard/broadcom/blast/Kconfig | 5 +---- src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 6 ++---- src/mainboard/gigabyte/m57sli/Kconfig | 6 ++---- src/mainboard/gigabyte/ma785gm/Kconfig | 4 ---- src/mainboard/gigabyte/ma785gmt/Kconfig | 4 ---- src/mainboard/gigabyte/ma78gm/Kconfig | 4 ---- src/mainboard/hp/dl145_g1/Kconfig | 6 ++---- src/mainboard/hp/dl145_g3/Kconfig | 6 ++---- src/mainboard/hp/dl165_g6_fam10/Kconfig | 5 +---- src/mainboard/iei/kino-780am2-fam10/Kconfig | 4 ---- src/mainboard/iwill/dk8_htx/Kconfig | 6 ++---- src/mainboard/jetway/pa78vm5/Kconfig | 4 ---- src/mainboard/kontron/kt690/Kconfig | 5 +---- src/mainboard/msi/ms7135/Kconfig | 6 ++---- src/mainboard/msi/ms7260/Kconfig | 6 ++---- src/mainboard/msi/ms9185/Kconfig | 6 ++---- src/mainboard/msi/ms9282/Kconfig | 5 +---- src/mainboard/msi/ms9652_fam10/Kconfig | 4 ---- src/mainboard/nvidia/l1_2pvv/Kconfig | 6 ++---- src/mainboard/siemens/sitemp_g1p1/Kconfig | 5 +---- src/mainboard/sunw/ultra40/Kconfig | 6 ++---- src/mainboard/supermicro/h8dme/Kconfig | 6 ++---- src/mainboard/supermicro/h8dmr/Kconfig | 6 ++---- src/mainboard/supermicro/h8dmr_fam10/Kconfig | 5 +---- src/mainboard/supermicro/h8qme_fam10/Kconfig | 5 +---- src/mainboard/supermicro/h8scm_fam10/Kconfig | 4 ---- src/mainboard/technexion/tim5690/Kconfig | 5 +---- src/mainboard/technexion/tim8690/Kconfig | 5 +---- src/mainboard/tyan/s2881/Kconfig | 6 ++---- src/mainboard/tyan/s2885/Kconfig | 6 ++---- src/mainboard/tyan/s2891/Kconfig | 6 ++---- src/mainboard/tyan/s2892/Kconfig | 6 ++---- src/mainboard/tyan/s2895/Kconfig | 6 ++---- src/mainboard/tyan/s2912/Kconfig | 6 ++---- src/mainboard/tyan/s2912_fam10/Kconfig | 5 +---- src/mainboard/winent/mb6047/Kconfig | 6 ++---- src/northbridge/amd/amdfam10/Kconfig | 6 ++++++ src/northbridge/amd/amdfam10/northbridge.c | 8 ++++---- src/northbridge/amd/amdk8/Kconfig | 6 ++++-- src/northbridge/amd/amdk8/northbridge.c | 8 ++++---- 64 files changed, 83 insertions(+), 250 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index ab77898..901d8c5 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -53,10 +53,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig index 1af8d64..ec19e42 100644 --- a/src/mainboard/amd/bimini_fam10/Kconfig +++ b/src/mainboard/amd/bimini_fam10/Kconfig @@ -53,10 +53,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index 70d63ad..9445893 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS690 select SOUTHBRIDGE_AMD_SB600 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_ITE_IT8712F select HAVE_ACPI_TABLES select HAVE_MP_TABLE @@ -36,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig index 394ad77..f8d3ce9 100644 --- a/src/mainboard/amd/mahogany/Kconfig +++ b/src/mainboard/amd/mahogany/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_ITE_IT8718F select HAVE_ACPI_TABLES select HAVE_MP_TABLE @@ -47,10 +48,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig index acf88ef..c477278 100644 --- a/src/mainboard/amd/mahogany_fam10/Kconfig +++ b/src/mainboard/amd/mahogany_fam10/Kconfig @@ -41,10 +41,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index 9a91eec..3e6d178 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS690 select SOUTHBRIDGE_AMD_SB600 + select SB_HT_CHAIN_ON_BUS0 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE @@ -44,10 +45,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index e1363eb..1d0f270 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -10,6 +10,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -55,10 +57,6 @@ config MEM_TRAIN_SEQ int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index 74f3c3b..5783cdd 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8132 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -42,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 8 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index b6c9448..5dfed59 100644 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -41,10 +41,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/arima/hdama/Kconfig b/src/mainboard/arima/hdama/Kconfig index 49860b3..ace9548 100644 --- a/src/mainboard/arima/hdama/Kconfig +++ b/src/mainboard/arima/hdama/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_NSC_PC87360 select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE @@ -38,10 +39,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig index cfaa599..ff7f172 100644 --- a/src/mainboard/asrock/939a785gmh/Kconfig +++ b/src/mainboard/asrock/939a785gmh/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_WINBOND_W83627DHG select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME @@ -49,10 +50,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig index 5b7c1e6..51bf531 100644 --- a/src/mainboard/asus/a8n_e/Kconfig +++ b/src/mainboard/asus/a8n_e/Kconfig @@ -5,6 +5,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_939 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT @@ -54,10 +56,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 13 diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig index 8ebff31..9bb9406 100644 --- a/src/mainboard/asus/a8v-e_deluxe/Kconfig +++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 select SOUTHBRIDGE_VIA_SUBTYPE_K8T890 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_WINBOND_W83627EHG select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES @@ -33,10 +34,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "A8V-E Deluxe" diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig index d819b0d..1c63c13 100644 --- a/src/mainboard/asus/a8v-e_se/Kconfig +++ b/src/mainboard/asus/a8v-e_se/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 select SOUTHBRIDGE_VIA_SUBTYPE_K8T890 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_WINBOND_W83627EHG select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES @@ -33,10 +34,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "A8V-E SE" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 1deb5b6..eea41b4 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 select SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES @@ -32,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "K8V-X" diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 92e01aa..95d6c30 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -36,10 +36,6 @@ config APIC_ID_OFFSET hex default 0 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "KFSN4-DRE" diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index 7292bf3..756866f 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -26,6 +26,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_ITE_IT8716F @@ -57,10 +59,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "M2N-E" diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 27b8253..cab6c16 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 select SOUTHBRIDGE_VIA_SUBTYPE_K8M890 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES @@ -67,10 +68,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig index 35ad38d..e30be2b 100644 --- a/src/mainboard/asus/m2v/Kconfig +++ b/src/mainboard/asus/m2v/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 select SOUTHBRIDGE_VIA_SUBTYPE_K8T890 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_ITE_IT8712F select BOARD_ROMSIZE_KB_512 select HAVE_ACPI_RESUME @@ -36,10 +37,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "M2V" diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig index 6118d12..fda5c8c 100644 --- a/src/mainboard/asus/m4a78-em/Kconfig +++ b/src/mainboard/asus/m4a78-em/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index dd58db3..b190852 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -41,10 +41,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 19d8fd2..6002716 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 3a0f70f..0b18381 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -51,10 +51,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 091dcee..db95492 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -53,10 +53,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig index b821f7a..1935cec 100644 --- a/src/mainboard/broadcom/blast/Kconfig +++ b/src/mainboard/broadcom/blast/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM5780 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -31,10 +32,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "Blast" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index a79c28f..eb5d2c2 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -6,6 +6,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_SIS_SIS966 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_ITE_IT8716F select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -37,10 +39,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "GA-2761GXDK" diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 6ef94ce..2eec3f0 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -6,6 +6,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_ITE_IT8716F @@ -41,10 +43,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "GA-M57SLI-S4" diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig index f830e81..1a00b37 100644 --- a/src/mainboard/gigabyte/ma785gm/Kconfig +++ b/src/mainboard/gigabyte/ma785gm/Kconfig @@ -41,10 +41,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig index 505d033..608162f 100644 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig +++ b/src/mainboard/gigabyte/ma785gmt/Kconfig @@ -41,10 +41,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig index b36640f..d2d2620 100644 --- a/src/mainboard/gigabyte/ma78gm/Kconfig +++ b/src/mainboard/gigabyte/ma78gm/Kconfig @@ -41,10 +41,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index 0c6d642..3d2bfb7 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -6,6 +6,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_HARD_RESET select HAVE_OPTION_TABLE @@ -28,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "ProLiant DL145 G1" diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index 439188a..a8e73cb 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -8,6 +8,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE @@ -56,10 +58,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x6 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 15 diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index f6aea01..dc3e095 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select DIMM_DDR2 @@ -56,10 +57,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x6 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 15 diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig index 069a4ae..8d1143a 100644 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig +++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig @@ -41,10 +41,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig index cdfd99a..6baa923 100644 --- a/src/mainboard/iwill/dk8_htx/Kconfig +++ b/src/mainboard/iwill/dk8_htx/Kconfig @@ -6,6 +6,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -38,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig index 56ad128..71f091f 100644 --- a/src/mainboard/jetway/pa78vm5/Kconfig +++ b/src/mainboard/jetway/pa78vm5/Kconfig @@ -41,10 +41,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index 8d1f039..3caf2a8 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS690 select SOUTHBRIDGE_AMD_SB600 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -37,10 +38,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index f2cfd9a..001861f 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -5,6 +5,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -43,10 +45,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 13 diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 0e7e592..05c2b14 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -6,6 +6,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG @@ -39,10 +41,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-7260" diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig index 0b0ff1c..38e81c8 100644 --- a/src/mainboard/msi/ms9185/Kconfig +++ b/src/mainboard/msi/ms9185/Kconfig @@ -8,6 +8,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM5780 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -34,10 +36,6 @@ config APIC_ID_OFFSET hex default 0x8 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-9185" diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index f109375..9b11dd0 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_WINBOND_W83627EHG select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -33,10 +34,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "MS-9282" diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 0b45db3..80c6e3e 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -77,10 +77,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x00 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config VAR_MTRR_HOLE bool default n diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 57911f7..4be737b 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -7,6 +7,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG @@ -43,10 +45,6 @@ config MCP55_NUM int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "l1_2pvv" diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index dff329f..80c2491 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS690 select SOUTHBRIDGE_AMD_SB600 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_ITE_IT8712F select HAVE_ACPI_TABLES select HAVE_MP_TABLE @@ -43,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig index 8f3ff2a..befcd5f 100644 --- a/src/mainboard/sunw/ultra40/Kconfig +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -5,6 +5,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SMSC_LPC47B397 select SUPERIO_SMSC_LPC47M10X select HAVE_OPTION_TABLE @@ -56,10 +58,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index 52d5581..a5123c1 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -7,6 +7,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -60,10 +62,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index f85460b..3562aa8 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -7,6 +7,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -59,10 +61,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index 3a72049..b7da02b 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -56,10 +57,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig index b3a1faf..b0058f5 100644 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig +++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_AMD8132 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -54,10 +55,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index 7fbbf66..7d56662 100644 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -41,10 +41,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 98dce39..83b0a92 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS690 select SOUTHBRIDGE_AMD_SB600 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -37,10 +38,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 4e0b25a..2e49cf1 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS690 select SOUTHBRIDGE_AMD_SB600 + select SB_HT_CHAIN_ON_BUS0 select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -36,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig index 6c759e1..833f043 100644 --- a/src/mainboard/tyan/s2881/Kconfig +++ b/src/mainboard/tyan/s2881/Kconfig @@ -6,6 +6,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -24,10 +26,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2881" diff --git a/src/mainboard/tyan/s2885/Kconfig b/src/mainboard/tyan/s2885/Kconfig index 86e43f8..9d1da13 100644 --- a/src/mainboard/tyan/s2885/Kconfig +++ b/src/mainboard/tyan/s2885/Kconfig @@ -7,6 +7,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8151 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -23,10 +25,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2885" diff --git a/src/mainboard/tyan/s2891/Kconfig b/src/mainboard/tyan/s2891/Kconfig index 3d1c1fb..060d7f3 100644 --- a/src/mainboard/tyan/s2891/Kconfig +++ b/src/mainboard/tyan/s2891/Kconfig @@ -6,6 +6,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -23,10 +25,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2891" diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig index b9c4105..6ccc11f 100644 --- a/src/mainboard/tyan/s2892/Kconfig +++ b/src/mainboard/tyan/s2892/Kconfig @@ -6,6 +6,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -43,10 +45,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig index 544b0c5..bf93d25 100644 --- a/src/mainboard/tyan/s2895/Kconfig +++ b/src/mainboard/tyan/s2895/Kconfig @@ -6,6 +6,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SMSC_LPC47B397 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -47,10 +49,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 26d9a53..9196b28 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -7,6 +7,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT @@ -38,10 +40,6 @@ config MEM_TRAIN_SEQ int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2912" diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 91a6e0d..ddc7571 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT @@ -36,10 +37,6 @@ config APIC_ID_OFFSET hex default 0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2912 (Fam10)" diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig index 86b0ae0..92cf33e 100644 --- a/src/mainboard/winent/mb6047/Kconfig +++ b/src/mainboard/winent/mb6047/Kconfig @@ -5,6 +5,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select SB_HT_CHAIN_ON_BUS0 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -25,10 +27,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MB6047" diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 071557a..925b909 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -69,6 +69,12 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n +config SB_HT_CHAIN_ON_BUS0 + def_bool y + +config HT_CHAIN_DISTRIBUTE + def_bool n + config DIMM_FBDIMM bool default n diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index f400558..b598a84 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -196,10 +196,10 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * so we set the subordinate bus number to 0xff for the moment. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) + if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink) max++; - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) + if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink) max = ALIGN_UP(max, 8); link->secondary = max; @@ -274,7 +274,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) /* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */ for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) + if (CONFIG_SB_HT_CHAIN_ON_BUS0 && is_sblink) max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); } @@ -284,7 +284,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) + if (CONFIG_SB_HT_CHAIN_ON_BUS0 && is_sblink) continue; max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 8dd8cea..9bd02ef 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -66,8 +66,10 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY default n config SB_HT_CHAIN_ON_BUS0 - int - default 0 + def_bool n + +config HT_CHAIN_DISTRIBUTE + def_bool n config QRANK_DIMM_SUPPORT bool diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 312830a..7b66e31 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -140,10 +140,10 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * so we set the subordinate bus number to 0xff for the moment. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) + if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink) max++; - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) + if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink) max = ALIGN_UP(max, 0x40); link->secondary = max; @@ -228,13 +228,13 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) + if (CONFIG_SB_HT_CHAIN_ON_BUS0 && is_sblink) max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); } for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) + if (CONFIG_SB_HT_CHAIN_ON_BUS0 && is_sblink) continue; max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max);

1 0

New patch to review for coreboot: 6aae997 AMD K8 fam10: Refactor logic around SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki 05 Feb '15

05 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8365 -gerrit commit 6aae99711d062192e726d62fa2f29f15c87aff57 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 13:36:54 2015 +0200 AMD K8 fam10: Refactor logic around SB_HT_CHAIN_ON_BUS0 Change-Id: I452a93af452073eeac4e6cb9bbc232dc59e911c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 13 ++----------- src/northbridge/amd/amdk8/northbridge.c | 11 +++-------- 2 files changed, 5 insertions(+), 19 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a81dd82..f400558 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -196,20 +196,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * so we set the subordinate bus number to 0xff for the moment. */ - if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) max++; - } else if (is_sblink) { - } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { - max++; - } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { - // We can have 16 segmment and every segment have 256 bus, - // For that case need the kernel support mmio pci config. - - // one node can have 8 link and segn is the same - max++; + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) max = ALIGN_UP(max, 8); - } link->secondary = max; link->subordinate = (max & ~0xff) | 0xfc; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 8fe38ff..312830a 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -139,17 +139,12 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ - if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { - max++; - } else if (is_sblink) { - } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { - max++; - } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { - // second chain will be on 0x40, third 0x80, forth 0xc0 + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) max++; + + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) max = ALIGN_UP(max, 0x40); - } link->secondary = max; link->subordinate = 0xff;

1 0

New patch to review for coreboot: 06c444f AMD K8 fam10: Eliminate local variable min_bus
by Kyösti Mälkki 05 Feb '15

05 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8364 -gerrit commit 06c444f683061dae1432ce488a8df118e4e27452 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 08:12:20 2015 +0200 AMD K8 fam10: Eliminate local variable min_bus Some cases of max==0xff wrapping around the 8-bit link->secondary register remain to be solved. Change-Id: I01e2ab6b2f23a03dbac49207ab584eccd1ca9b1f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 19 +++++++------------ src/northbridge/amd/amdk8/northbridge.c | 16 +++++++--------- 2 files changed, 14 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 287f468..a81dd82 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -166,7 +166,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool int i; u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 min_bus; u32 busses; u32 max_devfn; @@ -198,25 +197,21 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool */ if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { - min_bus = ++max; + max++; } else if (is_sblink) { - // first chain will on bus 0 - min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { - min_bus = ++max; + max++; } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { - // second chain will be on 0x40, third 0x80, forth 0xc0 - // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 - // >4 will use more segments, // We can have 16 segmment and every segment have 256 bus, // For that case need the kernel support mmio pci config. // one node can have 8 link and segn is the same - min_bus = (((max & 0xff)>>3) + 1) << 3; - max = (max & ~0xff) | min_bus; + max++; + max = ALIGN_UP(max, 8); } - link->secondary = min_bus; + link->secondary = max; link->subordinate = (max & ~0xff) | 0xfc; /* Read the existing primary/secondary/subordinate bus @@ -245,7 +240,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool } //if ext conf is enabled, only need use 0x1f - if (min_bus == 0) + if (link->secondary == 0) max_devfn = (0x17<<3) | 7; else max_devfn = (0x1f<<3) | 7; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index d96e113..8fe38ff 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -93,7 +93,6 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ u32 busses, config_busses; u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 min_bus; u32 max_devfn; link->cap = 0x80 + (link->link_num * 0x20); @@ -141,19 +140,18 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * so we set the subordinate bus number to 0xff for the moment. */ if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { - min_bus = ++max; + max++; } else if (is_sblink) { - // first chain will on bus 0 - min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { - min_bus = ++max; + max++; } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { // second chain will be on 0x40, third 0x80, forth 0xc0 - min_bus = (max & ~0x3f) + 0x40; - max = min_bus; + max++; + max = ALIGN_UP(max, 0x40); } - link->secondary = min_bus; + link->secondary = max; link->subordinate = 0xff; /* Read the existing primary/secondary/subordinate bus @@ -188,7 +186,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ ht_unitid_base[i] = 0x20; } - if (min_bus == 0) + if (link->secondary == 0) max_devfn = (0x17<<3) | 7; else max_devfn = (0x1f<<3) | 7;

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New patch to review for coreboot: f7840f7 AMD fam10: Eliminate local variable segn
by Kyösti Mälkki 05 Feb '15

05 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8363 -gerrit commit f7840f74b42bb9e48a31f5383b009d1c4b94df31 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 08:22:26 2015 +0200 AMD fam10: Eliminate local variable segn While max gets updated, by definition segn must remain the same. There is an (old) issue if max=0xff is passed to this function. Change-Id: I08470b79ff074123e343d5f48181407e02bdf3ad Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 0a69d4d..287f468 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -168,7 +168,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 min_bus; u32 busses; - u32 segn = max>>8; u32 max_devfn; if (link->link_num > 3) { @@ -214,11 +213,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool // one node can have 8 link and segn is the same min_bus = (((max & 0xff)>>3) + 1) << 3; - max = min_bus | (segn<<8); + max = (max & ~0xff) | min_bus; } link->secondary = min_bus; - link->subordinate = (segn<<8) | 0xfc; + link->subordinate = (max & ~0xff) | 0xfc; /* Read the existing primary/secondary/subordinate bus * number configuration.

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New patch to review for coreboot: e984cb8 AMD K8 fam10: Eliminate local variables busn and max_bus
by Kyösti Mälkki 05 Feb '15

05 Feb '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8362 -gerrit commit e984cb80caca54696c3824488139b98e55da81a9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 08:22:20 2015 +0200 AMD K8 fam10: Eliminate local variables busn and max_bus Change-Id: I297de09dcf93511acece4441593ef958a390fddb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 10 +++------- src/northbridge/amd/amdk8/northbridge.c | 4 +--- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index f28c726..f339558 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -166,13 +166,9 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool int i; u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 max_bus; u32 min_bus; u32 busses; u32 segn = max>>8; -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - u32 busn = max&0xff; -#endif u32 max_devfn; if (link->link_num > 3) { @@ -211,7 +207,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config. else { - min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same + // one node can have 8 link and segn is the same + min_bus = (((max & 0xff)>>3) + 1) << 3; } max = min_bus | (segn<<8); #else @@ -223,10 +220,9 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool #else min_bus = ++max; #endif - max_bus = 0xfc | (segn<<8); link->secondary = min_bus; - link->subordinate = max_bus; + link->subordinate = (segn<<8) | 0xfc; /* Read the existing primary/secondary/subordinate bus * number configuration. diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 29fa2a4..31149cf 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -93,7 +93,6 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ u32 busses, config_busses; u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 max_bus; u32 min_bus; u32 max_devfn; @@ -161,10 +160,9 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ #else min_bus = ++max; #endif - max_bus = 0xff; link->secondary = min_bus; - link->subordinate = max_bus; + link->subordinate = 0xff; /* Read the existing primary/secondary/subordinate bus * number configuration.

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coreboot-gerrit February 2015