coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

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509 discussions

New patch to review for coreboot: 445d040 ectool: remove extra printf("Not dumping EC IDX RAM.")
by Alexander Couzens 07 Feb '15

07 Feb '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8380 -gerrit commit 445d0405e125880cd357a76f41c15cffae91cae1 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Feb 7 02:50:30 2015 +0100 ectool: remove extra printf("Not dumping EC IDX RAM.") It doesn't provide any useful information. Change-Id: I13e68d443bbcadea45b8fbcc262ceb9deb3e2e61 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/ectool/ectool.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/util/ectool/ectool.c b/util/ectool/ectool.c index da5143a..fddf340 100644 --- a/util/ectool/ectool.c +++ b/util/ectool/ectool.c @@ -129,8 +129,6 @@ int main(int argc, char *argv[]) printf("%02x ", ec_idx_read(i)); } printf("\n\n"); - } else { - printf("Not dumping EC IDX RAM.\n"); } return 0;

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Patch set updated for coreboot: 63c9b0b ectool: add write support
by Alexander Couzens 07 Feb '15

07 Feb '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8323 -gerrit commit 63c9b0b4eb5b08ef45227ef4a2dd7c531d3e08cf Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Mon Feb 2 08:51:30 2015 +0100 ectool: add write support Use `ectool -w <addr> -z <data>` to write into ec ram Change-Id: Id4aca045f6b7c2343be96ea474ee74033897b8b7 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/ectool/ectool.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/util/ectool/ectool.c b/util/ectool/ectool.c index ab77282..da5143a 100644 --- a/util/ectool/ectool.c +++ b/util/ectool/ectool.c @@ -24,6 +24,7 @@ #include <getopt.h> #include <sys/io.h> #include <ec.h> +#include <stdlib.h> #define ECTOOL_VERSION "0.1" @@ -45,12 +46,14 @@ void print_version(void) void print_usage(const char *name) { - printf("usage: %s [-vh?Vi]\n", name); + printf("usage: %s [-vh?Vi] [-w 0x<addr> -z 0x<data>]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" " -V | --verbose: print debug information\n" " -i | --idx: print IDX RAM\n" + " -w <addr in hex> write to addr\n" + " -z <data in hex> write to data\n" "\n"); exit(1); } @@ -60,6 +63,8 @@ int verbose = 0, dump_idx = 0; int main(int argc, char *argv[]) { int i, opt, option_index = 0; + long write_data = -1; + long write_addr = -1; static struct option long_options[] = { {"version", 0, 0, 'v'}, @@ -69,7 +74,7 @@ int main(int argc, char *argv[]) {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?Vi", + while ((opt = getopt_long(argc, argv, "vh?Viw:z:", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -82,6 +87,12 @@ int main(int argc, char *argv[]) case 'i': dump_idx = 1; break; + case 'w': + write_addr = strtol(optarg , NULL, 16); + break; + case 'z': + write_data = strtol(optarg , NULL, 16); + break; case 'h': case '?': default: @@ -95,6 +106,12 @@ int main(int argc, char *argv[]) printf("You need to be root.\n"); exit(1); } + if (write_addr >= 0 && write_data >= 0) { + write_addr &= 0xff; + write_data &= 0xff; + printf("\nWriting ec %02lx = %02lx\n", write_addr & 0xff, write_data & 0xff); + ec_write(write_addr & 0xff, write_data & 0xff); + } printf("EC RAM:\n"); for (i = 0; i < 0x100; i++) {

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New patch to review for coreboot: b0ab884 hp/pavilion_m6_1035dx: Provide CMOS defaults
by Alexandru Gagniuc 07 Feb '15

07 Feb '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8379 -gerrit commit b0ab88414eee4f687416187a0ea4c288d8d4cb64 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Feb 6 17:03:28 2015 -0600 hp/pavilion_m6_1035dx: Provide CMOS defaults Trying to use option tables without a cmos.default is like raping an energized wall outlet: You know it won't end well. TEST: Boot with corrupted CMOS and make sure console level defaults to SPEW, instead of 0, and that cbmem console is not empty. Change-Id: I8ab2423e99bbe116f52ad27f4b20427d8557f6ff Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 1 + src/mainboard/hp/pavilion_m6_1035dx/cmos.default | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index eba58f2..ebe00a4 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_4096 select GFXUMA select UDELAY_LAPIC diff --git a/src/mainboard/hp/pavilion_m6_1035dx/cmos.default b/src/mainboard/hp/pavilion_m6_1035dx/cmos.default new file mode 100644 index 0000000..0bca0fc --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/cmos.default @@ -0,0 +1,5 @@ +boot_option = Fallback +last_boot = Fallback +debug_level = Spew +nmi = Disable +power_on_after_fail = Disable

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New patch to review for coreboot: b9aa528 hp/pavilion_m6_1035dx/cmos.layout: Remove unused options
by Alexandru Gagniuc 07 Feb '15

07 Feb '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8378 -gerrit commit b9aa5286d6a750fb37da53cc36181b119326f04b Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Feb 6 16:39:30 2015 -0600 hp/pavilion_m6_1035dx/cmos.layout: Remove unused options Some of the options in cmos.layout date back to the K8 days, and have not been used anywhere else, but K8. This makes nvramtool expose a very confusing set of options, most of which have no effect. Clean up the layout before it gets forked again. TEST: Booted linux, and checked 'nvramtool -a' output. Change-Id: I1c5f83790ec89ced4dcf954e4949f8554aef6087 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/cmos.layout | 100 ++++-------------------- 1 file changed, 15 insertions(+), 85 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout b/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout index 5520564..eb0e6b6 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout +++ b/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout @@ -1,70 +1,24 @@ -#***************************************************************************** -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -#***************************************************************************** - entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler + +# RTC_BOOT_BYTE (coreboot hardcoded) 0 384 r 0 reserved_memory 384 1 e 4 boot_option 385 1 e 4 last_boot -386 1 e 1 ECC_memory 388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core + +# southbridge/amd/agesa/hudson should use this but it doesn't 400 1 e 1 power_on_after_fail + +# The only option that is actually used 412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu + +# southbridge/amd/agesa/hudson should use this but it doesn't 444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data + 984 16 h 0 check_sum + # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved @@ -73,41 +27,17 @@ enumerations #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning 6 6 Notice 6 7 Info 6 8 Debug 6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% checksums

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Patch merged into coreboot/master: b5669ba drivers/pc80/mc146818rtc: Reduce superfluous preprocessor use
by gerrit＠coreboot.org 06 Feb '15

06 Feb '15

the following patch was just integrated into master: commit b5669ba57937f48ffe201395c3e3b1527c14d1fa Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 30 00:07:12 2015 -0600 drivers/pc80/mc146818rtc: Reduce superfluous preprocessor use cmos_init() had layers of preprocessor directives, which resulted in a complete mess. Refactor it to make use of the IS_ENABLED() macro. This improves readability significantly. One of the changes is to remove in inline stub declaration of (get|set)_option. Although that provided the ability for the compiler to optimize out code when USE_OPTION_TABLE is not selected, there is no evidence that such savings are measureable. Change-Id: I07f00084d809adbb55031b2079f71136ade3028e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/8306 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8306 for details. -gerrit

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Patch set updated for coreboot: 88fc17b mainboards/asus/kfsn4-dre: Ignore Coverity false positive
by Timothy Pearson 06 Feb '15

06 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8377 -gerrit commit 88fc17bce1f1fbe1b98a06516ddf46ddc349e253 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Feb 6 16:11:16 2015 -0600 mainboards/asus/kfsn4-dre: Ignore Coverity false positive Change-Id: I8c0b8f4bab7ac630d48924a40b2714e21b83b572 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre/romstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index cd8b9de..5711ff4 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -231,6 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); + /* coverity[CONSTANT_EXPRESSION_RESULT] */ if (CONFIG_MAX_PHYSICAL_CPUS != 2) printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!\n", CONFIG_MAX_PHYSICAL_CPUS);

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New patch to review for coreboot: 82b47af mainboards/asus/kfsn4-dre: Ignore Coverity false positive
by Timothy Pearson 06 Feb '15

06 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8377 -gerrit commit 82b47af67c0b3bf604633a94a349a2f6f1115485 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Feb 6 16:11:16 2015 -0600 mainboards/asus/kfsn4-dre: Ignore Coverity false positive Change-Id: I8c0b8f4bab7ac630d48924a40b2714e21b83b572 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index cd8b9de..f197373 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -232,7 +232,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); if (CONFIG_MAX_PHYSICAL_CPUS != 2) - printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!\n", CONFIG_MAX_PHYSICAL_CPUS); + /* coverity[CONSTANT_EXPRESSION_RESULT] */ printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!\n", CONFIG_MAX_PHYSICAL_CPUS); /* Halt if there was a built in self test failure */ report_bist_failure(bist);

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New patch to review for coreboot: 71ea297 amd/amdfam10: Fix invalid transition latency in PowerNow! _PSS objects
by Timothy Pearson 06 Feb '15

06 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8376 -gerrit commit 71ea29718d15452ad42b97d36ca9f26782abc657 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Feb 6 16:07:53 2015 -0600 amd/amdfam10: Fix invalid transition latency in PowerNow! _PSS objects Coverity caught a mistake that led to an invalid 0 latency in the automatically generated PowerNow! ACPI _PSS objects. Fixed remaining Coverity warnings. Change-Id: I03cecab694708136dc555ca2af7ee9a0bf9be5af Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/powernow_acpi.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c index e4e0289..f12d483 100644 --- a/src/cpu/amd/model_10xxx/powernow_acpi.c +++ b/src/cpu/amd/model_10xxx/powernow_acpi.c @@ -76,11 +76,11 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) u32 *v; struct cpuid_result cpuid1; - u16 Pstate_feq[10]; - u32 Pstate_power[10]; - u32 Pstate_latency[10]; - u32 Pstate_control[10]; - u32 Pstate_status[10]; + u16 Pstate_feq[10] = {0}; + u32 Pstate_power[10] = {0}; + u32 Pstate_latency[10] = {0}; + u32 Pstate_control[10] = {0}; + u32 Pstate_status[10] = {0}; u8 Pstate_num; u8 cmp_cap; u8 index; @@ -204,6 +204,9 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) case 0x3: expanded_cpuidv = 1000; break; + default: + /* Should never reach this statement, but avoid a crash if we do */ + expanded_cpuidv = 1; } core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10); @@ -212,7 +215,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) power_step_up = (dtemp & 0xf000000) >> 24; power_step_down = (dtemp & 0xf00000) >> 20; dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0); - pll_lock_time = (pll_lock_time & 0x3800) >> 11; + pll_lock_time = (dtemp & 0x3800) >> 11; if (all_enabled_cores_have_same_cpufid) core_latency = ((12 * power_step_down) + power_step_up) / 1000; else

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Patch set updated for coreboot: 8fa59b1 superio/fintek/f81216h: Add the correct unlock key values
by Dave Frodin 06 Feb '15

06 Feb '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8375 -gerrit commit 8fa59b17f87f2378abe2b4b9b2efda538bb63abf Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Feb 6 07:25:40 2015 -0700 superio/fintek/f81216h: Add the correct unlock key values TEST: amd/lamar shows the correct result. Change-Id: I8f20e3d0ce83dd87b6c233ee98c3e77a6b7c1b03 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/superio/fintek/f81216h/superio.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c index 89204c4..84116a0 100644 --- a/src/superio/fintek/f81216h/superio.c +++ b/src/superio/fintek/f81216h/superio.c @@ -46,15 +46,21 @@ static void pnp_enter_ext_func_mode(struct device *dev) */ switch(conf->conf_key_mode) { case MODE_6767: + key = 0x67; + break; case MODE_7777: + key = 0x77; + break; case MODE_8787: + key = 0x87; + break; case MODE_A0A0: - key = conf->conf_key_mode; + key = 0xA0; break; default: printk(BIOS_WARNING, "Warning: Undefined F81216 unlock key assignment!\n"); printk(BIOS_WARNING, "Setting conf_key_mode to default\n"); - key = MODE_7777; /* try the hw default */ + key = 0x77; /* try the hw default */ break; }

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Patch merged into coreboot/master: a4d784e include/types.h: Provide BIT() macro
by gerrit＠coreboot.org 06 Feb '15

06 Feb '15

the following patch was just integrated into master: commit a4d784eeab964a9cdb8e453ae98a14520ce13919 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Jan 25 21:08:42 2015 -0600 include/types.h: Provide BIT() macro This macro is controversial for arches where the bits are numbered MSb first, though we don't support such an arch. We've seen this macro creep into our tree in different places, so provide it in one place. Change-Id: I86cd8a16420f34ef31b615aec4e0f7bd3191ca35 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/8280 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)gmail.com> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/8280 for details. -gerrit

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coreboot-gerrit February 2015