coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: c21d7ae T124: perform ram_repair when CPU rail is powered on in coldboot
by Marc Jones 11 Feb '15

11 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8415 -gerrit commit c21d7aec315498521cb4ce8cb1e5c7e6a0912247 Author: Yen Lin <yelin(a)nvidia.com> Date: Thu Jul 10 11:46:10 2014 -0700 T124: perform ram_repair when CPU rail is powered on in coldboot This patch is to perform software triggered RAM re-repair in the cold boot path. BUG=chrome-os-partner:30430 BRANCH=nyan TEST=run cold reboot test on nyan. Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Change-Id: I87869431e80e7bc66948a7f67f35e5b907993765 Original-Reviewed-on: https://chromium-review.googlesource.com/207362 Original-Tested-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Yen Lin <yelin(a)nvidia.com> (cherry picked from commit d999f5ecc31d90c8dce1dd91533bc34ffd3c03f2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Iaee1d7f9fa8856f26d7ead70eaeeff9d80dbb181 --- src/soc/nvidia/tegra124/bootblock.c | 4 ++++ src/soc/nvidia/tegra124/flow.h | 14 +++++++++++++- src/soc/nvidia/tegra124/power.c | 16 ++++++++++++++++ src/soc/nvidia/tegra124/power.h | 2 ++ 4 files changed, 35 insertions(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 5900149..aec9145 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -79,6 +79,10 @@ void main(void) clock_cpu0_config(entry); power_enable_and_ungate_cpu(); + + /* Repair ram on cluster0 and cluster1 after CPU is powered on. */ + ram_repair(); + clock_cpu0_remove_reset(); clock_halt_avp(); diff --git a/src/soc/nvidia/tegra124/flow.h b/src/soc/nvidia/tegra124/flow.h index 531278c..416681a 100644 --- a/src/soc/nvidia/tegra124/flow.h +++ b/src/soc/nvidia/tegra124/flow.h @@ -35,8 +35,14 @@ struct flow_ctlr { u32 cpu_pwr_csr; /* offset 0x38 */ u32 mpid; /* offset 0x3c */ u32 ram_repair; /* offset 0x40 */ + u32 flow_dbg_sel; /* offset 0x44 */ + u32 flow_dbg_cnt0; /* offset 0x48 */ + u32 flow_dbg_cnt1; /* offset 0x4c */ + u32 flow_dbg_qual; /* offset 0x50 */ + u32 flow_ctlr_spare; /* offset 0x54 */ + u32 ram_repair_cluster1;/* offset 0x58 */ }; -check_member(flow_ctlr, ram_repair, 0x40); +check_member(flow_ctlr, ram_repair_cluster1, 0x58); enum { FLOW_MODE_SHIFT = 29, @@ -76,4 +82,10 @@ enum { FLOW_EVENT_JTAG = 1 << 28 }; +/* RAM_REPAIR, 0x40, 0x58 */ +enum { + RAM_REPAIR_REQ = 0x1 << 0, + RAM_REPAIR_STS = 0x1 << 1, +}; + #endif /* _TEGRA124_FLOW_H_ */ diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index ec44a0f..75f0494 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -25,8 +25,10 @@ #include "pmc.h" #include "power.h" +#include "flow.h" static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE; +static struct flow_ctlr * const flow = (void *)TEGRA_FLOW_BASE; static int partition_powered(int id) { @@ -92,3 +94,17 @@ int power_reset_status(void) { return read32(&pmc->rst_status) & 0x7; } + +void ram_repair(void) +{ + // Request RAM repair for cluster 0 + setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ); + // Poll for completion + while (!(read32(&flow->ram_repair) & RAM_REPAIR_STS)) + ; + // Request RAM repair for cluster 1 + setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); + // Poll for completion + while (!(read32(&flow->ram_repair_cluster1) & RAM_REPAIR_STS)) + ; +} diff --git a/src/soc/nvidia/tegra124/power.h b/src/soc/nvidia/tegra124/power.h index 995e737..f536865 100644 --- a/src/soc/nvidia/tegra124/power.h +++ b/src/soc/nvidia/tegra124/power.h @@ -36,4 +36,6 @@ enum { }; int power_reset_status(void); +void ram_repair(void); + #endif /* __SOC_NVIDIA_TEGRA124_POWER_H__ */

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New patch to review for coreboot: 294e775 tegra124: Correct cpu power on sequence and CPUPWRGOOD_TIME
by Marc Jones 11 Feb '15

11 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8414 -gerrit commit 294e775ae43cc6238c78cfb8a98c0b3596632c93 Author: Jimmy Zhang <jimmzhang(a)nvidia.com> Date: Wed Jul 2 17:45:18 2014 -0700 tegra124: Correct cpu power on sequence and CPUPWRGOOD_TIME Based on TRM, cpu clock enabling and reset vector setting should all be done properly before ungating cpu power partition. Otherwise, with current code, a race condition could occur where cpu starts but reset vector has not been set. BUG=chrome-os-partner:30064 BRANCH=none TEST=run nyan_big reboot test. No issue is experienced. Original-Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Change-Id: I571e128693bb2763ee673bd183b8cf60921dc475 Original-Reviewed-on: https://chromium-review.googlesource.com/206682 Original-Tested-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang(a)nvidia.com> (cherry picked from commit 106480ff32406c899a24544fdfab858db5afd1d9) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I3da6018dd68e4c15d2c58db566a9745b0b26c365 --- src/soc/nvidia/tegra124/bootblock.c | 11 ++++++----- src/soc/nvidia/tegra124/clock.c | 15 ++++++++++----- src/soc/nvidia/tegra124/include/soc/clock.h | 9 ++++++++- src/soc/nvidia/tegra124/power.c | 30 +++++++++++++++-------------- src/soc/nvidia/tegra124/power.h | 3 +-- 5 files changed, 41 insertions(+), 27 deletions(-) diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 5f1e850..5900149 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <assert.h> #include <arch/exception.h> #include <bootblock_common.h> #include <cbfs.h> @@ -69,16 +70,16 @@ void main(void) PINMUX_PWR_INT_N_FUNC_PMICINTR | PINMUX_INPUT_ENABLE); - power_enable_cpu_rail(); - power_ungate_cpu(); - if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) entry = (void *)verstage_vboot_main; else entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); - if (entry) - clock_cpu0_config_and_reset(entry); + ASSERT(entry); + clock_cpu0_config(entry); + + power_enable_and_ungate_cpu(); + clock_cpu0_remove_reset(); clock_halt_avp(); } diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index af2f96a..e3c0e71 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -480,7 +480,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, udelay(IO_STABILIZATION_DELAY); } -void clock_cpu0_config_and_reset(void *entry) +void clock_cpu0_config(void *entry) { void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; @@ -511,7 +511,10 @@ void clock_cpu0_config_and_reset(void *entry) setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); +} +void clock_cpu0_remove_reset(void) +{ // Disable the reset on the non-CPU parts of the fast cluster. write32(CRC_RST_CPUG_CLR_NONCPU, &clk_rst->rst_cpug_cmplx_clr); @@ -559,10 +562,12 @@ void clock_init(void) /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA * features section in the TRM). */ - write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT, - &clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */ - write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_CLKEN | PLL_OUT_RSTN, &clk_rst->pllc_out); + write32(TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT | + TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT, + &clk_rst->clk_sys_rate); + write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) << + PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | + PLL_OUT_RSTN, &clk_rst->pllc_out); write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT, &clk_rst->sclk_brst_pol); /* sclk = 300 MHz */ diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index ffe9a4e..82b2ad8 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -277,6 +277,12 @@ enum clock_source { /* Careful: Not true for all sources, always check TRM! */ #define TEGRA_PLLD_KHZ (925000) #define TEGRA_PLLU_KHZ (960000) +#define TEGRA_SCLK_KHZ (300000) +#define TEGRA_HCLK_RATIO 1 +#define TEGRA_HCLK_KHZ (TEGRA_SCLK_KHZ / (1 + TEGRA_HCLK_RATIO)) +#define TEGRA_PCLK_RATIO 0 +#define TEGRA_PCLK_KHZ (TEGRA_HCLK_KHZ / (1 + TEGRA_PCLK_RATIO)) + int clock_get_osc_khz(void); int clock_get_pll_input_khz(void); u32 clock_display(u32 frequency); @@ -285,7 +291,8 @@ void clock_external_output(int clk_id); void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, u32 same_freq); -void clock_cpu0_config_and_reset(void * entry); +void clock_cpu0_config(void * entry); +void clock_cpu0_remove_reset(void); void clock_halt_avp(void); void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); void clock_reset_l(u32 l); diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index 760d058..ec44a0f 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <console/console.h> #include <soc/addressmap.h> +#include <soc/clock.h> #include "pmc.h" #include "power.h" @@ -32,6 +33,11 @@ static int partition_powered(int id) return read32(&pmc->pwrgate_status) & (0x1 << id); } +static int partition_clamp_on(int id) +{ + return read32(&pmc->clamp_status) & (0x1 << id); +} + static void power_ungate_partition(uint32_t id) { printk(BIOS_INFO, "Ungating power partition %d.\n", id); @@ -51,34 +57,30 @@ static void power_ungate_partition(uint32_t id) // Wait for the partition to be powered. while (!partition_powered(id)) ; + + // Wait for clamp off. + while (partition_clamp_on(id)) + ; } printk(BIOS_INFO, "Ungated power partition %d.\n", id); } -void power_enable_cpu_rail(void) +void power_enable_and_ungate_cpu(void) { - // Set the power gate timer multiplier to 8 (why 8?). - uint32_t pwrgate_timer_mult = read32(&pmc->pwrgate_timer_mult); - pwrgate_timer_mult |= (0x3 << 0); - /* - * From U-Boot: - * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), - * set it for 5ms as per SysEng (102MHz/5mS = 510000). + * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (150MHz), + * set it for 5ms as per SysEng (5ms * PCLK_KHZ * 1000 / 1s). */ - write32(510000, &pmc->cpupwrgood_timer); - - power_ungate_partition(POWER_PARTID_CRAIL); + write32((TEGRA_PCLK_KHZ * 5), &pmc->cpupwrgood_timer); uint32_t cntrl = read32(&pmc->cntrl); cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY; cntrl |= PMC_CNTRL_CPUPWRREQ_OE; write32(cntrl, &pmc->cntrl); -} -void power_ungate_cpu(void) -{ + power_ungate_partition(POWER_PARTID_CRAIL); + // Ungate power to the non-core parts of the fast cluster. power_ungate_partition(POWER_PARTID_C0NC); diff --git a/src/soc/nvidia/tegra124/power.h b/src/soc/nvidia/tegra124/power.h index 130ed25..995e737 100644 --- a/src/soc/nvidia/tegra124/power.h +++ b/src/soc/nvidia/tegra124/power.h @@ -22,9 +22,8 @@ // This function does not enable the external power to the rail, it enables // the rail itself internal to the SOC. -void power_enable_cpu_rail(void); +void power_enable_and_ungate_cpu(void); -void power_ungate_cpu(void); // power_reset_status returns one of the following possible sources for the // most recent reset.

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New patch to review for coreboot: ce9e6ea tegra132: Add BCT support in tegra132 soc
by Marc Jones 11 Feb '15

11 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8413 -gerrit commit ce9e6ea815fe560ddaf30f734b3bcf028ec7da8e Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jun 9 13:26:38 2014 -0700 tegra132: Add BCT support in tegra132 soc Builds with cbootimage. BUG=None BRANCH=None TEST=build test Original-Change-Id: I796f171031bacf17106878d4a554e8f1cbfe93f8 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203145 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 4778ae4d08a25306407f0fd2fe47976d63463f9d) Increase the bootblock area for the larger BCT that is generated by the coreboot version of the cbootimage tool. Change-Id: I42b8208504bf4936a9fa14f820d665590f6a3754 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/soc/nvidia/tegra132/Kconfig | 4 ++-- src/soc/nvidia/tegra132/Makefile.inc | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index f11e60f..d90b8aa 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -16,10 +16,10 @@ config BOOTBLOCK_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" - default 0x18000 + default 0x40000 config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" - default 0x18080 + default 0x40080 endif diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index e31bbb6..f39dcb1 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -10,3 +10,32 @@ ramstage-y += cbmem.c ramstage-y += timer.c CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/ + +# We want to grab the bootblock right before it goes into the image and wrap +# it inside a BCT, but ideally we would do that without making special, one +# use modifications to the main ARM Makefile. We do this in two ways. First, +# we copy bootblock.elf to bootblock.raw.elf and allow the %.bin: %.elf +# template rule to turn it into bootblock.raw.bin. This makes sure whatever +# processing is supposed to happen to turn an .elf into a .bin happens. +# +# Second, we add our own rule for creating bootblock.bin from +# bootblock.raw.bin which displaces the template rule. When other rules that +# package up the image pull in bootblock.bin, it will be this wrapped version +# instead of the raw bootblock. + +$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf + cp $< $@ + +$(obj)/generated/bct.bin: $(obj)/generated/bct.cfg + @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" + $(CBOOTIMAGE) -gbct --soc tegra132 $< $@ + +BCT_BIN = $(obj)/generated/bct.bin +BCT_WRAPPER = $(obj)/generated/bct.wrapper +$(objcbfs)/bootblock.bin: $(CBOOTIMAGE) $(objcbfs)/bootblock.raw.bin $(BCT_BIN) + echo "Version = 1;" > $(BCT_WRAPPER) + echo "Redundancy = 1;" >> $(BCT_WRAPPER) + echo "Bctfile = $(BCT_BIN);" >> $(BCT_WRAPPER) + echo "BootLoader = $<,$(CONFIG_BOOTBLOCK_BASE),$(CONFIG_BOOTBLOCK_BASE),Complete;" >> $(BCT_WRAPPER) + @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" + $(CBOOTIMAGE) $(BCT_WRAPPER) $@

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New patch to review for coreboot: 9af5022 google/rush: Add BCT support in mainboard rush
by Marc Jones 11 Feb '15

11 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8412 -gerrit commit 9af502201f743b41e95bc8eebdfa63c3875911c0 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jun 9 13:22:07 2014 -0700 google/rush: Add BCT support in mainboard rush Changes might be required for .bct files as we get to know more. Pulling in files from mainboard nyan for now BUG=None BRANCH=None TEST=Compiles successfully for rush Change-Id: Iaf81a384af0469c77940cf7309ba68018110b5eb Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/203144 Tested-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit d3633f8cf8c01a07b54ceef2dd7bf7a64afd7c76) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/mainboard/google/rush/Kconfig | 18 ++ src/mainboard/google/rush/Makefile.inc | 10 + src/mainboard/google/rush/bct/Makefile.inc | 27 ++ src/mainboard/google/rush/bct/cfg2inc.sh | 34 +++ src/mainboard/google/rush/bct/emmc.cfg | 13 + src/mainboard/google/rush/bct/jtag.cfg | 16 ++ src/mainboard/google/rush/bct/odmdata.cfg | 1 + .../google/rush/bct/sdram-hynix-2GB-792.inc | 311 +++++++++++++++++++++ .../google/rush/bct/sdram-hynix-2GB-924.inc | 311 +++++++++++++++++++++ .../google/rush/bct/sdram-hynix-4GB-300.inc | 311 +++++++++++++++++++++ .../google/rush/bct/sdram-hynix-4GB-792.inc | 311 +++++++++++++++++++++ src/mainboard/google/rush/bct/sdram-unused.inc | 4 + src/mainboard/google/rush/bct/spi.cfg | 33 +++ 13 files changed, 1400 insertions(+) diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig index 96a17f8..9e36cac 100644 --- a/src/mainboard/google/rush/Kconfig +++ b/src/mainboard/google/rush/Kconfig @@ -36,4 +36,22 @@ config DRAM_SIZE_MB int default 2048 +choice + prompt "BCT boot media" + default RUSH_BCT_CFG_SPI + help + Which boot media to configure the BCT for. + +config RUSH_BCT_CFG_SPI + bool "SPI" + help + Configure the BCT for booting from SPI. + +config RUSH_BCT_CFG_EMMC + bool "eMMC" + help + Configure the BCT for booting from eMMC. + +endchoice + endif # BOARD_GOOGLE_RUSH diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc index 94a0e28..a0bd819 100644 --- a/src/mainboard/google/rush/Makefile.inc +++ b/src/mainboard/google/rush/Makefile.inc @@ -17,6 +17,16 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# Add a handler for BCT config files +$(call add-special-class,bct-cfg) +bct-cfg-handler= $(eval $(obj)/generated/bct.cfg: $(1)$(2)) + +$(obj)/generated/bct.cfg: + @printf " CAT $(subst $(obj)/,,$(@))\n" + cat $^ > $@ + +subdirs-y += bct + romstage-y += romstage.c ramstage-y += mainboard.c \ No newline at end of file diff --git a/src/mainboard/google/rush/bct/Makefile.inc b/src/mainboard/google/rush/bct/Makefile.inc new file mode 100644 index 0000000..d4a2c24 --- /dev/null +++ b/src/mainboard/google/rush/bct/Makefile.inc @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +bct-cfg-$(CONFIG_RUSH_BCT_CFG_EMMC) += emmc.cfg +bct-cfg-$(CONFIG_RUSH_BCT_CFG_SPI) += spi.cfg +bct-cfg-y += odmdata.cfg +bct-cfg-y += jtag.cfg + +# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate +# the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg". +# TODO(hungte) Change cfg2inc.sh to NVIDIA's official tool in cbootimage. diff --git a/src/mainboard/google/rush/bct/cfg2inc.sh b/src/mainboard/google/rush/bct/cfg2inc.sh new file mode 100755 index 0000000..a9c629b --- /dev/null +++ b/src/mainboard/google/rush/bct/cfg2inc.sh @@ -0,0 +1,34 @@ +#!/bin/sh +# +# This file is part of the coreboot project. +# +# Copyright 2014 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +bct_cfg2inc() { + local in_file="$1" + local out_file="$2" + echo "{ /* generated from ${in_file}; do not edit. */" >"${out_file}" + # Note currently we can only handle DDR3 type memory, even in C + # implementation. + sed "/^#.*$/d; s/^SDRAM.0./ /; s/\r$//; s/;$/,/;" \ + "${in_file}" >> "${out_file}" + echo "}," >>"${out_file}" +} + +for file in $@; do + echo "Generating $file => ${file%cfg}inc..." + bct_cfg2inc "${file}" "${file%cfg}inc" +done diff --git a/src/mainboard/google/rush/bct/emmc.cfg b/src/mainboard/google/rush/bct/emmc.cfg new file mode 100644 index 0000000..be8f79f --- /dev/null +++ b/src/mainboard/google/rush/bct/emmc.cfg @@ -0,0 +1,13 @@ +# Copyright (c) 2013 The Chromium OS Authors. All rights reserved. +# Distributed under the terms of the GNU General Public License v2 + +Version = 0x00350001; +BlockSize = 0x00004000; +PageSize = 0x00000200; +PartitionSize = 0x01000000; + +DevType[0] = NvBootDevType_Sdmmc; +DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009; +DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit; +DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000; +DeviceParam[0].SdmmcParams.MultiPageSupport = 0x00000000; diff --git a/src/mainboard/google/rush/bct/jtag.cfg b/src/mainboard/google/rush/bct/jtag.cfg new file mode 100644 index 0000000..f43e143 --- /dev/null +++ b/src/mainboard/google/rush/bct/jtag.cfg @@ -0,0 +1,16 @@ +# +# Set JtagCtrl to 1 to reenable Jtag +# +JtagCtrl = 0; +# +# Fill in chip unique id +# +# ChipUid can be found by running tegrarcm in tegra recovery mode +# (also hooking up A-A USB cable) and looking for console output +# on line starting with "Chip UID:" +# +# Command example: +# $ sudo tegrarcm --bct=/build/nyan/firmware/bct/board.bct --bootloader=/build/nyan/firmware/u-boot.bin --loadaddr=0x80108000 +# Where board.bct and u-boot.bin do not have to be prebuilt. +# +ChipUid = 0x00000000000000000000000000000000; diff --git a/src/mainboard/google/rush/bct/odmdata.cfg b/src/mainboard/google/rush/bct/odmdata.cfg new file mode 100644 index 0000000..d0ab2bf --- /dev/null +++ b/src/mainboard/google/rush/bct/odmdata.cfg @@ -0,0 +1 @@ +OdmData = 0x80080000; diff --git a/src/mainboard/google/rush/bct/sdram-hynix-2GB-792.inc b/src/mainboard/google/rush/bct/sdram-hynix-2GB-792.inc new file mode 100644 index 0000000..d175e7b --- /dev/null +++ b/src/mainboard/google/rush/bct/sdram-hynix-2GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000025, + .EmcRfc = 0x000000cd, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x00000019, + .EmcRp = 0x0000000a, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000007, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x0000000a, + .EmcWrRcd = 0x0000000a, + .EmcRrd = 0x00000003, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000003, + .EmcEInputDuration = 0x0000000c, + .EmcPutermExtra = 0x00090000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000002, + .EmcQSafe = 0x00000011, + .EmcRdv = 0x00000017, + .EmcRdvMask = 0x00000019, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017eb, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005fa, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000003, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000c7, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x000000d7, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x0000182c, + .EmcFbioCfg5 = 0x104ab898, + .EmcFbioCfg6 = 0x00000002, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80001d71, + .EmcEmrs = 0x80100002, + .EmcEmrs2 = 0x80200018, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00f7000e, + .EmcMrsWaitCnt2 = 0x00f7000e, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x000040a0, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003025, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00701b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000008, + .EmcDllXformDqs1 = 0x00000008, + .EmcDllXformDqs2 = 0x00000008, + .EmcDllXformDqs3 = 0x00000008, + .EmcDllXformDqs4 = 0x00000008, + .EmcDllXformDqs5 = 0x00000008, + .EmcDllXformDqs6 = 0x00000008, + .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs8 = 0x00000008, + .EmcDllXformDqs9 = 0x00000008, + .EmcDllXformDqs10 = 0x00000008, + .EmcDllXformDqs11 = 0x00000008, + .EmcDllXformDqs12 = 0x00000008, + .EmcDllXformDqs13 = 0x00000008, + .EmcDllXformDqs14 = 0x00000008, + .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x0000000e, + .EmcDllXformAddr1 = 0x0000000e, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x0000000e, + .EmcDllXformAddr4 = 0x00000000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x0000000b, + .EmcDllXformDq1 = 0x0000000b, + .EmcDllXformDq2 = 0x0000000b, + .EmcDllXformDq3 = 0x0000000b, + .EmcDllXformDq4 = 0x0000000b, + .EmcDllXformDq5 = 0x0000000b, + .EmcDllXformDq6 = 0x0000000b, + .EmcDllXformDq7 = 0x0000000b, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80001d71, + .EmcWarmBootMrsExtra = 0x80100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0020013d, + .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000707, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x017fffff, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0505003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000005, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000005, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08050202, + .McEmemArbDaCovers = 0x00170e13, + .McEmemArbMisc0 = 0x736c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/rush/bct/sdram-hynix-2GB-924.inc b/src/mainboard/google/rush/bct/sdram-hynix-2GB-924.inc new file mode 100644 index 0000000..b10a696 --- /dev/null +++ b/src/mainboard/google/rush/bct/sdram-hynix-2GB-924.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-hynix-2GB-924.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x0000004d, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430101, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x0000002b, + .EmcRfc = 0x000000f0, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001e, + .EmcRp = 0x0000000b, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x0000000a, + .EmcW2r = 0x0000000f, + .EmcR2p = 0x00000005, + .EmcW2p = 0x00000016, + .EmcRdRcd = 0x0000000b, + .EmcWrRcd = 0x0000000b, + .EmcRrd = 0x00000004, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000007, + .EmcWdvMask = 0x00000007, + .EmcQUse = 0x0000000d, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000f, + .EmcPutermExtra = 0x000a0000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000016, + .EmcRdv = 0x0000001a, + .EmcRdvMask = 0x0000001c, + .EmcQpop = 0x00000011, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x00001be7, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000006f9, + .EmcPdEx2Wr = 0x00000004, + .EmcPdEx2Rd = 0x00000015, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000e7, + .EmcRw2Pden = 0x0000001b, + .EmcTxsr = 0x000000fb, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000006, + .EmcTckesr = 0x00000007, + .EmcTpd = 0x00000006, + .EmcTfaw = 0x00000022, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x0000000a, + .EmcTClkStop = 0x0000000a, + .EmcTRefBw = 0x00001c28, + .EmcFbioCfg5 = 0x104ab898, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80000f15, + .EmcEmrs = 0x80100002, + .EmcEmrs2 = 0x80200020, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00cd000e, + .EmcMrsWaitCnt2 = 0x00cd000e, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x00004080, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x800037ea, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00400b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x007fc005, + .EmcDllXformDqs1 = 0x007fc005, + .EmcDllXformDqs2 = 0x007f8008, + .EmcDllXformDqs3 = 0x007f8008, + .EmcDllXformDqs4 = 0x007fc005, + .EmcDllXformDqs5 = 0x007f8008, + .EmcDllXformDqs6 = 0x007fc005, + .EmcDllXformDqs7 = 0x007fc005, + .EmcDllXformDqs8 = 0x007fc005, + .EmcDllXformDqs9 = 0x007fc005, + .EmcDllXformDqs10 = 0x007f8008, + .EmcDllXformDqs11 = 0x007f8008, + .EmcDllXformDqs12 = 0x007fc005, + .EmcDllXformDqs13 = 0x007f8008, + .EmcDllXformDqs14 = 0x007fc005, + .EmcDllXformDqs15 = 0x007fc005, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x00018000, + .EmcDllXformAddr1 = 0x00018000, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x00018000, + .EmcDllXformAddr4 = 0x00018000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x00000007, + .EmcDllXformDq1 = 0x00000007, + .EmcDllXformDq2 = 0x00000007, + .EmcDllXformDq3 = 0x00000007, + .EmcDllXformDq4 = 0x00000007, + .EmcDllXformDq5 = 0x00000007, + .EmcDllXformDq6 = 0x00000007, + .EmcDllXformDq7 = 0x00000007, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x0000004c, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80000f15, + .EmcWarmBootMrsExtra = 0x80100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0120113d, + .EmcXm2DqsPadCtrl3 = 0x5d569720, + .EmcXm2DqsPadCtrl4 = 0x00492492, + .EmcXm2DqsPadCtrl5 = 0x00552452, + .EmcXm2DqsPadCtrl6 = 0x61751800, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000000, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x0e00000d, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000005, + .McEmemArbTimingRp = 0x00000006, + .McEmemArbTimingRc = 0x00000016, + .McEmemArbTimingRas = 0x0000000e, + .McEmemArbTimingFaw = 0x00000011, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000004, + .McEmemArbTimingWap2Pre = 0x0000000e, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000007, + .McEmemArbTimingW2R = 0x00000009, + .McEmemArbDaTurns = 0x09070202, + .McEmemArbDaCovers = 0x001a1016, + .McEmemArbMisc0 = 0x734e2a17, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/rush/bct/sdram-hynix-4GB-300.inc b/src/mainboard/google/rush/bct/sdram-hynix-4GB-300.inc new file mode 100644 index 0000000..21bf515 --- /dev/null +++ b/src/mainboard/google/rush/bct/sdram-hynix-4GB-300.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-hynix-4GB-300.cfg, do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000032, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x00000002, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430f0f, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000001, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x0000000d, + .EmcRfc = 0x00000067, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x00000009, + .EmcRp = 0x00000003, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000005, + .EmcW2r = 0x00000008, + .EmcR2p = 0x00000002, + .EmcW2p = 0x00000009, + .EmcRdRcd = 0x00000003, + .EmcWrRcd = 0x00000003, + .EmcRrd = 0x00000002, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000003, + .EmcWdvMask = 0x00000003, + .EmcQUse = 0x00000005, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x00000007, + .EmcPutermExtra = 0x00020000, + .EmcPutermWidth = 0x00000003, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x0000000e, + .EmcRdv = 0x00000010, + .EmcRdvMask = 0x00000012, + .EmcQpop = 0x00000009, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000003, + .EmcRefresh = 0x000008e4, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x00000239, + .EmcPdEx2Wr = 0x00000001, + .EmcPdEx2Rd = 0x00000008, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x00000065, + .EmcRw2Pden = 0x0000000e, + .EmcTxsr = 0x0000006c, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000004, + .EmcTckesr = 0x00000005, + .EmcTpd = 0x00000004, + .EmcTfaw = 0x00000009, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000005, + .EmcTClkStop = 0x00000005, + .EmcTRefBw = 0x00000924, + .EmcFbioCfg5 = 0x104ab098, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x00000321, + .EmcEmrs = 0x00100002, + .EmcEmrs2 = 0x00200000, + .EmcEmrs3 = 0x00300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x0117000e, + .EmcMrsWaitCnt2 = 0x0117000e, + .EmcCfg = 0x73340000, + .EmcCfg2 = 0x000008d5, + .EmcCfgPipe = 0x000052a3, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x800012d7, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0x002c00a0, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000000, + .EmcSelDpdCtrl = 0x00040128, + .EmcDllXformDqs0 = 0x00030000, + .EmcDllXformDqs1 = 0x00030000, + .EmcDllXformDqs2 = 0x00030000, + .EmcDllXformDqs3 = 0x00030000, + .EmcDllXformDqs4 = 0x00030000, + .EmcDllXformDqs5 = 0x00030000, + .EmcDllXformDqs6 = 0x00030000, + .EmcDllXformDqs7 = 0x00030000, + .EmcDllXformDqs8 = 0x00030000, + .EmcDllXformDqs9 = 0x00030000, + .EmcDllXformDqs10 = 0x00030000, + .EmcDllXformDqs11 = 0x00030000, + .EmcDllXformDqs12 = 0x00030000, + .EmcDllXformDqs13 = 0x00030000, + .EmcDllXformDqs14 = 0x00030000, + .EmcDllXformDqs15 = 0x00030000, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x00084000, + .EmcDllXformAddr1 = 0x00084000, + .EmcDllXformAddr2 = 0x00010000, + .EmcDllXformAddr3 = 0x00084000, + .EmcDllXformAddr4 = 0x00084000, + .EmcDllXformAddr5 = 0x00010000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x00060000, + .EmcDllXformDq1 = 0x00060000, + .EmcDllXformDq2 = 0x00060000, + .EmcDllXformDq3 = 0x00060000, + .EmcDllXformDq4 = 0x00006000, + .EmcDllXformDq5 = 0x00006000, + .EmcDllXformDq6 = 0x00006000, + .EmcDllXformDq7 = 0x00006000, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x00000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x40000011, + .EmcZcalInitWait = 0x00000002, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000002, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x00000321, + .EmcWarmBootMrsExtra = 0x00100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fffffff, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x10000280, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x01231339, + .EmcXm2DqsPadCtrl3 = 0x51451420, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x51451400, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc081, + .EmcXm2ClkPadCtrl2 = 0x00000000, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0000003f, + .EmcTxdsrvttgen = 0x00000096, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000001, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00001000, + .McEmemArbCfg = 0x08000004, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000001, + .McEmemArbTimingRp = 0x00000002, + .McEmemArbTimingRc = 0x00000007, + .McEmemArbTimingRas = 0x00000004, + .McEmemArbTimingFaw = 0x00000005, + .McEmemArbTimingRrd = 0x00000001, + .McEmemArbTimingRap2Pre = 0x00000002, + .McEmemArbTimingWap2Pre = 0x00000007, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000004, + .McEmemArbTimingW2R = 0x00000006, + .McEmemArbDaTurns = 0x06040202, + .McEmemArbDaCovers = 0x000b0607, + .McEmemArbMisc0 = 0x77450e08, + .McEmemArbMisc1 = 0x70000f03, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0x78000000, + .McMtsCarveoutAdrHi = 0x00000001, + .McMtsCarveoutSizeMb = 0x00000080, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/rush/bct/sdram-hynix-4GB-792.inc b/src/mainboard/google/rush/bct/sdram-hynix-4GB-792.inc new file mode 100644 index 0000000..70f6ccd --- /dev/null +++ b/src/mainboard/google/rush/bct/sdram-hynix-4GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-hynix-4GB-792.cfg, do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430808, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000001, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000024, + .EmcRfc = 0x00000114, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x00000019, + .EmcRp = 0x0000000a, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x0000000a, + .EmcWrRcd = 0x0000000a, + .EmcRrd = 0x00000003, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000d, + .EmcPutermExtra = 0x00080000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000014, + .EmcRdv = 0x00000017, + .EmcRdvMask = 0x00000019, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017e2, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005f8, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000011, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x0000010d, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x0000011e, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x00001822, + .EmcFbioCfg5 = 0x104ab098, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x00000d71, + .EmcEmrs = 0x00100002, + .EmcEmrs2 = 0x00200018, + .EmcEmrs3 = 0x00300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x006f000e, + .EmcMrsWaitCnt2 = 0x006f000e, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x000040a0, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003012, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00700b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000000, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000008, + .EmcDllXformDqs1 = 0x00000008, + .EmcDllXformDqs2 = 0x00000008, + .EmcDllXformDqs3 = 0x00000008, + .EmcDllXformDqs4 = 0x00000008, + .EmcDllXformDqs5 = 0x00000008, + .EmcDllXformDqs6 = 0x00000008, + .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs8 = 0x00000008, + .EmcDllXformDqs9 = 0x00000008, + .EmcDllXformDqs10 = 0x00000008, + .EmcDllXformDqs11 = 0x00000008, + .EmcDllXformDqs12 = 0x00000008, + .EmcDllXformDqs13 = 0x00000008, + .EmcDllXformDqs14 = 0x00000008, + .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x00038000, + .EmcDllXformAddr1 = 0x00038000, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x00038000, + .EmcDllXformAddr4 = 0x00038000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000005, + .EmcDliTrimTxDqs1 = 0x00000005, + .EmcDliTrimTxDqs2 = 0x00000003, + .EmcDliTrimTxDqs3 = 0x00000005, + .EmcDliTrimTxDqs4 = 0x00000005, + .EmcDliTrimTxDqs5 = 0x00000002, + .EmcDliTrimTxDqs6 = 0x00000005, + .EmcDliTrimTxDqs7 = 0x00000005, + .EmcDliTrimTxDqs8 = 0x00000005, + .EmcDliTrimTxDqs9 = 0x00000005, + .EmcDliTrimTxDqs10 = 0x00000003, + .EmcDliTrimTxDqs11 = 0x00000005, + .EmcDliTrimTxDqs12 = 0x00000005, + .EmcDliTrimTxDqs13 = 0x00000002, + .EmcDliTrimTxDqs14 = 0x00000005, + .EmcDliTrimTxDqs15 = 0x00000005, + .EmcDllXformDq0 = 0x00000009, + .EmcDllXformDq1 = 0x0000000c, + .EmcDllXformDq2 = 0x00000008, + .EmcDllXformDq3 = 0x0000000a, + .EmcDllXformDq4 = 0x0000000a, + .EmcDllXformDq5 = 0x00000008, + .EmcDllXformDq6 = 0x0000000a, + .EmcDllXformDq7 = 0x00000008, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x00000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x40000011, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x00000d71, + .EmcWarmBootMrsExtra = 0x00100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fffffff, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0120113d, + .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000000, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000001, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00001000, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000005, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08060202, + .McEmemArbDaCovers = 0x00170e13, + .McEmemArbMisc0 = 0x746c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/rush/bct/sdram-unused.inc b/src/mainboard/google/rush/bct/sdram-unused.inc new file mode 100644 index 0000000..bef63dc --- /dev/null +++ b/src/mainboard/google/rush/bct/sdram-unused.inc @@ -0,0 +1,4 @@ +{ /* dummy. */ + .MemoryType = NvBootMemoryType_Unused, + 0, +}, diff --git a/src/mainboard/google/rush/bct/spi.cfg b/src/mainboard/google/rush/bct/spi.cfg new file mode 100644 index 0000000..7d05363 --- /dev/null +++ b/src/mainboard/google/rush/bct/spi.cfg @@ -0,0 +1,33 @@ +# Copyright (c) 2013 The Chromium OS Authors. All rights reserved. +# Distributed under the terms of the GNU General Public License v2 + +Version = 0x00350001; +BlockSize = 32768; +PageSize = 2048; +PartitionSize = 4194304; + +Bctcopy = 1; + +DevType[0] = NvBootDevType_Spi; +DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[0].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0; + +DevType[1] = NvBootDevType_Spi; +DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[1].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0; + +DevType[2] = NvBootDevType_Spi; +DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[2].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0; + +DevType[3] = NvBootDevType_Spi; +DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[3].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0;

1 0

New patch to review for coreboot: 5677c5e cbootimage: Add HOSTCC and flags
by Marc Jones 11 Feb '15

11 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8411 -gerrit commit 5677c5ef09b4b4a9f8fbf62c7d716f988ed56a04 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Feb 10 14:15:45 2015 -0700 cbootimage: Add HOSTCC and flags Add the flags used by the Nvidia makefile and use HOSTCC to build cbootimage. Note that adding -g makes the BCT very large, so leave that flag out. Change-Id: I4431efffdfdcbd030665b26f5b799352e38d1f95 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- util/nvidia/Makefile.inc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/util/nvidia/Makefile.inc b/util/nvidia/Makefile.inc index c8be3bb..9540473 100644 --- a/util/nvidia/Makefile.inc +++ b/util/nvidia/Makefile.inc @@ -37,12 +37,14 @@ CBOOTIMAGE_RAW_SRCS:= \ CBOOTIMAGE_SRCS:=$(addprefix util/nvidia/cbootimage/src/,$(filter %.c,$(CBOOTIMAGE_RAW_SRCS))) CBOOTIMAGE_OBJS:=$(addprefix $(objutil)/nvidia/cbootimage/,$(patsubst %.c,%.o,$(filter %.c,$(CBOOTIMAGE_RAW_SRCS)))) +CBOOTIMAGE_FLAGS:=-Wall -std=c99 -O2 additional-dirs += $(sort $(dir $(CBOOTIMAGE_OBJS))) $(objutil)/nvidia/cbootimage/%.o: util/nvidia/cbootimage/src/%.c - gcc -c -o $@ $< + printf " HOSTCC $(subst $(objutil)/,,$(@))\n" + $(HOSTCC) $(CBOOTIMAGE_FLAGS) -c -o $@ $< $(CBOOTIMAGE): $(CBOOTIMAGE_OBJS) - gcc -o $@.tmp $^ -lm - mv $@.tmp $@ + printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" + $(HOSTCC) $(CBOOTIMAGE_FLAGS) -o $@ $^ -lm

1 0

New patch to review for coreboot: 07d4dac arm64: Cleanup of arch io header files
by Marc Jones 11 Feb '15

11 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8410 -gerrit commit 07d4dac0bd5a45ee6537d776882ec7acf241db11 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jun 9 13:08:06 2014 -0700 arm64: Cleanup of arch io header files BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: Ic8f5d91f6635ef12845ab049a20df5a6e33bbf55 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203142 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit ecf7822812d8745af74eaf135b7b806c23ef51a2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I79abbded94376ba90a8c729aaf856ce303509e48 --- src/arch/arm64/include/arch/io.h | 181 +++++++++++----------------- src/arch/arm64/include/armv8/arch/arch_io.h | 68 +++++++++++ 2 files changed, 137 insertions(+), 112 deletions(-) diff --git a/src/arch/arm64/include/arch/io.h b/src/arch/arm64/include/arch/io.h index 49d851d..cd75fb8 100644 --- a/src/arch/arm64/include/arch/io.h +++ b/src/arch/arm64/include/arch/io.h @@ -1,137 +1,94 @@ /* - * Based on (linux) arch/arm/include/asm/io.h + * Originally imported from linux/include/asm-arm/io.h. This file has changed + * substantially since then. * - * Copyright (C) 1996-2000 Russell King - * Copyright (C) 2012 ARM Ltd. - * Copyright 2013 Google, Inc. + * Copyright 2013 Google Inc. + * Copyright (C) 1996-2000 Russell King * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * Modifications: + * 08-Apr-2013 G Replaced several macros with inlines for type safety. + * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both + * constant addresses and variable addresses. + * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture + * specific IO header files. + * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. + * 04-Apr-1999 PJB Added check_signature. + * 12-Dec-1999 RMK More cleanups + * 18-Jun-2000 RMK Removed virt_to_* and friends definitions */ -#ifndef __ASM_ARM_IO_H -#define __ASM_ARM_IO_H +#ifndef __ASM_ARM64_IO_H +#define __ASM_ARM64_IO_H -#include <types.h> #include <arch/byteorder.h> -#include <arch/barrier.h> +#include <arch/arch_io.h> +#include <stdint.h> /* - * Generic IO read/write. These perform native-endian accesses. - */ -static inline void __raw_writeb(u8 val, volatile void *addr) -{ - asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr)); -} - -static inline void __raw_writew(u16 val, volatile void *addr) -{ - asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr)); -} - -static inline void __raw_writel(u32 val, volatile void *addr) -{ - asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr)); -} - -static inline void __raw_writeq(u64 val, volatile void *addr) -{ - asm volatile("str %0, [%1]" : : "r" (val), "r" (addr)); -} - -static inline u8 __raw_readb(const volatile void *addr) -{ - u8 val; - asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr)); - return val; -} - -static inline u16 __raw_readw(const volatile void *addr) -{ - u16 val; - asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr)); - return val; -} - -static inline u32 __raw_readl(const volatile void *addr) -{ - u32 val; - asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr)); - return val; -} - -static inline u64 __raw_readq(const volatile void *addr) -{ - u64 val; - asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr)); - return val; -} - -/* IO barriers */ -#define __iormb() rmb() -#define __iowmb() wmb() - -#define mmiowb() do { } while (0) + * FIXME: These are to avoid breaking existing ARM code. We should eventually + * re-factor all code to specify the data length intended. + */ +#define readb(a) read8(a) +#define writeb(v,a) write8(v,a) +#define readl(a) read32(a) +#define writel(v,a) write32(v,a) /* - * Relaxed I/O memory access primitives. These follow the Device memory - * ordering rules but do not guarantee any ordering relative to Normal memory - * accesses. + * Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. */ -#define readb_relaxed(c) ({ u8 __u = __raw_readb(c); __u; }) -#define readw_relaxed(c) ({ u16 __u = le16_to_cpu((__force __le16)__raw_readw(c)); __u; }) -#define readl_relaxed(c) ({ u32 __u = le32_to_cpu((__force __le32)__raw_readl(c)); __u; }) -#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c))) -#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) -#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) +#define out_arch(type,endian,a,v) write##type(cpu_to_##endian(v),a) +#define in_arch(type,endian,a) endian##_to_cpu(read##type(a)) -/* - * I/O memory access primitives. Reads are ordered relative to any - * following Normal memory access. Writes are ordered relative to any prior - * Normal memory access. - */ -#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) -#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) -#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) +#define out_le32(a,v) out_arch(l,le32,a,v) +#define out_le16(a,v) out_arch(w,le16,a,v) -#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); }) -#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); }) -#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); }) +#define in_le32(a) in_arch(l,le32,a) +#define in_le16(a) in_arch(w,le16,a) -#define inb_p(addr) inb(addr) -#define inw_p(addr) inw(addr) -#define inl_p(addr) inl(addr) +#define out_be32(a,v) out_arch(l,be32,a,v) +#define out_be16(a,v) out_arch(w,be16,a,v) -#define outb_p(x, addr) outb((x), (addr)) -#define outw_p(x, addr) outw((x), (addr)) -#define outl_p(x, addr) outl((x), (addr)) +#define in_be32(a) in_arch(l,be32,a) +#define in_be16(a) in_arch(w,be16,a) -#define insb_p(port,to,len) insb(port,to,len) -#define insw_p(port,to,len) insw(port,to,len) -#define insl_p(port,to,len) insl(port,to,len) +#define out_8(a,v) writeb(v,a) +#define in_8(a) readb(a) -#define outsb_p(port,from,len) outsb(port,from,len) -#define outsw_p(port,from,len) outsw(port,from,len) -#define outsl_p(port,from,len) outsl(port,from,len) +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) -/* - * String version of I/O memory access operations. - */ -extern void __memcpy_fromio(void *, const volatile void *, size_t); -extern void __memcpy_toio(volatile void *, const void *, size_t); -extern void __memset_io(volatile void *, int, size_t); +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) -#define memset_io(c,v,l) __memset_io((c),(v),(l)) -#define memcpy_fromio(a,c,l) __memcpy_fromio((a),(c),(l)) -#define memcpy_toio(c,a,l) __memcpy_toio((c),(a),(l)) +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) -#endif /* __ASM_ARM_IO_H */ +#endif /* __ASM_ARM64_IO_H */ diff --git a/src/arch/arm64/include/armv8/arch/arch_io.h b/src/arch/arm64/include/armv8/arch/arch_io.h new file mode 100644 index 0000000..56ed86d --- /dev/null +++ b/src/arch/arm64/include/armv8/arch/arch_io.h @@ -0,0 +1,68 @@ +/* + * Originally imported from linux/include/asm-arm/io.h. This file has changed + * substantially since then. + * + * Copyright 2014 Google Inc. + * Copyright (C) 1996-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Modifications: + * 08-Apr-2013 G Replaced several macros with inlines for type safety. + * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both + * constant addresses and variable addresses. + * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture + * specific IO header files. + * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. + * 04-Apr-1999 PJB Added check_signature. + * 12-Dec-1999 RMK More cleanups + * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + */ +#ifndef __ASM_ARM64_ARCH_IO_H +#define __ASM_ARM64_ARCH_IO_H + +#include <arch/cache.h> /* for dmb() */ +#include <stdint.h> + +static inline uint8_t read8(const void *addr) +{ + dmb(); + return *(volatile uint8_t *)addr; +} + +static inline uint16_t read16(const void *addr) +{ + dmb(); + return *(volatile uint16_t *)addr; +} + +static inline uint32_t read32(const void *addr) +{ + dmb(); + return *(volatile uint32_t *)addr; +} + +static inline void write8(uint8_t val, void *addr) +{ + dmb(); + *(volatile uint8_t *)addr = val; + dmb(); +} + +static inline void write16(uint16_t val, void *addr) +{ + dmb(); + *(volatile uint16_t *)addr = val; + dmb(); +} + +static inline void write32(uint32_t val, void *addr) +{ + dmb(); + *(volatile uint32_t *)addr = val; + dmb(); +} + +#endif /* __ASM_ARM64_ARCH_IO_H */

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New patch to review for coreboot: be91680 tegra132: Fix build for verstage
by Marc Jones 11 Feb '15

11 Feb '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8409 -gerrit commit be916806d2b79c7a960a5277849ad21cfffe616f Author: Marc Jones <marc.jones(a)se-eng.com> Date: Wed Jan 28 13:15:46 2015 +0800 tegra132: Fix build for verstage Verstage isn't included yet, but we need to have the Kconfig option for toolchain.inc to pass. Change-Id: I7fae73cd3b77fd347398221489caf745274701eb Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/soc/nvidia/tegra132/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index df58f06..f11e60f 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -2,6 +2,7 @@ config SOC_NVIDIA_TEGRA132 bool default n select ARCH_BOOTBLOCK_ARMV4 + select ARCH_VERSTAGE_ARMV4 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 select ARM_LPAE

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Patch set updated for coreboot: 289da28 northbridge/amd/amdfam10: Allow mainboards to set maximum HT link frequency
by Timothy Pearson 10 Feb '15

10 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8405 -gerrit commit 289da28319ee43f1ae33b74231971246fda8a8e7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 10 13:13:39 2015 -0600 northbridge/amd/amdfam10: Allow mainboards to set maximum HT link frequency Most K10 mainboards are designed to a maximum HT frequency specification. Coreboot supports CPUs that were released after mainboard production; these CPUs may support and autodetect HT link frequencies beyond the mainboard design capabilities. This patch allows mainboards to set an HT frequency limit if needed. Moved K10 specific menu to amdfam10 Kconfig file. Change-Id: If7ff40dccb4c22829062511ca0046aa2caf15580 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/Kconfig | 132 ---------------------- src/northbridge/amd/amdfam10/Kconfig | 205 +++++++++++++++++++++++++++++++++++ 2 files changed, 205 insertions(+), 132 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index 17f15c3..98a0e9e 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -5,135 +5,3 @@ source src/northbridge/amd/lx/Kconfig source src/northbridge/amd/agesa/Kconfig source src/northbridge/amd/cimx/Kconfig source src/northbridge/amd/pi/Kconfig - -menu "HyperTransport setup" - #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) - depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT - -choice - prompt "HyperTransport frequency" - default LIMIT_HT_SPEED_AUTO - help - This option sets the maximum permissible HyperTransport link - frequency. - - Use of this option will only limit the autodetected HT frequency. - It will not (and cannot) increase the frequency beyond the - autodetected limits. - - This is primarily used to work around poorly designed or laid out - HT traces on certain motherboards. - -config LIMIT_HT_SPEED_200 - bool "Limit HT frequency to 200MHz" -config LIMIT_HT_SPEED_300 - bool "Limit HT frequency to 300MHz" -config LIMIT_HT_SPEED_400 - bool "Limit HT frequency to 400MHz" -config LIMIT_HT_SPEED_500 - bool "Limit HT frequency to 500MHz" -config LIMIT_HT_SPEED_600 - bool "Limit HT frequency to 600MHz" -config LIMIT_HT_SPEED_800 - bool "Limit HT frequency to 800MHz" -config LIMIT_HT_SPEED_1000 - bool "Limit HT frequency to 1.0GHz" -config LIMIT_HT_SPEED_1200 - bool "Limit HT frequency to 1.2GHz" -config LIMIT_HT_SPEED_1400 - bool "Limit HT frequency to 1.4GHz" -config LIMIT_HT_SPEED_1600 - bool "Limit HT frequency to 1.6GHz" -config LIMIT_HT_SPEED_1800 - bool "Limit HT frequency to 1.8GHz" -config LIMIT_HT_SPEED_2000 - bool "Limit HT frequency to 2.0GHz" -config LIMIT_HT_SPEED_2200 - bool "Limit HT frequency to 2.2GHz" -config LIMIT_HT_SPEED_2400 - bool "Limit HT frequency to 2.4GHz" -config LIMIT_HT_SPEED_2600 - bool "Limit HT frequency to 2.6GHz" -config LIMIT_HT_SPEED_AUTO - bool "Autodetect HT frequency" -endchoice - -choice - prompt "HyperTransport downlink width" - default LIMIT_HT_DOWN_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - downlink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_DOWN_WIDTH_8 - bool "8 bits" -config LIMIT_HT_DOWN_WIDTH_16 - bool "16 bits" -endchoice - -choice - prompt "HyperTransport uplink width" - default LIMIT_HT_UP_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - uplink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_UP_WIDTH_8 - bool "8 bits" -config LIMIT_HT_UP_WIDTH_16 - bool "16 bits" -endchoice - -config AMDMCT_ENABLE_ECC_REDIR - bool - depends on CPU_AMD_MODEL_10XXX - default n - -config AMDMCT_BACKGROUND_SCRUB_RATE - hex - depends on CPU_AMD_MODEL_10XXX - default 0x00 - help - This option sets the background ECC memory scub rate - - Permissible values are: - - 0x00; Disabled - 0x01; 40ns - 0x02; 80ns - 0x03; 160ns - 0x04; 320ns - 0x05; 640ns - 0x06; 1.28us - 0x07; 2.56us - 0x08; 5.12us - 0x09; 10.2us - 0x0a; 20.5us - 0x0b; 41us - 0x0c; 81.9us - 0x0d; 163.8us - 0x0e; 327.7us - 0x0f; 655.4us - 0x10; 1.31ms - 0x11; 2.62ms - 0x12; 5.24ms - 0x13; 10.49ms - 0x14; 20.97sms - 0x15; 42ms - 0x16; 84ms - -endmenu diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 13b912e..35a683e 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -124,4 +124,209 @@ config SVI_HIGH_FREQ Select this for boards with a Voltage Regulator able to operate at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. +config FORCE_LIMIT_HT_SPEED_200 + bool + default n + +config FORCE_LIMIT_HT_SPEED_300 + bool + default n + +config FORCE_LIMIT_HT_SPEED_400 + bool + default n + +config FORCE_LIMIT_HT_SPEED_500 + bool + default n + +config FORCE_LIMIT_HT_SPEED_600 + bool + default n + +config FORCE_LIMIT_HT_SPEED_800 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1000 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1200 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1400 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1600 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1800 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2000 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2200 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2400 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2600 + bool + default n + +menu "HyperTransport setup" + # FIXME uncomment when coreboot gains "visible if" support + # visible if EXPERT + +choice + prompt "HyperTransport frequency" + default LIMIT_HT_SPEED_AUTO if (!FORCE_LIMIT_HT_SPEED_200 && !FORCE_LIMIT_HT_SPEED_300 && !FORCE_LIMIT_HT_SPEED_400 && !FORCE_LIMIT_HT_SPEED_500 && !FORCE_LIMIT_HT_SPEED_600 && !FORCE_LIMIT_HT_SPEED_800 && !FORCE_LIMIT_HT_SPEED_1000 && !FORCE_LIMIT_HT_SPEED_1200 && !FORCE_LIMIT_HT_SPEED_1400 && !FORCE_LIMIT_HT_SPEED_1600 && !FORCE_LIMIT_HT_SPEED_1800 && !FORCE_LIMIT_HT_SPEED_2000 && !FORCE_LIMIT_HT_SPEED_2200 && !FORCE_LIMIT_HT_SPEED_2400 && !FORCE_LIMIT_HT_SPEED_2600) + default LIMIT_HT_SPEED_200 if FORCE_LIMIT_HT_SPEED_200 + default LIMIT_HT_SPEED_300 if FORCE_LIMIT_HT_SPEED_300 + default LIMIT_HT_SPEED_400 if FORCE_LIMIT_HT_SPEED_400 + default LIMIT_HT_SPEED_500 if FORCE_LIMIT_HT_SPEED_500 + default LIMIT_HT_SPEED_600 if FORCE_LIMIT_HT_SPEED_600 + default LIMIT_HT_SPEED_800 if FORCE_LIMIT_HT_SPEED_800 + default LIMIT_HT_SPEED_1000 if FORCE_LIMIT_HT_SPEED_1000 + default LIMIT_HT_SPEED_1200 if FORCE_LIMIT_HT_SPEED_1200 + default LIMIT_HT_SPEED_1400 if FORCE_LIMIT_HT_SPEED_1400 + default LIMIT_HT_SPEED_1600 if FORCE_LIMIT_HT_SPEED_1600 + default LIMIT_HT_SPEED_1800 if FORCE_LIMIT_HT_SPEED_1800 + default LIMIT_HT_SPEED_2000 if FORCE_LIMIT_HT_SPEED_2000 + default LIMIT_HT_SPEED_2200 if FORCE_LIMIT_HT_SPEED_2200 + default LIMIT_HT_SPEED_2400 if FORCE_LIMIT_HT_SPEED_2400 + default LIMIT_HT_SPEED_2600 if FORCE_LIMIT_HT_SPEED_2600 + help + This option sets the maximum permissible HyperTransport link + frequency. + + Use of this option will only limit the autodetected HT frequency. + It will not (and cannot) increase the frequency beyond the + autodetected limits. + + This is primarily used to work around poorly designed or laid out + HT traces on certain motherboards. + +config LIMIT_HT_SPEED_200 + bool "Limit HT frequency to 200MHz" +config LIMIT_HT_SPEED_300 + bool "Limit HT frequency to 300MHz" +config LIMIT_HT_SPEED_400 + bool "Limit HT frequency to 400MHz" +config LIMIT_HT_SPEED_500 + bool "Limit HT frequency to 500MHz" +config LIMIT_HT_SPEED_600 + bool "Limit HT frequency to 600MHz" +config LIMIT_HT_SPEED_800 + bool "Limit HT frequency to 800MHz" +config LIMIT_HT_SPEED_1000 + bool "Limit HT frequency to 1.0GHz" +config LIMIT_HT_SPEED_1200 + bool "Limit HT frequency to 1.2GHz" +config LIMIT_HT_SPEED_1400 + bool "Limit HT frequency to 1.4GHz" +config LIMIT_HT_SPEED_1600 + bool "Limit HT frequency to 1.6GHz" +config LIMIT_HT_SPEED_1800 + bool "Limit HT frequency to 1.8GHz" +config LIMIT_HT_SPEED_2000 + bool "Limit HT frequency to 2.0GHz" +config LIMIT_HT_SPEED_2200 + bool "Limit HT frequency to 2.2GHz" +config LIMIT_HT_SPEED_2400 + bool "Limit HT frequency to 2.4GHz" +config LIMIT_HT_SPEED_2600 + bool "Limit HT frequency to 2.6GHz" +config LIMIT_HT_SPEED_AUTO + bool "Autodetect HT frequency" +endchoice + +choice + prompt "HyperTransport downlink width" + default LIMIT_HT_DOWN_WIDTH_16 + help + This option sets the maximum permissible HyperTransport + downlink width. + + Use of this option will only limit the autodetected HT width. + It will not (and cannot) increase the width beyond the autodetected + limits. + + This is primarily used to work around poorly designed or laid out HT + traces on certain motherboards. + +config LIMIT_HT_DOWN_WIDTH_8 + bool "8 bits" +config LIMIT_HT_DOWN_WIDTH_16 + bool "16 bits" +endchoice + +choice + prompt "HyperTransport uplink width" + default LIMIT_HT_UP_WIDTH_16 + help + This option sets the maximum permissible HyperTransport + uplink width. + + Use of this option will only limit the autodetected HT width. + It will not (and cannot) increase the width beyond the autodetected + limits. + + This is primarily used to work around poorly designed or laid out HT + traces on certain motherboards. + +config LIMIT_HT_UP_WIDTH_8 + bool "8 bits" +config LIMIT_HT_UP_WIDTH_16 + bool "16 bits" +endchoice + +config AMDMCT_ENABLE_ECC_REDIR + bool + default n + +config AMDMCT_BACKGROUND_SCRUB_RATE + hex + default 0x00 + help + This option sets the background ECC memory scub rate + + Permissible values are: + + 0x00; Disabled + 0x01; 40ns + 0x02; 80ns + 0x03; 160ns + 0x04; 320ns + 0x05; 640ns + 0x06; 1.28us + 0x07; 2.56us + 0x08; 5.12us + 0x09; 10.2us + 0x0a; 20.5us + 0x0b; 41us + 0x0c; 81.9us + 0x0d; 163.8us + 0x0e; 327.7us + 0x0f; 655.4us + 0x10; 1.31ms + 0x11; 2.62ms + 0x12; 5.24ms + 0x13; 10.49ms + 0x14; 20.97sms + 0x15; 42ms + 0x16; 84ms + +endmenu + endif # NORTHBRIDGE_AMD_AMDFAM10

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Patch set updated for coreboot: 0fb749c northbridge/amd/amdfam10: Allow mainboards to set maximum HT link frequency
by Timothy Pearson 10 Feb '15

10 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8405 -gerrit commit 0fb749c9fa1c6908bd7a8df9c082669b7d433b14 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 10 13:13:39 2015 -0600 northbridge/amd/amdfam10: Allow mainboards to set maximum HT link frequency Most K10 mainboards are designed to a maximum HT frequency specification. Coreboot supports CPUs that were released after mainboard production; these CPUs may support and autodetect HT link frequencies beyond the mainboard design capabilities. This patch allows mainboards to set an HT frequency limit if needed. Moved K10 specific menu to amdfam10 Kconfig file. Change-Id: If7ff40dccb4c22829062511ca0046aa2caf15580 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/Kconfig | 132 ---------------------- src/northbridge/amd/amdfam10/Kconfig | 209 +++++++++++++++++++++++++++++++++++ 2 files changed, 209 insertions(+), 132 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index 17f15c3..98a0e9e 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -5,135 +5,3 @@ source src/northbridge/amd/lx/Kconfig source src/northbridge/amd/agesa/Kconfig source src/northbridge/amd/cimx/Kconfig source src/northbridge/amd/pi/Kconfig - -menu "HyperTransport setup" - #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) - depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT - -choice - prompt "HyperTransport frequency" - default LIMIT_HT_SPEED_AUTO - help - This option sets the maximum permissible HyperTransport link - frequency. - - Use of this option will only limit the autodetected HT frequency. - It will not (and cannot) increase the frequency beyond the - autodetected limits. - - This is primarily used to work around poorly designed or laid out - HT traces on certain motherboards. - -config LIMIT_HT_SPEED_200 - bool "Limit HT frequency to 200MHz" -config LIMIT_HT_SPEED_300 - bool "Limit HT frequency to 300MHz" -config LIMIT_HT_SPEED_400 - bool "Limit HT frequency to 400MHz" -config LIMIT_HT_SPEED_500 - bool "Limit HT frequency to 500MHz" -config LIMIT_HT_SPEED_600 - bool "Limit HT frequency to 600MHz" -config LIMIT_HT_SPEED_800 - bool "Limit HT frequency to 800MHz" -config LIMIT_HT_SPEED_1000 - bool "Limit HT frequency to 1.0GHz" -config LIMIT_HT_SPEED_1200 - bool "Limit HT frequency to 1.2GHz" -config LIMIT_HT_SPEED_1400 - bool "Limit HT frequency to 1.4GHz" -config LIMIT_HT_SPEED_1600 - bool "Limit HT frequency to 1.6GHz" -config LIMIT_HT_SPEED_1800 - bool "Limit HT frequency to 1.8GHz" -config LIMIT_HT_SPEED_2000 - bool "Limit HT frequency to 2.0GHz" -config LIMIT_HT_SPEED_2200 - bool "Limit HT frequency to 2.2GHz" -config LIMIT_HT_SPEED_2400 - bool "Limit HT frequency to 2.4GHz" -config LIMIT_HT_SPEED_2600 - bool "Limit HT frequency to 2.6GHz" -config LIMIT_HT_SPEED_AUTO - bool "Autodetect HT frequency" -endchoice - -choice - prompt "HyperTransport downlink width" - default LIMIT_HT_DOWN_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - downlink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_DOWN_WIDTH_8 - bool "8 bits" -config LIMIT_HT_DOWN_WIDTH_16 - bool "16 bits" -endchoice - -choice - prompt "HyperTransport uplink width" - default LIMIT_HT_UP_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - uplink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_UP_WIDTH_8 - bool "8 bits" -config LIMIT_HT_UP_WIDTH_16 - bool "16 bits" -endchoice - -config AMDMCT_ENABLE_ECC_REDIR - bool - depends on CPU_AMD_MODEL_10XXX - default n - -config AMDMCT_BACKGROUND_SCRUB_RATE - hex - depends on CPU_AMD_MODEL_10XXX - default 0x00 - help - This option sets the background ECC memory scub rate - - Permissible values are: - - 0x00; Disabled - 0x01; 40ns - 0x02; 80ns - 0x03; 160ns - 0x04; 320ns - 0x05; 640ns - 0x06; 1.28us - 0x07; 2.56us - 0x08; 5.12us - 0x09; 10.2us - 0x0a; 20.5us - 0x0b; 41us - 0x0c; 81.9us - 0x0d; 163.8us - 0x0e; 327.7us - 0x0f; 655.4us - 0x10; 1.31ms - 0x11; 2.62ms - 0x12; 5.24ms - 0x13; 10.49ms - 0x14; 20.97sms - 0x15; 42ms - 0x16; 84ms - -endmenu diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 13b912e..5fc7584 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -124,4 +124,213 @@ config SVI_HIGH_FREQ Select this for boards with a Voltage Regulator able to operate at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. +config FORCE_LIMIT_HT_SPEED_200 + bool + default n + +config FORCE_LIMIT_HT_SPEED_300 + bool + default n + +config FORCE_LIMIT_HT_SPEED_400 + bool + default n + +config FORCE_LIMIT_HT_SPEED_500 + bool + default n + +config FORCE_LIMIT_HT_SPEED_600 + bool + default n + +config FORCE_LIMIT_HT_SPEED_800 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1000 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1200 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1400 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1600 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1800 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2000 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2200 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2400 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2600 + bool + default n + +menu "HyperTransport setup" + #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) + depends on (NORTHBRIDGE_AMD_AMDFAM10) + # FIXME uncomment when coreboot gains "visible if" support + # visible if EXPERT + +choice + prompt "HyperTransport frequency" + default LIMIT_HT_SPEED_AUTO if (!FORCE_LIMIT_HT_SPEED_200 && !FORCE_LIMIT_HT_SPEED_300 && !FORCE_LIMIT_HT_SPEED_400 && !FORCE_LIMIT_HT_SPEED_500 && !FORCE_LIMIT_HT_SPEED_600 && !FORCE_LIMIT_HT_SPEED_800 && !FORCE_LIMIT_HT_SPEED_1000 && !FORCE_LIMIT_HT_SPEED_1200 && !FORCE_LIMIT_HT_SPEED_1400 && !FORCE_LIMIT_HT_SPEED_1600 && !FORCE_LIMIT_HT_SPEED_1800 && !FORCE_LIMIT_HT_SPEED_2000 && !FORCE_LIMIT_HT_SPEED_2200 && !FORCE_LIMIT_HT_SPEED_2400 && !FORCE_LIMIT_HT_SPEED_2600) + default LIMIT_HT_SPEED_200 if FORCE_LIMIT_HT_SPEED_200 + default LIMIT_HT_SPEED_300 if FORCE_LIMIT_HT_SPEED_300 + default LIMIT_HT_SPEED_400 if FORCE_LIMIT_HT_SPEED_400 + default LIMIT_HT_SPEED_500 if FORCE_LIMIT_HT_SPEED_500 + default LIMIT_HT_SPEED_600 if FORCE_LIMIT_HT_SPEED_600 + default LIMIT_HT_SPEED_800 if FORCE_LIMIT_HT_SPEED_800 + default LIMIT_HT_SPEED_1000 if FORCE_LIMIT_HT_SPEED_1000 + default LIMIT_HT_SPEED_1200 if FORCE_LIMIT_HT_SPEED_1200 + default LIMIT_HT_SPEED_1400 if FORCE_LIMIT_HT_SPEED_1400 + default LIMIT_HT_SPEED_1600 if FORCE_LIMIT_HT_SPEED_1600 + default LIMIT_HT_SPEED_1800 if FORCE_LIMIT_HT_SPEED_1800 + default LIMIT_HT_SPEED_2000 if FORCE_LIMIT_HT_SPEED_2000 + default LIMIT_HT_SPEED_2200 if FORCE_LIMIT_HT_SPEED_2200 + default LIMIT_HT_SPEED_2400 if FORCE_LIMIT_HT_SPEED_2400 + default LIMIT_HT_SPEED_2600 if FORCE_LIMIT_HT_SPEED_2600 + help + This option sets the maximum permissible HyperTransport link + frequency. + + Use of this option will only limit the autodetected HT frequency. + It will not (and cannot) increase the frequency beyond the + autodetected limits. + + This is primarily used to work around poorly designed or laid out + HT traces on certain motherboards. + +config LIMIT_HT_SPEED_200 + bool "Limit HT frequency to 200MHz" +config LIMIT_HT_SPEED_300 + bool "Limit HT frequency to 300MHz" +config LIMIT_HT_SPEED_400 + bool "Limit HT frequency to 400MHz" +config LIMIT_HT_SPEED_500 + bool "Limit HT frequency to 500MHz" +config LIMIT_HT_SPEED_600 + bool "Limit HT frequency to 600MHz" +config LIMIT_HT_SPEED_800 + bool "Limit HT frequency to 800MHz" +config LIMIT_HT_SPEED_1000 + bool "Limit HT frequency to 1.0GHz" +config LIMIT_HT_SPEED_1200 + bool "Limit HT frequency to 1.2GHz" +config LIMIT_HT_SPEED_1400 + bool "Limit HT frequency to 1.4GHz" +config LIMIT_HT_SPEED_1600 + bool "Limit HT frequency to 1.6GHz" +config LIMIT_HT_SPEED_1800 + bool "Limit HT frequency to 1.8GHz" +config LIMIT_HT_SPEED_2000 + bool "Limit HT frequency to 2.0GHz" +config LIMIT_HT_SPEED_2200 + bool "Limit HT frequency to 2.2GHz" +config LIMIT_HT_SPEED_2400 + bool "Limit HT frequency to 2.4GHz" +config LIMIT_HT_SPEED_2600 + bool "Limit HT frequency to 2.6GHz" +config LIMIT_HT_SPEED_AUTO + bool "Autodetect HT frequency" +endchoice + +choice + prompt "HyperTransport downlink width" + default LIMIT_HT_DOWN_WIDTH_16 + help + This option sets the maximum permissible HyperTransport + downlink width. + + Use of this option will only limit the autodetected HT width. + It will not (and cannot) increase the width beyond the autodetected + limits. + + This is primarily used to work around poorly designed or laid out HT + traces on certain motherboards. + +config LIMIT_HT_DOWN_WIDTH_8 + bool "8 bits" +config LIMIT_HT_DOWN_WIDTH_16 + bool "16 bits" +endchoice + +choice + prompt "HyperTransport uplink width" + default LIMIT_HT_UP_WIDTH_16 + help + This option sets the maximum permissible HyperTransport + uplink width. + + Use of this option will only limit the autodetected HT width. + It will not (and cannot) increase the width beyond the autodetected + limits. + + This is primarily used to work around poorly designed or laid out HT + traces on certain motherboards. + +config LIMIT_HT_UP_WIDTH_8 + bool "8 bits" +config LIMIT_HT_UP_WIDTH_16 + bool "16 bits" +endchoice + +config AMDMCT_ENABLE_ECC_REDIR + bool + depends on CPU_AMD_MODEL_10XXX + default n + +config AMDMCT_BACKGROUND_SCRUB_RATE + hex + depends on CPU_AMD_MODEL_10XXX + default 0x00 + help + This option sets the background ECC memory scub rate + + Permissible values are: + + 0x00; Disabled + 0x01; 40ns + 0x02; 80ns + 0x03; 160ns + 0x04; 320ns + 0x05; 640ns + 0x06; 1.28us + 0x07; 2.56us + 0x08; 5.12us + 0x09; 10.2us + 0x0a; 20.5us + 0x0b; 41us + 0x0c; 81.9us + 0x0d; 163.8us + 0x0e; 327.7us + 0x0f; 655.4us + 0x10; 1.31ms + 0x11; 2.62ms + 0x12; 5.24ms + 0x13; 10.49ms + 0x14; 20.97sms + 0x15; 42ms + 0x16; 84ms + +endmenu + endif # NORTHBRIDGE_AMD_AMDFAM10

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New patch to review for coreboot: 9f97ddf intel/fsp_baytrail: Add Windows 8.1 boot support for BayTrail SoCs
by Brenton Dong 10 Feb '15

10 Feb '15

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8408 -gerrit commit 9f97ddf21b0060cfa833e3dee3d255c9fb8d4ee9 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Tue Feb 10 14:02:31 2015 -0700 intel/fsp_baytrail: Add Windows 8.1 boot support for BayTrail SoCs Added PCI Root Port IRQ Routing in new file pcie.asl needed for Windows Added 3 more XHCI ports that are supported by Baytrail to xhci.asl Change-Id: I1d01f9589407219f533c70fde867cb948751fb20 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/soc/intel/fsp_baytrail/acpi/pcie.asl | 166 +++++++++++++++++++++++ src/soc/intel/fsp_baytrail/acpi/southcluster.asl | 5 + src/soc/intel/fsp_baytrail/acpi/xhci.asl | 3 + 3 files changed, 174 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/acpi/pcie.asl b/src/soc/intel/fsp_baytrail/acpi/pcie.asl new file mode 100755 index 0000000..df9fc4f --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/pcie.asl @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(RP1P, Package() +{ + // PCIE Port #1 Slot + Package() {0x0000FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() {0x0000FFFF, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() {0x0000FFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() {0x0000FFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 }, +}) + +Name(RP1A, Package() +{ + // PCIE Port #1 Slot + Package() {0x0000FFFF, 0, 0, 16 }, + Package() {0x0000FFFF, 1, 0, 17 }, + Package() {0x0000FFFF, 2, 0, 18 }, + Package() {0x0000FFFF, 3, 0, 19 }, +}) + +Name(RP2P, Package() +{ + // PCIE Port #2 Slot + Package() {0x0000FFFF, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() {0x0000FFFF, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() {0x0000FFFF, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() {0x0000FFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 }, +}) + +Name(RP2A, Package() +{ + // PCIE Port #2 Slot + Package() {0x0000FFFF, 0, 0, 17 }, + Package() {0x0000FFFF, 1, 0, 18 }, + Package() {0x0000FFFF, 2, 0, 19 }, + Package() {0x0000FFFF, 3, 0, 16 }, +}) + +Name(RP3P, Package() +{ + // PCIE Port #3 Slot + Package() {0x0000FFFF, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() {0x0000FFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() {0x0000FFFF, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() {0x0000FFFF, 3, \_SB.PCI0.LPCB.LNKB, 0 }, +}) + +Name(RP3A, Package() +{ + // PCIE Port #3 Slot + Package() {0x0000FFFF, 0, 0, 18 }, + Package() {0x0000FFFF, 1, 0, 19 }, + Package() {0x0000FFFF, 2, 0, 16 }, + Package() {0x0000FFFF, 3, 0, 17 }, +}) + +Name(RP4P, Package() +{ + // PCIE Port #4 Slot + Package() {0x0000FFFF, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() {0x0000FFFF, 1, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() {0x0000FFFF, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() {0x0000FFFF, 3, \_SB.PCI0.LPCB.LNKC, 0 }, +}) + +Name(RP4A, Package() +{ + // PCIE Port #4 Slot + Package() {0x0000FFFF, 0, 0, 19 }, + Package() {0x0000FFFF, 1, 0, 16 }, + Package() {0x0000FFFF, 2, 0, 17 }, + Package() {0x0000FFFF, 3, 0, 18 }, +}) + +// +// PCIE Root Port #1 +// +Device(RP01) +{ + Name(_ADR, 0x001C0000) + Name(_PRW, Package() { + 0, 0 + }) + + Method(_PRT,0) { + If(PICM) { + Return (RP1A) + } Else { + Return (RP1P) + } + } +} + +// +// PCIE Root Port #2 +// +Device(RP02) +{ + Name(_ADR, 0x001C0001) + Name(_PRW, Package() { + 0, 0 + }) + + Method(_PRT,0) { + If(PICM) { + Return (RP2A) + } Else { + Return (RP2P) + } + } +} + +// +// PCIE Root Port #3 +// +Device(RP03) +{ + Name(_ADR, 0x001C0002) + Name(_PRW, Package() { + 0, 0 + }) + + Method(_PRT,0) { + If(PICM) { + Return (RP3A) + } Else { + Return (RP3P) + } + } +} + +// +// PCIE Root Port #4 +// +Device(RP04) +{ + Name(_ADR, 0x001C0003) + Name(_PRW, Package() { + 0, 0 + }) + + Method(_PRT,0) { + If(PICM) { + Return (RP4A) + } Else { + Return (RP4P) + } + } +} diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl old mode 100644 new mode 100755 index 3ee9ee0..f074a55 --- a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl +++ b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl @@ -259,6 +259,11 @@ Device (IOSF) #include "xhci.asl" #endif +#if INCLUDE_PCIE +// PCIE Device +#include "pcie.asl" +#endif + // IRQ routing for each PCI device #include "irqroute.asl" diff --git a/src/soc/intel/fsp_baytrail/acpi/xhci.asl b/src/soc/intel/fsp_baytrail/acpi/xhci.asl old mode 100644 new mode 100755 index 4d5367a..e51ecf2 --- a/src/soc/intel/fsp_baytrail/acpi/xhci.asl +++ b/src/soc/intel/fsp_baytrail/acpi/xhci.asl @@ -32,5 +32,8 @@ Device (XHCI) Device (PRT2) { Name (_ADR, 2) } Device (PRT3) { Name (_ADR, 3) } Device (PRT4) { Name (_ADR, 4) } + Device (PRT5) { Name (_ADR, 5) } + Device (PRT6) { Name (_ADR, 6) } + Device (PRT7) { Name (_ADR, 7) } } }

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coreboot-gerrit February 2015