coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 982a45d intel/fsp_baytrail: Add Android boot support for BayTrail SoCs
by Brenton Dong 10 Feb '15

10 Feb '15

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8407 -gerrit commit 982a45dcc35139ddb3492b6b7cf6a6db7beea3c2 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Tue Feb 10 09:00:25 2015 -0700 intel/fsp_baytrail: Add Android boot support for BayTrail SoCs IRQ and GPIO routing needed to be added for Android. Change-Id: I9286125736c2572205e64a464884ee935c483df2 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/soc/intel/fsp_baytrail/acpi/gpio.asl | 213 +++++++++++++++++++----------- src/soc/intel/fsp_baytrail/southcluster.c | 53 ++++++++ 2 files changed, 191 insertions(+), 75 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/acpi/gpio.asl b/src/soc/intel/fsp_baytrail/acpi/gpio.asl old mode 100644 new mode 100755 index f2618a8..bb07a76 --- a/src/soc/intel/fsp_baytrail/acpi/gpio.asl +++ b/src/soc/intel/fsp_baytrail/acpi/gpio.asl @@ -22,89 +22,152 @@ #include <soc/intel/fsp_baytrail/baytrail/iomap.h> #include <soc/intel/fsp_baytrail/baytrail/irq.h> -/* SouthCluster GPIO */ -Device (GPSC) -{ - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") - Name (_UID, 1) +Name (GPBS, 0x0500) - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) - { - GPIO_SC_IRQ - } - }) +/* SouthCluster GPIO */ + Device (GPO0) + { + Name (_ADR, Zero) // _ADR: Address + Name (_HID, "INT33B2") // _HID: Hardware ID + Name (_CID, "INT33B2") // _CID: Compatible ID + Name (_DDN, "ValleyView General Purpose Input/Output (GPIO) controller") // _DDN: DOS Device Name + Name (_UID, One) // _UID: Unique ID + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED0C000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) + { + 0x00000031, + } + }) + Return (RBUF) + } - Method (_CRS) - { - CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) - Return (^RBUF) - } + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } - Method (_STA) - { - Return (0xF) - } -} + Name (AVBL, Zero) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If (LEqual (Arg0, 0x08)) + { + Store (Arg1, AVBL) + } + } -/* NorthCluster GPIO */ -Device (GPNC) -{ - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") - Name (_UID, 2) + OperationRegion (GPOP, SystemIO, GPBS, 0x50) + Field (GPOP, ByteAcc, NoLock, Preserve) + { + Offset (0x28), + , 21, + BTD3, 1, + Offset (0x48), + , 30, + SHD3, 1 + } - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) - { - GPIO_NC_IRQ - } - }) + OperationRegion (GPO2, GeneralPurposeIo, Zero, 0x0C) + Field (GPO2, ByteAcc, NoLock, Preserve) + { + Connection ( + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO0", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x005F + } + ), + SHS3, 1 + } + } - Method (_CRS) - { - CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) - Return (^RBUF) - } + Device (GPO1) + { + Name (_ADR, Zero) // _ADR: Address + Name (_HID, "INT33B2") // _HID: Hardware ID + Name (_CID, "INT33B2") // _CID: Compatible ID + Name (_DDN, "ValleyView GPNCORE controller") // _DDN: DOS Device Name + Name (_UID, 0x02) // _UID: Unique ID + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED0D000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) + { + 0x00000030, + } + }) + Return (RBUF) + } - Method (_STA) - { - Return (0xF) - } -} + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + } -/* SUS GPIO */ -Device (GPSS) -{ - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") - Name (_UID, 3) + Device (GPO2) + { + Name (_ADR, Zero) // _ADR: Address + Name (_HID, "INT33B2") // _HID: Hardware ID + Name (_CID, "INT33B2") // _CID: Compatible ID + Name (_DDN, "ValleyView GPSUS controller") // _DDN: DOS Device Name + Name (_UID, 0x03) // _UID: Unique ID + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED0E000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) + { + 0x00000032, + } + }) + Return (RBUF) + } - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) - { - GPIO_SUS_IRQ - } - }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } - Method (_CRS) - { - CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) - Return (^RBUF) - } + Name (AVBL, Zero) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If (LEqual (Arg0, 0x08)) + { + Store (Arg1, AVBL) + } + } - Method (_STA) - { - Return (0xF) - } -} + Name (GMOD, ResourceTemplate () + { + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO2", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0015 + } + }) + OperationRegion (GPOP, SystemIO, GPBS, 0x0100) + Field (GPOP, ByteAcc, NoLock, Preserve) + { + Offset (0x88), + , 20, + WFD3, 1 + } + } diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c old mode 100644 new mode 100755 index d87935b..c0f16dd --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -50,6 +50,40 @@ typedef struct soc_intel_fsp_baytrail_config config_t; +typedef struct { + uint8_t bus; + uint8_t dev; + uint8_t func; + uint8_t irq; +} irq_tbl_t; + +static const irq_tbl_t soc_irq_tbl[] = { + /*Bus Dev Fun Irq*/ + { 0, 2, 0, 7 }, /* DISPLAY */ + { 0, 21, 0, 29 }, /* LPE Audio */ + { 0, 24, 1, 32 }, /* I2C1 */ + { 0, 24, 2, 33 }, /* I2C2 */ + { 0, 24, 3, 34 }, /* I2C3 */ + { 0, 24, 4, 35 }, /* I2C4 */ + { 0, 24, 5, 36 }, /* I2C5 */ + { 0, 24, 6, 37 }, /* I2C6 */ + { 0, 24, 7, 38 }, /* I2C7 */ + { 0, 30, 3, 39 }, /* HSUART1 */ + { 0, 30, 4, 40 }, /* HSUART1 */ + { 0, 30, 5, 41 }, /* SPI1 */ + { 0, 30, 0, 42 }, /* LI01 DMA */ + { 0, 24, 0, 43 }, /* LI02 DMA */ + { 0, 23, 0, 44 }, /* MIPI-HSI */ + { 0, 16, 0, 45 }, /* SDIO1/eMMC */ + { 0, 17, 0, 46 }, /* SDIO2/SDIO */ + { 0, 18, 0, 47 }, /* SDIO3/SD */ + { 0, 29, 0, 11 }, /* USB */ + { 0, 20, 0, 23 }, /* OTG */ + { 0, 22, 0, 16 }, /* XHCI */ + { 0, 26, 0, 23 }, /* SEC */ + { 0, 27, 0, 22 } /* HD Audio */ +}; + static inline void add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) { @@ -156,6 +190,22 @@ static void sc_enable_serial_irqs(struct device *dev) #endif /* DON'T SET UP IRQS */ } +static uint8_t update_soc_irq (struct device *dev) +{ + int i; + uint8_t irq; + + irq = PIRQ_PIC_IRQDISABLE; + + for (i = 0; i < sizeof(soc_irq_tbl)/sizeof(soc_irq_tbl[0]); i++) { + if (PCI_DEVFN(soc_irq_tbl[i].dev, soc_irq_tbl[i].func) == dev->path.pci.devfn) { + irq = soc_irq_tbl[i].irq; + break; + } + } + return irq; +} + /* * Write PCI config space IRQ assignments. PCI devices have the INT_LINE * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing @@ -230,7 +280,10 @@ static void write_pci_config_irqs(void) pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF; /* Get the INT_LINE this device/function will use */ + int_line = update_soc_irq (irq_dev); + if (int_line == PIRQ_PIC_IRQDISABLE) { int_line = ir->pic[pirq]; + } if (int_line != PIRQ_PIC_IRQDISABLE) { /* Set this IRQ to level triggered since it is used by a PCI device */

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Patch set updated for coreboot: dcab66d northbridge/amd/amdfam10: Allow mainboards to set maximum HT link frequency
by Timothy Pearson 10 Feb '15

10 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8405 -gerrit commit dcab66dbb628f8223b87926d3d7f86a3077c8b1b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 10 13:13:39 2015 -0600 northbridge/amd/amdfam10: Allow mainboards to set maximum HT link frequency Most K10 mainboards are designed to a maximum HT frequency specification. Coreboot supports CPUs that were released after mainboard production; these CPUs may support and autodetect HT link frequencies beyond the mainboard design capabilities. This patch allows mainboards to set an HT frequency limit if needed. Change-Id: If7ff40dccb4c22829062511ca0046aa2caf15580 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/Kconfig | 132 ---------------------- src/northbridge/amd/amdfam10/Kconfig | 209 +++++++++++++++++++++++++++++++++++ 2 files changed, 209 insertions(+), 132 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index 17f15c3..98a0e9e 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -5,135 +5,3 @@ source src/northbridge/amd/lx/Kconfig source src/northbridge/amd/agesa/Kconfig source src/northbridge/amd/cimx/Kconfig source src/northbridge/amd/pi/Kconfig - -menu "HyperTransport setup" - #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) - depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT - -choice - prompt "HyperTransport frequency" - default LIMIT_HT_SPEED_AUTO - help - This option sets the maximum permissible HyperTransport link - frequency. - - Use of this option will only limit the autodetected HT frequency. - It will not (and cannot) increase the frequency beyond the - autodetected limits. - - This is primarily used to work around poorly designed or laid out - HT traces on certain motherboards. - -config LIMIT_HT_SPEED_200 - bool "Limit HT frequency to 200MHz" -config LIMIT_HT_SPEED_300 - bool "Limit HT frequency to 300MHz" -config LIMIT_HT_SPEED_400 - bool "Limit HT frequency to 400MHz" -config LIMIT_HT_SPEED_500 - bool "Limit HT frequency to 500MHz" -config LIMIT_HT_SPEED_600 - bool "Limit HT frequency to 600MHz" -config LIMIT_HT_SPEED_800 - bool "Limit HT frequency to 800MHz" -config LIMIT_HT_SPEED_1000 - bool "Limit HT frequency to 1.0GHz" -config LIMIT_HT_SPEED_1200 - bool "Limit HT frequency to 1.2GHz" -config LIMIT_HT_SPEED_1400 - bool "Limit HT frequency to 1.4GHz" -config LIMIT_HT_SPEED_1600 - bool "Limit HT frequency to 1.6GHz" -config LIMIT_HT_SPEED_1800 - bool "Limit HT frequency to 1.8GHz" -config LIMIT_HT_SPEED_2000 - bool "Limit HT frequency to 2.0GHz" -config LIMIT_HT_SPEED_2200 - bool "Limit HT frequency to 2.2GHz" -config LIMIT_HT_SPEED_2400 - bool "Limit HT frequency to 2.4GHz" -config LIMIT_HT_SPEED_2600 - bool "Limit HT frequency to 2.6GHz" -config LIMIT_HT_SPEED_AUTO - bool "Autodetect HT frequency" -endchoice - -choice - prompt "HyperTransport downlink width" - default LIMIT_HT_DOWN_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - downlink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_DOWN_WIDTH_8 - bool "8 bits" -config LIMIT_HT_DOWN_WIDTH_16 - bool "16 bits" -endchoice - -choice - prompt "HyperTransport uplink width" - default LIMIT_HT_UP_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - uplink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_UP_WIDTH_8 - bool "8 bits" -config LIMIT_HT_UP_WIDTH_16 - bool "16 bits" -endchoice - -config AMDMCT_ENABLE_ECC_REDIR - bool - depends on CPU_AMD_MODEL_10XXX - default n - -config AMDMCT_BACKGROUND_SCRUB_RATE - hex - depends on CPU_AMD_MODEL_10XXX - default 0x00 - help - This option sets the background ECC memory scub rate - - Permissible values are: - - 0x00; Disabled - 0x01; 40ns - 0x02; 80ns - 0x03; 160ns - 0x04; 320ns - 0x05; 640ns - 0x06; 1.28us - 0x07; 2.56us - 0x08; 5.12us - 0x09; 10.2us - 0x0a; 20.5us - 0x0b; 41us - 0x0c; 81.9us - 0x0d; 163.8us - 0x0e; 327.7us - 0x0f; 655.4us - 0x10; 1.31ms - 0x11; 2.62ms - 0x12; 5.24ms - 0x13; 10.49ms - 0x14; 20.97sms - 0x15; 42ms - 0x16; 84ms - -endmenu diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 13b912e..5fc7584 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -124,4 +124,213 @@ config SVI_HIGH_FREQ Select this for boards with a Voltage Regulator able to operate at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. +config FORCE_LIMIT_HT_SPEED_200 + bool + default n + +config FORCE_LIMIT_HT_SPEED_300 + bool + default n + +config FORCE_LIMIT_HT_SPEED_400 + bool + default n + +config FORCE_LIMIT_HT_SPEED_500 + bool + default n + +config FORCE_LIMIT_HT_SPEED_600 + bool + default n + +config FORCE_LIMIT_HT_SPEED_800 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1000 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1200 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1400 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1600 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1800 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2000 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2200 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2400 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2600 + bool + default n + +menu "HyperTransport setup" + #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) + depends on (NORTHBRIDGE_AMD_AMDFAM10) + # FIXME uncomment when coreboot gains "visible if" support + # visible if EXPERT + +choice + prompt "HyperTransport frequency" + default LIMIT_HT_SPEED_AUTO if (!FORCE_LIMIT_HT_SPEED_200 && !FORCE_LIMIT_HT_SPEED_300 && !FORCE_LIMIT_HT_SPEED_400 && !FORCE_LIMIT_HT_SPEED_500 && !FORCE_LIMIT_HT_SPEED_600 && !FORCE_LIMIT_HT_SPEED_800 && !FORCE_LIMIT_HT_SPEED_1000 && !FORCE_LIMIT_HT_SPEED_1200 && !FORCE_LIMIT_HT_SPEED_1400 && !FORCE_LIMIT_HT_SPEED_1600 && !FORCE_LIMIT_HT_SPEED_1800 && !FORCE_LIMIT_HT_SPEED_2000 && !FORCE_LIMIT_HT_SPEED_2200 && !FORCE_LIMIT_HT_SPEED_2400 && !FORCE_LIMIT_HT_SPEED_2600) + default LIMIT_HT_SPEED_200 if FORCE_LIMIT_HT_SPEED_200 + default LIMIT_HT_SPEED_300 if FORCE_LIMIT_HT_SPEED_300 + default LIMIT_HT_SPEED_400 if FORCE_LIMIT_HT_SPEED_400 + default LIMIT_HT_SPEED_500 if FORCE_LIMIT_HT_SPEED_500 + default LIMIT_HT_SPEED_600 if FORCE_LIMIT_HT_SPEED_600 + default LIMIT_HT_SPEED_800 if FORCE_LIMIT_HT_SPEED_800 + default LIMIT_HT_SPEED_1000 if FORCE_LIMIT_HT_SPEED_1000 + default LIMIT_HT_SPEED_1200 if FORCE_LIMIT_HT_SPEED_1200 + default LIMIT_HT_SPEED_1400 if FORCE_LIMIT_HT_SPEED_1400 + default LIMIT_HT_SPEED_1600 if FORCE_LIMIT_HT_SPEED_1600 + default LIMIT_HT_SPEED_1800 if FORCE_LIMIT_HT_SPEED_1800 + default LIMIT_HT_SPEED_2000 if FORCE_LIMIT_HT_SPEED_2000 + default LIMIT_HT_SPEED_2200 if FORCE_LIMIT_HT_SPEED_2200 + default LIMIT_HT_SPEED_2400 if FORCE_LIMIT_HT_SPEED_2400 + default LIMIT_HT_SPEED_2600 if FORCE_LIMIT_HT_SPEED_2600 + help + This option sets the maximum permissible HyperTransport link + frequency. + + Use of this option will only limit the autodetected HT frequency. + It will not (and cannot) increase the frequency beyond the + autodetected limits. + + This is primarily used to work around poorly designed or laid out + HT traces on certain motherboards. + +config LIMIT_HT_SPEED_200 + bool "Limit HT frequency to 200MHz" +config LIMIT_HT_SPEED_300 + bool "Limit HT frequency to 300MHz" +config LIMIT_HT_SPEED_400 + bool "Limit HT frequency to 400MHz" +config LIMIT_HT_SPEED_500 + bool "Limit HT frequency to 500MHz" +config LIMIT_HT_SPEED_600 + bool "Limit HT frequency to 600MHz" +config LIMIT_HT_SPEED_800 + bool "Limit HT frequency to 800MHz" +config LIMIT_HT_SPEED_1000 + bool "Limit HT frequency to 1.0GHz" +config LIMIT_HT_SPEED_1200 + bool "Limit HT frequency to 1.2GHz" +config LIMIT_HT_SPEED_1400 + bool "Limit HT frequency to 1.4GHz" +config LIMIT_HT_SPEED_1600 + bool "Limit HT frequency to 1.6GHz" +config LIMIT_HT_SPEED_1800 + bool "Limit HT frequency to 1.8GHz" +config LIMIT_HT_SPEED_2000 + bool "Limit HT frequency to 2.0GHz" +config LIMIT_HT_SPEED_2200 + bool "Limit HT frequency to 2.2GHz" +config LIMIT_HT_SPEED_2400 + bool "Limit HT frequency to 2.4GHz" +config LIMIT_HT_SPEED_2600 + bool "Limit HT frequency to 2.6GHz" +config LIMIT_HT_SPEED_AUTO + bool "Autodetect HT frequency" +endchoice + +choice + prompt "HyperTransport downlink width" + default LIMIT_HT_DOWN_WIDTH_16 + help + This option sets the maximum permissible HyperTransport + downlink width. + + Use of this option will only limit the autodetected HT width. + It will not (and cannot) increase the width beyond the autodetected + limits. + + This is primarily used to work around poorly designed or laid out HT + traces on certain motherboards. + +config LIMIT_HT_DOWN_WIDTH_8 + bool "8 bits" +config LIMIT_HT_DOWN_WIDTH_16 + bool "16 bits" +endchoice + +choice + prompt "HyperTransport uplink width" + default LIMIT_HT_UP_WIDTH_16 + help + This option sets the maximum permissible HyperTransport + uplink width. + + Use of this option will only limit the autodetected HT width. + It will not (and cannot) increase the width beyond the autodetected + limits. + + This is primarily used to work around poorly designed or laid out HT + traces on certain motherboards. + +config LIMIT_HT_UP_WIDTH_8 + bool "8 bits" +config LIMIT_HT_UP_WIDTH_16 + bool "16 bits" +endchoice + +config AMDMCT_ENABLE_ECC_REDIR + bool + depends on CPU_AMD_MODEL_10XXX + default n + +config AMDMCT_BACKGROUND_SCRUB_RATE + hex + depends on CPU_AMD_MODEL_10XXX + default 0x00 + help + This option sets the background ECC memory scub rate + + Permissible values are: + + 0x00; Disabled + 0x01; 40ns + 0x02; 80ns + 0x03; 160ns + 0x04; 320ns + 0x05; 640ns + 0x06; 1.28us + 0x07; 2.56us + 0x08; 5.12us + 0x09; 10.2us + 0x0a; 20.5us + 0x0b; 41us + 0x0c; 81.9us + 0x0d; 163.8us + 0x0e; 327.7us + 0x0f; 655.4us + 0x10; 1.31ms + 0x11; 2.62ms + 0x12; 5.24ms + 0x13; 10.49ms + 0x14; 20.97sms + 0x15; 42ms + 0x16; 84ms + +endmenu + endif # NORTHBRIDGE_AMD_AMDFAM10

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New patch to review for coreboot: 771a427 Drop Intel E7501 / i82801ex and Tyan s2735
by Stefan Reinauer 10 Feb '15

10 Feb '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8406 -gerrit commit 771a427b10318e93d707ace0acfc35c493f37497 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Feb 10 21:22:36 2015 +0100 Drop Intel E7501 / i82801ex and Tyan s2735 Change-Id: I0830d0f54189e855ef14b0d84bed74ba41b84efb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/tyan/Kconfig | 3 - src/mainboard/tyan/s2735/Kconfig | 41 - src/mainboard/tyan/s2735/board_info.txt | 3 - src/mainboard/tyan/s2735/cmos.layout | 82 -- src/mainboard/tyan/s2735/devicetree.cb | 86 -- src/mainboard/tyan/s2735/irq_tables.c | 45 - src/mainboard/tyan/s2735/mptable.c | 130 -- src/mainboard/tyan/s2735/romstage.c | 76 - src/northbridge/intel/Kconfig | 1 - src/northbridge/intel/Makefile.inc | 1 - src/northbridge/intel/e7501/Kconfig | 5 - src/northbridge/intel/e7501/Makefile.inc | 1 - src/northbridge/intel/e7501/debug.c | 275 ---- src/northbridge/intel/e7501/e7501.h | 79 - src/northbridge/intel/e7501/northbridge.c | 140 -- src/northbridge/intel/e7501/raminit.c | 2007 -------------------------- src/northbridge/intel/e7501/raminit.h | 20 - src/northbridge/intel/e7501/reset_test.c | 18 - src/southbridge/intel/Kconfig | 1 - src/southbridge/intel/Makefile.inc | 1 - src/southbridge/intel/i82801ex/Kconfig | 14 - src/southbridge/intel/i82801ex/Makefile.inc | 11 - src/southbridge/intel/i82801ex/ac97.c | 37 - src/southbridge/intel/i82801ex/chip.h | 34 - src/southbridge/intel/i82801ex/early_smbus.c | 130 -- src/southbridge/intel/i82801ex/ehci.c | 51 - src/southbridge/intel/i82801ex/i82801ex.c | 48 - src/southbridge/intel/i82801ex/i82801ex.h | 22 - src/southbridge/intel/i82801ex/ide.c | 42 - src/southbridge/intel/i82801ex/lpc.c | 381 ----- src/southbridge/intel/i82801ex/pci.c | 44 - src/southbridge/intel/i82801ex/reset.c | 8 - src/southbridge/intel/i82801ex/sata.c | 59 - src/southbridge/intel/i82801ex/smbus.c | 48 - src/southbridge/intel/i82801ex/smbus.h | 104 -- src/southbridge/intel/i82801ex/uhci.c | 55 - src/southbridge/intel/i82801ex/watchdog.c | 28 - 37 files changed, 4131 deletions(-) diff --git a/src/mainboard/tyan/Kconfig b/src/mainboard/tyan/Kconfig index 4a135bd..fb16996 100644 --- a/src/mainboard/tyan/Kconfig +++ b/src/mainboard/tyan/Kconfig @@ -23,8 +23,6 @@ choice config BOARD_TYAN_S1846 bool "S1846 (Tsunami ATX)" -config BOARD_TYAN_S2735 - bool "S2735 (Tiger i7501R)" config BOARD_TYAN_S2850 bool "S2850 (Tomcat K8S)" config BOARD_TYAN_S2875 @@ -56,7 +54,6 @@ config BOARD_TYAN_S8226 endchoice source "src/mainboard/tyan/s1846/Kconfig" -source "src/mainboard/tyan/s2735/Kconfig" source "src/mainboard/tyan/s2850/Kconfig" source "src/mainboard/tyan/s2875/Kconfig" source "src/mainboard/tyan/s2880/Kconfig" diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig deleted file mode 100644 index a64c0e3..0000000 --- a/src/mainboard/tyan/s2735/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ -if BOARD_TYAN_S2735 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_MPGA604 - select NORTHBRIDGE_INTEL_E7501 - select SOUTHBRIDGE_INTEL_I82870 - select SOUTHBRIDGE_INTEL_I82801EX - select SUPERIO_WINBOND_W83627HF - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select UDELAY_TSC - select HAVE_OPTION_TABLE - select USE_WATCHDOG_ON_BOOT - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default tyan/s2735 - -config DCACHE_RAM_BASE - hex - default 0xcf000 - -config DCACHE_RAM_SIZE - hex - default 0x1000 - -config MAINBOARD_PART_NUMBER - string - default "S2735" - -config IRQ_SLOT_COUNT - int - default 15 - -config MAX_CPUS - int - default 4 - -endif # BOARD_TYAN_S2735 diff --git a/src/mainboard/tyan/s2735/board_info.txt b/src/mainboard/tyan/s2735/board_info.txt deleted file mode 100644 index 3eb1393..0000000 --- a/src/mainboard/tyan/s2735/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Board name: Tiger i7501R (S2735) -Category: server -Board URL: http://www.tyan.com/archive/products/html/tigeri7501r.html diff --git a/src/mainboard/tyan/s2735/cmos.layout b/src/mainboard/tyan/s2735/cmos.layout deleted file mode 100644 index 58585a2..0000000 --- a/src/mainboard/tyan/s2735/cmos.layout +++ /dev/null @@ -1,82 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -396 1 e 1 thermal_monitoring -397 1 e 1 remap_memory_high -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -#440 4 e 9 slow_cpu -444 1 e 1 nmi -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb deleted file mode 100644 index d3b6b1e..0000000 --- a/src/mainboard/tyan/s2735/devicetree.cb +++ /dev/null @@ -1,86 +0,0 @@ -chip northbridge/intel/e7501 - device domain 0 on - subsystemid 0x10f1 0x2735 inherit - device pci 0.0 on end - device pci 0.1 on end - device pci 2.0 on - chip southbridge/intel/i82870 - device pci 1c.0 on end - device pci 1d.0 on - device pci 1.0 on end # intel lan - device pci 1.1 on end - end - device pci 1e.0 on end - device pci 1f.0 on end - end - end - device pci 6.0 on end - chip southbridge/intel/i82801ex - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - device pci 1e.0 on - device pci 1.0 on end # intel lan 10/100 - device pci 2.0 on end # ati - end - device pci 1f.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1f.1 off end - device pci 1f.2 on end - device pci 1f.3 on end - device pci 1f.5 off end - device pci 1f.6 off end - end # SB - end # PCI domain - device cpu_cluster 0 on - chip cpu/intel/socket_mPGA604 - device lapic 0 on end - end - chip cpu/intel/socket_mPGA604 - device lapic 6 on end - end - end -end - diff --git a/src/mainboard/tyan/s2735/irq_tables.c b/src/mainboard/tyan/s2735/irq_tables.c deleted file mode 100644 index 3d69b49..0000000 --- a/src/mainboard/tyan/s2735/irq_tables.c +++ /dev/null @@ -1,45 +0,0 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x24d0, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x9a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x04,(0x08<<3)|0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x1d<<3)|0x0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x0, 0x0}, - {0x04,(0x03<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x60, 0xdcf8}, {0x61, 0x0dcf8}}, 0x3, 0x0}, - {0x04,(0x02<<3)|0x0, {{0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x03,(0x1f<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x02,(0x1f<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x03,(0x03<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x1, 0x0}, - {0x03,(0x06<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x2, 0x0}, - {0x02,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x02,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x04,(0x01<<3)|0x0, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x04,(0x04<<3)|0x0, {{0x63, 0xdcf8}, {0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0x0dcf8}}, 0x4, 0x0}, - {0x03,(0x04<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, - {0x03,(0x05<<3)|0x0, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x60, 0x0dcf8}}, 0x6, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c deleted file mode 100644 index 9073728..0000000 --- a/src/mainboard/tyan/s2735/mptable.c +++ /dev/null @@ -1,130 +0,0 @@ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - mptable_write_buses(mc, NULL, &isa_bus); -/*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x09, 0x20, res->base); - } - } - dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x0a, 0x20, res->base); - } - } - } - mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0); - -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# -*/ -//USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7c, 0x8, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x8, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x8, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x8, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x8, 0x17); - -//onboard ati - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x8, 0x8, 0x12); - -//onboard intel 82551 10/100 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x8, 0x11); - -// onboard Intel 82547 1000 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0xa, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x5, 0xa, 0x1); - -//Slot 4 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|0, 0x8, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|1, 0x8, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|2, 0x8, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|3, 0x8, 0x11); -//Slot 3 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|0, 0x8, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|1, 0x8, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|2, 0x8, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|3, 0x8, 0x12); -//Slot 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|0, 0x9, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|1, 0x9, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|2, 0x9, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|3, 0x9, 0x3); -//Slot 2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|0, 0x9, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|1, 0x9, 0x5); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|2, 0x9, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|3, 0x9, 0x7); - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, 0x0); -/* -MP Config Extended Table Entries: - --- -System Address Space - bus ID: 0 address type: I/O address - address base: 0x9000 - address range: 0x6000 --- -System Address Space - bus ID: 0 address type: I/O address - address base: 0x0 - address range: 0x100 --- -System Address Space - bus ID: 0 address type: memory address - address base: 0xa0000 - address range: 0x20000 --- -System Address Space - bus ID: 0 address type: memory address - address base: 0xfc700000 - address range: 0x2500000 --- -System Address Space - bus ID: 0 address type: prefetch address - address base: 0xff600000 - address range: 0x500000 --- -Bus Heirarchy - bus ID: 5 bus info: 0x01 parent bus ID: 0-- -Compatibility Bus Address - bus ID: 0 address modifier: add - predefined range: 0x00000000-- -Compatibility Bus Address - bus ID: 0 address modifier: add - predefined range: 0x00000001 // There is no extension information... -*/ - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c deleted file mode 100644 index 5d4fd0e..0000000 --- a/src/mainboard/tyan/s2735/romstage.c +++ /dev/null @@ -1,76 +0,0 @@ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include <lib.h> -#include <spd.h> -#include "southbridge/intel/i82801ex/early_smbus.c" -#include "northbridge/intel/e7501/raminit.h" -#include "northbridge/intel/e7501/debug.c" -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -// FIXME: There's another hard_reset() in reset.c. Why? -static void hard_reset(void) -{ - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/e7501/raminit.c" -#include "northbridge/intel/e7501/reset_test.c" -#include "lib/generic_sdram.c" - -#include <cpu/intel/romstage.h> -void main(unsigned long bist) -{ - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 0), - .d0f1 = PCI_DEV(0, 0, 1), - .channel0 = { DIMM0, DIMM1, DIMM2, 0 }, - .channel1 = { DIMM4, DIMM5, DIMM6, 0 }, - }, - }; - - if (bist == 0) - enable_lapic(); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (bios_reset_detected()) - hard_reset(); - - enable_smbus(); -#if 0 - dump_spd_registers(&memctrl[0]); - dump_smbus_registers(); -#endif - - sdram_initialize(1, memctrl); - -#if 0 - dump_pci_devices(); -#endif - -#if 1 - dump_pci_device(PCI_DEV(0, 0, 0)); -#endif -} diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig index 9ff66d3..b3df67b 100644 --- a/src/northbridge/intel/Kconfig +++ b/src/northbridge/intel/Kconfig @@ -1,4 +1,3 @@ -source src/northbridge/intel/e7501/Kconfig source src/northbridge/intel/e7505/Kconfig source src/northbridge/intel/e7525/Kconfig source src/northbridge/intel/i3100/Kconfig diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 020caa8..2239675 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -1,4 +1,3 @@ -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7501) += e7501 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7505) += e7505 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7525) += e7525 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I3100) += i3100 diff --git a/src/northbridge/intel/e7501/Kconfig b/src/northbridge/intel/e7501/Kconfig deleted file mode 100644 index 88c0b45..0000000 --- a/src/northbridge/intel/e7501/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -config NORTHBRIDGE_INTEL_E7501 - bool - select HAVE_DEBUG_RAM_SETUP - select PER_DEVICE_ACPI_TABLES - diff --git a/src/northbridge/intel/e7501/Makefile.inc b/src/northbridge/intel/e7501/Makefile.inc deleted file mode 100644 index 23eada5..0000000 --- a/src/northbridge/intel/e7501/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-y += northbridge.c diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c deleted file mode 100644 index 07f1596..0000000 --- a/src/northbridge/intel/e7501/debug.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * generic debug code, used by mainboard specific romstage.c - * - */ -#if 1 -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} - -static inline void print_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\n"); - } -} - -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - - for(i = 0; i < 256; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%02x:",i); -#else - print_debug("\n"); - print_debug_hex8(i); - print_debug_char(':'); -#endif - } - val = pci_read_config8(dev, i); -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, " %02x", val); -#else - print_debug_char(' '); - print_debug_hex8(val); -#endif - } - print_debug("\n"); -} - -static inline void dump_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -static inline void dump_pci_devices_on_bus(unsigned busn) -{ - device_t dev; - for(dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -static inline void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - print_debug("\n"); - for(i = 0; i < 4; i++) { - unsigned device; - device = ctrl->channel0[i]; - if (device) { - int j; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); -#else - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".0: "); - print_debug_hex8(device); -#endif - for(j = 0; j < 128; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%02x: ", j); -#else - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); -#endif - } - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - byte = status & 0xff; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%02x ", byte); -#else - print_debug_hex8(byte); - print_debug_char(' '); -#endif - } - print_debug("\n"); - } - device = ctrl->channel1[i]; - if (device) { - int j; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); -#else - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".1: "); - print_debug_hex8(device); -#endif - for(j = 0; j < 128; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%02x: ", j); -#else - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); -#endif - } - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - byte = status & 0xff; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%02x ", byte); -#else - print_debug_hex8(byte); - print_debug_char(' '); -#endif - } - print_debug("\n"); - } - } -} -static inline void dump_smbus_registers(void) -{ - unsigned device; - print_debug("\n"); - for(device = 1; device < 0x80; device++) { - int j; - if( smbus_read_byte(device, 0) < 0 ) continue; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "smbus: %02x", device); -#else - print_debug("smbus: "); - print_debug_hex8(device); -#endif - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - if ((j & 0xf) == 0) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%02x: ",j); -#else - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); -#endif - } - byte = status & 0xff; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%02x ", byte); -#else - print_debug_hex8(byte); - print_debug_char(' '); -#endif - } - print_debug("\n"); - } -} - -static inline void dump_io_resources(unsigned port) -{ - - int i; -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%04x:\n", port); -#else - print_debug_hex16(port); - print_debug(":\n"); -#endif - for(i=0;i<256;i++) { - uint8_t val; - if ((i & 0x0f) == 0) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%02x:", i); -#else - print_debug_hex8(i); - print_debug_char(':'); -#endif - } - val = inb(port); -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, " %02x",val); -#else - print_debug_char(' '); - print_debug_hex8(val); -#endif - if ((i & 0x0f) == 0x0f) { - print_debug("\n"); - } - port++; - } -} - -static inline void dump_mem(unsigned start, unsigned end) -{ - unsigned i; - print_debug("dump_mem:"); - for(i=start;i<end;i++) { - if((i & 0xf)==0) { -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%08x:", i); -#else - print_debug("\n"); - print_debug_hex32(i); - print_debug(":"); -#endif - } -#if !defined(__ROMCC__) - printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); -#else - print_debug(" "); - print_debug_hex8((unsigned char)*((unsigned char *)i)); -#endif - } - print_debug("\n"); - } -#endif diff --git a/src/northbridge/intel/e7501/e7501.h b/src/northbridge/intel/e7501/e7501.h deleted file mode 100644 index 1e431b1..0000000 --- a/src/northbridge/intel/e7501/e7501.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * e7501.h: PCI configuration space for the Intel E7501 memory controller - */ - -/************ D0:F0 ************/ -// Register offsets -#define MAYBE_SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? (if similar to 855PM) */ -#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */ -#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */ -#define DRB_ROW_1 0x61 -#define DRB_ROW_2 0x62 -#define DRB_ROW_3 0x63 -#define DRB_ROW_4 0x64 -#define DRB_ROW_5 0x65 -#define DRB_ROW_6 0x66 -#define DRB_ROW_7 0x67 - -#define DRA 0x70 /* DRAM Row Attributes registers, 4 x 8 bit */ -#define DRT 0x78 /* DRAM Timing register, 32 bit */ -#define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ -#define MAYBE_DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ -#define CKDIS 0x8C /* Clock disable register, 8 bit */ -#define TOLM 0xC4 /* Top of Low Memory register, 16 bit */ -#define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ -#define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */ -#define SKPD 0xDE /* Scratchpad register, 16 bit */ -#define MAYBE_MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */ - -// CAS# Latency bits in the DRAM Timing (DRT) register -#define DRT_CAS_2_5 (0<<4) -#define DRT_CAS_2_0 (1<<4) -#define DRT_CAS_MASK (3<<4) - -// Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register -#define RAM_COMMAND_NOP (1<<4) -#define RAM_COMMAND_PRECHARGE (2<<4) -#define RAM_COMMAND_MRS (3<<4) -#define RAM_COMMAND_EMRS (4<<4) -#define RAM_COMMAND_CBR (6<<4) -#define RAM_COMMAND_NORMAL (7<<4) - - -// RCOMP Memory Map offsets -// Conjecture based on apparent similarity between E7501 and 855PM -// Intel doc. 252613-003 describes these for 855PM - -#define MAYBE_SMRCTL 0x20 /* System Memory RCOMP Control Register? */ -#define MAYBE_DQCMDSTR 0x30 /* Strength control for DQ and CMD signal groups? */ -#define MAYBE_CKESTR 0x31 /* Strength control for CKE signal group? */ -#define MAYBE_CSBSTR 0x32 /* Strength control for CS# signal group? */ -#define MAYBE_CKSTR 0x33 /* Strength control for CK signal group? */ -#define MAYBE_RCVENSTR 0x34 /* Strength control for RCVEnOut# signal group? */ - -/************ D0:F1 ************/ -// Register offsets -#define FERR_GLOBAL 0x40 /* First global error register, 32 bits */ -#define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ -#define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ -#define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c deleted file mode 100644 index 64bf840..0000000 --- a/src/northbridge/intel/e7501/northbridge.c +++ /dev/null @@ -1,140 +0,0 @@ -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <device/device.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/cpu.h> -#include <stdlib.h> -#include <string.h> -#include <cbmem.h> - -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - -#endif - - -static void pci_domain_set_resources(device_t dev) -{ - device_t mc_dev; - uint32_t pci_tolm; - - pci_tolm = find_pci_tolm(dev->link_list); - mc_dev = dev->link_list->children; - if (mc_dev) { - /* Figure out which areas are/should be occupied by RAM. - * This is all computed in kilobytes and converted to/from - * the memory controller right at the edges. - * Having different variables in different units is - * too confusing to get right. Kilobytes are good up to - * 4 Terabytes of RAM... - */ - uint16_t tolm_r, remapbase_r, remaplimit_r; - unsigned long tomk, tolmk; - unsigned long remapbasek, remaplimitk; - int idx; - - /* Get the value of the highest DRB. This tells the end of - * the physical memory. The units are ticks of 64MB - * i.e. 1 means 64MB. - */ - tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16; - /* Compute the top of Low memory */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does not overlap memory - * we won't use the remap window. - */ - tolmk = tomk; - remapbasek = 0x3ff << 16; - remaplimitk = 0 << 16; - } - else { - /* The PCI memory hole overlaps memory - * setup the remap window. - */ - /* Find the bottom of the remap window - * is it above 4G? - */ - remapbasek = 4*1024*1024; - if (tomk > remapbasek) { - remapbasek = tomk; - } - /* Find the limit of the remap window */ - remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16)); - } - /* Write the ram configuration registers, - * preserving the reserved bits. - */ - tolm_r = pci_read_config16(mc_dev, 0xc4); - tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff); - pci_write_config16(mc_dev, 0xc4, tolm_r); - - remapbase_r = pci_read_config16(mc_dev, 0xc6); - remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00); - pci_write_config16(mc_dev, 0xc6, remapbase_r); - - remaplimit_r = pci_read_config16(mc_dev, 0xc8); - remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00); - pci_write_config16(mc_dev, 0xc8, remaplimit_r); - - /* Report the memory regions */ - idx = 10; - ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, tolmk - 768); - if (tomk > 4*1024*1024) { - ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024); - } - if (remaplimitk >= remapbasek) { - ram_resource(dev, idx++, remapbasek, - (remaplimitk + 64*1024) - remapbasek); - } - - set_top_of_ram(tolmk * 1024); - } - assign_resources(dev->link_list); -} - -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, -}; - -static void cpu_bus_init(device_t dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, -}; - -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_intel_e7501_ops = { - CHIP_NAME("Intel E7501 Northbridge") - .enable_dev = enable_dev, -}; diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c deleted file mode 100644 index 2247a25..0000000 --- a/src/northbridge/intel/e7501/raminit.c +++ /dev/null @@ -1,2007 +0,0 @@ -/* This was originally for the e7500, modified for e7501 - * The primary differences are that 7501 apparently can - * support single channel RAM (i haven't tested), - * CAS1.5 is no longer supported, The ECC scrubber - * now supports a mode to zero RAM and init ECC in one step - * and the undocumented registers at 0x80 require new - * (undocumented) values determined by guesswork and - * comparison w/ OEM BIOS values. - * Steven James 02/06/2003 - */ - -/* converted to C 6/2004 yhlu */ - -#include <assert.h> -#include <spd.h> -#include <sdram_mode.h> -#include <stdlib.h> -#include "e7501.h" - -/*----------------------------------------------------------------------------- -Definitions: ------------------------------------------------------------------------------*/ - -// Uncomment this to enable run-time checking of DIMM parameters -// for dual-channel operation -// Unfortunately the code seems to chew up several K of space. -//#define VALIDATE_DIMM_COMPATIBILITY - -#if CONFIG_DEBUG_RAM_SETUP -#define RAM_DEBUG_MESSAGE(x) print_debug(x) -#define RAM_DEBUG_HEX32(x) print_debug_hex32(x) -#define RAM_DEBUG_HEX8(x) print_debug_hex8(x) -#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) -#else -#define RAM_DEBUG_MESSAGE(x) -#define RAM_DEBUG_HEX32(x) -#define RAM_DEBUG_HEX8(x) -#define DUMPNORTH() -#endif - -#define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) -#define SPD_ERROR "Error reading SPD info\n" - -// NOTE: This used to be 0x100000. -// That doesn't work on systems where A20M# is asserted, because -// attempts to access 0x1000NN end up accessing 0x0000NN. -#define RCOMP_MMIO 0x200000 - -struct dimm_size { - unsigned long side1; - unsigned long side2; -}; - -static const uint32_t refresh_frequency[] = { - /* Relative frequency (array value) of each E7501 Refresh Mode Select - * (RMS) value (array index) - * 0 == least frequent refresh (longest interval between refreshes) - * [0] disabled -> 0 - * [1] 15.6 usec -> 2 - * [2] 7.8 usec -> 3 - * [3] 64 usec -> 1 - * [4] reserved -> 0 - * [5] reserved -> 0 - * [6] reserved -> 0 - * [7] 64 clocks -> 4 - */ - 0, 2, 3, 1, 0, 0, 0, 4 -}; - -static const uint32_t refresh_rate_map[] = { - /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode - * Select values (array value) - * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 - * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and - * 64 clock (481 ns) (7) refresh. - * [0] == 15.625 us -> 15.6 us - * [1] == 3.9 us -> 481 ns - * [2] == 7.8 us -> 7.8 us - * [3] == 31.3 us -> 15.6 us - * [4] == 62.5 us -> 15.6 us - * [5] == 125 us -> 64 us - */ - 1, 7, 2, 1, 1, 3 -}; - -#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) - -// SPD parameters that must match for dual-channel operation -static const uint8_t dual_channel_parameters[] = { - SPD_MEMORY_TYPE, - SPD_MODULE_VOLTAGE, - SPD_NUM_COLUMNS, - SPD_NUM_ROWS, - SPD_NUM_DIMM_BANKS, - SPD_PRIMARY_SDRAM_WIDTH, - SPD_NUM_BANKS_PER_SDRAM -}; - - /* - * Table: constant_register_values - */ -static const long constant_register_values[] = { - /* SVID - Subsystem Vendor Identification Register - * 0x2c - 0x2d - * [15:00] Subsytem Vendor ID (Indicates system board vendor) - */ - /* SID - Subsystem Identification Register - * 0x2e - 0x2f - * [15:00] Subsystem ID - */ - // Not everyone wants to be Super Micro Computer, Inc. - // The mainboard should set this if desired. - // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16), - - /* Undocumented - * (DRAM Read Timing Control, if similar to 855PM?) - * 0x80 - 0x81 - * This register has something to do with CAS latencies, - * possibily this is the real chipset control. - * At 0x00 CAS latency 1.5 works. - * At 0x06 CAS latency 2.5 works. - * At 0x01 CAS latency 2.0 works. - */ - /* This is still undocumented in e7501, but with different values - * CAS 2.0 values taken from Intel BIOS settings, others are a guess - * and may be terribly wrong. Old values preserved as comments until I - * figure this out for sure. - * e7501 docs claim that CAS1.5 is unsupported, so it may or may not - * work at all. - * Steven James 02/06/2003 - */ - /* NOTE: values now configured in configure_e7501_cas_latency() based - * on SPD info and total number of DIMMs (per Intel) - */ - - /* FDHC - Fixed DRAM Hole Control - * 0x58 - * [7:7] Hole_Enable - * 0 == No memory Hole - * 1 == Memory Hole from 15MB to 16MB - * [6:0] Reserved - * - * PAM - Programmable Attribute Map - * 0x59 [1:0] Reserved - * 0x59 [5:4] 0xF0000 - 0xFFFFF - * 0x5A [1:0] 0xC0000 - 0xC3FFF - * 0x5A [5:4] 0xC4000 - 0xC7FFF - * 0x5B [1:0] 0xC8000 - 0xCBFFF - * 0x5B [5:4] 0xCC000 - 0xCFFFF - * 0x5C [1:0] 0xD0000 - 0xD3FFF - * 0x5C [5:4] 0xD4000 - 0xD7FFF - * 0x5D [1:0] 0xD8000 - 0xDBFFF - * 0x5D [5:4] 0xDC000 - 0xDFFFF - * 0x5E [1:0] 0xE0000 - 0xE3FFF - * 0x5E [5:4] 0xE4000 - 0xE7FFF - * 0x5F [1:0] 0xE8000 - 0xEBFFF - * 0x5F [5:4] 0xEC000 - 0xEFFFF - * 00 == DRAM Disabled (All Access go to memory mapped I/O space) - * 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space) - * 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space) - * 11 == Normal (All Access go to DRAM) - */ - - // Map all legacy ranges to DRAM - 0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24), - 0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24), - - /* DRB - DRAM Row Boundary Registers - * 0x60 - 0x6F - * An array of 8 byte registers, which hold the ending - * memory address assigned to each pair of DIMMS, in 64MB - * granularity. - */ - // Conservatively say each row has 64MB of ram, we will fix this up later - // NOTE: These defaults allow us to prime all of the DIMMs on the board - // without jumping through 36-bit adddressing hoops, even if the - // total memory is > 4 GB. Changing these values may break do_ram_command()! - 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24), - 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24), - - /* DRA - DRAM Row Attribute Register - * 0x70 Row 0,1 - * 0x71 Row 2,3 - * 0x72 Row 4,5 - * 0x73 Row 6,7 - * [7:7] Device width for Odd numbered rows - * 0 == 8 bits wide x8 - * 1 == 4 bits wide x4 - * [6:4] Row Attributes for Odd numbered rows - * 010 == 8KB (for dual-channel) - * 011 == 16KB (for dual-channel) - * 100 == 32KB (for dual-channel) - * 101 == 64KB (for dual-channel) - * Others == Reserved - * [3:3] Device width for Even numbered rows - * 0 == 8 bits wide x8 - * 1 == 4 bits wide x4 - * [2:0] Row Attributes for Even numbered rows - * 010 == 8KB (for dual-channel) - * 011 == 16KB (for dual-channel) - * 100 == 32KB (for dual-channel) - * 101 == 64KB (This page size appears broken) - * Others == Reserved - */ - // NOTE: overridden by configure_e7501_row_attributes(), later - 0x70, 0x00000000, 0, - - /* DRT - DRAM Timing Register - * 0x78 - * [31:30] Reserved - * [29:29] Back to Back Write-Read Turn Around - * 0 == 3 clocks between WR-RD commands - * 1 == 2 clocks between WR-RD commands - * [28:28] Back to Back Read-Write Turn Around - * 0 == 5 clocks between RD-WR commands - * 1 == 4 clocks between RD-WR commands - * [27:27] Back to Back Read Turn Around - * 0 == 4 clocks between RD commands - * 1 == 3 clocks between RD commands - * [26:24] Read Delay (tRD) - * 000 == 7 clocks - * 001 == 6 clocks - * 010 == 5 clocks - * Others == Reserved - * [23:19] Reserved - * [18:16] DRAM idle timer - * 000 == infinite - * 011 == 16 dram clocks - * 001 == 0 clocks - * [15:11] Reserved - * [10:09] Active to Precharge (tRAS) - * 00 == 7 clocks - * 01 == 6 clocks - * 10 == 5 clocks - * 11 == Reserved - * [08:06] Reserved - * [05:04] Cas Latency (tCL) - * 00 == 2.5 Clocks - * 01 == 2.0 Clocks - * 10 == Reserved (was 1.5 Clocks for E7500) - * 11 == Reserved - * [03:03] Write Ras# to Cas# Delay (tRCD) - * 0 == 3 DRAM Clocks - * 1 == 2 DRAM Clocks - * [02:01] Read RAS# to CAS# Delay (tRCD) - * 00 == reserved - * 01 == reserved - * 10 == 3 DRAM Clocks - * 11 == 2 DRAM Clocks - * [00:00] DRAM RAS# to Precharge (tRP) - * 0 == 3 DRAM Clocks - * 1 == 2 DRAM Clocks - */ - - // Some earlier settings: - /* Most aggressive settings possible */ -// 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0), -// 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), -// 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), - - // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and - // Back-to-Back Write-Read Turnaround. All others are configured based on SPD. - 0x78, 0xD7F8FFFF, (1 << 29) | (1 << 27) | (1 << 16), - - /* FIXME why was I attempting to set a reserved bit? */ - /* 0x0100040f */ - - /* DRC - DRAM Contoller Mode Register - * 0x7c - * [31:30] Reserved - * [29:29] Initialization Complete - * 0 == Not Complete - * 1 == Complete - * [28:23] Reserved - * [22:22] Channels - * 0 == Single channel - * 1 == Dual Channel - * [21:20] DRAM Data Integrity Mode - * 00 == Disabled, no ECC - * 01 == Reserved - * 10 == Error checking, using chip-kill, with correction - * 11 == Reserved - * [19:18] DRB Granularity (Read-Only) - * 00 == 32 MB quantities (single channel mode) - * 01 == 64 MB quantities (dual-channel mode) - * 10 == Reserved - * 11 == Reserved - * [17:17] (Intel Undocumented) should always be set to 1 (SJM: comment inconsistent with current setting, below) - * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC) - * 0 == 2n Rule - * 1 == 1n rule - * [15:11] Reserved - * [10:08] Refresh mode select - * 000 == Refresh disabled - * 001 == Refresh interval 15.6 usec - * 010 == Refresh interval 7.8 usec - * 011 == Refresh interval 64 usec - * 111 == Refresh every 64 clocks (fast refresh) - * [07:07] Reserved - * [06:04] Mode Select (SMS) - * 000 == Reserved (was Self Refresh Mode in E7500) - * 001 == NOP Command - * 010 == All Banks Precharge - * 011 == Mode Register Set - * 100 == Extended Mode Register Set - * 101 == Reserved - * 110 == CBR Refresh - * 111 == Normal Operation - * [03:00] Reserved - */ -// .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8), -// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8), -// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8), - - // Default to dual-channel mode, ECC, 1-clock address/cmd hold - // NOTE: configure_e7501_dram_controller_mode() configures further - 0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8), - - /* Another Intel undocumented register - * 0x88 - 0x8B - * [31:31] Purpose unknown - * [26:26] Master DLL Reset? - * 0 == Normal operation? - * 1 == Reset? - * [07:07] Periodic memory recalibration? - * 0 == Disabled? - * 1 == Enabled? - * [04:04] Receive FIFO RE-Sync? - * 0 == Normal operation? - * 1 == Reset? - */ - // NOTE: Some factory BIOSs don't do this. - // Doesn't seem to matter either way. - 0x88, 0xffffff00, 0x80, - - /* CLOCK_DIS - CK/CK# Disable Register - * 0x8C - * [7:7] DDR Frequency - * 0 == 100 MHz (200 MHz data rate) - * 1 == 133 MHz (266 MHz data rate) - * [6:4] Reserved - * [3:3] CK3 - * 0 == Enable - * 1 == Disable - * [2:2] CK2 - * 0 == Enable - * 1 == Disable - * [1:1] CK1 - * 0 == Enable - * 1 == Disable - * [0:0] CK0 - * 0 == Enable - * 1 == Disable - */ - // NOTE: Disable all clocks initially; turn ones we need back on - // in enable_e7501_clocks() - 0x8C, 0xfffffff0, 0xf, - - /* TOLM - Top of Low Memory Register - * 0xC4 - 0xC5 - * [15:11] Top of low memory (TOLM) - * The address below 4GB that should be treated as RAM, - * on a 128MB granularity. - * [10:00] Reserved - */ - /* REMAPBASE - Remap Base Address Regsiter - * 0xC6 - 0xC7 - * [15:10] Reserved - * [09:00] Remap Base Address [35:26] 64M aligned - * Bits [25:0] are assumed to be 0. - */ - - // NOTE: TOLM overridden by configure_e7501_ram_addresses() - 0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16), - - /* REMAPLIMIT - Remap Limit Address Register - * 0xC8 - 0xC9 - * [15:10] Reserved - * [09:00] Remap Limit Address [35:26] 64M aligned - * When remaplimit < remapbase the remap window is disabled. - */ - 0xc8, 0xfffffc00, 0, - - /* DVNP - Device Not Present Register - * 0xE0 - 0xE1 - * [15:05] Reserved - * [04:04] Device 4 Function 1 Present - * 0 == Present - * 1 == Absent - * [03:03] Device 3 Function 1 Present - * 0 == Present - * 1 == Absent - * [02:02] Device 2 Function 1 Present - * 0 == Present - * 1 == Absent - * [01:01] Reserved - * [00:00] Device 0 Function 1 Present - * 0 == Present - * 1 == Absent - */ - - // Enable D0:D1, disable D2:F1, D3:F1, D4:F1 - 0xe0, 0xffffffe2, (1 << 4) | (1 << 3) | (1 << 2) | (0 << 0), - - // Undocumented - 0xd8, 0xffff9fff, 0x00000000, - - // Undocumented - this is pure conjecture based on similarity to 855PM - /* MCHTST - MCH Test Register - * 0xF4 - 0xF7 - * [31:31] Purpose unknown - * [30:30] Purpose unknown - * [29:23] Unknown - not used? - * [22:22] System Memory MMR Enable - * 0 == Disable: mem space and BAR at 0x14 are not accessible - * 1 == Enable: mem space and BAR at 0x14 are accessible - * [21:20] Purpose unknown - * [19:02] Unknown - not used? - * [01:01] D6EN (Device #6 enable) - * 0 == Disable - * 1 == Enable - * [00:00] Unknown - not used? - */ - - 0xf4, 0x3f8ffffd, 0x40300002, - -#ifdef SUSPICIOUS_LOOKING_CODE - // SJM: Undocumented. - // This will access D2:F0:0x50, is this correct?? - 0x1050, 0xffffffcf, 0x00000030, -#endif -}; - - /* DDR RECOMP tables */ - -// Slew table for 1x drive? -static const uint32_t maybe_1x_slew_table[] = { - 0x44332211, 0xc9776655, 0xffffffff, 0xffffffff, - 0x22111111, 0x55444332, 0xfffca876, 0xffffffff, -}; - -// Slew table for 2x drive? -static const uint32_t maybe_2x_slew_table[] = { - 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff, - 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff, -}; - -// Pull Up / Pull Down offset table, if analogous to IXP2800? -static const uint32_t maybe_pull_updown_offset_table[] = { - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0x88888888, 0x88888888, 0x88888888, 0x88888888, -}; - -/*----------------------------------------------------------------------------- -Delay functions: ------------------------------------------------------------------------------*/ - -#define SLOW_DOWN_IO inb(0x80) -//#define SLOW_DOWN_IO udelay(40); - - /* Estimate that SLOW_DOWN_IO takes about 50&76us */ - /* delay for 200us */ - -#if 1 -static void do_delay(void) -{ - int i; - for (i = 0; i < 16; i++) { - SLOW_DOWN_IO; - } -} - -#define DO_DELAY do_delay() -#else -#define DO_DELAY \ - udelay(200) -#endif - -#define EXTRA_DELAY DO_DELAY - -static void die_on_spd_error(int spd_return_value) -{ - if (spd_return_value < 0) - die("Error reading SPD info\n"); -} - -/*----------------------------------------------------------------------------- -Serial presence detect (SPD) functions: ------------------------------------------------------------------------------*/ - -/** - * Calculate the page size for each physical bank of the DIMM: - * log2(page size) = (# columns) + log2(data width) - * - * NOTE: Page size is the total number of data bits in a row. - * - * @param dimm_socket_address SMBus address of DIMM socket to interrogate. - * @return log2(page size) for each side of the DIMM. - */ -static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) -{ - uint16_t module_data_width; - int value; - struct dimm_size pgsz; - - pgsz.side1 = 0; - pgsz.side2 = 0; - - // Side 1 - value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); - if (value < 0) - goto hw_err; - pgsz.side1 = value & 0xf; // # columns in bank 1 - - /* Get the module data width and convert it to a power of two */ - value = - spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); - if (value < 0) - goto hw_err; - module_data_width = (value & 0xff) << 8; - - value = - spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); - if (value < 0) - goto hw_err; - module_data_width |= (value & 0xff); - - pgsz.side1 += log2(module_data_width); - - /* side two */ - value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); - if (value < 0) - goto hw_err; - if (value > 2) - die("Bad SPD value\n"); - if (value == 2) { - - pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently - value = - spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); - if (value < 0) - goto hw_err; - if ((value & 0xf0) != 0) { - // Asymmetric banks - pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */ - pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */ - } - } - - return pgsz; - - hw_err: - die(SPD_ERROR); - return pgsz; // Never reached -} - -/** - * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16). - * - * @param dimm_socket_address SMBus address of DIMM socket to interrogate. - * @return Width in bits of each DIMM side's DRAMs. - */ -static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) -{ - int value; - struct dimm_size width; - - width.side1 = 0; - width.side2 = 0; - - value = - spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); - die_on_spd_error(value); - - width.side1 = value & 0x7f; // Mask off bank 2 flag - - if (value & 0x80) { - width.side2 = width.side1 << 1; // Bank 2 exists and is double-width - } else { - // If bank 2 exists, it's the same width as bank 1 - value = - spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); - die_on_spd_error(value); - -#ifdef ROMCC_IF_BUG_FIXED - if (value == 2) - width.side2 = width.side1; -#else - switch (value) { - case 2: - width.side2 = width.side1; - break; - - default: - break; - } -#endif - } - - return width; -} - -/** - * Calculate the log base 2 size in bits of both DIMM sides. - * - * log2(# bits) = (# columns) + log2(data width) + - * (# rows) + log2(banks per SDRAM) - * - * Note that it might be easier to use SPD byte 31 here, it has the DIMM size - * as a multiple of 4MB. The way we do it now we can size both sides of an - * asymmetric DIMM. - * - * @param dimm_socket_address SMBus address of DIMM socket to interrogate. - * @return log2(number of bits) for each side of the DIMM. - */ -static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) -{ - int value; - - // Start with log2(page size) - struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address); - - if (sz.side1 > 0) { - - value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS); - die_on_spd_error(value); - - sz.side1 += value & 0xf; - - if (sz.side2 > 0) { - - // Double-sided DIMM - if (value & 0xF0) - sz.side2 += value >> 4; // Asymmetric - else - sz.side2 += value; // Symmetric - } - - value = - spd_read_byte(dimm_socket_address, - SPD_NUM_BANKS_PER_SDRAM); - die_on_spd_error(value); - - value = log2(value); - sz.side1 += value; - if (sz.side2 > 0) - sz.side2 += value; - } - - return sz; -} - -#ifdef VALIDATE_DIMM_COMPATIBILITY - -/** - * Determine whether two DIMMs have the same value for an SPD parameter. - * - * @param spd_byte_number The SPD byte number to compare in both DIMMs. - * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate. - * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate. - * @return 1 if both DIMM sockets report the same value for the specified - * SPD parameter, 0 if the values differed or an error occurred. - */ -static uint8_t are_spd_values_equal(uint8_t spd_byte_number, - uint16_t dimm0_address, - uint16_t dimm1_address) -{ - uint8_t bEqual = 0; - int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number); - int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number); - - if ((dimm0_value >= 0) && (dimm1_value >= 0) - && (dimm0_value == dimm1_value)) - bEqual = 1; - - return bEqual; -} -#endif - -/** - * Scan for compatible DIMMs. - * - * The code in this module only supports dual-channel operation, so we test - * that compatible DIMMs are paired. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - * @return A bitmask indicating which of the possible sockets for each channel - * was found to contain a compatible DIMM. - * Bit 0 corresponds to the closest socket for channel 0 - * Bit 1 to the next socket for channel 0 - * ... - * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0 - * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1 - * ... - * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 - */ -static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) -{ - int i; - uint8_t dimm_mask = 0; - - // Have to increase size of dimm_mask if this assertion is violated - ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4); - - // Find DIMMs we can support on channel 0. - // Then see if the corresponding channel 1 DIMM has the same parameters, - // since we only support dual-channel. - - for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - - uint16_t channel0_dimm = ctrl->channel0[i]; - uint16_t channel1_dimm = ctrl->channel1[i]; - uint8_t bDualChannel = 1; -#ifdef VALIDATE_DIMM_COMPATIBILITY - struct dimm_size page_size; - struct dimm_size sdram_width; -#endif - int spd_value; - - if (channel0_dimm == 0) - continue; // No such socket on this mainboard - - if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != - SPD_MEMORY_TYPE_SDRAM_DDR) - continue; - -#ifdef VALIDATE_DIMM_COMPATIBILITY - if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != - SPD_VOLTAGE_SSTL2) - continue; // Unsupported voltage - - // E7501 does not support unregistered DIMMs - spd_value = - spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); - if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) - continue; - - // Must support burst = 4 for dual-channel operation on E7501 - // NOTE: for single-channel, burst = 8 is required - spd_value = - spd_read_byte(channel0_dimm, - SPD_SUPPORTED_BURST_LENGTHS); - if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) - continue; - - page_size = sdram_spd_get_page_size(channel0_dimm); - sdram_width = sdram_spd_get_width(channel0_dimm); - - // Validate DIMM page size - // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel - // NOTE: 4 KB = 32 Kb = 2^15 - // 32 KB = 262 Kb = 2^18 - - if ((page_size.side1 < 15) || (page_size.side1 > 18)) - continue; - - // If DIMM is double-sided, verify side2 page size - if (page_size.side2 != 0) { - if ((page_size.side2 < 15) - || (page_size.side2 > 18)) - continue; - } - // Validate SDRAM width - // The E7501 only supports x4 and x8 devices - - if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8)) - continue; - - // If DIMM is double-sided, verify side2 width - if (sdram_width.side2 != 0) { - if ((sdram_width.side2 != 4) - && (sdram_width.side2 != 8)) - continue; - } -#endif - // Channel 0 DIMM looks compatible. - // Now see if it is paired with the proper DIMM on channel 1. - - ASSERT(channel1_dimm != 0); // No such socket on this mainboard?? - - // NOTE: unpopulated DIMMs cause read to fail - spd_value = - spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); - if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) { - - print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); - continue; - } -#ifdef VALIDATE_DIMM_COMPATIBILITY - spd_value = - spd_read_byte(channel1_dimm, - SPD_SUPPORTED_BURST_LENGTHS); - if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) - continue; - - int j; - for (j = 0; j < sizeof(dual_channel_parameters); ++j) { - if (!are_spd_values_equal - (dual_channel_parameters[j], channel0_dimm, - channel1_dimm)) { - - bDualChannel = 0; - break; - } - } -#endif - - // Code around ROMCC bug in optimization of "if" statements -#ifdef ROMCC_IF_BUG_FIXED - if (bDualChannel) { - // Made it through all the checks, this DIMM pair is usable - dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i))); - } else - print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); -#else - switch (bDualChannel) { - case 0: - print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); - break; - - default: - // Made it through all the checks, this DIMM pair is usable - dimm_mask |= (1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)); - break; - } -#endif - } - - return dimm_mask; -} - -/*----------------------------------------------------------------------------- -SDRAM configuration functions: ------------------------------------------------------------------------------*/ - -/** - * Send the specified command to all DIMMs. - * - * @param command Specifies the command to be sent to the DIMMs. - * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the - * register value in JEDEC format. - */ -static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) -{ - int i; - uint32_t dram_controller_mode; - uint8_t dimm_start_64M_multiple = 0; - uint16_t e7501_mode_bits = jedec_mode_bits; - - // Configure the RAM command - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); - dram_controller_mode &= 0xFFFFFF8F; - dram_controller_mode |= command; - pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); - - // RAM_COMMAND_NORMAL is an exception. - // It affects only the memory controller and does not need to be "sent" to the DIMMs. - - if (command != RAM_COMMAND_NORMAL) { - - // Send the command to all DIMMs by accessing a memory location within each - // NOTE: for mode select commands, some of the location address bits - // are part of the command - - // Map JEDEC mode bits to E7501 - if (command == RAM_COMMAND_MRS) { - // Host address lines [15:5] map to DIMM address lines [12:11, 9:1] - // The E7501 hard-sets DIMM address lines 10 & 0 to zero - - ASSERT(!(jedec_mode_bits & 0x0401)); - - e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15 - 12)) | // JEDEC bits 11-12 move to bits 14-15 - ((jedec_mode_bits & 0x03FE) << (13 - 9)); // JEDEC bits 1-9 move to bits 5-13 - - } else if (command == RAM_COMMAND_EMRS) { - // Host address lines [15:3] map to DIMM address lines [12:0] - e7501_mode_bits = jedec_mode_bits <<= 3; - } else - ASSERT(jedec_mode_bits == 0); - - dimm_start_64M_multiple = 0; - - for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) { - - uint8_t dimm_end_64M_multiple = - pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i); - if (dimm_end_64M_multiple > dimm_start_64M_multiple) { - - // This code assumes DRAM row boundaries are all set below 4 GB - // NOTE: 0x40 * 64 MB == 4 GB - ASSERT(dimm_start_64M_multiple < 0x40); - - // NOTE: 2^26 == 64 MB - - uint32_t dimm_start_address = - dimm_start_64M_multiple << 26; - - RAM_DEBUG_MESSAGE(" Sending RAM command to 0x"); - RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits); - RAM_DEBUG_MESSAGE("\n"); - - read32(dimm_start_address + e7501_mode_bits); - - // Set the start of the next DIMM - dimm_start_64M_multiple = - dimm_end_64M_multiple; - } - } - } -} - -/** - * Set the mode register of all DIMMs. - * - * The proper CAS# latency setting is added to the mode bits specified - * by the caller. - * - * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the - * register value in JEDEC format. - */ -static void set_ram_mode(uint16_t jedec_mode_bits) -{ - ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK)); - - uint32_t dram_cas_latency = - pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; - - switch (dram_cas_latency) { - case DRT_CAS_2_5: - jedec_mode_bits |= SDRAM_CAS_2_5; - break; - - case DRT_CAS_2_0: - jedec_mode_bits |= SDRAM_CAS_2_0; - break; - - default: - BUG(); - break; - } - - do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits); -} - -/*----------------------------------------------------------------------------- -DIMM-independant configuration functions: ------------------------------------------------------------------------------*/ - -/** - * Configure the E7501's DRAM Row Boundary (DRB) registers for the memory - * present in the specified DIMM. - * - * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of - * the DIMM. - * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of - * 64 MB) for DIMMs < dimm_index. - * @param dimm_index Which DIMM pair is being processed - * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). - * @return New multiple of 64 MB total DRAM in the system. - */ -static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index) -{ - int i; - - ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL); - - // DIMM sides must be at least 32 MB - ASSERT(dimm_log2_num_bits.side1 >= 28); - ASSERT((dimm_log2_num_bits.side2 == 0) - || (dimm_log2_num_bits.side2 >= 28)); - - // In dual-channel mode, we are called only once for each pair of DIMMs. - // Each time we process twice the capacity of a single DIMM. - - // Convert single DIMM capacity to paired DIMM capacity - // (multiply by two ==> add 1 to log2) - dimm_log2_num_bits.side1++; - if (dimm_log2_num_bits.side2 > 0) - dimm_log2_num_bits.side2++; - - // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB) - // to the total capacity of the system - // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29 - - total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29)); - - // Configure the boundary address for the row on side 1 - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1), - total_dram_64M_multiple); - - // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair - // (as a multiple of 64 MB) to the total capacity of the system - if (dimm_log2_num_bits.side2 >= 29) - total_dram_64M_multiple += - (1 << (dimm_log2_num_bits.side2 - 29)); - - // Configure the boundary address for the row (if any) on side 2 - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (dimm_index << 1), - total_dram_64M_multiple); - - // Update boundaries for rows subsequent to these. - // These settings will be overridden by a subsequent call if a populated physical slot exists - - for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (i << 1), - total_dram_64M_multiple); - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (i << 1), - total_dram_64M_multiple); - } - - return total_dram_64M_multiple; -} - -/** - * Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM). - * - * If necessary, set up a remap window so we don't waste DRAM that ordinarily - * would lie behind addresses reserved for memory-mapped I/O. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). - */ -static void configure_e7501_ram_addresses(const struct mem_controller - *ctrl, uint8_t dimm_mask) -{ - int i; - uint8_t total_dram_64M_multiple = 0; - - // Configure the E7501's DRAM row boundaries - // Start by zeroing out the temporary initial configuration - pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_0, 0); - pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_4, 0); - - for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - - uint16_t dimm_socket_address = ctrl->channel0[i]; - struct dimm_size sz; - - if (!(dimm_mask & (1 << i))) - continue; // This DIMM not present - - sz = spd_get_dimm_size(dimm_socket_address); - - RAM_DEBUG_MESSAGE("dimm size ="); - RAM_DEBUG_HEX32((u32)sz.side1); - RAM_DEBUG_MESSAGE(" "); - RAM_DEBUG_HEX32((u32)sz.side2); - RAM_DEBUG_MESSAGE("\n"); - - if (sz.side1 == 0) - die("Bad SPD value\n"); - - total_dram_64M_multiple = - configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i); - } - - // Configure the Top Of Low Memory (TOLM) in the E7501 - // This address must be a multiple of 128 MB that is less than 4 GB. - // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address - // in the highest 5 bits. - - // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system. - // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes - // such as flash and memory-mapped I/O. - - // If there is more than 3 GB of DRAM, we define a remap window which - // makes the DRAM "behind" the reserved region available above the top of physical - // memory. - - // NOTE: 0xC0000000 / (64 MB) == 0x30 - - if (total_dram_64M_multiple <= 0x30) { - - // <= 3 GB total RAM - - /* I should really adjust all of this in C after I have resources - * to all of the pci devices. - */ - - // Round up to 128MB granularity - // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down? - - uint8_t total_dram_128M_multiple = - (total_dram_64M_multiple + 1) >> 1; - - // Convert to high 16 bits of address - uint16_t top_of_low_memory = - total_dram_128M_multiple << 11; - - pci_write_config16(PCI_DEV(0, 0, 0), TOLM, - top_of_low_memory); - - } else { - - // > 3 GB total RAM - - // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory - uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0 - uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF - - // Put TOLM at 3 GB - - pci_write_config16(PCI_DEV(0, 0, 0), TOLM, 0xc000); - - // Define a remap window to make the RAM that would appear from 3 GB - 4 GB - // visible just beyond 4 GB or the end of physical memory, whichever is larger - // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address, - // (i.e. a multiple of 64 MB) in the lowest 10 bits. - // NOTE: 0x100000000 / (64 MB) == 0x40 - - if (total_dram_64M_multiple < 0x40) { - remap_base = 0x40; // 0x100000000 - remap_limit = - 0x40 + (total_dram_64M_multiple - 0x30) - 1; - } - - pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE, - remap_base); - pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT, - remap_limit); - } -} - -/** - * If we're configured to use ECC, initialize the SDRAM and clear the E7501's - * ECC error flags. - */ -static void initialize_ecc(void) -{ - uint32_t dram_controller_mode; - - /* Test to see if ECC support is enabled */ - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); - dram_controller_mode >>= 20; - dram_controller_mode &= 3; - if (dram_controller_mode == 2) { - - uint8_t byte; - - RAM_DEBUG_MESSAGE("Initializing ECC state...\n"); - /* Initialize ECC bits , use ECC zero mode (new to 7501) */ - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06); - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07); - - // Wait for scrub cycle to complete - do { - byte = - pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS); - } while ((byte & 0x08) == 0); - - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc); - RAM_DEBUG_MESSAGE("ECC state initialized.\n"); - - /* Clear the ECC error bits */ - pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03); - pci_write_config8(PCI_DEV(0, 0, 1), DRAM_NERR, 0x03); - - // Clear DRAM Interface error bits (write-one-clear) - pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1 << 18); - pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1 << 18); - - // Start normal ECC scrub - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 5); - } - -} - -/** - * Program the DRAM Timing register (DRT) of the E7501 (except for CAS# - * latency, which is assumed to have been programmed already), based on the - * parameters of the various installed DIMMs. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). - */ -static void configure_e7501_dram_timing(const struct mem_controller *ctrl, - uint8_t dimm_mask) -{ - int i; - uint32_t dram_timing; - int value; - uint8_t slowest_row_precharge = 0; - uint8_t slowest_ras_cas_delay = 0; - uint8_t slowest_active_to_precharge_delay = 0; - uint32_t current_cas_latency = - pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; - - // CAS# latency must be programmed beforehand - ASSERT((current_cas_latency == DRT_CAS_2_0) - || (current_cas_latency == DRT_CAS_2_5)); - - // Each timing parameter is determined by the slowest DIMM - - for (i = 0; i < MAX_DIMM_SOCKETS; i++) { - uint16_t dimm_socket_address; - - if (!(dimm_mask & (1 << i))) - continue; // This DIMM not present - - if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) - dimm_socket_address = ctrl->channel0[i]; - else - dimm_socket_address = - ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; - - value = - spd_read_byte(dimm_socket_address, - SPD_MIN_ROW_PRECHARGE_TIME); - if (value < 0) - goto hw_err; - if (value > slowest_row_precharge) - slowest_row_precharge = value; - - value = - spd_read_byte(dimm_socket_address, - SPD_MIN_RAS_TO_CAS_DELAY); - if (value < 0) - goto hw_err; - if (value > slowest_ras_cas_delay) - slowest_ras_cas_delay = value; - - value = - spd_read_byte(dimm_socket_address, - SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); - if (value < 0) - goto hw_err; - if (value > slowest_active_to_precharge_delay) - slowest_active_to_precharge_delay = value; - } - - // NOTE for timing parameters: - // At 133 MHz, 1 clock == 7.52 ns - - /* Read the initial state */ - dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); - - /* Trp */ - - // E7501 supports only 2 or 3 clocks for tRP - if (slowest_row_precharge > ((22 << 2) | (2 << 0))) - die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks - else if (slowest_row_precharge > (15 << 2)) - dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks - else - dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks - - /* Trcd */ - - // E7501 supports only 2 or 3 clocks for tRCD - // Use the same value for both read & write - dram_timing &= ~((1 << 3) | (3 << 1)); - if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0))) - die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks - else if (slowest_ras_cas_delay > (15 << 2)) - dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks - else - dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks - - /* Tras */ - - // E7501 supports only 5, 6, or 7 clocks for tRAS - // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns - dram_timing &= ~(3 << 9); - - if (slowest_active_to_precharge_delay > 52) - die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks - else if (slowest_active_to_precharge_delay > 45) - dram_timing |= (0 << 9); // 46-52 ns: 7 clocks - else if (slowest_active_to_precharge_delay > 37) - dram_timing |= (1 << 9); // 38-45 ns: 6 clocks - else - dram_timing |= (2 << 9); // < 38 ns: 5 clocks - - /* Trd */ - - /* Set to a 7 clock read delay. This is for 133MHz - * with a CAS latency of 2.5 if 2.0 a 6 clock - * delay is good */ - - dram_timing &= ~(7 << 24); // 7 clocks - if (current_cas_latency == DRT_CAS_2_0) - dram_timing |= (1 << 24); // 6 clocks - - /* - * Back to Back Read-Write Turn Around - */ - /* Set to a 5 clock back to back read to write turn around. - * 4 is a good delay if the CAS latency is 2.0 */ - - dram_timing &= ~(1 << 28); // 5 clocks - if (current_cas_latency == DRT_CAS_2_0) - dram_timing |= (1 << 28); // 4 clocks - - pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); - - return; - - hw_err: - die(SPD_ERROR); -} - -/** - * Determine the shortest CAS# latency that the E7501 and all DIMMs have in - * common, and program the E7501 to use it. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). - */ -static void configure_e7501_cas_latency(const struct mem_controller *ctrl, - uint8_t dimm_mask) -{ - int i; - int value; - uint32_t dram_timing; - uint16_t maybe_dram_read_timing; - uint32_t dword; - - // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format - // NOTE: E7501 supports only 2.0 and 2.5 - uint32_t system_compatible_cas_latencies = - SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; - uint32_t current_cas_latency; - uint32_t dimm_compatible_cas_latencies; - - for (i = 0; i < MAX_DIMM_SOCKETS; i++) { - - uint16_t dimm_socket_address; - - if (!(dimm_mask & (1 << i))) - continue; // This DIMM not usable - - if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) - dimm_socket_address = ctrl->channel0[i]; - else - dimm_socket_address = - ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; - - value = - spd_read_byte(dimm_socket_address, - SPD_ACCEPTABLE_CAS_LATENCIES); - if (value < 0) - goto hw_err; - - dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM - current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM - - // Can we support the highest CAS# latency? - - value = - spd_read_byte(dimm_socket_address, - SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - if (value < 0) - goto hw_err; - - // NOTE: At 133 MHz, 1 clock == 7.52 ns - if (value > 0x75) { - // Our bus is too fast for this CAS# latency - // Remove it from the bitmask of those supported by the DIMM that are compatible - dimm_compatible_cas_latencies &= ~current_cas_latency; - } - // Can we support the next-highest CAS# latency (max - 0.5)? - - current_cas_latency >>= 1; - if (current_cas_latency != 0) { - value = - spd_read_byte(dimm_socket_address, - SPD_SDRAM_CYCLE_TIME_2ND); - if (value < 0) - goto hw_err; - if (value > 0x75) - dimm_compatible_cas_latencies &= - ~current_cas_latency; - } - // Can we support the next-highest CAS# latency (max - 1.0)? - current_cas_latency >>= 1; - if (current_cas_latency != 0) { - value = - spd_read_byte(dimm_socket_address, - SPD_SDRAM_CYCLE_TIME_3RD); - if (value < 0) - goto hw_err; - if (value > 0x75) - dimm_compatible_cas_latencies &= - ~current_cas_latency; - } - // Restrict the system to CAS# latencies compatible with this DIMM - system_compatible_cas_latencies &= - dimm_compatible_cas_latencies; - - /* go to the next DIMM */ - } - - /* After all of the arduous calculation setup with the fastest - * cas latency I can use. - */ - - dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); - dram_timing &= ~(DRT_CAS_MASK); - - maybe_dram_read_timing = - pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL); - maybe_dram_read_timing &= 0xF00C; - - if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) { - dram_timing |= DRT_CAS_2_0; - maybe_dram_read_timing |= 0xBB1; - } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) { - - uint32_t dram_row_attributes = - pci_read_config32(PCI_DEV(0, 0, 0), DRA); - - dram_timing |= DRT_CAS_2_5; - - // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly - // different value if all DIMM slots are populated - - if ((dram_row_attributes & 0xff) - && (dram_row_attributes & 0xff00) - && (dram_row_attributes & 0xff0000) - && (dram_row_attributes & 0xff000000)) { - - // All slots populated - maybe_dram_read_timing |= 0x0882; - } else { - // Some unpopulated slots - maybe_dram_read_timing |= 0x0662; - } - } else - die("No CAS# latencies compatible with all DIMMs!!\n"); - - pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); - - /* set master DLL reset */ - dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); - dword |= (1 << 26); - pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); - - dword &= 0x0c0007ff; /* patch try register 88 is undocumented tnz */ - dword |= 0xd2109800; - - pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); - - pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL, - maybe_dram_read_timing); - - dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); /* reset master DLL reset */ - dword &= ~(1 << 26); - pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); - - return; - - hw_err: - die(SPD_ERROR); -} - -/** - * Configure the refresh interval so that we refresh no more often than - * required by the "most needy" DIMM. Also disable ECC if any of the DIMMs - * don't support it. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). - */ -static void configure_e7501_dram_controller_mode(const struct - mem_controller *ctrl, - uint8_t dimm_mask) -{ - int i; - - // Initial settings - uint32_t controller_mode = - pci_read_config32(PCI_DEV(0, 0, 0), DRC); - uint32_t system_refresh_mode = (controller_mode >> 8) & 7; - - // Code below assumes that most aggressive settings are in - // force when we are called, either via E7501 reset defaults - // or by sdram_set_registers(): - // - ECC enabled - // - No refresh - - ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC - ASSERT(!(controller_mode & (7 << 8))); // Refresh - - /* Walk through _all_ dimms and find the least-common denominator for: - * - ECC support - * - refresh rates - */ - - for (i = 0; i < MAX_DIMM_SOCKETS; i++) { - - uint32_t dimm_refresh_mode; - int value; - uint16_t dimm_socket_address; - - if (!(dimm_mask & (1 << i))) { - continue; // This DIMM not usable - } - - if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) - dimm_socket_address = ctrl->channel0[i]; - else - dimm_socket_address = - ctrl->channel1[i - - MAX_DIMM_SOCKETS_PER_CHANNEL]; - - // Disable ECC mode if any one of the DIMMs does not support ECC - // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported. - - value = - spd_read_byte(dimm_socket_address, - SPD_DIMM_CONFIG_TYPE); - die_on_spd_error(value); - if (value != ERROR_SCHEME_ECC) { - controller_mode &= ~(3 << 20); - } - - value = spd_read_byte(dimm_socket_address, SPD_REFRESH); - die_on_spd_error(value); - value &= 0x7f; // Mask off self-refresh bit - if (value > MAX_SPD_REFRESH_RATE) { - print_err("unsupported refresh rate\n"); - continue; - } - // Get the appropriate E7501 refresh mode for this DIMM - dimm_refresh_mode = refresh_rate_map[value]; - if (dimm_refresh_mode > 7) { - print_err("unsupported refresh rate\n"); - continue; - } - // If this DIMM requires more frequent refresh than others, - // update the system setting - if (refresh_frequency[dimm_refresh_mode] > - refresh_frequency[system_refresh_mode]) - system_refresh_mode = dimm_refresh_mode; - -#ifdef SUSPICIOUS_LOOKING_CODE -// SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller -// than the clock period of the memory controller. Also, no other northbridge -// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME. - - // Switch to 2 clocks for address/command if required by any one of the DIMMs - // NOTE: At 133 MHz, 1 clock == 7.52 ns - value = - spd_read_byte(dimm_socket_address, - SPD_CMD_SIGNAL_INPUT_HOLD_TIME); - die_on_spd_error(value); - if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */ - controller_mode &= ~(1 << 16); /* Use two clock cyles instead of one */ - } -#endif - - /* go to the next DIMM */ - } - - controller_mode |= (system_refresh_mode << 8); - - // Configure the E7501 - pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode); -} - -/** - * Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM - * parameters read via SPD. This tells the controller the width of the SDRAM - * chips on each DIMM side (x4 or x8) and the page size of each DIMM side - * (4, 8, 16, or 32 KB). - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). - */ -static void configure_e7501_row_attributes(const struct mem_controller - *ctrl, uint8_t dimm_mask) -{ - int i; - uint32_t row_attributes = 0; - - for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - - uint16_t dimm_socket_address = ctrl->channel0[i]; - struct dimm_size page_size; - struct dimm_size sdram_width; - - if (!(dimm_mask & (1 << i))) - continue; // This DIMM not usable - - // Get the relevant parameters via SPD - page_size = sdram_spd_get_page_size(dimm_socket_address); - sdram_width = sdram_spd_get_width(dimm_socket_address); - - // Update the DRAM Row Attributes. - // Page size is encoded as log2(page size in bits) - log2(8 Kb) - // NOTE: 8 Kb = 2^13 - row_attributes |= (page_size.side1 - 13) << (i << 3); // Side 1 of each DIMM is an EVEN row - - if (sdram_width.side2 > 0) - row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4); // Side 2 is ODD - - // Set x4 flags if appropriate - if (sdram_width.side1 == 4) { - row_attributes |= 0x08 << (i << 3); - } - - if (sdram_width.side2 == 4) { - row_attributes |= 0x08 << ((i << 3) + 4); - } - - /* go to the next DIMM */ - } - - /* Write the new row attributes register */ - pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes); -} - -/* - * Enable clock signals for populated DIMM sockets and disable them for - * unpopulated sockets (to reduce EMI). - * - * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). - */ -static void enable_e7501_clocks(uint8_t dimm_mask) -{ - int i; - uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS); - - for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - - uint8_t socket_mask = 1 << i; - - if (dimm_mask & socket_mask) - clock_disable &= ~socket_mask; // DIMM present, enable clock - else - clock_disable |= socket_mask; // DIMM absent, disable clock - } - - pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable); -} - -/* DIMM-dedependent configuration functions */ - -/** - * DDR Receive FIFO RE-Sync (?) - */ -static void RAM_RESET_DDR_PTR(void) -{ - uint8_t byte; - byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88); - byte |= (1 << 4); - pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte); - - byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88); - byte &= ~(1 << 4); - pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte); -} - -/** - * Set E7501 registers that are either independent of DIMM specifics, or - * establish default settings that will be overridden when we learn the - * specifics. - * - * This sets PCI configuration registers to known good values based on the - * table 'constant_register_values', which are a triple of configuration - * register offset, mask, and bits to set. - */ -static void ram_set_d0f0_regs(void) -{ - int i; - int num_values = ARRAY_SIZE(constant_register_values); - - ASSERT((num_values % 3) == 0); // Bad table? - - for (i = 0; i < num_values; i += 3) { - - uint32_t register_offset = constant_register_values[i]; - uint32_t bits_to_mask = constant_register_values[i + 1]; - uint32_t bits_to_set = constant_register_values[i + 2]; - uint32_t register_value; - - // It's theoretically possible to set values for something other than D0:F0, - // but it's not typically done here - ASSERT(!(register_offset & 0xFFFFFF00)); - - // bits_to_mask and bits_to_set should not reference the same bits - // Again, not strictly an error, but flagged as a potential bug - ASSERT((bits_to_mask & bits_to_set) == 0); - - register_value = - pci_read_config32(PCI_DEV(0, 0, 0), register_offset); - register_value &= bits_to_mask; - register_value |= bits_to_set; - - pci_write_config32(PCI_DEV(0, 0, 0), register_offset, - register_value); - } -} - -/** - * Copy 64 bytes from one location to another. - * - * @param src_addr TODO - * @param dst_addr TODO - */ -static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr) -{ - int i; - for (i = 0; i < 8; i++) { - write32(dst_addr, *src_addr); - src_addr++; - dst_addr += sizeof(uint32_t); - } -} - -/** - * Set the E7501's (undocumented) RCOMP registers. - * - * Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual, - * RCOMP registers appear to affect drive strength, pullup/pulldown offset, - * and slew rate of various signal groups. - * - * Comments below are conjecture based on apparent similarity between the - * E7501 and these two chips. - */ -static void ram_set_rcomp_regs(void) -{ - uint32_t dword; - uint8_t maybe_strength_control; - - RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n"); - - /*enable access to the rcomp bar */ - dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); - dword |= (1 << 22); - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); - - // Set the RCOMP MMIO base address - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO); - - // Block RCOMP updates while we configure the registers - dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); - dword |= (1 << 9); - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - - /* Begin to write the RCOMP registers */ - - // Set CMD and DQ/DQS strength to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88; - maybe_strength_control |= 0x44; - write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control); - - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80); - write16(RCOMP_MMIO + 0x42, 0); - - write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60); - - // NOTE: some factory BIOS set 0x9088 here. Seems to work either way. - write16(RCOMP_MMIO + 0x40, 0); - - // Set RCVEnOut# strength to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8; - maybe_strength_control |= 4; - write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control); - - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0); - write16(RCOMP_MMIO + 0x50, 0); - - // Set CS# strength for x4 SDRAM to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8; - maybe_strength_control |= 4; - write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control); - - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140); - write16(RCOMP_MMIO + 0x48, 0); - - // Set CKE strength for x4 SDRAM to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8; - maybe_strength_control |= 4; - write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control); - - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0); - write16(RCOMP_MMIO + 0x44, 0); - - // Set CK strength for x4 SDRAM to 1x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8; - maybe_strength_control |= 1; - write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control); - - write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180); - write16(RCOMP_MMIO + 0x4c, 0); - - write8(RCOMP_MMIO + 0x2c, 0xff); - - // Set the digital filter length to 8 (?) - dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); - - // NOTE: Some factory BIOS don't do this. - // Doesn't seem to matter either way. - dword &= ~2; - - dword |= 1; - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - - /* Wait 40 usec */ - SLOW_DOWN_IO; - - /* unblock updates */ - dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); - dword &= ~(1 << 9); - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - - // Force a RCOMP measurement cycle? - dword |= (1 << 8); - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - dword &= ~(1 << 8); - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - - /* Wait 40 usec */ - SLOW_DOWN_IO; - - /*disable access to the rcomp bar */ - dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); - dword &= ~(1 << 22); - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); - -} - -/*----------------------------------------------------------------------------- -Public interface: ------------------------------------------------------------------------------*/ - -/** - * Go through the JEDEC initialization sequence for all DIMMs, then enable - * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up - * and running. - * - * @param controllers Not used. - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - */ -static void sdram_enable(int controllers, - const struct mem_controller *ctrl) -{ - uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD); - uint32_t dram_controller_mode; - - if (dimm_mask == 0) - return; - - /* 1 & 2 Power up and start clocks */ - RAM_DEBUG_MESSAGE("Ram Enable 1\n"); - RAM_DEBUG_MESSAGE("Ram Enable 2\n"); - - /* A 200us delay is needed */ - DO_DELAY; EXTRA_DELAY; - - /* 3. Apply NOP */ - RAM_DEBUG_MESSAGE("Ram Enable 3\n"); - do_ram_command(RAM_COMMAND_NOP, 0); - EXTRA_DELAY; - - /* 4 Precharge all */ - RAM_DEBUG_MESSAGE("Ram Enable 4\n"); - do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY; - /* wait until the all banks idle state... */ - - /* 5. Issue EMRS to enable DLL */ - RAM_DEBUG_MESSAGE("Ram Enable 5\n"); - do_ram_command(RAM_COMMAND_EMRS, - SDRAM_EXTMODE_DLL_ENABLE | - SDRAM_EXTMODE_DRIVE_NORMAL); - EXTRA_DELAY; - - /* 6. Reset DLL */ - RAM_DEBUG_MESSAGE("Ram Enable 6\n"); - set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET); - EXTRA_DELAY; - /* Ensure a 200us delay between the DLL reset in step 6 and the final - * mode register set in step 9. - * Infineon needs this before any other command is sent to the ram. - */ - DO_DELAY; EXTRA_DELAY; - - /* 7 Precharge all */ - RAM_DEBUG_MESSAGE("Ram Enable 7\n"); - do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY; - - /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ - RAM_DEBUG_MESSAGE("Ram Enable 8\n"); - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - - /* And for good luck 6 more CBRs */ - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - - /* 9 mode register set */ - RAM_DEBUG_MESSAGE("Ram Enable 9\n"); - set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); - EXTRA_DELAY; - - /* 10 DDR Receive FIFO RE-Sync */ - RAM_DEBUG_MESSAGE("Ram Enable 10\n"); - RAM_RESET_DDR_PTR(); - EXTRA_DELAY; - - /* 11 normal operation */ - RAM_DEBUG_MESSAGE("Ram Enable 11\n"); - do_ram_command(RAM_COMMAND_NORMAL, 0); - EXTRA_DELAY; - - // Reconfigure the row boundaries and Top of Low Memory - // to match the true size of the DIMMs - configure_e7501_ram_addresses(ctrl, dimm_mask); - - /* Finally enable refresh */ - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); - dram_controller_mode |= (1 << 29); - pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); - EXTRA_DELAY; - initialize_ecc(); - - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */ - dram_controller_mode |= (1 << 17); // NOTE: undocumented reserved bit - pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); - - RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n"); - DUMPNORTH(); -} - -/** - * Configure SDRAM controller parameters that depend on characteristics of the - * DIMMs installed in the system. These characteristics are read from the - * DIMMs via the standard Serial Presence Detect (SPD) interface. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - */ -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - uint8_t dimm_mask; - - RAM_DEBUG_MESSAGE("Reading SPD data...\n"); - - dimm_mask = spd_get_supported_dimms(ctrl); - - if (dimm_mask == 0) { - print_debug("No usable memory for this controller\n"); - } else { - enable_e7501_clocks(dimm_mask); - - RAM_DEBUG_MESSAGE("setting based on SPD data...\n"); - - configure_e7501_row_attributes(ctrl, dimm_mask); - configure_e7501_dram_controller_mode(ctrl, dimm_mask); - configure_e7501_cas_latency(ctrl, dimm_mask); - RAM_RESET_DDR_PTR(); - - configure_e7501_dram_timing(ctrl, dimm_mask); - DO_DELAY; - RAM_DEBUG_MESSAGE("done\n"); - } - - /* NOTE: configure_e7501_ram_addresses() is NOT called here. - * We want to keep the default 64 MB/row mapping until sdram_enable() is called, - * even though the default mapping is almost certainly incorrect. - * The default mapping makes it easy to initialize all of the DIMMs - * even if the total system memory is > 4 GB. - * - * Save the dimm_mask for when sdram_enable is called, so it can call - * configure_e7501_ram_addresses() without having to regenerate the bitmask - * of usable DIMMs. - */ - pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask); -} - -/** - * Do basic RAM setup that does NOT depend on serial presence detect - * information (i.e. independent of DIMM specifics). - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. - */ -static void sdram_set_registers(const struct mem_controller *ctrl) -{ - RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); - DUMPNORTH(); - - ram_set_rcomp_regs(); - ram_set_d0f0_regs(); -} diff --git a/src/northbridge/intel/e7501/raminit.h b/src/northbridge/intel/e7501/raminit.h deleted file mode 100644 index 05c3889..0000000 --- a/src/northbridge/intel/e7501/raminit.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef RAMINIT_H -#define RAMINIT_H - -#define MAX_DIMM_SOCKETS_PER_CHANNEL 4 -#define MAX_NUM_CHANNELS 2 -#define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL) - -struct mem_controller { - device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller - - // SMBus addresses of DIMM slots for each channel, - // in order from closest to MCH to furthest away - // 0 == not present - uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL]; - uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; -}; - -void sdram_initialize(int controllers, const struct mem_controller *ctrl); - -#endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/e7501/reset_test.c b/src/northbridge/intel/e7501/reset_test.c deleted file mode 100644 index 1c0dad5..0000000 --- a/src/northbridge/intel/e7501/reset_test.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Convert to C by yhlu */ -#define MCH_DRC 0x7c -#define DRC_DONE (1 << 29) - /* If I have already booted once skip a bunch of initialization */ - /* To see if I have already booted I check to see if memory - * has been enabled. - */ -static int bios_reset_detected(void) { - uint32_t dword; - - dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - - if( (dword & DRC_DONE) != 0 ) { - return 1; - } - - return 0; -} diff --git a/src/southbridge/intel/Kconfig b/src/southbridge/intel/Kconfig index 426ac0b..26c1476 100644 --- a/src/southbridge/intel/Kconfig +++ b/src/southbridge/intel/Kconfig @@ -6,7 +6,6 @@ source src/southbridge/intel/i82801ax/Kconfig source src/southbridge/intel/i82801bx/Kconfig source src/southbridge/intel/i82801cx/Kconfig source src/southbridge/intel/i82801dx/Kconfig -source src/southbridge/intel/i82801ex/Kconfig source src/southbridge/intel/i82801gx/Kconfig source src/southbridge/intel/i82801ix/Kconfig source src/southbridge/intel/i82870/Kconfig diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc index dd20d46..76ea2a4 100644 --- a/src/southbridge/intel/Makefile.inc +++ b/src/southbridge/intel/Makefile.inc @@ -6,7 +6,6 @@ subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801AX) += i82801ax subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801BX) += i82801bx subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CX) += i82801cx subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) += i82801dx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801EX) += i82801ex subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) += i82801ix subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870 diff --git a/src/southbridge/intel/i82801ex/Kconfig b/src/southbridge/intel/i82801ex/Kconfig deleted file mode 100644 index caa5c79..0000000 --- a/src/southbridge/intel/i82801ex/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -config SOUTHBRIDGE_INTEL_I82801EX - bool - select SOUTHBRIDGE_INTEL_COMMON - select IOAPIC - select HAVE_HARD_RESET - select HAVE_USBDEBUG - -if SOUTHBRIDGE_INTEL_I82801EX - -config EHCI_BAR - hex - default 0xfef00000 - -endif diff --git a/src/southbridge/intel/i82801ex/Makefile.inc b/src/southbridge/intel/i82801ex/Makefile.inc deleted file mode 100644 index fb76a98..0000000 --- a/src/southbridge/intel/i82801ex/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -ramstage-y += i82801ex.c -ramstage-y += uhci.c -ramstage-y += lpc.c -ramstage-y += ide.c -ramstage-y += sata.c -ramstage-y += ehci.c -ramstage-y += smbus.c -ramstage-y += pci.c -ramstage-y += ac97.c -ramstage-y += watchdog.c -ramstage-y += reset.c diff --git a/src/southbridge/intel/i82801ex/ac97.c b/src/southbridge/intel/i82801ex/ac97.c deleted file mode 100644 index 08efe15..0000000 --- a/src/southbridge/intel/i82801ex/ac97.c +++ /dev/null @@ -1,37 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i82801ex.h" - -static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = ac97_set_subsystem, -}; -static struct device_operations ac97_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ac97_audio_driver __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_AC97_AUDIO, -}; -static const struct pci_driver ac97_modem_driver __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_AC97_MODEM, -}; diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h deleted file mode 100644 index 291fcd7..0000000 --- a/src/southbridge/intel/i82801ex/chip.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef I82801EX_CHIP_H -#define I82801EX_CHIP_H - -struct southbridge_intel_i82801ex_config -{ - -#define ICH5R_GPIO_USE_MASK 0x03 -#define ICH5R_GPIO_USE_DEFAULT 0x00 -#define ICH5R_GPIO_USE_AS_NATIVE 0x01 -#define ICH5R_GPIO_USE_AS_GPIO 0x02 - -#define ICH5R_GPIO_SEL_MASK 0x0c -#define ICH5R_GPIO_SEL_DEFAULT 0x00 -#define ICH5R_GPIO_SEL_OUTPUT 0x04 -#define ICH5R_GPIO_SEL_INPUT 0x08 - -#define ICH5R_GPIO_LVL_MASK 0x30 -#define ICH5R_GPIO_LVL_DEFAULT 0x00 -#define ICH5R_GPIO_LVL_LOW 0x10 -#define ICH5R_GPIO_LVL_HIGH 0x20 -#define ICH5R_GPIO_LVL_BLINK 0x30 - -#define ICH5R_GPIO_INV_MASK 0xc0 -#define ICH5R_GPIO_INV_DEFAULT 0x00 -#define ICH5R_GPIO_INV_OFF 0x40 -#define ICH5R_GPIO_INV_ON 0x80 - - /* GPIO use select */ - unsigned char gpio[64]; - unsigned int pirq_a_d; - unsigned int pirq_e_h; -}; - -#endif /* I82801EX_CHIP_H */ diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c deleted file mode 100644 index cdf1f62..0000000 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ /dev/null @@ -1,130 +0,0 @@ -#include "smbus.h" - -#define SMBUS_IO_BASE 0x0f00 - -static void enable_smbus(void) -{ - device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - print_spew("SMBus controller enabled\n"); - - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - print_debug_hex32(pci_read_config32(dev, 0x20)); - /* Set smbus enable */ - pci_write_config8(dev, 0x40, 1); - /* Set smbus iospace enable */ - pci_write_config8(dev, 0x4, 1); - /* SMBALERT_DIS */ - pci_write_config8(dev, 0x11, 4); - - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); -} - -static int smbus_read_byte(unsigned device, unsigned address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -#ifdef UNUSED_CODE -static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) -{ - if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { - return; - } - - print_debug("Unimplemented smbus_write_byte() called.\n"); - -#if 0 - /* setup transaction */ - /* disable interrupts */ - outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), - SMBUS_IO_BASE + SMBGCTL); - /* set the device I'm talking too */ - outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR); - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data write */ /* FIXME */ - outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x1), SMBUS_IO_BASE + SMBGCTL); - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); - - /* clear the data word...*/ - outw(val, SMBUS_IO_BASE + SMBHSTDAT); - - /* start the command */ - outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(SMBUS_IO_BASE); -#endif - return; -} - -static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, - unsigned data1, unsigned data2) -{ - unsigned char byte; - unsigned char stat; - int i; - - /* chear the PM timeout flags, SECOND_TO_STS */ - outw(inw(0x0400 + 0x66), 0x0400 + 0x66); - - if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { - return -2; - } - - /* setup transaction */ - /* Obtain ownership */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - for(stat=0;(stat&0x40)==0;) { - stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } - /* clear the done bit */ - outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); - - /* set the command address */ - outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - - /* set the block length */ - outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0); - - /* try sending out the first byte of data here */ - byte=(data1>>(0))&0x0ff; - outb(byte,SMBUS_IO_BASE + SMBBLKDAT); - /* issue a block write command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, - SMBUS_IO_BASE + SMBHSTCTL); - - for(i=0;i<length;i++) { - - /* poll for transaction completion */ - if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { - return -3; - } - - /* load the next byte */ - if(i>3) - byte=(data2>>(i%4))&0x0ff; - else - byte=(data1>>(i))&0x0ff; - outb(byte,SMBUS_IO_BASE + SMBBLKDAT); - - /* clear the done bit */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), - SMBUS_IO_BASE + SMBHSTSTAT); - } - - print_debug("SMBUS Block complete\n"); - return 0; -} -#endif diff --git a/src/southbridge/intel/i82801ex/ehci.c b/src/southbridge/intel/i82801ex/ehci.c deleted file mode 100644 index 28164c5..0000000 --- a/src/southbridge/intel/i82801ex/ehci.c +++ /dev/null @@ -1,51 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/pci_ehci.h> -#include "i82801ex.h" - -static void ehci_init(struct device *dev) -{ - uint32_t cmd; - - printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_MASTER); - - printk(BIOS_DEBUG, "done.\n"); -} - -static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - uint8_t access_cntl; - access_cntl = pci_read_config8(dev, 0x80); - /* Enable writes to protected registers */ - pci_write_config8(dev, 0x80, access_cntl | 1); - /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - /* Restore protection */ - pci_write_config8(dev, 0x80, access_cntl); -} - -static struct pci_operations lops_pci = { - .set_subsystem = &ehci_set_subsystem, -}; -static struct device_operations ehci_ops = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ehci_init, - .scan_bus = 0, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ehci_driver __pci_driver = { - .ops = &ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_EHCI, -}; diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c deleted file mode 100644 index fc41645..0000000 --- a/src/southbridge/intel/i82801ex/i82801ex.c +++ /dev/null @@ -1,48 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "i82801ex.h" - -void i82801ex_enable(device_t dev) -{ - device_t lpc_dev; - unsigned index = 0; - uint16_t reg_old, reg; - - /* See if we are behind the i82801ex pci bridge */ - lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0)); - if((dev->path.pci.devfn &0xf8)== 0xf8) { - index = dev->path.pci.devfn & 7; - } - else if((dev->path.pci.devfn &0xf8)== 0xe8) { - index = (dev->path.pci.devfn & 7) +8; - } - if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) { - return; - } - if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) || - (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_LPC)) { - uint32_t id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_INTEL | - (PCI_DEVICE_ID_INTEL_82801ER_LPC << 16))) { - return; - } - } - - reg = reg_old = pci_read_config16(lpc_dev, 0xf2); - reg &= ~(1 << index); - if (!dev->enabled) { - reg |= (1 << index); - } - if (reg != reg_old) { - pci_write_config16(lpc_dev, 0xf2, reg); - } - -} - -struct chip_operations southbridge_intel_i82801ex_ops = { - CHIP_NAME("Intel ICH5 (82801Ex) Series Southbridge") - .enable_dev = i82801ex_enable, -}; diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h deleted file mode 100644 index 3c7321a..0000000 --- a/src/southbridge/intel/i82801ex/i82801ex.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef I82801EX_H -#define I82801EX_H - -#include "chip.h" - -extern void i82801ex_enable(device_t dev); - -#define PCI_DMA_CFG 0x90 -#define SERIRQ_CNTL 0x64 -#define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 -#define RTC_CONF 0xd8 -#define GEN_PMCON_3 0xa4 - -#define PMBASE 0x40 -#define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 4) -#define GPIO_BASE 0x58 -#define GPIO_CNTL 0x5C -#define GPIO_EN (1 << 4) - -#endif /* I82801EX_H */ diff --git a/src/southbridge/intel/i82801ex/ide.c b/src/southbridge/intel/i82801ex/ide.c deleted file mode 100644 index 542c594..0000000 --- a/src/southbridge/intel/i82801ex/ide.c +++ /dev/null @@ -1,42 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i82801ex.h" - -static void ide_init(struct device *dev) -{ - /* Enable IDE devices and timmings */ - pci_write_config16(dev, 0x40, 0x0a307); // IDE0 - pci_write_config16(dev, 0x42, 0x0a307); // IDE1 - pci_write_config8(dev, 0x48, 0x05); - pci_write_config16(dev, 0x4a, 0x0101); - pci_write_config16(dev, 0x54, 0x5055); - printk(BIOS_DEBUG, "IDE Enabled\n"); -} - -static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - /* This value is also visible in uchi[0-2] and smbus functions */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = i82801ex_ide_set_subsystem, -}; -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_IDE, -}; diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c deleted file mode 100644 index 1823e65..0000000 --- a/src/southbridge/intel/i82801ex/lpc.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * (C) 2004 Linux Networx - */ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> -#include <pc80/isa-dma.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include "i82801ex.h" - - -#define NMI_OFF 0 -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - -/** - * Enable ACPI I/O range. - * - * @param dev PCI device with ACPI and PM BAR's - */ -static void i82801ex_enable_acpi(struct device *dev) -{ - u8 gpio_cntl; - - /* Enable ACPI I/O range decode and ACPI power management. */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - - /* Enable the GPIO bar */ - gpio_cntl = pci_read_config8(dev, GPIO_CNTL); - gpio_cntl |= GPIO_EN; - pci_write_config8(dev, GPIO_CNTL, gpio_cntl); -} - -/** - * Set miscellanous static southbridge features. - * - * @param dev PCI device with I/O APIC configuration registers - */ -static void i82801ex_general_cntl(struct device *dev) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ - reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ - pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); - - reg32 = pci_read_config32(dev, GEN_STS); - reg32 |= (1<<1); - pci_write_config32(dev, GEN_STS, reg32); - -} - -#define SERIRQ_CNTL 0x64 -static void i82801ex_enable_serial_irqs(device_t dev) -{ - /* set packet length and toggle silent mode bit */ - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0)); -} - -#define PCI_DMA_CFG 0x90 -static void i82801ex_pci_dma_cfg(device_t dev) -{ - /* Set PCI DMA CFG to lpc I/F DMA */ - pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); -} - -#define LPC_EN 0xe6 -static void i82801ex_enable_lpc(device_t dev) -{ - /* lpc i/f enable */ - pci_write_config8(dev, LPC_EN, 0x0d); -} - -typedef struct southbridge_intel_i82801ex_config config_t; - -static void set_i82801ex_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) -{ - uint32_t gpio_use_sel, gpio_use_sel2; - int i; - - gpio_use_sel = 0x1A003180; - gpio_use_sel2 = 0x00000007; - for(i = 0; i < 64; i++) { - int val; - switch(config->gpio[i] & ICH5R_GPIO_USE_MASK) { - case ICH5R_GPIO_USE_AS_NATIVE: val = 0; break; - case ICH5R_GPIO_USE_AS_GPIO: val = 1; break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_use_sel &= ~( 1 << i); - gpio_use_sel |= (val << i); - } else { - gpio_use_sel2 &= ~( 1 << (i - 32)); - gpio_use_sel2 |= (val << (i - 32)); - } - } - outl(gpio_use_sel, res->base + 0x00); - outl(gpio_use_sel2, res->base + 0x30); -} - -static void set_i82801ex_gpio_direction( - device_t dev, struct resource *res, config_t *config) -{ - uint32_t gpio_io_sel, gpio_io_sel2; - int i; - - gpio_io_sel = 0x0000ffff; - gpio_io_sel2 = 0x00000300; - for(i = 0; i < 64; i++) { - int val; - switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) { - case ICH5R_GPIO_SEL_OUTPUT: val = 0; break; - case ICH5R_GPIO_SEL_INPUT: val = 1; break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_io_sel &= ~( 1 << i); - gpio_io_sel |= (val << i); - } else { - gpio_io_sel2 &= ~( 1 << (i - 32)); - gpio_io_sel2 |= (val << (i - 32)); - } - } - outl(gpio_io_sel, res->base + 0x04); - outl(gpio_io_sel2, res->base + 0x34); -} - -static void set_i82801ex_gpio_level( - device_t dev, struct resource *res, config_t *config) -{ - uint32_t gpio_lvl, gpio_lvl2; - uint32_t gpio_blink; - int i; - - gpio_lvl = 0x1b3f0000; - gpio_blink = 0x00040000; - gpio_lvl2 = 0x00030207; - for(i = 0; i < 64; i++) { - int val, blink; - switch(config->gpio[i] & ICH5R_GPIO_LVL_MASK) { - case ICH5R_GPIO_LVL_LOW: val = 0; blink = 0; break; - case ICH5R_GPIO_LVL_HIGH: val = 1; blink = 0; break; - case ICH5R_GPIO_LVL_BLINK: val = 1; blink = 1; break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_lvl &= ~( 1 << i); - gpio_blink &= ~( 1 << i); - gpio_lvl |= ( val << i); - gpio_blink |= (blink << i); - } else { - gpio_lvl2 &= ~( 1 << (i - 32)); - gpio_lvl2 |= (val << (i - 32)); - } - } - outl(gpio_lvl, res->base + 0x0c); - outl(gpio_blink, res->base + 0x18); - outl(gpio_lvl2, res->base + 0x38); -} - -static void set_i82801ex_gpio_inv( - device_t dev, struct resource *res, config_t *config) -{ - uint32_t gpio_inv; - int i; - - gpio_inv = 0x00000000; - for(i = 0; i < 32; i++) { - int val; - switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) { - case ICH5R_GPIO_INV_OFF: val = 0; break; - case ICH5R_GPIO_INV_ON: val = 1; break; - default: - continue; - } - gpio_inv &= ~( 1 << i); - gpio_inv |= (val << i); - } - outl(gpio_inv, res->base + 0x2c); -} - -static void i82801ex_pirq_init(device_t dev) -{ - config_t *config; - - /* Get the chip configuration */ - config = dev->chip_info; - - if(config->pirq_a_d) { - pci_write_config32(dev, 0x60, config->pirq_a_d); - } - if(config->pirq_e_h) { - pci_write_config32(dev, 0x68, config->pirq_e_h); - } -} - - -static void i82801ex_gpio_init(device_t dev) -{ - struct resource *res; - config_t *config; - - /* Skip if I don't have any configuration */ - if (!dev->chip_info) { - return; - } - /* The programmer is responsible for ensuring - * a valid gpio configuration. - */ - - /* Get the chip configuration */ - config = dev->chip_info; - /* Find the GPIO bar */ - res = find_resource(dev, GPIO_BASE); - if (!res) { - return; - } - - /* Set the use selects */ - set_i82801ex_gpio_use_sel(dev, res, config); - - /* Set the IO direction */ - set_i82801ex_gpio_direction(dev, res, config); - - /* Setup the input inverters */ - set_i82801ex_gpio_inv(dev, res, config); - - /* Set the value on the GPIO output pins */ - set_i82801ex_gpio_level(dev, res, config); - -} - -static void enable_hpet(struct device *dev) -{ - const unsigned long hpet_address = 0xfed00000; - - uint32_t dword; - uint32_t code = (0 & 0x3); - - dword = pci_read_config32(dev, GEN_CNTL); - dword |= (1 << 17); /* enable hpet */ - - /* Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh - */ - - dword &= ~(3 << 15); /* clear it */ - dword |= (code<<15); - pci_write_config32(dev, GEN_CNTL, dword); - - printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) ); -} - -static void lpc_init(struct device *dev) -{ - uint8_t byte; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - - i82801ex_general_cntl(dev); - - /* IO APIC initialization. */ - setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID. - - i82801ex_enable_serial_irqs(dev); - - i82801ex_pci_dma_cfg(dev); - - i82801ex_enable_lpc(dev); - - /* Clear SATA to non raid */ - pci_write_config8(dev, 0xae, 0x00); - - get_option(&pwr_on, "power_on_after_fail"); - byte = pci_read_config8(dev, 0xa4); - byte &= 0xfe; - if (!pwr_on) { - byte |= 1; - } - pci_write_config8(dev, 0xa4, byte); - printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off"); - - /* Set up the PIRQ */ - i82801ex_pirq_init(dev); - - /* Set the state of the gpio lines */ - i82801ex_gpio_init(dev); - - /* Initialize the real time clock */ - cmos_init(0); - - /* Initialize isa dma */ - isa_dma_init(); - - /* Disable IDE (needed when sata is enabled) */ - pci_write_config8(dev, 0xf2, 0x60); - - enable_hpet(dev); -} - -static void i82801ex_lpc_read_resources(device_t dev) -{ - struct resource *res; - - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add the ACPI BAR */ - res = pci_get_resource(dev, PMBASE); - - /* Add the GPIO BAR */ - res = pci_get_resource(dev, GPIO_BASE); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void i82801ex_lpc_enable_resources(device_t dev) -{ - /* Enable the normal PCI resources. */ - pci_dev_enable_resources(dev); - - /* Enable ACPI and GPIO BARs. */ - i82801ex_enable_acpi(dev); -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations lpc_ops = { - .read_resources = i82801ex_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = i82801ex_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_LPC, -}; diff --git a/src/southbridge/intel/i82801ex/pci.c b/src/southbridge/intel/i82801ex/pci.c deleted file mode 100644 index f1c8183..0000000 --- a/src/southbridge/intel/i82801ex/pci.c +++ /dev/null @@ -1,44 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i82801ex.h" - -static void pci_init(struct device *dev) -{ - uint16_t word; - - /* Clear system errors */ - word = pci_read_config16(dev, 0x06); - word |= 0xf900; /* Clear possible errors */ - pci_write_config16(dev, 0x06, word); - -#if 0 - /* System error enable */ - uint32_t dword; - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* SERR# Enable */ - dword |= (1<<6); /* Parity Error Response */ - pci_write_config32(dev, 0x04, dword); -#endif - - word = pci_read_config16(dev, 0x1e); - word |= 0xf800; /* Clear possible errors */ - pci_write_config16(dev, 0x1e, word); -} - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_PCI, -}; diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c deleted file mode 100644 index 9936892..0000000 --- a/src/southbridge/intel/i82801ex/reset.c +++ /dev/null @@ -1,8 +0,0 @@ -#include <arch/io.h> -#include <reset.h> - -void hard_reset(void) -{ - /* Try rebooting through port 0xcf9 */ - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); -} diff --git a/src/southbridge/intel/i82801ex/sata.c b/src/southbridge/intel/i82801ex/sata.c deleted file mode 100644 index b3d8f37..0000000 --- a/src/southbridge/intel/i82801ex/sata.c +++ /dev/null @@ -1,59 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i82801ex.h" - -static void sata_init(struct device *dev) -{ - printk(BIOS_DEBUG, "SATA init\n"); - /* SATA configuration */ - pci_write_config8(dev, 0x04, 0x07); - pci_write_config8(dev, 0x09, 0x8f); - - /* Set timmings */ - pci_write_config16(dev, 0x40, 0x0a307); - pci_write_config16(dev, 0x42, 0x0a307); - - /* Sync DMA */ - pci_write_config16(dev, 0x48, 0x000f); - pci_write_config16(dev, 0x4a, 0x1111); - - /* 66 mhz */ - pci_write_config16(dev, 0x54, 0xf00f); - - /* Combine ide - sata configuration */ - pci_write_config8(dev, 0x90, 0x0); - - /* port 0 & 1 enable */ - pci_write_config8(dev, 0x92, 0x33); - - /* initialize SATA */ - pci_write_config16(dev, 0xa0, 0x0018); - pci_write_config32(dev, 0xa4, 0x00000264); - pci_write_config16(dev, 0xa0, 0x0040); - pci_write_config32(dev, 0xa4, 0x00220043); - -} - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static const struct pci_driver sata_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_SATA, -}; - -static const struct pci_driver sata_driver_nr __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801EB_SATA, -}; diff --git a/src/southbridge/intel/i82801ex/smbus.c b/src/southbridge/intel/i82801ex/smbus.c deleted file mode 100644 index fe49e11..0000000 --- a/src/southbridge/intel/i82801ex/smbus.c +++ /dev/null @@ -1,48 +0,0 @@ -#include <device/device.h> -#include <device/path.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/smbus.h> -#include <arch/io.h> -#include "i82801ex.h" -#include "smbus.h" - -static int lsmbus_read_byte(device_t dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); - - return do_smbus_read_byte(res->base, device, address); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, -}; - -static struct pci_operations lops_pci = { - /* The subsystem id follows the ide controller */ - .set_subsystem = 0, -}; - -static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_SMB, -}; diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h deleted file mode 100644 index b166797..0000000 --- a/src/southbridge/intel/i82801ex/smbus.h +++ /dev/null @@ -1,104 +0,0 @@ -#include <device/smbus_def.h> - -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -#define SMBUS_TIMEOUT (100*1000*10) - - -static void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); - } while(byte & 1); - return loops?0:-1; -} - -static int smbus_wait_until_done(unsigned smbus_io_base) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); - } while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0); - return loops?0:-1; -} - -static inline int smbus_wait_until_blk_done(unsigned smbus_io_base) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); - } while((byte&(1<<7)) == 0); - return loops?0:-1; -} - -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) -{ - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - /* setup transaction */ - /* disable interrupts */ - outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); - /* set the command/address... */ - outb(address & 0xFF, smbus_io_base + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL); - /* clear any lingering errors, so the transaction will run */ - outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, smbus_io_base + SMBHSTDAT0); - - /* start the command */ - outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inb(smbus_io_base + SMBHSTSTAT); - - /* Ignore the In Use Status... */ - global_status_register &= ~(3 << 5); - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - if (global_status_register != (1 << 1)) { - return SMBUS_ERROR; - } - return byte; -} diff --git a/src/southbridge/intel/i82801ex/uhci.c b/src/southbridge/intel/i82801ex/uhci.c deleted file mode 100644 index c9cf82e..0000000 --- a/src/southbridge/intel/i82801ex/uhci.c +++ /dev/null @@ -1,55 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i82801ex.h" - -static void uhci_init(struct device *dev) -{ - uint32_t cmd; - -#if 1 - printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); - cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_MASTER); - - - printk(BIOS_DEBUG, "done.\n"); -#endif - -} - -static struct pci_operations lops_pci = { - /* The subsystem id follows the ide controller */ - .set_subsystem = 0, -}; - -static struct device_operations uhci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = uhci_init, - .scan_bus = 0, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver uhci_driver __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_USB1, -}; - -static const struct pci_driver usb2_driver __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_USB2, -}; - -static const struct pci_driver usb3_driver __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801ER_USB3, -}; diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c deleted file mode 100644 index 28e1f5e..0000000 --- a/src/southbridge/intel/i82801ex/watchdog.c +++ /dev/null @@ -1,28 +0,0 @@ -#include <console/console.h> -#include <watchdog.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> - -void watchdog_off(void) -{ - device_t dev; - unsigned long value,base; - - /* turn off the ICH5 watchdog */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); - /* Enable I/O space */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - /* Get TCO base */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; - /* Disable the watchdog timer */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - /* Clear TCO timeout status */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); -}

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New patch to review for coreboot: 45457eb northbridge/amd: Allow mainboards to set maximum HT link frequency
by Timothy Pearson 10 Feb '15

10 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8405 -gerrit commit 45457eb5d0a89466b46da2e9e64b61ad510f6f43 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 10 13:13:39 2015 -0600 northbridge/amd: Allow mainboards to set maximum HT link frequency Most mainboards are designed to a maximum HT frequency specification. Coreboot supports CPUs that were released after mainboard production; these CPUs may support and autodetect HT link frequencies beyond the mainboard design capabilities. This patch allows mainboards to set an HT frequency limit if needed. Change-Id: If7ff40dccb4c22829062511ca0046aa2caf15580 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/Kconfig | 80 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 78 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index 17f15c3..2a178ca 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -6,13 +6,89 @@ source src/northbridge/amd/agesa/Kconfig source src/northbridge/amd/cimx/Kconfig source src/northbridge/amd/pi/Kconfig +config FORCE_LIMIT_HT_SPEED_200 + bool + default n + +config FORCE_LIMIT_HT_SPEED_300 + bool + default n + +config FORCE_LIMIT_HT_SPEED_400 + bool + default n + +config FORCE_LIMIT_HT_SPEED_500 + bool + default n + +config FORCE_LIMIT_HT_SPEED_600 + bool + default n + +config FORCE_LIMIT_HT_SPEED_800 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1000 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1200 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1400 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1600 + bool + default n + +config FORCE_LIMIT_HT_SPEED_1800 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2000 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2200 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2400 + bool + default n + +config FORCE_LIMIT_HT_SPEED_2600 + bool + default n + menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) - depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT + depends on (NORTHBRIDGE_AMD_AMDFAM10) + # visible if EXPERT choice prompt "HyperTransport frequency" - default LIMIT_HT_SPEED_AUTO + default LIMIT_HT_SPEED_AUTO if (!FORCE_LIMIT_HT_SPEED_200 && !FORCE_LIMIT_HT_SPEED_300 && !FORCE_LIMIT_HT_SPEED_400 && !FORCE_LIMIT_HT_SPEED_500 && !FORCE_LIMIT_HT_SPEED_600 && !FORCE_LIMIT_HT_SPEED_800 && !FORCE_LIMIT_HT_SPEED_1000 && !FORCE_LIMIT_HT_SPEED_1200 && !FORCE_LIMIT_HT_SPEED_1400 && !FORCE_LIMIT_HT_SPEED_1600 && !FORCE_LIMIT_HT_SPEED_1800 && !FORCE_LIMIT_HT_SPEED_2000 && !FORCE_LIMIT_HT_SPEED_2200 && !FORCE_LIMIT_HT_SPEED_2400 && !FORCE_LIMIT_HT_SPEED_2600) + default LIMIT_HT_SPEED_200 if FORCE_LIMIT_HT_SPEED_200 + default LIMIT_HT_SPEED_300 if FORCE_LIMIT_HT_SPEED_300 + default LIMIT_HT_SPEED_400 if FORCE_LIMIT_HT_SPEED_400 + default LIMIT_HT_SPEED_500 if FORCE_LIMIT_HT_SPEED_500 + default LIMIT_HT_SPEED_600 if FORCE_LIMIT_HT_SPEED_600 + default LIMIT_HT_SPEED_800 if FORCE_LIMIT_HT_SPEED_800 + default LIMIT_HT_SPEED_1000 if FORCE_LIMIT_HT_SPEED_1000 + default LIMIT_HT_SPEED_1200 if FORCE_LIMIT_HT_SPEED_1200 + default LIMIT_HT_SPEED_1400 if FORCE_LIMIT_HT_SPEED_1400 + default LIMIT_HT_SPEED_1600 if FORCE_LIMIT_HT_SPEED_1600 + default LIMIT_HT_SPEED_1800 if FORCE_LIMIT_HT_SPEED_1800 + default LIMIT_HT_SPEED_2000 if FORCE_LIMIT_HT_SPEED_2000 + default LIMIT_HT_SPEED_2200 if FORCE_LIMIT_HT_SPEED_2200 + default LIMIT_HT_SPEED_2400 if FORCE_LIMIT_HT_SPEED_2400 + default LIMIT_HT_SPEED_2600 if FORCE_LIMIT_HT_SPEED_2600 help This option sets the maximum permissible HyperTransport link frequency.

1 0

New patch to review for coreboot: 8541d21 drivers/intel/i210: Add new driver for Intel i210 MACPHY
by Werner Zeh 10 Feb '15

10 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8404 -gerrit commit 8541d21cc33dc1fd84242c37ec5f4ec3a2647a2b Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 15:09:00 2015 +0100 drivers/intel/i210: Add new driver for Intel i210 MACPHY Add a new driver for Intel i210 MACPHY with the goal to update the MAC address in i210 if it is found during PCI scan. Change-Id: I4d4e797543a9f278fb649596f63ae8e1f285b3c3 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/intel/Makefile.inc | 1 + src/drivers/intel/i210/Makefile.inc | 1 + src/drivers/intel/i210/i210.c | 238 ++++++++++++++++++++++++++++++++++++ src/drivers/intel/i210/i210.h | 58 +++++++++ 4 files changed, 298 insertions(+) diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc index 7bc6dd5..f12511c 100644 --- a/src/drivers/intel/Makefile.inc +++ b/src/drivers/intel/Makefile.inc @@ -1,3 +1,4 @@ subdirs-y += gma subdirs-y += wifi subdirs-$(CONFIG_PLATFORM_USES_FSP) += fsp +subdirs-y += i210 diff --git a/src/drivers/intel/i210/Makefile.inc b/src/drivers/intel/i210/Makefile.inc new file mode 100644 index 0000000..a1f15de --- /dev/null +++ b/src/drivers/intel/i210/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += i210.c \ No newline at end of file diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c new file mode 100644 index 0000000..5094999 --- /dev/null +++ b/src/drivers/intel/i210/i210.c @@ -0,0 +1,238 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "i210.h" +#include <device/device.h> +#include <console/console.h> +#include <string.h> + +/* We need one function we can call to get a MAC-address to use*/ +/* This function can be coded somewhere else but must exist.*/ +extern u8* get_mac_address(u32 pci_bdf); + +/* This is a private function to wait for a bit mask in a given register*/ +/* To avoid endless loops, a timeout is implemented here.*/ +static int i210_wait_done(u32* reg, u32 mask) +{ + u32 timeout = I210_POLL_TIMEOUT; + do { + if (!(*reg & mask)) { + udelay(1); + timeout--; + } + } while((!(*reg & mask)) && timeout); + return timeout ? I210_NO_ERROR:I210_NOT_READY; +} + +/** \brief This function is the driver entry point for the init phase + * of the PCI bus allocator. It will program a MAC-address + * into the MACPHY. + * @param *dev Pointer to the used PCI device + * @return void Nothing is given back + */ +void i210_init(struct device *dev) +{ + u8 cur_adr[6]; + u8 *adr_to_set; + + /*Check first whether there is a valid MAC address available*/ + adr_to_set=get_mac_address((dev->bus->subordinate <<8)|dev->path.pci.devfn); + if (adr_to_set == NULL) { + printk(BIOS_ERR, "I210: No valid MAC-Address found\n"); + return; + } + /* Before we will write a new address, check the existing one*/ + if (i210_read_mac_adr(dev, cur_adr)) { + printk(BIOS_ERR, "I210: Not able to read current MAC-Address.\n"); + return; + } + if (memcmp(cur_adr, adr_to_set, 6)) { + if (i210_write_mac_adr(dev, adr_to_set)) { + printk(BIOS_ERR, "I210: Error while setting MAC-Address\n"); + } else { + printk(BIOS_INFO, "I210: MAC-Address successfully changed.\n"); + } + } else { + printk(BIOS_INFO, "I210: MAC-Address is up to date, nothing to do.\n"); + } + return; +} + +/** \brief This function can read the MAC-address out of the MACPHY + * @param *dev Pointer to the PCI device of this MACPHY + * @param *MACAdr Pointer to the buffer where to store read MAC-address + * @return void I210_NO_ERROR or an error code + */ +u32 i210_read_mac_adr(struct device *dev, u8 *MACAdr) +{ + u16 adr[3]; + if (!dev || !MACAdr) + return I210_INVALID_PARAM; + if (i210_read_flash(dev, 0, 3, adr)) + return I210_READ_ERROR; + /* Copy the address into destination. This is done because of possible*/ + /* not matching alignment for destination to u16 boundary*/ + memcpy(MACAdr, (u8*)adr, 6); + return I210_NO_ERROR; +} + +/** \brief This function can write the MAC-address to the MACPHY + * @param *dev Pointer to the PCI device of this MACPHY + * @param *MACAdr Pointer to the buffer where the desired MAC-address is + * @return void I210_NO_ERROR or an error code + */ +u32 i210_write_mac_adr(struct device *dev, u8 *MACAdr) +{ + u16 adr[3]; + if (!dev || !MACAdr) + return I210_INVALID_PARAM; + /* Copy desired address into a local buffer to avoid alignment issues*/ + memcpy((u8*)adr, MACAdr, 6); + return i210_write_flash(dev, 0, 3, adr); +} + +/** \brief This function can read the configuration space of the MACPHY + * For this purpose, the EEPROM interface is used. No direct access + * to the flash memory will be done. + * @param *dev Pointer to the PCI device of this MACPHY + * @param address Address inside the flash where reading will start + * @param count Number of words (16 bit values) to read + * @param *buffer Pointer to the buffer where to store read data + * @return void I210_NO_ERROR or an error code + */ +u32 i210_read_flash(struct device *dev, u32 address, u32 count, u16 *buffer) +{ + u32 bar; + u32 *eeprd; + u32 i; + + /* Get the BAR to memory mapped space*/ + bar = pci_read_config32(dev, 0x10); + if ((!bar) || ((address + count) > 0x40)) + return I210_INVALID_PARAM; + eeprd = (u32*)(bar + I210_REG_EEREAD); + /*Prior to start, ensure flash interface is ready by checking DONE-bit*/ + if (i210_wait_done(eeprd, I210_DONE)) + return I210_NOT_READY; + + /*OK, interface is ready, we can use it now*/ + for (i = 0; i < count; i++) { + /* To start a read cycle, write desired address in bits 12..2*/ + *eeprd = ((address + i) << 2) & 0x1FFC; + /* Wait until read is done and check for timeout*/ + if (i210_wait_done(eeprd, I210_DONE)) + return I210_READ_ERROR; + /* Here, we can read back desired word in bits 31..16*/ + buffer[i] = (*eeprd & 0xffff0000) >> 16; + } + return I210_NO_ERROR; +} + +/** \brief This function can write the configuration space of the MACPHY + * For this purpose, the EEPROM interface is used. No direct access + * to the flash memory will be done. This function will update + * the checksum after a value was changed. + * @param *dev Pointer to the PCI device of this MACPHY + * @param address Address inside the flash where writing will start + * @param count Number of words (16 bit values) to write + * @param *buffer Pointer to the buffer where data to write is stored in + * @return void I210_NO_ERROR or an error code + */ +u32 i210_write_flash(struct device *dev, u32 address, u32 count, u16 *buffer) +{ + u32 bar; + u32 *eepwr; + u32 *eectrl; + u16 checksum; + u32 i; + + /* Get the BAR to memory mapped space*/ + bar = pci_read_config32(dev, 0x10); + if ((!bar) || ((address + count) > 0x40)) + return I210_INVALID_PARAM; + eepwr = (u32*)(bar + I210_REG_EEWRITE); + eectrl = (u32*)(bar + I210_REG_EECTRL); + /* Prior to start, ensure flash interface is ready by checking DONE-bit*/ + if (i210_wait_done(eepwr, I210_DONE)) + return I210_NOT_READY; + + /* OK, interface is ready, we can use it now*/ + for (i = 0; i < count; i++) { + /* To start a write cycle, write desired address in bits 12..2*/ + /* and data to write in bits 31..16 into EEWRITE-register*/ + *eepwr = ((((address + i) << 2) & 0x1FFC) | (buffer[i] << 16)); + /* Wait until write is done and check for timeout*/ + if (i210_wait_done(eepwr, I210_DONE)) + return I210_WRITE_ERROR; + } + /* Since we have modified data, we need to update the checksum*/ + if (i210_compute_checksum(dev, &checksum)) + return I210_CHECKSUM_ERROR; + *eepwr = (0x3f << 2) | checksum << 16; + if (i210_wait_done(eepwr, I210_DONE)) + return I210_WRITE_ERROR; + /* Up to now, desired data was written into shadowed RAM. We now need*/ + /* to perform a flash cycle to bring the shadowed RAM into flash memory*/ + /* To start a flash cycle, we need to set FLUPD-bit and wait for FLDONE*/ + *eectrl = *eectrl | I210_FLUPD; + if (i210_wait_done(eectrl, I210_FLUDONE)) + return I210_FLASH_UPDATE_ERROR; + else + return I210_NO_ERROR; +} + +/** \brief This function computes the checksum for the configuration space. + * The address range for the checksum is 0x00..0x3e. + * @param *dev Pointer to the PCI device of this MACPHY + * @param *checksum Pointer to the buffer where to store the checksum + * @return void I210_NO_ERROR or an error code + */ +u32 i210_compute_checksum(struct device *dev, u16 *checksum) +{ + u16 eep_data[0x40]; + u32 i; + + /* First read back data to compute the checksum for*/ + if (i210_read_flash(dev, 0, 0x3f, eep_data)) + return I210_READ_ERROR; + /* The checksum is computed in that way that after summarize all the data*/ + /* from word address 0 to 0x3f the result is 0xBABA.*/ + *checksum = 0; + for (i = 0; i < 0x3f; i++) + *checksum += eep_data[i]; + *checksum = I210_TARGET_CHECKSUM - *checksum; + return I210_NO_ERROR; +} + +static struct device_operations i210_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = i210_init, + .scan_bus = 0, + .ops_pci = 0, +}; + +static const unsigned short i210_device_ids[] = { 0x1538, 0x1533, 0 }; + +static const struct pci_driver i210_driver __pci_driver = { + .ops = &i210_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = i210_device_ids, +}; diff --git a/src/drivers/intel/i210/i210.h b/src/drivers/intel/i210/i210.h new file mode 100644 index 0000000..ae8867d --- /dev/null +++ b/src/drivers/intel/i210/i210.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _INTEL_I210_H_ +#define _INTEL_I210_H_ +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <delay.h> + +#define I210_PCI_MEM_BAR_OFFSET 0x10 +#define I210_REG_EECTRL 0x12010 /* Offset for EEPROM control reg*/ +#define I210_FLUPD 0x800000 /* Start flash update bit*/ +#define I210_FLUDONE 0x4000000 /* Flash update done indicator*/ +#define I210_REG_EEREAD 0x12014 /* Offset for EEPROM read reg*/ +#define I210_REG_EEWRITE 0x12018 /* Offset for EEPROM write reg*/ +#define I210_CMDV 0x01 /* Command valid bit*/ +#define I210_DONE 0x02 /* command done bit*/ +#define I210_TARGET_CHECKSUM 0xBABA /* resulting checksum*/ + + +/*define some other useful values here*/ +#define I210_POLL_TIMEOUT 300000 /* use 300 ms as timeout*/ +/*Define some error states here*/ +#define I210_NO_ERROR 0x00000000 +#define I210_INVALID_PARAM 0x00000001 +#define I210_NOT_READY 0x00000002 +#define I210_READ_ERROR 0x00000004 +#define I210_WRITE_ERROR 0x00000008 +#define I210_CHECKSUM_ERROR 0x00000010 +#define I210_FLASH_UPDATE_ERROR 0x00000020 + +void i210_init(struct device *dev); +u32 i210_read_mac_adr(struct device *dev, u8 *MACAdr); +u32 i210_write_mac_adr(struct device *dev, u8 *MACAdr); +u32 i210_read_flash(struct device *dev, u32 address, u32 count, u16 *buffer); +u32 i210_write_flash(struct device *dev, u32 address, u32 count, u16 *buffer); +u32 i210_compute_checksum(struct device *dev, u16 *checksum); + + + +#endif /* _INTEL_I210_H_ */

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New patch to review for coreboot: ef91199 lint: exclude *.hex files from whitespace checking
by Werner Zeh 10 Feb '15

10 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8403 -gerrit commit ef9119908e317ccd8ed05eef0941d8be9d7ed52e Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 14:34:17 2015 +0100 lint: exclude *.hex files from whitespace checking If one needs raw binary files, .bin extension cannot be used due to settings in .gitignore. This patch allows to use .hex files. To avoid lint checks on these files, exculde the .hex extension from the test. Change-Id: I4b503229d63694c48cce12ca8cd33ea58172af01 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- util/lint/lint-stable-003-whitespace | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 47853ba..f13aa98 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -19,6 +19,6 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch|\.bin$)"` | \ +grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$)"` | \ sed -e "s,^.*$,File & has lines ending with whitespace.,"

1 0

Patch set updated for coreboot: 2c011f2 lint: exclude nvidia submodule from file list
by Werner Zeh 10 Feb '15

10 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8372 -gerrit commit 2c011f2e6671f8d78b81a7c97adfa44bc444feed Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 5 23:38:45 2015 +0100 lint: exclude nvidia submodule from file list From git's point of view submodules are a weird third thing between file and directory. Avoid trying to apply file handling on a directory. Change-Id: Ibbc9c28e1657d96413c5fb08705d30e25171254d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/lint/lint-stable-003-whitespace | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 22c5c3c..47853ba 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -19,6 +19,6 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch|\.bin$)"` | \ +grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch|\.bin$)"` | \ sed -e "s,^.*$,File & has lines ending with whitespace.,"

1 0

New patch to review for coreboot: e26f6ae fsp_baytrail: Add macros to define 20K pull-up and down
by Werner Zeh 10 Feb '15

10 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8402 -gerrit commit e26f6aef59503d374e246e1ef1b39523e2219839 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 13:32:51 2015 +0100 fsp_baytrail: Add macros to define 20K pull-up and down Add two macros to gpio.h which allow to setup 20K pull-up or pull-down resistor for a given GPIO. Change-Id: Ie3bc4d40df588ed682cc692e2a80527b9e62a483 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/baytrail/gpio.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h index e13b663..a45254a 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h +++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h @@ -170,6 +170,20 @@ .use_sel = GPIO_USE_MMIO, \ .is_gpio = 1 } +#define GPIO_INPUT_PU_20K \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_PD_20K \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + #define GPIO_INPUT_NOPU \ { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \

1 0

New patch to review for coreboot: ed0f413 fsp_baytrail: Add I2C driver
by Werner Zeh 10 Feb '15

10 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8401 -gerrit commit ed0f4138e8c6a01bf031cbf0565881dde6b84ddd Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 13:02:34 2015 +0100 fsp_baytrail: Add I2C driver Add a driver wich can handle the internal I2C controllers of Baytrail SoC. This driver is not suitable for the SMBUS-controller. Change-Id: I841c3991a2fb0f8b92b8e59ec02d62f5866f5bdf Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Makefile.inc | 1 + src/soc/intel/fsp_baytrail/baytrail/i2c.h | 138 +++++++++++++++ src/soc/intel/fsp_baytrail/i2c.c | 269 ++++++++++++++++++++++++++++++ 3 files changed, 408 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 3896e85..2dfb9cb 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -54,6 +54,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c +ramstage-y += i2c.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/ CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp diff --git a/src/soc/intel/fsp_baytrail/baytrail/i2c.h b/src/soc/intel/fsp_baytrail/baytrail/i2c.h new file mode 100644 index 0000000..3799fbb --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/i2c.h @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ +#define __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> + +/* SMBus controller settings in PCI configuration space*/ +#define I2C_PCI_VENDOR_ID 0x8086 +#define I2C0_PCI_DEV_ID 0x0f41 +#define I2C1_PCI_DEV_ID 0x0f42 +#define I2C2_PCI_DEV_ID 0x0f43 +#define I2C3_PCI_DEV_ID 0x0f44 +#define I2C4_PCI_DEV_ID 0x0f45 +#define I2C5_PCI_DEV_ID 0x0f46 +#define I2C6_PCI_DEV_ID 0x0f47 + +#define I2C0_MEM_BASE 0xd0921000 +#define I2C1_MEM_BASE 0xd0923000 +#define I2C2_MEM_BASE 0xd0925000 +#define I2C3_MEM_BASE 0xd0927000 +#define I2C4_MEM_BASE 0xd0929000 +#define I2C5_MEM_BASE 0xd092b000 +#define I2C6_MEM_BASE 0xd092d000 + +#define I2C_STANDARD_MODE 0x1 +#define I2C_FAST_MODE 0x2 + +/* Define relevant registers in PCI space.*/ +#define I2C_PCI_COMMAND 0x4 +#define I2C_PCI_STATUS 0x6 + +/* Define memory mapped registers.*/ +#define I2C_CTRL 0x0 +#define I2C_SLAVE_DISABLE 0x40 +#define I2C_RESTART_EN 0x20 +#define I2C_ADR_MODE 0x10 +#define I2C_SPEED_MASK 0x6 +#define I2C_STD_MODE 0x1 +#define I2C_FAST_MODE 0x2 +#define I2C_MASTER_ENABLE 0x1 + +#define I2C_TARGET_ADR 0x4 +#define I2C_TARGET_ADR_MASK 0x3ff + +#define I2C_DATA_CMD 0x10 +#define I2C_RESTART 0x400 +#define I2C_STOP 0x200 +#define I2C_RW_CMD 0x100 + +#define I2C_SS_SCL_HCNT 0x14 /* Counter for high period for 100 kHz SCL*/ +#define I2C_SS_SCL_LCNT 0x18 /* Counter for low period for 100 kHz SCL*/ +#define I2C_FS_SCL_HCNT 0x1c /* Counter for high period for 400 kHz SCL*/ +#define I2C_FS_SCL_LCNT 0x20 /* Counter for low period for 400 kHz SCL*/ + +#define I2C_INTR_STAT 0x2c /* Interrupt status register, read only*/ +#define I2C_INTR_MASK 0x30 /*Interrupt mask register*/ +#define I2C_RAW_INTR_STAT 0x34 /* Raw interrupt status, read only*/ +#define I2C_START_DETECT 0x400 +#define I2C_STOP_DETECT 0x200 +#define I2C_ACTIVITY 0x100 +#define I2C_TX_ABORT 0x40 +#define I2C_RD_REQ 0x20 /* Read request in slave mode*/ +#define I2C_TX_EMPTY 0x10 +#define I2C_TX_OVERFLOW 0x8 +#define I2C_RX_FULL 0x4 +#define I2C_RX_OVERFLOW 0x2 +#define I2C_RX_UNDERFLOW 0x1 + +#define I2C_RX_TL 0x38 /* Rx FIFO threshold level 0..255*/ +#define I2C_TX_TL 0x3c /* Tx FIFO threshold level 0..255*/ +#define I2C_CLR_INTR 0x40 /* Clear all events with a read*/ +#define I2C_CLR_TX_ABRT 0x54 /* Clear TX-Abort event with a read*/ + +/*There are a bunch of interrupt clearing registers now which I do not use!*/ +/*So proceed somewhat later with definition*/ +#define I2C_ENABLE 0x6c /* 0: disable I2C controller, 1: enable*/ +#define I2C_STATUS 0x70 +#define I2C_MST_ACTIVITY 0x20 /* Master FSM activity*/ +#define I2C_RFF 0x10 /* Receive FIFO completely full*/ +#define I2C_RFNE 0x8 /* Receive FIFO not empty*/ +#define I2C_TFE 0x4 /* Transmit FIFO completely empty*/ +#define I2C_TFNF 0x2 /* Transmit FIFO not full*/ +#define I2C_ACTIVE 0x1 /* 1: I2C currently in operation*/ + +#define I2C_TXFLR 0x74 /* Current transmit FIFO level*/ +#define I2C_RXFLR 0x78 /* Current receive FIFO level*/ +#define I2C_SDA_HOLD 0x7c /* Data hold time after SCL goes low*/ +#define I2C_ABORT_SOURCE 0x80 +#define I2C_ARB_LOST 0x1000 /* Arbitration lost*/ +#define I2C_MASTER_DIS 0x800 /* Master was disabled by user*/ +#define I2C_10B_RD_NORSTRT 0x400 /* 10 bit address read and RESTART disabled*/ +#define I2C_SBYTE_NORSTRT 0x200 /* START with RESTART disabled*/ +#define I2C_START_ACKDET 0x80 /* START byte was acknowledged*/ +#define I2C_TX_DATA_NOACK 0x8 /* TX data not acknowledged*/ +#define I2C_10B_ADR2_NOACK 0x4 /* Second address byte in 10 bit mode NACK*/ +#define I2C_10B_ADR1_NOACK 0x2 /* First address byte in 10 bit not ACK*/ +#define I2C_7B_ADDR_NACK 0x1 /* 7 bit address byte not acknowledged*/ + +#define I2C_ENABLE_STATUS 0x9c + +/* Define some status and error values*/ +#define I2C_ERR_INVALID_ADR 0x1000000 +#define I2C_ERR_TIMEOUT 0x2000000 +#define I2C_ERR_ABORT 0x4000000 +#define I2C_NO_ERROR 0x0000000 + + +#define I2C_TIMEOUT 2000 /* Use 2000 us as timeout for the bus*/ + +/* Prototype section*/ +int i2c_init(unsigned bus); +int i2c_read(unsigned bus, unsigned chip, unsigned addr, + uint8_t *buf, unsigned len); +int i2c_write(unsigned bus, unsigned chip, unsigned addr, + const uint8_t *buf, unsigned len); + +#endif /* __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ */ diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c new file mode 100644 index 0000000..05c21a3 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci.h> +#include <baytrail/baytrail.h> +#include <baytrail/pci_devs.h> +#include <baytrail/iosf.h> +#include <delay.h> +#include <baytrail/i2c.h> + +/* Wait for the transmit FIFO till there is at least one slot empty. + * FIFO stall due to transmit abort will be checked and resolved + */ +static int wait_tx_fifo(char *base_adr) { + int i; + + if (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff) { + /*Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO*/ + i = *((volatile unsigned int *)(base_adr + I2C_CLR_TX_ABRT)); + return I2C_ERR_ABORT | + (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff); + } + + /*Wait here for a free slot in TX-FIFO */ + i = I2C_TIMEOUT; + while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_TFNF)) + && (i)) { + udelay(1); + i--; + } + + if (i == 0) { + return I2C_ERR_TIMEOUT; + } else { + return I2C_NO_ERROR; + } +} + +/* Wait for the receive FIFO till there is at least one valid entry to read. + * FIFO stall due to transmit abort will be checked and resolved + */ +static int wait_rx_fifo(char *base_adr) { + int i; + + if (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff) { + /*Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO*/ + i = *((volatile unsigned int *)(base_adr + I2C_CLR_TX_ABRT)); + return I2C_ERR_ABORT | + (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff); + } + + /*Wait here for a received entry in RX-FIFO */ + i = I2C_TIMEOUT; + while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_RFNE)) + && (i)) { + udelay(1); + i--; + } + + if (i == 0) { + return I2C_ERR_TIMEOUT; + } else { + return I2C_NO_ERROR; + } +} + +/* When there will be a fast switch between send and receive, one have + * to wait until the first operation is completely finished + * before starting the second operation + */ +static int wait_for_idle(char *base_adr) +{ + int i; + volatile int status; + + /*For IDLE, increase timeout by ten times*/ + i = I2C_TIMEOUT * 10; + status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + while(((status & I2C_MST_ACTIVITY) || (!(status & I2C_TFE))) && (i)) { + status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + udelay(1); + i--; + } + + if (i == 0) { + return I2C_ERR_TIMEOUT; + } else { + return I2C_NO_ERROR; + } +} + +/** \brief Enables I2C-controller, sets up BAR and timing parameters + * @param bus Number of the I2C-controller to use (0...6) + * @return 0 on success, otherwise error code + */ +int i2c_init(unsigned bus) +{ + device_t dev; + int base_adr[7] = {I2C0_MEM_BASE, I2C1_MEM_BASE, I2C2_MEM_BASE, + I2C3_MEM_BASE, I2C4_MEM_BASE, I2C5_MEM_BASE, + I2C6_MEM_BASE}; + char *base_ptr = (char*)base_adr[bus]; + /* Ensure the desired device is valid*/ + if (bus > 6) { + printk (BIOS_ERR, "I2C: Only I2C controllers 0...6 are available"); + return 1; + } + + /*Set the I2C-device the user wants to use */ + dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1)); + + /* Ensure we have the right PCI device */ + if ((pci_read_config16(dev, 0x0) != I2C_PCI_VENDOR_ID) || + (pci_read_config16(dev, 0x2) != (I2C0_PCI_DEV_ID + bus))) { + printk(BIOS_ERR, "I2C: Controller %d not found!", bus); + return 2; + } + + /* Set memory base*/ + pci_write_config32(dev, PCI_BASE_ADDRESS_0,(int)base_ptr); + + /* Enable memory space*/ + pci_write_config32(dev, PCI_COMMAND, + (pci_read_config32(dev, PCI_COMMAND) | 0x2)); + + /*Set up some settings of I2C controller*/ + *((unsigned int *)(base_ptr + I2C_CTRL)) = (I2C_RESTART_EN + | (I2C_STANDARD_MODE << 1) + | I2C_MASTER_ENABLE); + /*Adjust frequency for standard mode to 100 kHz*/ + /*The counter value can be computed by N=100MHz/2/I2C_CLK*/ + /*Thus, for 100 kHz I2C_CLK, N is 0x1F4*/ + *((unsigned int *)(base_ptr + I2C_SS_SCL_HCNT)) = 0x1f4; + *((unsigned int *)(base_ptr + I2C_SS_SCL_LCNT)) = 0x1f4; + /*For 400 kHz, the counter value is 0x7d*/ + *((unsigned int *)(base_ptr + I2C_FS_SCL_HCNT)) = 0x7d; + *((unsigned int *)(base_ptr + I2C_FS_SCL_LCNT)) = 0x7d; + + /* Enable the I2C controller for operation*/ + *((unsigned int *)(base_ptr + I2C_ENABLE)) = 0x1; + + printk(BIOS_INFO, "I2C: Controller %d enabled.\n", bus); + return I2C_NO_ERROR; +} + +/** \brief Read bytes over I2C-Bus from a slave. This function tries only one + * time to transmit data. In case of an error (abort) error code is + * returned. Retransmission has to be done from caller! + * @param bus Number of the I2C-controller to use (0...6) + * @param chip 7 Bit of the slave address on I2C bus + * @param addr Address inside slave where to read from + * @param *buf Pointer to the buffer where to store read data + * @param len Number of bytes to read + * @return I2C_NO_ERROR when read was successful, otherwise error code + */ +int i2c_read(unsigned bus, unsigned chip, unsigned addr, + uint8_t *buf, unsigned len) +{ + int i = 0; + char *base_ptr = NULL; + device_t dev; + unsigned int val; + int stat; + + /*Get base address of desired I2C-controller*/ + dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1)); + base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if (base_ptr == NULL) { + printk(BIOS_INFO, "I2C: Invalid Base address\n"); + return I2C_ERR_INVALID_ADR; + } + + /*Ensure I2C controller is not active before setting slave address*/ + stat = wait_for_idle(base_ptr); + if (stat != I2C_NO_ERROR) { + return stat; + } + /* Now we can program the desired slave address and start transfer*/ + *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + /* Send address inside slave to read from*/ + *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + + /* For the next byte we need a repeated start condition*/ + val = I2C_RW_CMD | I2C_RESTART; + /* Now we can read desired amount of data over I2C*/ + for (i = 0; i < len; i++) { + /*A read is initiated by writing dummy data to the DATA-register*/ + *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + stat = wait_rx_fifo(base_ptr); + if (stat) { + return stat; + } + buf[i] = (*((unsigned int *)(base_ptr + I2C_DATA_CMD))) & 0xff; + val = I2C_RW_CMD; + if (i == (len -2)) { + /* For the last byte we need a stop condition to be generated*/ + val |= I2C_STOP; + } + } + return I2C_NO_ERROR; +} + +/** \brief Write bytes over I2C-Bus from a slave. This function tries only one + * time to transmit data. In case of an error (abort) error code is + * returned. Retransmission has to be done from caller! + * @param bus Number of the I2C-controller to use (0...6) + * @param chip 7 Bit of the slave address on I2C bus + * @param addr Address inside slave where to write to + * @param *buf Pointer to the buffer where data to write is stored + * @param len Number of bytes to write + * @return I2C_NO_ERROR when read was successful, otherwise error code + */ +int i2c_write(unsigned bus, unsigned chip, unsigned addr, + const uint8_t *buf, unsigned len) +{ + int i; + char *base_ptr; + device_t dev; + unsigned int val; + int stat; + + /*Get base address of desired I2C-controller*/ + dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1)); + base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if (base_ptr == NULL) { + return I2C_ERR_INVALID_ADR; + } + + /*Ensure I2C controller is not active jet*/ + stat = wait_for_idle(base_ptr); + if (stat) { + return stat; + } + /*Program slave address to use for this transfer*/ + *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + + /* Send address inside slave to write data to*/ + *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + + for (i = 0; i < len; i++) { + val = (unsigned int)(buf[i] & 0xff); /* Take only 8 bits*/ + if (i == (len -1)) { + /* For the last byte we need a stop condition to be generated*/ + val |= I2C_STOP; + } + stat = wait_tx_fifo(base_ptr); + if (stat) { + return stat; + } + *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + } + return I2C_NO_ERROR; +}

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New patch to review for coreboot: 08a838c add amdtool: an opponent to inteltool
by Alexander Couzens 10 Feb '15

10 Feb '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8400 -gerrit commit 08a838c02755b066e2279c60b1f9d99da6f821c5 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sun Feb 8 12:00:28 2015 +0100 add amdtool: an opponent to inteltool This first version only dumps the index register space for AMD 14h. Change-Id: I86627ef319f9732f9188161551bdcd0605c4c112 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/amdtool/Makefile | 39 ++++++++++++ util/amdtool/amdtool.c | 38 ++++++++++++ util/amdtool/amdtool.h | 37 ++++++++++++ util/amdtool/cmn.c | 160 +++++++++++++++++++++++++++++++++++++++++++++++++ util/amdtool/cmn.h | 42 +++++++++++++ util/amdtool/index.c | 98 ++++++++++++++++++++++++++++++ 6 files changed, 414 insertions(+) diff --git a/util/amdtool/Makefile b/util/amdtool/Makefile new file mode 100644 index 0000000..21350c4 --- /dev/null +++ b/util/amdtool/Makefile @@ -0,0 +1,39 @@ +## +## Makefile for amd_10h_tool +## +## Copyright (C) 2014 Alexander Couzens <lynxis(a)fe80.eu> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +CC = gcc +CFLAGS = -O2 -Wall -W -std=c99 +PROGRAM = amdtool +INSTALL = /usr/bin/install +PREFIX = /usr/local +LDFLAGS = -lpci + +all: $(PROGRAM) + +$(PROGRAM): amdtool.o cmn.o index.o + $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) + +install: $(PROGRAM) + $(INSTALL) $(PROGRAM) $(PREFIX)/sbin + +clean: + rm *.o $(PROGRAM) + +%.o: %.c + $(CC) $(CFLAGS) -c $^ -I. -o $@ diff --git a/util/amdtool/amdtool.c b/util/amdtool/amdtool.c new file mode 100644 index 0000000..f6ef7ac --- /dev/null +++ b/util/amdtool/amdtool.c @@ -0,0 +1,38 @@ +/* + * amdtool - dump all registers on an AMD CPU + chipset based system. + * + * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <stdio.h> +#include <stdint.h> +#include <pci/pci.h> + +#include "amdtool.h" +#include "cmn.h" + +int main() { + struct pci_access *pci_acc = pci_alloc(); + struct pci_dev *dev = NULL; + + pci_init(pci_acc); + dev = pci_get_dev(pci_acc, 0, 0, 0, 0); + pci_fill_info(dev, PCI_FILL_CLASS|PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS); + + print_index(dev); + + return 0; +} diff --git a/util/amdtool/amdtool.h b/util/amdtool/amdtool.h new file mode 100644 index 0000000..b9a7eb9 --- /dev/null +++ b/util/amdtool/amdtool.h @@ -0,0 +1,37 @@ +/* + * amdtool - dump all registers on an AMD CPU + chipset based system. + * + * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef AMDTOOL_H_ +#define AMDTOOL_H_ + +#include <stdint.h> + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#endif + +#define PCI_VENDOR_ID_AMD 0x1022 + +#define PCI_VENDOR_ID_AMD_NB_14H 0x1510 + +typedef struct { uint32_t addr; int size; char *name; } io_register_t; + +void print_index(struct pci_dev *nb); + +#endif /* AMDTOOL_H_ */ diff --git a/util/amdtool/cmn.c b/util/amdtool/cmn.c new file mode 100644 index 0000000..4795e5a --- /dev/null +++ b/util/amdtool/cmn.c @@ -0,0 +1,160 @@ +/* + * amdtool - dump all registers on an AMD CPU + chipset based system. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <stdint.h> +#include <pci/pci.h> + +#define NBMISC_INDEX 0x60 +#define NBPCIE_INDEX 0xE0 +#define NBMC_INDEX 0xE8 +#define NBHTIU_INDEX 0x94 + +#define pci_read_config32 pci_read_long +#define pci_read_config8 pci_read_byte +#define pci_write_config32 pci_write_long +#define pci_write_config8 pci_write_byte + +static u32 nb_read_index(struct pci_dev * dev, u32 index_reg, u32 index) +{ + pci_write_config32(dev, index_reg, index); + return pci_read_config32(dev, index_reg + 0x4); +} + +static void nb_write_index(struct pci_dev * dev, u32 index_reg, u32 index, u32 data) +{ + pci_write_config32(dev, index_reg, index); + pci_write_config32(dev, index_reg + 0x4, data); +} + + +u32 nbmisc_read_index(struct pci_dev * nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBMISC_INDEX, (index)); +} + +void nbmisc_write_index(struct pci_dev * nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); +} + +u32 nbpcie_p_read_index(struct pci_dev * dev, u32 index) +{ + return nb_read_index((dev), NBPCIE_INDEX, (index)); +} + +void nbpcie_p_write_index(struct pci_dev * dev, u32 index, u32 data) +{ + nb_write_index((dev), NBPCIE_INDEX, (index), (data)); +} + +u32 nbpcie_ind_read_index(struct pci_dev * nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBPCIE_INDEX, (index)); +} + +void nbpcie_ind_write_index(struct pci_dev * nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data)); +} + +u32 htiu_read_index(struct pci_dev * nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); +} + +void htiu_write_index(struct pci_dev * nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); +} + +u32 nbmc_read_index(struct pci_dev * nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBMC_INDEX, (index)); +} + +void nbmc_write_index(struct pci_dev * nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); +} + +void set_nbcfg_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = pci_read_config32(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + pci_write_config32(nb_dev, reg_pos, reg); + } +} + +void set_nbcfg_enable_bits_8(struct pci_dev * nb_dev, u32 reg_pos, u8 mask, u8 val) +{ + u8 reg_old, reg; + reg = reg_old = pci_read_config8(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + pci_write_config8(nb_dev, reg_pos, reg); + } +} + +void set_nbmc_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = nbmc_read_index(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + nbmc_write_index(nb_dev, reg_pos, reg); + } +} + +void set_htiu_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = htiu_read_index(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + htiu_write_index(nb_dev, reg_pos, reg); + } +} + +void set_nbmisc_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + nbmisc_write_index(nb_dev, reg_pos, reg); + } +} + +void set_pcie_enable_bits(struct pci_dev * dev, u32 reg_pos, u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg); + } +} diff --git a/util/amdtool/cmn.h b/util/amdtool/cmn.h new file mode 100644 index 0000000..b78254f --- /dev/null +++ b/util/amdtool/cmn.h @@ -0,0 +1,42 @@ +/* + * amdtool - dump all registers on an AMD CPU + chipset based system. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef CMN_H__H_ +#define CMN_H__H_ + +struct pci_dev; + +u32 nbmisc_read_index(struct pci_dev * nb_dev, u32 index); +void nbmisc_write_index(struct pci_dev * nb_dev, u32 index, u32 data); +u32 nbpcie_p_read_index(struct pci_dev * dev, u32 index); +void nbpcie_p_write_index(struct pci_dev * dev, u32 index, u32 data); +u32 nbpcie_ind_read_index(struct pci_dev * nb_dev, u32 index); +void nbpcie_ind_write_index(struct pci_dev * nb_dev, u32 index, u32 data); +u32 htiu_read_index(struct pci_dev * nb_dev, u32 index); +void htiu_write_index(struct pci_dev * nb_dev, u32 index, u32 data); +u32 nbmc_read_index(struct pci_dev * nb_dev, u32 index); +void nbmc_write_index(struct pci_dev * nb_dev, u32 index, u32 data); +void set_nbcfg_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val); +void set_nbcfg_enable_bits_8(struct pci_dev * nb_dev, u32 reg_pos, u8 mask, u8 val); +void set_nbmc_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val); +void set_htiu_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val); +void set_nbmisc_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val); +void set_pcie_enable_bits(struct pci_dev * dev, u32 reg_pos, u32 mask, u32 val); + +#endif /* CMN_H__H_ */ diff --git a/util/amdtool/index.c b/util/amdtool/index.c new file mode 100644 index 0000000..b2d870e --- /dev/null +++ b/util/amdtool/index.c @@ -0,0 +1,98 @@ +/* + * amdtool - dump all registers on an AMD CPU + chipset based system. + * + * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <stdio.h> +#include <stdint.h> +#include <pci/pci.h> + +#include "amdtool.h" +#include "cmn.h" + +/* AMD 14h documentation based on + * BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors + * 43170 Rev 3.13 - February 17, 2012 + */ + +static const io_register_t amd_14_e4[] = { + /* IO Link */ + { 0x01010002, 4, "IO Link Hardware Debug"}, + { 0x01010010, 4, "IO Link Control 1"}, + { 0x01010011, 4, "IO Link Config Control"}, + { 0x0101001C, 4, "IO Link Control 2"}, + { 0x01010020, 4, "IO Link Chip Interface Control"}, + { 0x01010040, 4, "IO Link Phy Control"}, + { 0x010100B0, 4, "IO Link Strap Control"}, + { 0x010100C0, 4, "IO Link Strap Miscellaneous"}, + { 0x010100C1, 4, "IO Link Strap Miscellaneous"}, + /* Impedance Controller Registers */ + { 0x01088071, 4, "Receiver Impedance Adjustment"}, + { 0x01088072, 4, "Transmitter Impedance Adjustment"}, + /* TODO: PIF Registers */ + /* Wrapper Registers */ + { 0x01300000, 4, "BIF Core Feature Enable"}, + { 0x01300002, 4, "Link Speed Control"}, + { 0x01300080, 4, "Link Configuration"}, + { 0x01300800, 4, "Device 8 Link Training Control"}, + { 0x01300803, 4, "Device 8 Link De-emphasis Control"}, + { 0x01300900, 4, "Device 4 Link Training Control"}, + { 0x01300903, 4, "Device 4 Link De-emphasis Control"}, + { 0x01300a00, 4, "Device 5 Link Training Control"}, + { 0x01300a03, 4, "Device 5 Link De-emphasis Control"}, + { 0x01300b00, 4, "Device 6 Link Training Control"}, + { 0x01300b03, 4, "Device 6 Link De-emphasis Control"}, + { 0x01300c00, 4, "Device 7 Link Training Control"}, + { 0x01300c03, 4, "Device 7 Link De-emphasis Control"}, + { 0x01308002, 4, "Subsystem and Subvendor ID Control"}, + { 0x01308011, 4, "Link Transmit Clock Gating Control"}, + { 0x01308012, 4, "Link Transmit Clock Gating Control 2"}, + { 0x01308013, 4, "Transmit Clock PLL Control"}, + { 0x01308016, 4, "Link Clock Switching Control"}, + { 0x01308021, 4, "Transmitter Lane Mux"}, + { 0x01308022, 4, "Receiver Lane Mux"}, + { 0x01308023, 4, "Lane Enable"}, + { 0x01308025, 4, "Lane Mux Power Sequence Control 0"}, + { 0x01308031, 4, "Lane Counter Status"}, + { 0x01308060, 4, "Soft Reset Command 0"}, + { 0x01308061, 4, "Soft Reset Command 1"}, + { 0x01308062, 4, "Soft Reset Control 0"}, + { 0x013080F0, 4, "BIOS Timer"}, + { 0x013080F1, 4, "BIOS Timer Control"}, +}; + +void print_index(struct pci_dev *nb) +{ + int index_size = 0; + const io_register_t *index; + + printf("=== Index Register Space ===\n"); + switch (nb->device_id) { + case PCI_VENDOR_ID_AMD_NB_14H: + index_size = ARRAY_SIZE(amd_14_e4); + index = amd_14_e4; + break; + default: + printf("Unsupported Northbridge pci %x\n", nb->device_id); + return; + break; + } + + for (int i=0; i < index_size; i++) { + printf("0x%08x = 0x%08x - %s\n", index[i].addr, nbpcie_p_read_index(nb, index[i].addr), index[i].name); + } +}

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coreboot-gerrit February 2015