coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

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509 discussions

New patch to review for coreboot: b4b625a Baytrail_fsp: Add new microcode for Baytrail M
by Werner Zeh 10 Feb '15

10 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8399 -gerrit commit b4b625a1f6d24707e57a621e659fb6b15b54d05d Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 10:16:12 2015 +0100 Baytrail_fsp: Add new microcode for Baytrail M Add a new microcode for Baytrail M D0 stepping used in cpu N2807 silicon. Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 3 ++- src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 709ff92..527550d 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,10 +19,11 @@ unsigned microcode[] = { -/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ +/* Region size is 0x3CC00 - update in microcode_size.h if it gets larger. */ #include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 #include "M0130673322.h" // M0130673: Baytrail I B2 / B3 #include "M0130679901.h" // M0130679: Baytrail I D0 +#include "M0C30678829.h" // M0C30678: Baytrail M D Stepping /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h index ec55314..51453f0 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -1,2 +1,2 @@ /* Maximum size of the area that the FSP will search for the correct microcode */ -#define MICROCODE_REGION_LENGTH 0x30000 +#define MICROCODE_REGION_LENGTH 0x3CC00

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Patch merged into coreboot/master: 754fac4 PCI subsystem: Remove AGP bridge type
by gerrit＠coreboot.org 10 Feb '15

10 Feb '15

the following patch was just integrated into master: commit 754fac43467f87d6b926a181b6150867a08fb9b3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 2 15:56:27 2015 +0200 PCI subsystem: Remove AGP bridge type There is no auto-detection for AGP type and we have no hardware that selects this. Furthermore, we treat AGP bridges just like PCI bridges, there is no optimisation for higher bandwidth. Change-Id: I4fe87c83411643cb9b8d3216f2af07bf098174d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8367 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8367 for details. -gerrit

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Patch merged into coreboot/master: b474abe Baytrail_fsp: Make ME path configurable in menuconfig
by gerrit＠coreboot.org 10 Feb '15

10 Feb '15

the following patch was just integrated into master: commit b474abee84445b6ad84a9f2a920d96ec55bdf2d3 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 09:16:56 2015 +0100 Baytrail_fsp: Make ME path configurable in menuconfig By adding a description to ME_PATH it becomes visible and editable in menuconfig. Change-Id: I8c2f6a30c10f16b19f3667263db02c93688c9f8f Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: http://review.coreboot.org/8398 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8398 for details. -gerrit

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New patch to review for coreboot: 62ed127 Baytrail_fsp: Make ME path configurable in menuconfig
by Werner Zeh 10 Feb '15

10 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8398 -gerrit commit 62ed1276c6293fcd9ba14105ec15c11b89accc06 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 09:16:56 2015 +0100 Baytrail_fsp: Make ME path configurable in menuconfig By adding a description to ME_PATH it becomes visible and editable in menuconfig. Change-Id: I8c2f6a30c10f16b19f3667263db02c93688c9f8f Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 0ebb5c7..639071a 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -122,7 +122,7 @@ config INCLUDE_ME to build it in here. config ME_PATH - string + string "Path to ME" depends on INCLUDE_ME help The path of the TXE and Descriptor files.

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New patch to review for coreboot: 4d1d19f mainboards/asus/kfsn4-dre: Run BSP FIDVID before AP FIDVID
by Timothy Pearson 10 Feb '15

10 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8397 -gerrit commit 4d1d19ffab984e77a984b06c51e17e379b888743 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 10 00:37:21 2015 -0600 mainboards/asus/kfsn4-dre: Run BSP FIDVID before AP FIDVID This resolves an issue on Shanghai dual CPU configurations where the APs on node 0 would not start. Single CPU configurations are unaffected by this issue. TEST: Booted KFSN4-DRE with dual Opteron 8389 CPUs and verified proper BSP/AP start and microcode patch levels. Change-Id: I0f5d4e0e356c6bd64e324b4399ef43b400ecab0c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre/romstage.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index cd8b9de..0dab8e8 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -271,19 +271,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - } - - printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n"); - ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID); - - post_code(0x38); - if (IS_ENABLED(CONFIG_SET_FIDVID)) { msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); @@ -303,6 +290,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); } + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + } + + printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n"); + ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID); + + post_code(0x38); + init_timer(); // Need to use TMICT to synconize FID/VID wants_reset = ck804_early_setup_x();

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Patch merged into coreboot/master: 208a535 lenovo/x200: Increase default CBFS_SIZE to 2 MiB
by gerrit＠coreboot.org 10 Feb '15

10 Feb '15

the following patch was just integrated into master: commit 208a53527a01ad989eef797c1f8e002f6a4140ec Author: Michał Masłowski <mtjm(a)mtjm.eu> Date: Tue Feb 3 22:59:45 2015 +0100 lenovo/x200: Increase default CBFS_SIZE to 2 MiB The original firmware has a 2 MiB BIOS region in both 4 MiB and 8 MiB flash variants. Let's allow using the whole region instead of the gm45 default of 1 MiB. Change-Id: I2d8a04bcb992bf2e8e15890a5c6719810b1cf405 Signed-off-by: Michał Masłowski <mtjm(a)mtjm.eu> Reviewed-on: http://review.coreboot.org/8392 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8392 for details. -gerrit

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Patch merged into coreboot/master: c1f47c1 amd/amdfam10: Fix invalid transition latency in PowerNow! _PSS objects
by gerrit＠coreboot.org 10 Feb '15

10 Feb '15

the following patch was just integrated into master: commit c1f47c1460cc69c232aa90480d41a4c10474aacb Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Feb 6 16:07:53 2015 -0600 amd/amdfam10: Fix invalid transition latency in PowerNow! _PSS objects Fix a mistake that led to an invalid 0ms latency in the automatically generated PowerNow! ACPI _PSS objects. TEST: Booted FreeBSD and Linux and verified correct latency values. Found-by: Coverity Scan Change-Id: I03cecab694708136dc555ca2af7ee9a0bf9be5af Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8376 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8376 for details. -gerrit

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New patch to review for coreboot: aea71b4 Use ALIGN_UP instead of manual alignment
by Paul Menzel 09 Feb '15

09 Feb '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8396 -gerrit commit aea71b43c96a8ba2022bca4ce17a5ff16c4cc780 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Wed Jan 21 17:37:34 2015 +0100 Use ALIGN_UP instead of manual alignment BUG=none BRANCH=none TEST=none Change-Id: I56f357db6d37120772a03a1f7f84ce2a5b5620e9 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/241855 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Commit-Queue: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/libc/malloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 1d99a9c..edda0b4 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -130,7 +130,7 @@ static void *alloc(int len, struct memory_type *type) hdrtype_t volatile *ptr = (hdrtype_t volatile *)type->start; /* Align the size. */ - len = (len + HDRSIZE - 1) & ~(HDRSIZE - 1); + len = ALIGN_UP(len, HDRSIZE); if (!len || len > MAX_SIZE) return (void *)NULL;

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Patch set updated for coreboot: fab13b5 lenovo/x200/board_info.txt: Add SOIC-8 to ROM package
by Michał Masłowski 09 Feb '15

09 Feb '15

Michał Masłowski (mtjm(a)mtjm.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8391 -gerrit commit fab13b590ac6d1715cb7905403f434c10e0e802b Author: Michał Masłowski <mtjm(a)mtjm.eu> Date: Tue Feb 3 22:51:18 2015 +0100 lenovo/x200/board_info.txt: Add SOIC-8 to ROM package Some X200 use a 4 MiB SOIC-8 flash chip. Change-Id: Ie5bd359ef08cf1be369a026be376c21555d0ea18 Signed-off-by: Michał Masłowski <mtjm(a)mtjm.eu> --- src/mainboard/lenovo/x200/board_info.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x200/board_info.txt b/src/mainboard/lenovo/x200/board_info.txt index 60496f5..3362d6e 100644 --- a/src/mainboard/lenovo/x200/board_info.txt +++ b/src/mainboard/lenovo/x200/board_info.txt @@ -1,5 +1,5 @@ Category: laptop -ROM package: SOIC-16 +ROM package: SOIC-16 or SOIC-8 ROM protocol: SPI ROM socketed: n Flashrom support: n

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Patch set updated for coreboot: f1b35ad lenovo/x200: Increase default CBFS_SIZE to 2 MiB
by Michał Masłowski 09 Feb '15

09 Feb '15

Michał Masłowski (mtjm(a)mtjm.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8392 -gerrit commit f1b35ad2288d2491dca4f2a0f7309c38abf62dfa Author: Michał Masłowski <mtjm(a)mtjm.eu> Date: Tue Feb 3 22:59:45 2015 +0100 lenovo/x200: Increase default CBFS_SIZE to 2 MiB The original firmware has a 2 MiB BIOS region in both 4 MiB and 8 MiB flash variants. Let's allow using the whole region instead of the gm45 default of 1 MiB. Change-Id: I2d8a04bcb992bf2e8e15890a5c6719810b1cf405 Signed-off-by: Michał Masłowski <mtjm(a)mtjm.eu> --- src/mainboard/lenovo/x200/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 67fc388..01556b3 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -42,4 +42,8 @@ config MAX_CPUS int default 2 +config CBFS_SIZE + hex + default 0x200000 + endif # BOARD_LENOVO_X200

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coreboot-gerrit February 2015