coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 393b7f1 acpi: Generate valid ACPI processor objects
by Timothy Pearson 11 Feb '15

11 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8422 -gerrit commit 393b7f1ceefd1d2940fe79e5ecb242cf697854a2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 10 22:21:39 2015 -0600 acpi: Generate valid ACPI processor objects The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/arch/x86/boot/acpigen.c | 2 +- src/cpu/intel/fsp_model_206ax/acpi/cpu.asl | 74 ++++++++--------- src/cpu/intel/fsp_model_406dx/acpi/cpu.asl | 74 ++++++++--------- src/cpu/intel/haswell/acpi/cpu.asl | 74 ++++++++--------- src/cpu/intel/model_206ax/acpi/cpu.asl | 74 ++++++++--------- src/cpu/intel/model_6dx/acpi/cpu.asl | 20 ++--- src/ec/quanta/ene_kb3940q/acpi/ec.asl | 10 +-- src/include/cpu/intel/speedstep.h | 2 +- src/mainboard/amd/dbm690t/fadt.c | 2 +- src/mainboard/amd/pistachio/fadt.c | 2 +- src/mainboard/amd/torpedo/fadt.c | 2 +- src/mainboard/getac/p470/acpi/ec.asl | 2 +- src/mainboard/getac/p470/acpi/platform.asl | 10 +-- src/mainboard/getac/p470/acpi/thermal.asl | 4 +- src/mainboard/ibase/mb899/acpi/thermal.asl | 4 +- src/mainboard/intel/d945gclf/acpi/thermal.asl | 4 +- src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl | 4 +- src/mainboard/kontron/986lcd-m/acpi/thermal.asl | 4 +- src/mainboard/kontron/kt690/fadt.c | 2 +- src/mainboard/lenovo/x200/acpi/platform.asl | 16 ++-- src/mainboard/roda/rk886ex/acpi/thermal.asl | 4 +- src/mainboard/roda/rk9/acpi/platform.asl | 16 ++-- src/mainboard/roda/rk9/acpi/thermal.asl | 4 +- .../siemens/sitemp_g1p1/acpi/platform.asl | 4 +- src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl | 4 +- src/mainboard/siemens/sitemp_g1p1/fadt.c | 2 +- src/mainboard/technexion/tim5690/fadt.c | 2 +- src/mainboard/technexion/tim8690/fadt.c | 2 +- src/mainboard/via/vt8454c/dsdt.asl | 2 +- src/northbridge/amd/amdk8/thermal_mixin.asl | 6 +- .../intel/fsp_sandybridge/acpi/hostbridge.asl | 6 +- src/northbridge/intel/haswell/acpi/hostbridge.asl | 6 +- src/northbridge/intel/nehalem/acpi/hostbridge.asl | 6 +- .../intel/sandybridge/acpi/hostbridge.asl | 6 +- src/soc/intel/baytrail/acpi/cpu.asl | 38 ++++----- src/soc/intel/baytrail/acpi/dptf/cpu.asl | 38 ++++----- src/soc/intel/broadwell/acpi/cpu.asl | 94 +++++++++++----------- src/soc/intel/broadwell/acpi/ctdp.asl | 6 +- src/soc/intel/fsp_baytrail/acpi/cpu.asl | 38 ++++----- src/southbridge/amd/agesa/hudson/hudson.c | 2 +- src/southbridge/amd/cimx/sb800/fadt.c | 2 +- src/southbridge/amd/pi/hudson/hudson.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- 44 files changed, 340 insertions(+), 340 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 8e7ce46..76fe2d6 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -293,7 +293,7 @@ int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) len = acpigen_write_len_f(); snprintf(pscope, sizeof (pscope), - "\\_PR.CPU%x", (unsigned int) cpuindex); + "\\_PR.CP%02d", (unsigned int) cpuindex); len += acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex); acpigen_emit_byte(pblock_addr & 0xff); diff --git a/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl b/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl index 558a9d3..472ac08 100644 --- a/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl +++ b/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl @@ -20,31 +20,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -52,18 +52,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -71,18 +71,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,13 +90,13 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, + \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl b/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl index 558a9d3..472ac08 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl +++ b/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl @@ -20,31 +20,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -52,18 +52,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -71,18 +71,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,13 +90,13 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, + \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/cpu/intel/haswell/acpi/cpu.asl b/src/cpu/intel/haswell/acpi/cpu.asl index 558a9d3..472ac08 100644 --- a/src/cpu/intel/haswell/acpi/cpu.asl +++ b/src/cpu/intel/haswell/acpi/cpu.asl @@ -20,31 +20,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -52,18 +52,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -71,18 +71,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,13 +90,13 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, + \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/cpu/intel/model_206ax/acpi/cpu.asl b/src/cpu/intel/model_206ax/acpi/cpu.asl index 558a9d3..472ac08 100644 --- a/src/cpu/intel/model_206ax/acpi/cpu.asl +++ b/src/cpu/intel/model_206ax/acpi/cpu.asl @@ -20,31 +20,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -52,18 +52,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -71,18 +71,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,13 +90,13 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, + \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/cpu/intel/model_6dx/acpi/cpu.asl b/src/cpu/intel/model_6dx/acpi/cpu.asl index 8928c38..04438a2 100644 --- a/src/cpu/intel/model_6dx/acpi/cpu.asl +++ b/src/cpu/intel/model_6dx/acpi/cpu.asl @@ -4,34 +4,34 @@ External(PDC1) // Power notification -External (\_PR_.CPU0, DeviceObj) -External (\_PR_.CPU1, DeviceObj) -External (\_PR_.CPU0._PPC) -External (\_PR_.CPU1._PPC) +External (\_PR_.CP00, DeviceObj) +External (\_PR_.CP01, DeviceObj) +External (\_PR_.CP00._PPC) +External (\_PR_.CP01._PPC) Method (PNOT) { If (MPEN) { If(And(PDC0, 0x08)) { - Notify (\_PR_.CPU0, 0x80) // _PPC + Notify (\_PR_.CP00, 0x80) // _PPC If (And(PDC0, 0x10)) { Sleep(100) - Notify(\_PR_.CPU0, 0x81) // _CST + Notify(\_PR_.CP00, 0x81) // _CST } } If(And(PDC1, 0x08)) { - Notify (\_PR_.CPU1, 0x80) // _PPC + Notify (\_PR_.CP01, 0x80) // _PPC If (And(PDC1, 0x10)) { Sleep(100) - Notify(\_PR_.CPU1, 0x81) // _CST + Notify(\_PR_.CP01, 0x81) // _CST } } } Else { // UP - Notify (\_PR_.CPU0, 0x80) + Notify (\_PR_.CP00, 0x80) Sleep(0x64) - Notify(\_PR_.CPU0, 0x81) + Notify(\_PR_.CP00, 0x81) } } diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 4e703fe..3d9aa62 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -23,7 +23,7 @@ * re-evaluate their _PPC and _CST tables. */ -External (\_PR.CPU0._PPC, IntObj) +External (\_PR.CP00._PPC, IntObj) Device (EC0) { @@ -148,12 +148,12 @@ Device (EC0) Store (CTMP, Local0) // Find and program number of P-States - Store (SizeOf (\_PR.CPU0._PSS), MPST) + Store (SizeOf (\_PR.CP00._PSS), MPST) Store ("Programming number of P-states: ", Debug) Store (MPST, Debug) // Find and program the current P-State - Store(\_PR.CPU0._PPC, NPST) + Store(\_PR.CP00._PPC, NPST) Store ("Programming Current P-state: ", Debug) Store (NPST, Debug) } @@ -192,7 +192,7 @@ Device (EC0) { Store ("Pstate Event 0x0E", Debug) - Store(\_PR.CPU0._PPC, Local0) + Store(\_PR.CP00._PPC, Local0) Subtract(PPCM, 0x01, Local1) If(LLess(Local0, Local1)) { @@ -207,7 +207,7 @@ Device (EC0) Method (_Q0F) { Store ("Pstate Event 0x0F", Debug) - Store(\_PR.CPU0._PPC, Local0) + Store(\_PR.CP00._PPC, Local0) If(Local0) { Decrement(Local0) diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 8bfae60..eb8b506 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -29,7 +29,7 @@ #define SPEEDSTEP_APIC_MAGIC 0xACAC /* MWAIT coordination I/O base address. This must match - * the \_PR_.CPU0 PM base address. + * the \_PR_.CP00 PM base address. */ #define PMB0_BASE 0x510 diff --git a/src/mainboard/amd/dbm690t/fadt.c b/src/mainboard/amd/dbm690t/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/amd/dbm690t/fadt.c +++ b/src/mainboard/amd/dbm690t/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/amd/pistachio/fadt.c +++ b/src/mainboard/amd/pistachio/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 4bc88ac..5d66791 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -81,7 +81,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) val = GPE0_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ val = CPU_CNT_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); val = 0; diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 1b1c157..70e4224 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -105,7 +105,7 @@ Device(EC0) // EC Query methods, called upon SCI interrupts. Method (_Q01, 0) { - Notify (\_PR.CPU0, 0x80) + Notify (\_PR.CP00, 0x80) If(ADP) { Store(1, \_SB.AC.ACST) TRAP(0xe3) diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index 2b081e0..cad5a71 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -95,15 +95,15 @@ Method(_WAK,1) // Windows XP SP2 P-State restore If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) { - If (LGreater(\_PR.CPU0._PPC, 0)) { - Subtract(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + If (LGreater(\_PR.CP00._PPC, 0)) { + Subtract(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) PNOT() - Add(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + Add(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) PNOT() } Else { - Add(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + Add(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) PNOT() - Subtract(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + Subtract(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) PNOT() } } diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl index eefc1b7..f103561 100644 --- a/src/mainboard/getac/p470/acpi/thermal.asl +++ b/src/mainboard/getac/p470/acpi/thermal.asl @@ -79,9 +79,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } // TC1 value for passive cooling diff --git a/src/mainboard/ibase/mb899/acpi/thermal.asl b/src/mainboard/ibase/mb899/acpi/thermal.asl index 128d677..c5994d5 100644 --- a/src/mainboard/ibase/mb899/acpi/thermal.asl +++ b/src/mainboard/ibase/mb899/acpi/thermal.asl @@ -65,9 +65,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU1, \_PR.CPU2}) + Return (Package() {\_PR.CP01, \_PR.CP02}) } - Return (Package() {\_PR.CPU1}) + Return (Package() {\_PR.CP01}) } // TC1 value for passive cooling diff --git a/src/mainboard/intel/d945gclf/acpi/thermal.asl b/src/mainboard/intel/d945gclf/acpi/thermal.asl index fc9f24e..10e241d 100644 --- a/src/mainboard/intel/d945gclf/acpi/thermal.asl +++ b/src/mainboard/intel/d945gclf/acpi/thermal.asl @@ -65,9 +65,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU1, \_PR.CPU2}) + Return (Package() {\_PR.CP01, \_PR.CP02}) } - Return (Package() {\_PR.CPU1}) + Return (Package() {\_PR.CP01}) } // TC1 value for passive cooling diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl b/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl index 5330309..1ba2338 100644 --- a/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl +++ b/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl @@ -67,9 +67,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU1, \_PR.CPU2}) + Return (Package() {\_PR.CP01, \_PR.CP02}) } - Return (Package() {\_PR.CPU1}) + Return (Package() {\_PR.CP01}) } // TC1 value for passive cooling diff --git a/src/mainboard/kontron/986lcd-m/acpi/thermal.asl b/src/mainboard/kontron/986lcd-m/acpi/thermal.asl index 128d677..c5994d5 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/thermal.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/thermal.asl @@ -65,9 +65,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU1, \_PR.CPU2}) + Return (Package() {\_PR.CP01, \_PR.CP02}) } - Return (Package() {\_PR.CPU1}) + Return (Package() {\_PR.CP01}) } // TC1 value for passive cooling diff --git a/src/mainboard/kontron/kt690/fadt.c b/src/mainboard/kontron/kt690/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/kontron/kt690/fadt.c +++ b/src/mainboard/kontron/kt690/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/lenovo/x200/acpi/platform.asl b/src/mainboard/lenovo/x200/acpi/platform.asl index 19b1e00..2aa556f 100644 --- a/src/mainboard/lenovo/x200/acpi/platform.asl +++ b/src/mainboard/lenovo/x200/acpi/platform.asl @@ -100,33 +100,33 @@ Method(_WAK,1) // Power notification -External (\_PR_.CPU0, DeviceObj) -External (\_PR_.CPU1, DeviceObj) +External (\_PR_.CP00, DeviceObj) +External (\_PR_.CP01, DeviceObj) Method (PNOT) { If (MPEN) { If(And(PDC0, 0x08)) { - Notify (\_PR_.CPU0, 0x80) // _PPC + Notify (\_PR_.CP00, 0x80) // _PPC If (And(PDC0, 0x10)) { Sleep(100) - Notify(\_PR_.CPU0, 0x81) // _CST + Notify(\_PR_.CP00, 0x81) // _CST } } If(And(PDC1, 0x08)) { - Notify (\_PR_.CPU1, 0x80) // _PPC + Notify (\_PR_.CP01, 0x80) // _PPC If (And(PDC1, 0x10)) { Sleep(100) - Notify(\_PR_.CPU1, 0x81) // _CST + Notify(\_PR_.CP01, 0x81) // _CST } } } Else { // UP - Notify (\_PR_.CPU0, 0x80) + Notify (\_PR_.CP00, 0x80) Sleep(0x64) - Notify(\_PR_.CPU0, 0x81) + Notify(\_PR_.CP00, 0x81) } } diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl index e445d3c..873b089 100644 --- a/src/mainboard/roda/rk886ex/acpi/thermal.asl +++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl @@ -67,9 +67,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } // TC1 value for passive cooling diff --git a/src/mainboard/roda/rk9/acpi/platform.asl b/src/mainboard/roda/rk9/acpi/platform.asl index 3d4a214..decceaf 100644 --- a/src/mainboard/roda/rk9/acpi/platform.asl +++ b/src/mainboard/roda/rk9/acpi/platform.asl @@ -100,33 +100,33 @@ Method(_WAK,1) // Power notification -External (\_PR_.CPU0, DeviceObj) -External (\_PR_.CPU1, DeviceObj) +External (\_PR_.CP00, DeviceObj) +External (\_PR_.CP01, DeviceObj) Method (PNOT) { If (MPEN) { If(And(PDC0, 0x08)) { - Notify (\_PR_.CPU0, 0x80) // _PPC + Notify (\_PR_.CP00, 0x80) // _PPC If (And(PDC0, 0x10)) { Sleep(100) - Notify(\_PR_.CPU0, 0x81) // _CST + Notify(\_PR_.CP00, 0x81) // _CST } } If(And(PDC1, 0x08)) { - Notify (\_PR_.CPU1, 0x80) // _PPC + Notify (\_PR_.CP01, 0x80) // _PPC If (And(PDC1, 0x10)) { Sleep(100) - Notify(\_PR_.CPU1, 0x81) // _CST + Notify(\_PR_.CP01, 0x81) // _CST } } } Else { // UP - Notify (\_PR_.CPU0, 0x80) + Notify (\_PR_.CP00, 0x80) Sleep(0x64) - Notify(\_PR_.CPU0, 0x81) + Notify(\_PR_.CP00, 0x81) } // Notify the Batteries diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl index 6e28f17..f4868b4 100644 --- a/src/mainboard/roda/rk9/acpi/thermal.asl +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -86,9 +86,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } // TC1 value for passive cooling diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl index 8af607d..37daa36 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl @@ -30,8 +30,8 @@ Method(_PIC, 1, NotSerialized) } } -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) Scope(\_SB) { diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl index 02b1df1..fbcd0e7 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl @@ -56,9 +56,9 @@ Scope(\_TZ) { Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ diff --git a/src/mainboard/siemens/sitemp_g1p1/fadt.c b/src/mainboard/siemens/sitemp_g1p1/fadt.c index f9acfe4..d62caa0 100644 --- a/src/mainboard/siemens/sitemp_g1p1/fadt.c +++ b/src/mainboard/siemens/sitemp_g1p1/fadt.c @@ -80,7 +80,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/technexion/tim5690/fadt.c b/src/mainboard/technexion/tim5690/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/technexion/tim5690/fadt.c +++ b/src/mainboard/technexion/tim5690/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/technexion/tim8690/fadt.c b/src/mainboard/technexion/tim8690/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/technexion/tim8690/fadt.c +++ b/src/mainboard/technexion/tim8690/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/via/vt8454c/dsdt.asl b/src/mainboard/via/vt8454c/dsdt.asl index d13a6b7..4901041 100644 --- a/src/mainboard/via/vt8454c/dsdt.asl +++ b/src/mainboard/via/vt8454c/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) */ Scope (\_PR) { - Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {} + Processor (\_PR.CP00, 0x00, 0x00000410, 0x06) {} } /* For now only define 2 power states: diff --git a/src/northbridge/amd/amdk8/thermal_mixin.asl b/src/northbridge/amd/amdk8/thermal_mixin.asl index 62590ff..f6257a6 100644 --- a/src/northbridge/amd/amdk8/thermal_mixin.asl +++ b/src/northbridge/amd/amdk8/thermal_mixin.asl @@ -139,7 +139,7 @@ ThermalZone (K8T1) { Name(_UID, "k8-1") Name(_STR, Unicode("K8 compatible CPU Core 1 Thermal Sensor 2")) - Name(_TZD, Package () {\_PR.CPU0}) + Name(_TZD, Package () {\_PR.CP00}) Method(_STA) { Store(CORE, Local0) @@ -190,7 +190,7 @@ ThermalZone (K8T2) { Name(_UID, "k8-2") Name(_STR, Unicode("K8 compatible CPU Core 2 Thermal Sensor 1")) - Name(_TZD, Package () {\_PR.CPU0}) + Name(_TZD, Package () {\_PR.CP00}) Method(_STA) { Store(CORE, Local0) @@ -241,7 +241,7 @@ ThermalZone (K8T3) { Name(_UID, "k8-3") Name(_STR, Unicode("K8 compatible CPU Core 2 Thermal Sensor 2")) - Name(_TZD, Package () {\_PR.CPU0}) + Name(_TZD, Package () {\_PR.CP00}) Method(_STA) { Store(CORE, Local0) diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl index e569cf3..e82758c 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl @@ -147,16 +147,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index bb8e95e..9bc5549 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -157,16 +157,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index 79736bc..d210a95 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -109,16 +109,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 4279271..26f7514 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -147,16 +147,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/soc/intel/baytrail/acpi/cpu.asl b/src/soc/intel/baytrail/acpi/cpu.asl index 16f62ba..f7e404d 100644 --- a/src/soc/intel/baytrail/acpi/cpu.asl +++ b/src/soc/intel/baytrail/acpi/cpu.asl @@ -20,21 +20,21 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } } @@ -42,12 +42,12 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } } @@ -55,12 +55,12 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } } @@ -68,10 +68,10 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl index 3cbfc5f..58c1c7b 100644 --- a/src/soc/intel/baytrail/acpi/dptf/cpu.asl +++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl @@ -1,8 +1,8 @@ -External (\_PR.CPU0._TSS, MethodObj) -External (\_PR.CPU0._TPC, MethodObj) -External (\_PR.CPU0._PTC, PkgObj) -External (\_PR.CPU0._TSD, PkgObj) -External (\_PR.CPU0._PSS, MethodObj) +External (\_PR.CP00._TSS, MethodObj) +External (\_PR.CP00._TPC, MethodObj) +External (\_PR.CP00._PTC, PkgObj) +External (\_PR.CP00._TSD, PkgObj) +External (\_PR.CP00._PSS, MethodObj) Device (TCPU) { @@ -24,8 +24,8 @@ Device (TCPU) Method (_TSS) { - If (CondRefOf (\_PR.CPU0._TSS)) { - Return (\_PR.CPU0._TSS) + If (CondRefOf (\_PR.CP00._TSS)) { + Return (\_PR.CP00._TSS) } Else { Return (Package () { @@ -36,8 +36,8 @@ Device (TCPU) Method (_TPC) { - If (CondRefOf (\_PR.CPU0._TPC)) { - Return (\_PR.CPU0._TPC) + If (CondRefOf (\_PR.CP00._TPC)) { + Return (\_PR.CP00._TPC) } Else { Return (0) } @@ -45,8 +45,8 @@ Device (TCPU) Method (_PTC) { - If (CondRefOf (\_PR.CPU0._PTC)) { - Return (\_PR.CPU0._PTC) + If (CondRefOf (\_PR.CP00._PTC)) { + Return (\_PR.CP00._PTC) } Else { Return (Package () { @@ -58,8 +58,8 @@ Device (TCPU) Method (_TSD) { - If (CondRefOf (\_PR.CPU0._TSD)) { - Return (\_PR.CPU0._TSD) + If (CondRefOf (\_PR.CP00._TSD)) { + Return (\_PR.CP00._TSD) } Else { Return (Package () { @@ -70,8 +70,8 @@ Device (TCPU) Method (_TDL) { - If (CondRefOf (\_PR.CPU0._TSS)) { - Store (SizeOf (\_PR.CPU0._TSS ()), Local0) + If (CondRefOf (\_PR.CP00._TSS)) { + Store (SizeOf (\_PR.CP00._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -98,8 +98,8 @@ Device (TCPU) Method (_PSS) { - If (CondRefOf (\_PR.CPU0._PSS)) { - Return (\_PR.CPU0._PSS) + If (CondRefOf (\_PR.CP00._PSS)) { + Return (\_PR.CP00._PSS) } Else { Return (Package () { @@ -113,8 +113,8 @@ Device (TCPU) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CPU0._PSS)) { - Store (SizeOf (\_PR.CPU0._PSS ()), Local0) + } ElseIf (CondRefOf (\_PR.CP00._PSS)) { + Store (SizeOf (\_PR.CP00._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else { diff --git a/src/soc/intel/broadwell/acpi/cpu.asl b/src/soc/intel/broadwell/acpi/cpu.asl index f0da2de..2921cea 100644 --- a/src/soc/intel/broadwell/acpi/cpu.asl +++ b/src/soc/intel/broadwell/acpi/cpu.asl @@ -18,31 +18,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -50,18 +50,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -69,18 +69,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,33 +90,33 @@ Method (PPKG) If (LGreaterEqual (\PCNT, 8)) { Return (Package() { - \_PR.CPU0, - \_PR.CPU1, - \_PR.CPU2, - \_PR.CPU3, - \_PR.CPU4, - \_PR.CPU5, - \_PR.CPU6, - \_PR.CPU7 + \_PR.CP00, + \_PR.CP01, + \_PR.CP02, + \_PR.CP03, + \_PR.CP04, + \_PR.CP05, + \_PR.CP06, + \_PR.CP07 }) } ElseIf (LGreaterEqual (\PCNT, 4)) { Return (Package () { - \_PR.CPU0, - \_PR.CPU1, - \_PR.CPU2, - \_PR.CPU3 + \_PR.CP00, + \_PR.CP01, + \_PR.CP02, + \_PR.CP03 }) } ElseIf (LGreaterEqual (\PCNT, 2)) { Return (Package () { - \_PR.CPU0, - \_PR.CPU1 + \_PR.CP00, + \_PR.CP01 }) } Else { Return (Package () { - \_PR.CPU0 + \_PR.CP00 }) } } diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index 2aefda9..a2a8fb4 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -76,16 +76,16 @@ Scope (\_SB.PCI0.MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/soc/intel/fsp_baytrail/acpi/cpu.asl b/src/soc/intel/fsp_baytrail/acpi/cpu.asl index 16f62ba..f7e404d 100644 --- a/src/soc/intel/fsp_baytrail/acpi/cpu.asl +++ b/src/soc/intel/fsp_baytrail/acpi/cpu.asl @@ -20,21 +20,21 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } } @@ -42,12 +42,12 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } } @@ -55,12 +55,12 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } } @@ -68,10 +68,10 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index fd2c268..b51edfb 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -147,7 +147,7 @@ static void hudson_init_acpi_ports(void) pm_write16(0x62, ACPI_PM1_CNT_BLK); pm_write16(0x64, ACPI_PM_TMR_BLK); pm_write16(0x68, ACPI_GPE0_BLK); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(0x66, ACPI_CPU_CONTROL); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 9442edc..2931328 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -83,7 +83,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) val = GPE0_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ val = CPU_CNT_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); val = 0; diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index e5382b4..2d40d3f 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -107,7 +107,7 @@ static void hudson_init_acpi_ports(void) pm_write16(0x62, ACPI_PM1_CNT_BLK); pm_write16(0x64, ACPI_PM_TMR_BLK); pm_write16(0x68, ACPI_GPE0_BLK); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(0x66, ACPI_CPU_CONTROL); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 855cbc4..94f33b7 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -56,7 +56,7 @@ static void sb700_acpi_init(void) pmio_write(0x28, ACPI_GPE0_BLK & 0xFF); pmio_write(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pmio_write(0x26, ACPI_CPU_CONTROL & 0xFF); pmio_write(0x27, ACPI_CPU_CONTROL >> 8); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 24aa200..69bc3bd 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -53,7 +53,7 @@ static void sb800_acpi_init(void) pmio_write(0x68, ACPI_GPE0_BLK & 0xFF); pmio_write(0x69, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pmio_write(0x66, ACPI_CPU_CONTROL & 0xFF); pmio_write(0x67, ACPI_CPU_CONTROL >> 8);

1 0

Patch set updated for coreboot: a67f91f drivers/intel/i210: Add new driver for Intel i210 MACPHY
by Werner Zeh 11 Feb '15

11 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8404 -gerrit commit a67f91fdbebde8bee1fab9f1699862ac06cd0016 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 15:09:00 2015 +0100 drivers/intel/i210: Add new driver for Intel i210 MACPHY Add a new driver for Intel i210 MACPHY with the goal to update the MAC address in i210 if it is found during PCI scan. Change-Id: I4d4e797543a9f278fb649596f63ae8e1f285b3c3 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/intel/Makefile.inc | 1 + src/drivers/intel/i210/Makefile.inc | 1 + src/drivers/intel/i210/i210.c | 241 ++++++++++++++++++++++++++++++++++++ src/drivers/intel/i210/i210.h | 56 +++++++++ 4 files changed, 299 insertions(+) diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc index 7bc6dd5..6cf8f00 100644 --- a/src/drivers/intel/Makefile.inc +++ b/src/drivers/intel/Makefile.inc @@ -1,3 +1,4 @@ subdirs-y += gma subdirs-y += wifi subdirs-$(CONFIG_PLATFORM_USES_FSP) += fsp +subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210 \ No newline at end of file diff --git a/src/drivers/intel/i210/Makefile.inc b/src/drivers/intel/i210/Makefile.inc new file mode 100644 index 0000000..a1f15de --- /dev/null +++ b/src/drivers/intel/i210/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += i210.c \ No newline at end of file diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c new file mode 100644 index 0000000..76326a8 --- /dev/null +++ b/src/drivers/intel/i210/i210.c @@ -0,0 +1,241 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "i210.h" +#include <device/device.h> +#include <console/console.h> +#include <string.h> +#include <types.h> + +/* We need one function we can call to get a MAC address to use */ +/* This function can be coded somewhere else but must exist. */ +extern enum cb_err get_mac_address(u32 pci_bdf, u8 mac[6]); + +/* This is a private function to wait for a bit mask in a given register */ +/* To avoid endless loops, a time-out is implemented here. */ +static int wait_done(u32* reg, u32 mask) +{ + u32 timeout = I210_POLL_TIMEOUT_US; + do { + if (!(*reg & mask)) { + udelay(1); + timeout--; + } + } while((!(*reg & mask)) && timeout); + return timeout ? I210_NO_ERROR : I210_NOT_READY; +} + +/** \brief This function is the driver entry point for the init phase + * of the PCI bus allocator. It will program a MAC address + * into the MACPHY. + * @param *dev Pointer to the used PCI device + * @return void Nothing is given back + */ +static void init(struct device *dev) +{ + u8 cur_adr[6]; + u8 adr_to_set[6]; + enum cb_err status; + + /*Check first whether there is a valid MAC address available */ + status = get_mac_address((dev->bus->subordinate << 16) | + dev->path.pci.devfn << 8, adr_to_set); + if (status != CB_SUCCESS) { + printk(BIOS_ERR, "I210: No valid MAC address found\n"); + return; + } + /* Before we will write a new address, check the existing one */ + if (read_mac_adr(dev, cur_adr)) { + printk(BIOS_ERR, "I210: Not able to read MAC address.\n"); + return; + } + if (memcmp(cur_adr, adr_to_set, 6)) { + if (write_mac_adr(dev, adr_to_set)) { + printk(BIOS_ERR, "I210: Error setting MAC address\n"); + } else { + printk(BIOS_INFO, "I210: MAC address changed.\n"); + } + } else { + printk(BIOS_INFO, "I210: MAC address is up to date.\n"); + } + return; +} + +/** \brief This function can read the MAC address out of the MACPHY + * @param *dev Pointer to the PCI device of this MACPHY + * @param *MACAdr Pointer to the buffer where to store read MAC address + * @return void I210_NO_ERROR or an error code + */ +static u32 read_mac_adr(struct device *dev, u8 *MACAdr) +{ + u16 adr[3]; + if (!dev || !MACAdr) + return I210_INVALID_PARAM; + if (read_flash(dev, 0, 3, adr)) + return I210_READ_ERROR; + /* Copy the address into destination. This is done because of */ + /* possible not matching alignment for destination to u16 boundary. */ + memcpy(MACAdr, (u8*)adr, 6); + return I210_NO_ERROR; +} + +/** \brief This function can write the MAC address to the MACPHY + * @param *dev Pointer to the PCI device of this MACPHY + * @param *MACAdr Pointer to the buffer where the desired MAC address is + * @return void I210_NO_ERROR or an error code + */ +static u32 write_mac_adr(struct device *dev, u8 *MACAdr) +{ + u16 adr[3]; + if (!dev || !MACAdr) + return I210_INVALID_PARAM; + /* Copy desired address into a local buffer to avoid alignment issues */ + memcpy((u8*)adr, MACAdr, 6); + return write_flash(dev, 0, 3, adr); +} + +/** \brief This function can read the configuration space of the MACPHY + * For this purpose, the EEPROM interface is used. No direct access + * to the flash memory will be done. + * @param *dev Pointer to the PCI device of this MACPHY + * @param address Address inside the flash where reading will start + * @param count Number of words (16 bit values) to read + * @param *buffer Pointer to the buffer where to store read data + * @return void I210_NO_ERROR or an error code + */ +static u32 read_flash(struct device *dev, u32 address, u32 count, u16 *buffer) +{ + u32 bar; + u32 *eeprd; + u32 i; + + /* Get the BAR to memory mapped space*/ + bar = pci_read_config32(dev, 0x10); + if ((!bar) || ((address + count) > 0x40)) + return I210_INVALID_PARAM; + eeprd = (u32*)(bar + I210_REG_EEREAD); + /* Prior to start ensure flash interface is ready by checking DONE-bit */ + if (wait_done(eeprd, I210_DONE)) + return I210_NOT_READY; + + /*OK, interface is ready, we can use it now */ + for (i = 0; i < count; i++) { + /* To start a read cycle write desired address in bits 12..2 */ + *eeprd = ((address + i) << 2) & 0x1FFC; + /* Wait until read is done */ + if (wait_done(eeprd, I210_DONE)) + return I210_READ_ERROR; + /* Here, we can read back desired word in bits 31..16 */ + buffer[i] = (*eeprd & 0xffff0000) >> 16; + } + return I210_NO_ERROR; +} + +/** \brief This function can write the configuration space of the MACPHY + * For this purpose, the EEPROM interface is used. No direct access + * to the flash memory will be done. This function will update + * the checksum after a value was changed. + * @param *dev Pointer to the PCI device of this MACPHY + * @param address Address inside the flash where writing will start + * @param count Number of words (16 bit values) to write + * @param *buffer Pointer to the buffer where data to write is stored in + * @return void I210_NO_ERROR or an error code + */ +static u32 write_flash(struct device *dev, u32 address, u32 count, u16 *buffer) +{ + u32 bar; + u32 *eepwr; + u32 *eectrl; + u16 checksum; + u32 i; + + /* Get the BAR to memory mapped space */ + bar = pci_read_config32(dev, 0x10); + if ((!bar) || ((address + count) > 0x40)) + return I210_INVALID_PARAM; + eepwr = (u32*)(bar + I210_REG_EEWRITE); + eectrl = (u32*)(bar + I210_REG_EECTRL); + /* Prior to start ensure flash interface is ready by checking DONE-bit */ + if (wait_done(eepwr, I210_DONE)) + return I210_NOT_READY; + + /* OK, interface is ready, we can use it now */ + for (i = 0; i < count; i++) { + /* To start a write cycle write desired address in bits 12..2 */ + /* and data to write in bits 31..16 into EEWRITE-register */ + *eepwr = ((((address + i) << 2) & 0x1FFC) | (buffer[i] << 16)); + /* Wait until write is done */ + if (wait_done(eepwr, I210_DONE)) + return I210_WRITE_ERROR; + } + /* Since we have modified data, we need to update the checksum */ + if (compute_checksum(dev, &checksum)) + return I210_CHECKSUM_ERROR; + *eepwr = (0x3f << 2) | checksum << 16; + if (wait_done(eepwr, I210_DONE)) + return I210_WRITE_ERROR; + /* Up to now, desired data was written into shadowed RAM. We now need */ + /* to perform a flash cycle to bring the shadowed RAM into flash memory. */ + /* To start a flash cycle we need to set FLUPD-bit and wait for FLDONE. */ + *eectrl = *eectrl | I210_FLUPD; + if (wait_done(eectrl, I210_FLUDONE)) + return I210_FLASH_UPDATE_ERROR; + else + return I210_NO_ERROR; +} + +/** \brief This function computes the checksum for the configuration space. + * The address range for the checksum is 0x00..0x3e. + * @param *dev Pointer to the PCI device of this MACPHY + * @param *checksum Pointer to the buffer where to store the checksum + * @return void I210_NO_ERROR or an error code + */ +static u32 compute_checksum(struct device *dev, u16 *checksum) +{ + u16 eep_data[0x40]; + u32 i; + + /* First read back data to compute the checksum for */ + if (read_flash(dev, 0, 0x3f, eep_data)) + return I210_READ_ERROR; + /* The checksum is computed in that way that after summarize all the */ + /* data from word address 0 to 0x3f the result is 0xBABA. */ + *checksum = 0; + for (i = 0; i < 0x3f; i++) + *checksum += eep_data[i]; + *checksum = I210_TARGET_CHECKSUM - *checksum; + return I210_NO_ERROR; +} + +static struct device_operations i210_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = init, + .scan_bus = 0, + .ops_pci = 0, +}; + +static const unsigned short i210_device_ids[] = { 0x1538, 0x1533, 0 }; + +static const struct pci_driver i210_driver __pci_driver = { + .ops = &i210_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = i210_device_ids, +}; diff --git a/src/drivers/intel/i210/i210.h b/src/drivers/intel/i210/i210.h new file mode 100644 index 0000000..c1fd58a --- /dev/null +++ b/src/drivers/intel/i210/i210.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _INTEL_I210_H_ +#define _INTEL_I210_H_ +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <delay.h> + +#define I210_PCI_MEM_BAR_OFFSET 0x10 +#define I210_REG_EECTRL 0x12010 /* Offset for EEPROM control reg */ +#define I210_FLUPD 0x800000 /* Start flash update bit */ +#define I210_FLUDONE 0x4000000 /* Flash update done indicator */ +#define I210_REG_EEREAD 0x12014 /* Offset for EEPROM read reg */ +#define I210_REG_EEWRITE 0x12018 /* Offset for EEPROM write reg */ +#define I210_CMDV 0x01 /* command valid bit */ +#define I210_DONE 0x02 /* command done bit */ +#define I210_TARGET_CHECKSUM 0xBABA /* resulting checksum */ + + +/*define some other useful values here */ +#define I210_POLL_TIMEOUT_US 300000 /* 300 ms */ +/*Define some error states here*/ +#define I210_NO_ERROR 0x00000000 +#define I210_INVALID_PARAM 0x00000001 +#define I210_NOT_READY 0x00000002 +#define I210_READ_ERROR 0x00000004 +#define I210_WRITE_ERROR 0x00000008 +#define I210_CHECKSUM_ERROR 0x00000010 +#define I210_FLASH_UPDATE_ERROR 0x00000020 + +static void init(struct device *dev); +static u32 read_mac_adr(struct device *dev, u8 *MACAdr); +static u32 write_mac_adr(struct device *dev, u8 *MACAdr); +static u32 read_flash(struct device *dev, u32 address, u32 count, u16 *buffer); +static u32 write_flash(struct device *dev, u32 address, u32 count, u16 *buffer); +static u32 compute_checksum(struct device *dev, u16 *checksum); + +#endif /* _INTEL_I210_H_ */

1 0

Patch set updated for coreboot: 82f859e acpi: Generate valid ACPI processor objects
by Timothy Pearson 11 Feb '15

11 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8422 -gerrit commit 82f859e09d2fa7e24f69ec7a72e4c469bf71f5fa Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 10 22:21:39 2015 -0600 acpi: Generate valid ACPI processor objects The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/arch/x86/boot/acpigen.c | 2 +- src/cpu/intel/fsp_model_206ax/acpi/cpu.asl | 74 ++++++++--------- src/cpu/intel/fsp_model_406dx/acpi/cpu.asl | 74 ++++++++--------- src/cpu/intel/haswell/acpi/cpu.asl | 74 ++++++++--------- src/cpu/intel/model_206ax/acpi/cpu.asl | 74 ++++++++--------- src/ec/quanta/ene_kb3940q/acpi/ec.asl | 10 +-- src/mainboard/amd/dbm690t/fadt.c | 2 +- src/mainboard/amd/pistachio/fadt.c | 2 +- src/mainboard/amd/torpedo/fadt.c | 2 +- src/mainboard/getac/p470/acpi/ec.asl | 2 +- src/mainboard/getac/p470/acpi/platform.asl | 10 +-- src/mainboard/getac/p470/acpi/thermal.asl | 4 +- src/mainboard/ibase/mb899/acpi/thermal.asl | 4 +- src/mainboard/intel/d945gclf/acpi/thermal.asl | 4 +- src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl | 4 +- src/mainboard/kontron/986lcd-m/acpi/thermal.asl | 4 +- src/mainboard/kontron/kt690/fadt.c | 2 +- src/mainboard/roda/rk886ex/acpi/thermal.asl | 4 +- src/mainboard/roda/rk9/acpi/thermal.asl | 4 +- .../siemens/sitemp_g1p1/acpi/platform.asl | 4 +- src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl | 4 +- src/mainboard/siemens/sitemp_g1p1/fadt.c | 2 +- src/mainboard/technexion/tim5690/fadt.c | 2 +- src/mainboard/technexion/tim8690/fadt.c | 2 +- src/mainboard/via/vt8454c/dsdt.asl | 2 +- src/northbridge/amd/amdk8/thermal_mixin.asl | 6 +- .../intel/fsp_sandybridge/acpi/hostbridge.asl | 6 +- src/northbridge/intel/haswell/acpi/hostbridge.asl | 6 +- src/northbridge/intel/nehalem/acpi/hostbridge.asl | 6 +- .../intel/sandybridge/acpi/hostbridge.asl | 6 +- src/soc/intel/baytrail/acpi/cpu.asl | 38 ++++----- src/soc/intel/baytrail/acpi/dptf/cpu.asl | 38 ++++----- src/soc/intel/broadwell/acpi/cpu.asl | 94 +++++++++++----------- src/soc/intel/broadwell/acpi/ctdp.asl | 6 +- src/soc/intel/fsp_baytrail/acpi/cpu.asl | 38 ++++----- src/southbridge/amd/agesa/hudson/hudson.c | 2 +- src/southbridge/amd/cimx/sb800/fadt.c | 2 +- src/southbridge/amd/pi/hudson/hudson.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- 40 files changed, 313 insertions(+), 313 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 8e7ce46..76fe2d6 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -293,7 +293,7 @@ int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) len = acpigen_write_len_f(); snprintf(pscope, sizeof (pscope), - "\\_PR.CPU%x", (unsigned int) cpuindex); + "\\_PR.CP%02d", (unsigned int) cpuindex); len += acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex); acpigen_emit_byte(pblock_addr & 0xff); diff --git a/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl b/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl index 558a9d3..472ac08 100644 --- a/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl +++ b/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl @@ -20,31 +20,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -52,18 +52,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -71,18 +71,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,13 +90,13 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, + \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl b/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl index 558a9d3..472ac08 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl +++ b/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl @@ -20,31 +20,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -52,18 +52,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -71,18 +71,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,13 +90,13 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, + \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/cpu/intel/haswell/acpi/cpu.asl b/src/cpu/intel/haswell/acpi/cpu.asl index 558a9d3..472ac08 100644 --- a/src/cpu/intel/haswell/acpi/cpu.asl +++ b/src/cpu/intel/haswell/acpi/cpu.asl @@ -20,31 +20,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -52,18 +52,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -71,18 +71,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,13 +90,13 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, + \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/cpu/intel/model_206ax/acpi/cpu.asl b/src/cpu/intel/model_206ax/acpi/cpu.asl index 558a9d3..472ac08 100644 --- a/src/cpu/intel/model_206ax/acpi/cpu.asl +++ b/src/cpu/intel/model_206ax/acpi/cpu.asl @@ -20,31 +20,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -52,18 +52,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -71,18 +71,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,13 +90,13 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, + \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 4e703fe..3d9aa62 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -23,7 +23,7 @@ * re-evaluate their _PPC and _CST tables. */ -External (\_PR.CPU0._PPC, IntObj) +External (\_PR.CP00._PPC, IntObj) Device (EC0) { @@ -148,12 +148,12 @@ Device (EC0) Store (CTMP, Local0) // Find and program number of P-States - Store (SizeOf (\_PR.CPU0._PSS), MPST) + Store (SizeOf (\_PR.CP00._PSS), MPST) Store ("Programming number of P-states: ", Debug) Store (MPST, Debug) // Find and program the current P-State - Store(\_PR.CPU0._PPC, NPST) + Store(\_PR.CP00._PPC, NPST) Store ("Programming Current P-state: ", Debug) Store (NPST, Debug) } @@ -192,7 +192,7 @@ Device (EC0) { Store ("Pstate Event 0x0E", Debug) - Store(\_PR.CPU0._PPC, Local0) + Store(\_PR.CP00._PPC, Local0) Subtract(PPCM, 0x01, Local1) If(LLess(Local0, Local1)) { @@ -207,7 +207,7 @@ Device (EC0) Method (_Q0F) { Store ("Pstate Event 0x0F", Debug) - Store(\_PR.CPU0._PPC, Local0) + Store(\_PR.CP00._PPC, Local0) If(Local0) { Decrement(Local0) diff --git a/src/mainboard/amd/dbm690t/fadt.c b/src/mainboard/amd/dbm690t/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/amd/dbm690t/fadt.c +++ b/src/mainboard/amd/dbm690t/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/amd/pistachio/fadt.c +++ b/src/mainboard/amd/pistachio/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 4bc88ac..5d66791 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -81,7 +81,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) val = GPE0_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ val = CPU_CNT_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); val = 0; diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 1b1c157..70e4224 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -105,7 +105,7 @@ Device(EC0) // EC Query methods, called upon SCI interrupts. Method (_Q01, 0) { - Notify (\_PR.CPU0, 0x80) + Notify (\_PR.CP00, 0x80) If(ADP) { Store(1, \_SB.AC.ACST) TRAP(0xe3) diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index 2b081e0..cad5a71 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -95,15 +95,15 @@ Method(_WAK,1) // Windows XP SP2 P-State restore If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) { - If (LGreater(\_PR.CPU0._PPC, 0)) { - Subtract(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + If (LGreater(\_PR.CP00._PPC, 0)) { + Subtract(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) PNOT() - Add(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + Add(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) PNOT() } Else { - Add(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + Add(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) PNOT() - Subtract(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + Subtract(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) PNOT() } } diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl index eefc1b7..f103561 100644 --- a/src/mainboard/getac/p470/acpi/thermal.asl +++ b/src/mainboard/getac/p470/acpi/thermal.asl @@ -79,9 +79,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } // TC1 value for passive cooling diff --git a/src/mainboard/ibase/mb899/acpi/thermal.asl b/src/mainboard/ibase/mb899/acpi/thermal.asl index 128d677..c5994d5 100644 --- a/src/mainboard/ibase/mb899/acpi/thermal.asl +++ b/src/mainboard/ibase/mb899/acpi/thermal.asl @@ -65,9 +65,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU1, \_PR.CPU2}) + Return (Package() {\_PR.CP01, \_PR.CP02}) } - Return (Package() {\_PR.CPU1}) + Return (Package() {\_PR.CP01}) } // TC1 value for passive cooling diff --git a/src/mainboard/intel/d945gclf/acpi/thermal.asl b/src/mainboard/intel/d945gclf/acpi/thermal.asl index fc9f24e..10e241d 100644 --- a/src/mainboard/intel/d945gclf/acpi/thermal.asl +++ b/src/mainboard/intel/d945gclf/acpi/thermal.asl @@ -65,9 +65,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU1, \_PR.CPU2}) + Return (Package() {\_PR.CP01, \_PR.CP02}) } - Return (Package() {\_PR.CPU1}) + Return (Package() {\_PR.CP01}) } // TC1 value for passive cooling diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl b/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl index 5330309..1ba2338 100644 --- a/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl +++ b/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl @@ -67,9 +67,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU1, \_PR.CPU2}) + Return (Package() {\_PR.CP01, \_PR.CP02}) } - Return (Package() {\_PR.CPU1}) + Return (Package() {\_PR.CP01}) } // TC1 value for passive cooling diff --git a/src/mainboard/kontron/986lcd-m/acpi/thermal.asl b/src/mainboard/kontron/986lcd-m/acpi/thermal.asl index 128d677..c5994d5 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/thermal.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/thermal.asl @@ -65,9 +65,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU1, \_PR.CPU2}) + Return (Package() {\_PR.CP01, \_PR.CP02}) } - Return (Package() {\_PR.CPU1}) + Return (Package() {\_PR.CP01}) } // TC1 value for passive cooling diff --git a/src/mainboard/kontron/kt690/fadt.c b/src/mainboard/kontron/kt690/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/kontron/kt690/fadt.c +++ b/src/mainboard/kontron/kt690/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl index e445d3c..873b089 100644 --- a/src/mainboard/roda/rk886ex/acpi/thermal.asl +++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl @@ -67,9 +67,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } // TC1 value for passive cooling diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl index 6e28f17..f4868b4 100644 --- a/src/mainboard/roda/rk9/acpi/thermal.asl +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -86,9 +86,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } // TC1 value for passive cooling diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl index 8af607d..37daa36 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl @@ -30,8 +30,8 @@ Method(_PIC, 1, NotSerialized) } } -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) Scope(\_SB) { diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl index 02b1df1..fbcd0e7 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl @@ -56,9 +56,9 @@ Scope(\_TZ) { Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ diff --git a/src/mainboard/siemens/sitemp_g1p1/fadt.c b/src/mainboard/siemens/sitemp_g1p1/fadt.c index f9acfe4..d62caa0 100644 --- a/src/mainboard/siemens/sitemp_g1p1/fadt.c +++ b/src/mainboard/siemens/sitemp_g1p1/fadt.c @@ -80,7 +80,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/technexion/tim5690/fadt.c b/src/mainboard/technexion/tim5690/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/technexion/tim5690/fadt.c +++ b/src/mainboard/technexion/tim5690/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/technexion/tim8690/fadt.c b/src/mainboard/technexion/tim8690/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/technexion/tim8690/fadt.c +++ b/src/mainboard/technexion/tim8690/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/via/vt8454c/dsdt.asl b/src/mainboard/via/vt8454c/dsdt.asl index d13a6b7..4901041 100644 --- a/src/mainboard/via/vt8454c/dsdt.asl +++ b/src/mainboard/via/vt8454c/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) */ Scope (\_PR) { - Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {} + Processor (\_PR.CP00, 0x00, 0x00000410, 0x06) {} } /* For now only define 2 power states: diff --git a/src/northbridge/amd/amdk8/thermal_mixin.asl b/src/northbridge/amd/amdk8/thermal_mixin.asl index 62590ff..f6257a6 100644 --- a/src/northbridge/amd/amdk8/thermal_mixin.asl +++ b/src/northbridge/amd/amdk8/thermal_mixin.asl @@ -139,7 +139,7 @@ ThermalZone (K8T1) { Name(_UID, "k8-1") Name(_STR, Unicode("K8 compatible CPU Core 1 Thermal Sensor 2")) - Name(_TZD, Package () {\_PR.CPU0}) + Name(_TZD, Package () {\_PR.CP00}) Method(_STA) { Store(CORE, Local0) @@ -190,7 +190,7 @@ ThermalZone (K8T2) { Name(_UID, "k8-2") Name(_STR, Unicode("K8 compatible CPU Core 2 Thermal Sensor 1")) - Name(_TZD, Package () {\_PR.CPU0}) + Name(_TZD, Package () {\_PR.CP00}) Method(_STA) { Store(CORE, Local0) @@ -241,7 +241,7 @@ ThermalZone (K8T3) { Name(_UID, "k8-3") Name(_STR, Unicode("K8 compatible CPU Core 2 Thermal Sensor 2")) - Name(_TZD, Package () {\_PR.CPU0}) + Name(_TZD, Package () {\_PR.CP00}) Method(_STA) { Store(CORE, Local0) diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl index e569cf3..e82758c 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl @@ -147,16 +147,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index bb8e95e..9bc5549 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -157,16 +157,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index 79736bc..d210a95 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -109,16 +109,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 4279271..26f7514 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -147,16 +147,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/soc/intel/baytrail/acpi/cpu.asl b/src/soc/intel/baytrail/acpi/cpu.asl index 16f62ba..f7e404d 100644 --- a/src/soc/intel/baytrail/acpi/cpu.asl +++ b/src/soc/intel/baytrail/acpi/cpu.asl @@ -20,21 +20,21 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } } @@ -42,12 +42,12 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } } @@ -55,12 +55,12 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } } @@ -68,10 +68,10 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl index 3cbfc5f..58c1c7b 100644 --- a/src/soc/intel/baytrail/acpi/dptf/cpu.asl +++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl @@ -1,8 +1,8 @@ -External (\_PR.CPU0._TSS, MethodObj) -External (\_PR.CPU0._TPC, MethodObj) -External (\_PR.CPU0._PTC, PkgObj) -External (\_PR.CPU0._TSD, PkgObj) -External (\_PR.CPU0._PSS, MethodObj) +External (\_PR.CP00._TSS, MethodObj) +External (\_PR.CP00._TPC, MethodObj) +External (\_PR.CP00._PTC, PkgObj) +External (\_PR.CP00._TSD, PkgObj) +External (\_PR.CP00._PSS, MethodObj) Device (TCPU) { @@ -24,8 +24,8 @@ Device (TCPU) Method (_TSS) { - If (CondRefOf (\_PR.CPU0._TSS)) { - Return (\_PR.CPU0._TSS) + If (CondRefOf (\_PR.CP00._TSS)) { + Return (\_PR.CP00._TSS) } Else { Return (Package () { @@ -36,8 +36,8 @@ Device (TCPU) Method (_TPC) { - If (CondRefOf (\_PR.CPU0._TPC)) { - Return (\_PR.CPU0._TPC) + If (CondRefOf (\_PR.CP00._TPC)) { + Return (\_PR.CP00._TPC) } Else { Return (0) } @@ -45,8 +45,8 @@ Device (TCPU) Method (_PTC) { - If (CondRefOf (\_PR.CPU0._PTC)) { - Return (\_PR.CPU0._PTC) + If (CondRefOf (\_PR.CP00._PTC)) { + Return (\_PR.CP00._PTC) } Else { Return (Package () { @@ -58,8 +58,8 @@ Device (TCPU) Method (_TSD) { - If (CondRefOf (\_PR.CPU0._TSD)) { - Return (\_PR.CPU0._TSD) + If (CondRefOf (\_PR.CP00._TSD)) { + Return (\_PR.CP00._TSD) } Else { Return (Package () { @@ -70,8 +70,8 @@ Device (TCPU) Method (_TDL) { - If (CondRefOf (\_PR.CPU0._TSS)) { - Store (SizeOf (\_PR.CPU0._TSS ()), Local0) + If (CondRefOf (\_PR.CP00._TSS)) { + Store (SizeOf (\_PR.CP00._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -98,8 +98,8 @@ Device (TCPU) Method (_PSS) { - If (CondRefOf (\_PR.CPU0._PSS)) { - Return (\_PR.CPU0._PSS) + If (CondRefOf (\_PR.CP00._PSS)) { + Return (\_PR.CP00._PSS) } Else { Return (Package () { @@ -113,8 +113,8 @@ Device (TCPU) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CPU0._PSS)) { - Store (SizeOf (\_PR.CPU0._PSS ()), Local0) + } ElseIf (CondRefOf (\_PR.CP00._PSS)) { + Store (SizeOf (\_PR.CP00._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else { diff --git a/src/soc/intel/broadwell/acpi/cpu.asl b/src/soc/intel/broadwell/acpi/cpu.asl index f0da2de..2921cea 100644 --- a/src/soc/intel/broadwell/acpi/cpu.asl +++ b/src/soc/intel/broadwell/acpi/cpu.asl @@ -18,31 +18,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -50,18 +50,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -69,18 +69,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,33 +90,33 @@ Method (PPKG) If (LGreaterEqual (\PCNT, 8)) { Return (Package() { - \_PR.CPU0, - \_PR.CPU1, - \_PR.CPU2, - \_PR.CPU3, - \_PR.CPU4, - \_PR.CPU5, - \_PR.CPU6, - \_PR.CPU7 + \_PR.CP00, + \_PR.CP01, + \_PR.CP02, + \_PR.CP03, + \_PR.CP04, + \_PR.CP05, + \_PR.CP06, + \_PR.CP07 }) } ElseIf (LGreaterEqual (\PCNT, 4)) { Return (Package () { - \_PR.CPU0, - \_PR.CPU1, - \_PR.CPU2, - \_PR.CPU3 + \_PR.CP00, + \_PR.CP01, + \_PR.CP02, + \_PR.CP03 }) } ElseIf (LGreaterEqual (\PCNT, 2)) { Return (Package () { - \_PR.CPU0, - \_PR.CPU1 + \_PR.CP00, + \_PR.CP01 }) } Else { Return (Package () { - \_PR.CPU0 + \_PR.CP00 }) } } diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index 2aefda9..a2a8fb4 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -76,16 +76,16 @@ Scope (\_SB.PCI0.MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/soc/intel/fsp_baytrail/acpi/cpu.asl b/src/soc/intel/fsp_baytrail/acpi/cpu.asl index 16f62ba..f7e404d 100644 --- a/src/soc/intel/fsp_baytrail/acpi/cpu.asl +++ b/src/soc/intel/fsp_baytrail/acpi/cpu.asl @@ -20,21 +20,21 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } } @@ -42,12 +42,12 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } } @@ -55,12 +55,12 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } } @@ -68,10 +68,10 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index fd2c268..b51edfb 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -147,7 +147,7 @@ static void hudson_init_acpi_ports(void) pm_write16(0x62, ACPI_PM1_CNT_BLK); pm_write16(0x64, ACPI_PM_TMR_BLK); pm_write16(0x68, ACPI_GPE0_BLK); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(0x66, ACPI_CPU_CONTROL); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 9442edc..2931328 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -83,7 +83,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) val = GPE0_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ val = CPU_CNT_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); val = 0; diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index e5382b4..2d40d3f 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -107,7 +107,7 @@ static void hudson_init_acpi_ports(void) pm_write16(0x62, ACPI_PM1_CNT_BLK); pm_write16(0x64, ACPI_PM_TMR_BLK); pm_write16(0x68, ACPI_GPE0_BLK); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(0x66, ACPI_CPU_CONTROL); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 855cbc4..94f33b7 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -56,7 +56,7 @@ static void sb700_acpi_init(void) pmio_write(0x28, ACPI_GPE0_BLK & 0xFF); pmio_write(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pmio_write(0x26, ACPI_CPU_CONTROL & 0xFF); pmio_write(0x27, ACPI_CPU_CONTROL >> 8); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 24aa200..69bc3bd 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -53,7 +53,7 @@ static void sb800_acpi_init(void) pmio_write(0x68, ACPI_GPE0_BLK & 0xFF); pmio_write(0x69, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pmio_write(0x66, ACPI_CPU_CONTROL & 0xFF); pmio_write(0x67, ACPI_CPU_CONTROL >> 8);

1 0

Patch set updated for coreboot: 2dc2d85 fsp_baytrail: Add I2C driver
by Werner Zeh 11 Feb '15

11 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8401 -gerrit commit 2dc2d85176d62bcc19fe04a8aefe0a3080372347 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 13:02:34 2015 +0100 fsp_baytrail: Add I2C driver Add a driver wich can handle the internal I2C controllers of Baytrail SoC. This driver is not suitable for the SMBUS-controller. Change-Id: I841c3991a2fb0f8b92b8e59ec02d62f5866f5bdf Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Makefile.inc | 1 + src/soc/intel/fsp_baytrail/baytrail/i2c.h | 138 +++++++++++++++ src/soc/intel/fsp_baytrail/i2c.c | 269 ++++++++++++++++++++++++++++++ 3 files changed, 408 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 3896e85..2dfb9cb 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -54,6 +54,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c +ramstage-y += i2c.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/ CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp diff --git a/src/soc/intel/fsp_baytrail/baytrail/i2c.h b/src/soc/intel/fsp_baytrail/baytrail/i2c.h new file mode 100644 index 0000000..3799fbb --- /dev/null +++ b/src/soc/intel/fsp_baytrail/baytrail/i2c.h @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ +#define __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> + +/* SMBus controller settings in PCI configuration space*/ +#define I2C_PCI_VENDOR_ID 0x8086 +#define I2C0_PCI_DEV_ID 0x0f41 +#define I2C1_PCI_DEV_ID 0x0f42 +#define I2C2_PCI_DEV_ID 0x0f43 +#define I2C3_PCI_DEV_ID 0x0f44 +#define I2C4_PCI_DEV_ID 0x0f45 +#define I2C5_PCI_DEV_ID 0x0f46 +#define I2C6_PCI_DEV_ID 0x0f47 + +#define I2C0_MEM_BASE 0xd0921000 +#define I2C1_MEM_BASE 0xd0923000 +#define I2C2_MEM_BASE 0xd0925000 +#define I2C3_MEM_BASE 0xd0927000 +#define I2C4_MEM_BASE 0xd0929000 +#define I2C5_MEM_BASE 0xd092b000 +#define I2C6_MEM_BASE 0xd092d000 + +#define I2C_STANDARD_MODE 0x1 +#define I2C_FAST_MODE 0x2 + +/* Define relevant registers in PCI space.*/ +#define I2C_PCI_COMMAND 0x4 +#define I2C_PCI_STATUS 0x6 + +/* Define memory mapped registers.*/ +#define I2C_CTRL 0x0 +#define I2C_SLAVE_DISABLE 0x40 +#define I2C_RESTART_EN 0x20 +#define I2C_ADR_MODE 0x10 +#define I2C_SPEED_MASK 0x6 +#define I2C_STD_MODE 0x1 +#define I2C_FAST_MODE 0x2 +#define I2C_MASTER_ENABLE 0x1 + +#define I2C_TARGET_ADR 0x4 +#define I2C_TARGET_ADR_MASK 0x3ff + +#define I2C_DATA_CMD 0x10 +#define I2C_RESTART 0x400 +#define I2C_STOP 0x200 +#define I2C_RW_CMD 0x100 + +#define I2C_SS_SCL_HCNT 0x14 /* Counter for high period for 100 kHz SCL*/ +#define I2C_SS_SCL_LCNT 0x18 /* Counter for low period for 100 kHz SCL*/ +#define I2C_FS_SCL_HCNT 0x1c /* Counter for high period for 400 kHz SCL*/ +#define I2C_FS_SCL_LCNT 0x20 /* Counter for low period for 400 kHz SCL*/ + +#define I2C_INTR_STAT 0x2c /* Interrupt status register, read only*/ +#define I2C_INTR_MASK 0x30 /*Interrupt mask register*/ +#define I2C_RAW_INTR_STAT 0x34 /* Raw interrupt status, read only*/ +#define I2C_START_DETECT 0x400 +#define I2C_STOP_DETECT 0x200 +#define I2C_ACTIVITY 0x100 +#define I2C_TX_ABORT 0x40 +#define I2C_RD_REQ 0x20 /* Read request in slave mode*/ +#define I2C_TX_EMPTY 0x10 +#define I2C_TX_OVERFLOW 0x8 +#define I2C_RX_FULL 0x4 +#define I2C_RX_OVERFLOW 0x2 +#define I2C_RX_UNDERFLOW 0x1 + +#define I2C_RX_TL 0x38 /* Rx FIFO threshold level 0..255*/ +#define I2C_TX_TL 0x3c /* Tx FIFO threshold level 0..255*/ +#define I2C_CLR_INTR 0x40 /* Clear all events with a read*/ +#define I2C_CLR_TX_ABRT 0x54 /* Clear TX-Abort event with a read*/ + +/*There are a bunch of interrupt clearing registers now which I do not use!*/ +/*So proceed somewhat later with definition*/ +#define I2C_ENABLE 0x6c /* 0: disable I2C controller, 1: enable*/ +#define I2C_STATUS 0x70 +#define I2C_MST_ACTIVITY 0x20 /* Master FSM activity*/ +#define I2C_RFF 0x10 /* Receive FIFO completely full*/ +#define I2C_RFNE 0x8 /* Receive FIFO not empty*/ +#define I2C_TFE 0x4 /* Transmit FIFO completely empty*/ +#define I2C_TFNF 0x2 /* Transmit FIFO not full*/ +#define I2C_ACTIVE 0x1 /* 1: I2C currently in operation*/ + +#define I2C_TXFLR 0x74 /* Current transmit FIFO level*/ +#define I2C_RXFLR 0x78 /* Current receive FIFO level*/ +#define I2C_SDA_HOLD 0x7c /* Data hold time after SCL goes low*/ +#define I2C_ABORT_SOURCE 0x80 +#define I2C_ARB_LOST 0x1000 /* Arbitration lost*/ +#define I2C_MASTER_DIS 0x800 /* Master was disabled by user*/ +#define I2C_10B_RD_NORSTRT 0x400 /* 10 bit address read and RESTART disabled*/ +#define I2C_SBYTE_NORSTRT 0x200 /* START with RESTART disabled*/ +#define I2C_START_ACKDET 0x80 /* START byte was acknowledged*/ +#define I2C_TX_DATA_NOACK 0x8 /* TX data not acknowledged*/ +#define I2C_10B_ADR2_NOACK 0x4 /* Second address byte in 10 bit mode NACK*/ +#define I2C_10B_ADR1_NOACK 0x2 /* First address byte in 10 bit not ACK*/ +#define I2C_7B_ADDR_NACK 0x1 /* 7 bit address byte not acknowledged*/ + +#define I2C_ENABLE_STATUS 0x9c + +/* Define some status and error values*/ +#define I2C_ERR_INVALID_ADR 0x1000000 +#define I2C_ERR_TIMEOUT 0x2000000 +#define I2C_ERR_ABORT 0x4000000 +#define I2C_NO_ERROR 0x0000000 + + +#define I2C_TIMEOUT 2000 /* Use 2000 us as timeout for the bus*/ + +/* Prototype section*/ +int i2c_init(unsigned bus); +int i2c_read(unsigned bus, unsigned chip, unsigned addr, + uint8_t *buf, unsigned len); +int i2c_write(unsigned bus, unsigned chip, unsigned addr, + const uint8_t *buf, unsigned len); + +#endif /* __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ */ diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c new file mode 100644 index 0000000..05c21a3 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci.h> +#include <baytrail/baytrail.h> +#include <baytrail/pci_devs.h> +#include <baytrail/iosf.h> +#include <delay.h> +#include <baytrail/i2c.h> + +/* Wait for the transmit FIFO till there is at least one slot empty. + * FIFO stall due to transmit abort will be checked and resolved + */ +static int wait_tx_fifo(char *base_adr) { + int i; + + if (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff) { + /*Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO*/ + i = *((volatile unsigned int *)(base_adr + I2C_CLR_TX_ABRT)); + return I2C_ERR_ABORT | + (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff); + } + + /*Wait here for a free slot in TX-FIFO */ + i = I2C_TIMEOUT; + while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_TFNF)) + && (i)) { + udelay(1); + i--; + } + + if (i == 0) { + return I2C_ERR_TIMEOUT; + } else { + return I2C_NO_ERROR; + } +} + +/* Wait for the receive FIFO till there is at least one valid entry to read. + * FIFO stall due to transmit abort will be checked and resolved + */ +static int wait_rx_fifo(char *base_adr) { + int i; + + if (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff) { + /*Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO*/ + i = *((volatile unsigned int *)(base_adr + I2C_CLR_TX_ABRT)); + return I2C_ERR_ABORT | + (*((unsigned int *)(base_adr + I2C_ABORT_SOURCE)) & 0x1ffff); + } + + /*Wait here for a received entry in RX-FIFO */ + i = I2C_TIMEOUT; + while ((!(*((volatile unsigned int *)(base_adr + I2C_STATUS)) & I2C_RFNE)) + && (i)) { + udelay(1); + i--; + } + + if (i == 0) { + return I2C_ERR_TIMEOUT; + } else { + return I2C_NO_ERROR; + } +} + +/* When there will be a fast switch between send and receive, one have + * to wait until the first operation is completely finished + * before starting the second operation + */ +static int wait_for_idle(char *base_adr) +{ + int i; + volatile int status; + + /*For IDLE, increase timeout by ten times*/ + i = I2C_TIMEOUT * 10; + status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + while(((status & I2C_MST_ACTIVITY) || (!(status & I2C_TFE))) && (i)) { + status = *((volatile unsigned int *)(base_adr + I2C_STATUS)); + udelay(1); + i--; + } + + if (i == 0) { + return I2C_ERR_TIMEOUT; + } else { + return I2C_NO_ERROR; + } +} + +/** \brief Enables I2C-controller, sets up BAR and timing parameters + * @param bus Number of the I2C-controller to use (0...6) + * @return 0 on success, otherwise error code + */ +int i2c_init(unsigned bus) +{ + device_t dev; + int base_adr[7] = {I2C0_MEM_BASE, I2C1_MEM_BASE, I2C2_MEM_BASE, + I2C3_MEM_BASE, I2C4_MEM_BASE, I2C5_MEM_BASE, + I2C6_MEM_BASE}; + char *base_ptr = (char*)base_adr[bus]; + /* Ensure the desired device is valid*/ + if (bus > 6) { + printk (BIOS_ERR, "I2C: Only I2C controllers 0...6 are available"); + return 1; + } + + /*Set the I2C-device the user wants to use */ + dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1)); + + /* Ensure we have the right PCI device */ + if ((pci_read_config16(dev, 0x0) != I2C_PCI_VENDOR_ID) || + (pci_read_config16(dev, 0x2) != (I2C0_PCI_DEV_ID + bus))) { + printk(BIOS_ERR, "I2C: Controller %d not found!", bus); + return 2; + } + + /* Set memory base*/ + pci_write_config32(dev, PCI_BASE_ADDRESS_0,(int)base_ptr); + + /* Enable memory space*/ + pci_write_config32(dev, PCI_COMMAND, + (pci_read_config32(dev, PCI_COMMAND) | 0x2)); + + /*Set up some settings of I2C controller*/ + *((unsigned int *)(base_ptr + I2C_CTRL)) = (I2C_RESTART_EN + | (I2C_STANDARD_MODE << 1) + | I2C_MASTER_ENABLE); + /*Adjust frequency for standard mode to 100 kHz*/ + /*The counter value can be computed by N=100MHz/2/I2C_CLK*/ + /*Thus, for 100 kHz I2C_CLK, N is 0x1F4*/ + *((unsigned int *)(base_ptr + I2C_SS_SCL_HCNT)) = 0x1f4; + *((unsigned int *)(base_ptr + I2C_SS_SCL_LCNT)) = 0x1f4; + /*For 400 kHz, the counter value is 0x7d*/ + *((unsigned int *)(base_ptr + I2C_FS_SCL_HCNT)) = 0x7d; + *((unsigned int *)(base_ptr + I2C_FS_SCL_LCNT)) = 0x7d; + + /* Enable the I2C controller for operation*/ + *((unsigned int *)(base_ptr + I2C_ENABLE)) = 0x1; + + printk(BIOS_INFO, "I2C: Controller %d enabled.\n", bus); + return I2C_NO_ERROR; +} + +/** \brief Read bytes over I2C-Bus from a slave. This function tries only one + * time to transmit data. In case of an error (abort) error code is + * returned. Retransmission has to be done from caller! + * @param bus Number of the I2C-controller to use (0...6) + * @param chip 7 Bit of the slave address on I2C bus + * @param addr Address inside slave where to read from + * @param *buf Pointer to the buffer where to store read data + * @param len Number of bytes to read + * @return I2C_NO_ERROR when read was successful, otherwise error code + */ +int i2c_read(unsigned bus, unsigned chip, unsigned addr, + uint8_t *buf, unsigned len) +{ + int i = 0; + char *base_ptr = NULL; + device_t dev; + unsigned int val; + int stat; + + /*Get base address of desired I2C-controller*/ + dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1)); + base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if (base_ptr == NULL) { + printk(BIOS_INFO, "I2C: Invalid Base address\n"); + return I2C_ERR_INVALID_ADR; + } + + /*Ensure I2C controller is not active before setting slave address*/ + stat = wait_for_idle(base_ptr); + if (stat != I2C_NO_ERROR) { + return stat; + } + /* Now we can program the desired slave address and start transfer*/ + *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + /* Send address inside slave to read from*/ + *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + + /* For the next byte we need a repeated start condition*/ + val = I2C_RW_CMD | I2C_RESTART; + /* Now we can read desired amount of data over I2C*/ + for (i = 0; i < len; i++) { + /*A read is initiated by writing dummy data to the DATA-register*/ + *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + stat = wait_rx_fifo(base_ptr); + if (stat) { + return stat; + } + buf[i] = (*((unsigned int *)(base_ptr + I2C_DATA_CMD))) & 0xff; + val = I2C_RW_CMD; + if (i == (len -2)) { + /* For the last byte we need a stop condition to be generated*/ + val |= I2C_STOP; + } + } + return I2C_NO_ERROR; +} + +/** \brief Write bytes over I2C-Bus from a slave. This function tries only one + * time to transmit data. In case of an error (abort) error code is + * returned. Retransmission has to be done from caller! + * @param bus Number of the I2C-controller to use (0...6) + * @param chip 7 Bit of the slave address on I2C bus + * @param addr Address inside slave where to write to + * @param *buf Pointer to the buffer where data to write is stored + * @param len Number of bytes to write + * @return I2C_NO_ERROR when read was successful, otherwise error code + */ +int i2c_write(unsigned bus, unsigned chip, unsigned addr, + const uint8_t *buf, unsigned len) +{ + int i; + char *base_ptr; + device_t dev; + unsigned int val; + int stat; + + /*Get base address of desired I2C-controller*/ + dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1)); + base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if (base_ptr == NULL) { + return I2C_ERR_INVALID_ADR; + } + + /*Ensure I2C controller is not active jet*/ + stat = wait_for_idle(base_ptr); + if (stat) { + return stat; + } + /*Program slave address to use for this transfer*/ + *((unsigned int *)(base_ptr + I2C_TARGET_ADR)) = (chip & 0xff); + + /* Send address inside slave to write data to*/ + *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = (addr & 0xff); + + for (i = 0; i < len; i++) { + val = (unsigned int)(buf[i] & 0xff); /* Take only 8 bits*/ + if (i == (len -1)) { + /* For the last byte we need a stop condition to be generated*/ + val |= I2C_STOP; + } + stat = wait_tx_fifo(base_ptr); + if (stat) { + return stat; + } + *((unsigned int *)(base_ptr + I2C_DATA_CMD)) = val; + } + return I2C_NO_ERROR; +}

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Patch set updated for coreboot: 0354a58 lint: exclude *.hex files from whitespace checking
by Werner Zeh 11 Feb '15

11 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8403 -gerrit commit 0354a58ced74a4de3cf6488fa48c470b8e8735ce Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 14:34:17 2015 +0100 lint: exclude *.hex files from whitespace checking If one needs raw binary files, .bin extension cannot be used due to settings in .gitignore. This patch allows to use .hex files. To avoid lint checks on these files, exclude the .hex extension from the test. Change-Id: I4b503229d63694c48cce12ca8cd33ea58172af01 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- util/lint/lint-stable-003-whitespace | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 47853ba..f13aa98 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -19,6 +19,6 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch|\.bin$)"` | \ +grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$)"` | \ sed -e "s,^.*$,File & has lines ending with whitespace.,"

1 0

Patch set updated for coreboot: 76f2a4c fsp_baytrail: Add macros to define 20K pull-up and down
by Werner Zeh 11 Feb '15

11 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8402 -gerrit commit 76f2a4c103c4ac22dcbddcbe9f5a85641be6d53a Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 13:32:51 2015 +0100 fsp_baytrail: Add macros to define 20K pull-up and down Add two macros to gpio.h which allow to setup 20K pull-up or pull-down resistor for a given GPIO. Change-Id: Ie3bc4d40df588ed682cc692e2a80527b9e62a483 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/baytrail/gpio.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h index e13b663..a45254a 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h +++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h @@ -170,6 +170,20 @@ .use_sel = GPIO_USE_MMIO, \ .is_gpio = 1 } +#define GPIO_INPUT_PU_20K \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_PD_20K \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + #define GPIO_INPUT_NOPU \ { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \

1 0

Patch set updated for coreboot: 0a85f1d lint: exclude nvidia submodule from file list
by Werner Zeh 11 Feb '15

11 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8372 -gerrit commit 0a85f1d9db175846d448e048f2bd1ef9bea74fd8 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 5 23:38:45 2015 +0100 lint: exclude nvidia submodule from file list From git's point of view submodules are a weird third thing between file and directory. Avoid trying to apply file handling on a directory. Change-Id: Ibbc9c28e1657d96413c5fb08705d30e25171254d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/lint/lint-stable-003-whitespace | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 22c5c3c..47853ba 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -19,6 +19,6 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch|\.bin$)"` | \ +grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch|\.bin$)"` | \ sed -e "s,^.*$,File & has lines ending with whitespace.,"

1 0

Patch set updated for coreboot: fb810e3 Baytrail_fsp: Add new microcode for Baytrail M
by Werner Zeh 11 Feb '15

11 Feb '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8399 -gerrit commit fb810e32e1bf87f7c99122ad6444d5bd93a69505 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Feb 10 10:16:12 2015 +0100 Baytrail_fsp: Add new microcode for Baytrail M Add a new microcode for Baytrail M D0 stepping used in cpu N2807 silicon. In addition, a selection of the used CPU type has beed added (I or M/D) which allows to use only the realy needed microcode for a given CPU type. Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Kconfig | 9 +++++++++ src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 11 ++++++++--- src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 6 +++++- 3 files changed, 22 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 639071a..a7f3f77 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -51,6 +51,15 @@ config CPU_SPECIFIC_OPTIONS select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD select ROMSTAGE_RTC_INIT +choice + prompt "Baytrail CPU type" + default SOC_INTEL_FSP_BAYTRAIL_I +config SOC_INTEL_FSP_BAYTRAIL_I + bool "I" +config SOC_INTEL_FSP_BAYTRAIL_MD + bool "M/D" +endchoice + config BOOTBLOCK_CPU_INIT string default "soc/intel/fsp_baytrail/bootblock/bootblock.c" diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 709ff92..fc5ab08 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,10 +19,15 @@ unsigned microcode[] = { +#if IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_I) /* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ -#include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 -#include "M0130673322.h" // M0130673: Baytrail I B2 / B3 -#include "M0130679901.h" // M0130679: Baytrail I D0 + #include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 + #include "M0130673322.h" // M0130673: Baytrail I B2 / B3 + #include "M0130679901.h" // M0130679: Baytrail I D0 +#elif IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) + /* Region size is 0x10000 - update in microcode_size.h if it gets larger. */ + #include "M0C30678829.h" // M0C30678: Baytrail M D Stepping +#endif /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h index ec55314..213fc17 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -1,2 +1,6 @@ /* Maximum size of the area that the FSP will search for the correct microcode */ -#define MICROCODE_REGION_LENGTH 0x30000 +#if IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_I) + #define MICROCODE_REGION_LENGTH 0x30000 +#elif IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) + #define MICROCODE_REGION_LENGTH 0x10000 +#endif

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Patch merged into coreboot/master: f73179d mainboards/asus/kfsn4-dre: Run BSP FIDVID before AP FIDVID
by gerrit＠coreboot.org 11 Feb '15

11 Feb '15

the following patch was just integrated into master: commit f73179d4bea45d366c9407baf2b614ca5b44a12b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 10 00:37:21 2015 -0600 mainboards/asus/kfsn4-dre: Run BSP FIDVID before AP FIDVID This resolves an issue on Shanghai dual CPU configurations where the APs on node 0 would not start. Single CPU configurations are unaffected by this issue. TEST: Booted KFSN4-DRE with dual Opteron 8389 CPUs and verified proper BSP/AP start and microcode patch levels. Change-Id: I0f5d4e0e356c6bd64e324b4399ef43b400ecab0c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8397 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8397 for details. -gerrit

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New patch to review for coreboot: 2c3240a x86/boot: Generate valid ACPI processor objects
by Timothy Pearson 11 Feb '15

11 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8422 -gerrit commit 2c3240ae82a56b0a63b9f8c006eaec46392320e6 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 10 22:21:39 2015 -0600 x86/boot: Generate valid ACPI processor objects The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/arch/x86/boot/acpigen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 8e7ce46..76fe2d6 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -293,7 +293,7 @@ int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) len = acpigen_write_len_f(); snprintf(pscope, sizeof (pscope), - "\\_PR.CPU%x", (unsigned int) cpuindex); + "\\_PR.CP%02d", (unsigned int) cpuindex); len += acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex); acpigen_emit_byte(pblock_addr & 0xff);

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coreboot-gerrit February 2015