coreboot-gerrit February 2015

coreboot-gerrit@coreboot.org

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509 discussions

Patch merged into coreboot/master: 0908839 cpu/amd/model_10xxx: add Propus (00100F52h BL-C2) equivalent id
by gerrit＠coreboot.org 11 Feb '15

11 Feb '15

the following patch was just integrated into master: commit 090883932386b12fdfb85148041f551be4596f4f Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Wed Feb 11 23:01:17 2015 +0100 cpu/amd/model_10xxx: add Propus (00100F52h BL-C2) equivalent id Change-Id: I32eccfb4eae176e0155c53efaf463258653eefc2 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/8355 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8355 for details. -gerrit

1 0

Patch merged into coreboot/master: 6fdb4d5 amd/amdfam10: Fix incorrect core count identification
by gerrit＠coreboot.org 11 Feb '15

11 Feb '15

the following patch was just integrated into master: commit 6fdb4d5d3c556974f2a6b15fd01b9dd2a1d0adc7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 10 21:15:39 2015 -0600 amd/amdfam10: Fix incorrect core count identification The core count identification code in the PowerNow! _PSS ACPI object generation code was incorrectly copied from the model_fxx code. This code has been rewritten to properly return the number of cores installed in the system. Change-Id: I19567486f2de9dc2c43970addf4d91fa3d233a99 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8421 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8421 for details. -gerrit

1 0

Patch set updated for coreboot: 8c10623 acpi: Generate valid ACPI processor objects
by Timothy Pearson 11 Feb '15

11 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8422 -gerrit commit 8c106237ef4da972e3814acc197210267ed23751 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 10 22:21:39 2015 -0600 acpi: Generate valid ACPI processor objects The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/arch/x86/boot/acpigen.c | 2 +- src/cpu/intel/fsp_model_206ax/acpi/cpu.asl | 74 ++++++++--------- src/cpu/intel/fsp_model_406dx/acpi/cpu.asl | 74 ++++++++--------- src/cpu/intel/haswell/acpi/cpu.asl | 74 ++++++++--------- src/cpu/intel/model_206ax/acpi/cpu.asl | 74 ++++++++--------- src/cpu/intel/model_6dx/acpi/cpu.asl | 20 ++--- src/ec/quanta/ene_kb3940q/acpi/ec.asl | 10 +-- src/include/cpu/intel/speedstep.h | 2 +- src/mainboard/amd/dbm690t/fadt.c | 2 +- src/mainboard/amd/pistachio/fadt.c | 2 +- src/mainboard/amd/torpedo/fadt.c | 2 +- src/mainboard/getac/p470/acpi/ec.asl | 2 +- src/mainboard/getac/p470/acpi/platform.asl | 10 +-- src/mainboard/getac/p470/acpi/thermal.asl | 4 +- src/mainboard/ibase/mb899/acpi/thermal.asl | 4 +- src/mainboard/intel/d945gclf/acpi/thermal.asl | 4 +- src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl | 4 +- src/mainboard/kontron/986lcd-m/acpi/thermal.asl | 4 +- src/mainboard/kontron/kt690/fadt.c | 2 +- src/mainboard/lenovo/x200/acpi/platform.asl | 16 ++-- src/mainboard/roda/rk886ex/acpi/thermal.asl | 4 +- src/mainboard/roda/rk9/acpi/platform.asl | 16 ++-- src/mainboard/roda/rk9/acpi/thermal.asl | 4 +- .../siemens/sitemp_g1p1/acpi/platform.asl | 4 +- src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl | 4 +- src/mainboard/siemens/sitemp_g1p1/fadt.c | 2 +- src/mainboard/technexion/tim5690/fadt.c | 2 +- src/mainboard/technexion/tim8690/fadt.c | 2 +- src/mainboard/via/vt8454c/dsdt.asl | 2 +- src/northbridge/amd/amdk8/thermal_mixin.asl | 6 +- .../intel/fsp_sandybridge/acpi/hostbridge.asl | 6 +- src/northbridge/intel/haswell/acpi/hostbridge.asl | 6 +- src/northbridge/intel/nehalem/acpi/hostbridge.asl | 6 +- .../intel/sandybridge/acpi/hostbridge.asl | 6 +- src/soc/intel/baytrail/acpi/cpu.asl | 38 ++++----- src/soc/intel/baytrail/acpi/dptf/cpu.asl | 38 ++++----- src/soc/intel/broadwell/acpi/cpu.asl | 94 +++++++++++----------- src/soc/intel/broadwell/acpi/ctdp.asl | 6 +- src/soc/intel/fsp_baytrail/acpi/cpu.asl | 38 ++++----- src/southbridge/amd/agesa/hudson/hudson.c | 2 +- src/southbridge/amd/cimx/sb800/fadt.c | 2 +- src/southbridge/amd/pi/hudson/hudson.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- 44 files changed, 340 insertions(+), 340 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 8e7ce46..76fe2d6 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -293,7 +293,7 @@ int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) len = acpigen_write_len_f(); snprintf(pscope, sizeof (pscope), - "\\_PR.CPU%x", (unsigned int) cpuindex); + "\\_PR.CP%02d", (unsigned int) cpuindex); len += acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex); acpigen_emit_byte(pblock_addr & 0xff); diff --git a/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl b/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl index 558a9d3..472ac08 100644 --- a/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl +++ b/src/cpu/intel/fsp_model_206ax/acpi/cpu.asl @@ -20,31 +20,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -52,18 +52,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -71,18 +71,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,13 +90,13 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, + \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl b/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl index 558a9d3..472ac08 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl +++ b/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl @@ -20,31 +20,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -52,18 +52,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -71,18 +71,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,13 +90,13 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, + \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/cpu/intel/haswell/acpi/cpu.asl b/src/cpu/intel/haswell/acpi/cpu.asl index 558a9d3..472ac08 100644 --- a/src/cpu/intel/haswell/acpi/cpu.asl +++ b/src/cpu/intel/haswell/acpi/cpu.asl @@ -20,31 +20,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -52,18 +52,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -71,18 +71,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,13 +90,13 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, + \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/cpu/intel/model_206ax/acpi/cpu.asl b/src/cpu/intel/model_206ax/acpi/cpu.asl index 558a9d3..472ac08 100644 --- a/src/cpu/intel/model_206ax/acpi/cpu.asl +++ b/src/cpu/intel/model_206ax/acpi/cpu.asl @@ -20,31 +20,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -52,18 +52,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -71,18 +71,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,13 +90,13 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, - \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, + \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/cpu/intel/model_6dx/acpi/cpu.asl b/src/cpu/intel/model_6dx/acpi/cpu.asl index 8928c38..04438a2 100644 --- a/src/cpu/intel/model_6dx/acpi/cpu.asl +++ b/src/cpu/intel/model_6dx/acpi/cpu.asl @@ -4,34 +4,34 @@ External(PDC1) // Power notification -External (\_PR_.CPU0, DeviceObj) -External (\_PR_.CPU1, DeviceObj) -External (\_PR_.CPU0._PPC) -External (\_PR_.CPU1._PPC) +External (\_PR_.CP00, DeviceObj) +External (\_PR_.CP01, DeviceObj) +External (\_PR_.CP00._PPC) +External (\_PR_.CP01._PPC) Method (PNOT) { If (MPEN) { If(And(PDC0, 0x08)) { - Notify (\_PR_.CPU0, 0x80) // _PPC + Notify (\_PR_.CP00, 0x80) // _PPC If (And(PDC0, 0x10)) { Sleep(100) - Notify(\_PR_.CPU0, 0x81) // _CST + Notify(\_PR_.CP00, 0x81) // _CST } } If(And(PDC1, 0x08)) { - Notify (\_PR_.CPU1, 0x80) // _PPC + Notify (\_PR_.CP01, 0x80) // _PPC If (And(PDC1, 0x10)) { Sleep(100) - Notify(\_PR_.CPU1, 0x81) // _CST + Notify(\_PR_.CP01, 0x81) // _CST } } } Else { // UP - Notify (\_PR_.CPU0, 0x80) + Notify (\_PR_.CP00, 0x80) Sleep(0x64) - Notify(\_PR_.CPU0, 0x81) + Notify(\_PR_.CP00, 0x81) } } diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 4e703fe..3d9aa62 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -23,7 +23,7 @@ * re-evaluate their _PPC and _CST tables. */ -External (\_PR.CPU0._PPC, IntObj) +External (\_PR.CP00._PPC, IntObj) Device (EC0) { @@ -148,12 +148,12 @@ Device (EC0) Store (CTMP, Local0) // Find and program number of P-States - Store (SizeOf (\_PR.CPU0._PSS), MPST) + Store (SizeOf (\_PR.CP00._PSS), MPST) Store ("Programming number of P-states: ", Debug) Store (MPST, Debug) // Find and program the current P-State - Store(\_PR.CPU0._PPC, NPST) + Store(\_PR.CP00._PPC, NPST) Store ("Programming Current P-state: ", Debug) Store (NPST, Debug) } @@ -192,7 +192,7 @@ Device (EC0) { Store ("Pstate Event 0x0E", Debug) - Store(\_PR.CPU0._PPC, Local0) + Store(\_PR.CP00._PPC, Local0) Subtract(PPCM, 0x01, Local1) If(LLess(Local0, Local1)) { @@ -207,7 +207,7 @@ Device (EC0) Method (_Q0F) { Store ("Pstate Event 0x0F", Debug) - Store(\_PR.CPU0._PPC, Local0) + Store(\_PR.CP00._PPC, Local0) If(Local0) { Decrement(Local0) diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 8bfae60..eb8b506 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -29,7 +29,7 @@ #define SPEEDSTEP_APIC_MAGIC 0xACAC /* MWAIT coordination I/O base address. This must match - * the \_PR_.CPU0 PM base address. + * the \_PR_.CP00 PM base address. */ #define PMB0_BASE 0x510 diff --git a/src/mainboard/amd/dbm690t/fadt.c b/src/mainboard/amd/dbm690t/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/amd/dbm690t/fadt.c +++ b/src/mainboard/amd/dbm690t/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/amd/pistachio/fadt.c +++ b/src/mainboard/amd/pistachio/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 4bc88ac..5d66791 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -81,7 +81,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) val = GPE0_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ val = CPU_CNT_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); val = 0; diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 1b1c157..70e4224 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -105,7 +105,7 @@ Device(EC0) // EC Query methods, called upon SCI interrupts. Method (_Q01, 0) { - Notify (\_PR.CPU0, 0x80) + Notify (\_PR.CP00, 0x80) If(ADP) { Store(1, \_SB.AC.ACST) TRAP(0xe3) diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index 2b081e0..cad5a71 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -95,15 +95,15 @@ Method(_WAK,1) // Windows XP SP2 P-State restore If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) { - If (LGreater(\_PR.CPU0._PPC, 0)) { - Subtract(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + If (LGreater(\_PR.CP00._PPC, 0)) { + Subtract(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) PNOT() - Add(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + Add(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) PNOT() } Else { - Add(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + Add(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) PNOT() - Subtract(\_PR.CPU0._PPC, 1, \_PR.CPU0._PPC) + Subtract(\_PR.CP00._PPC, 1, \_PR.CP00._PPC) PNOT() } } diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl index eefc1b7..f103561 100644 --- a/src/mainboard/getac/p470/acpi/thermal.asl +++ b/src/mainboard/getac/p470/acpi/thermal.asl @@ -79,9 +79,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } // TC1 value for passive cooling diff --git a/src/mainboard/ibase/mb899/acpi/thermal.asl b/src/mainboard/ibase/mb899/acpi/thermal.asl index 128d677..c5994d5 100644 --- a/src/mainboard/ibase/mb899/acpi/thermal.asl +++ b/src/mainboard/ibase/mb899/acpi/thermal.asl @@ -65,9 +65,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU1, \_PR.CPU2}) + Return (Package() {\_PR.CP01, \_PR.CP02}) } - Return (Package() {\_PR.CPU1}) + Return (Package() {\_PR.CP01}) } // TC1 value for passive cooling diff --git a/src/mainboard/intel/d945gclf/acpi/thermal.asl b/src/mainboard/intel/d945gclf/acpi/thermal.asl index fc9f24e..10e241d 100644 --- a/src/mainboard/intel/d945gclf/acpi/thermal.asl +++ b/src/mainboard/intel/d945gclf/acpi/thermal.asl @@ -65,9 +65,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU1, \_PR.CPU2}) + Return (Package() {\_PR.CP01, \_PR.CP02}) } - Return (Package() {\_PR.CPU1}) + Return (Package() {\_PR.CP01}) } // TC1 value for passive cooling diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl b/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl index 5330309..1ba2338 100644 --- a/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl +++ b/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl @@ -67,9 +67,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU1, \_PR.CPU2}) + Return (Package() {\_PR.CP01, \_PR.CP02}) } - Return (Package() {\_PR.CPU1}) + Return (Package() {\_PR.CP01}) } // TC1 value for passive cooling diff --git a/src/mainboard/kontron/986lcd-m/acpi/thermal.asl b/src/mainboard/kontron/986lcd-m/acpi/thermal.asl index 128d677..c5994d5 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/thermal.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/thermal.asl @@ -65,9 +65,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU1, \_PR.CPU2}) + Return (Package() {\_PR.CP01, \_PR.CP02}) } - Return (Package() {\_PR.CPU1}) + Return (Package() {\_PR.CP01}) } // TC1 value for passive cooling diff --git a/src/mainboard/kontron/kt690/fadt.c b/src/mainboard/kontron/kt690/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/kontron/kt690/fadt.c +++ b/src/mainboard/kontron/kt690/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/lenovo/x200/acpi/platform.asl b/src/mainboard/lenovo/x200/acpi/platform.asl index 19b1e00..2aa556f 100644 --- a/src/mainboard/lenovo/x200/acpi/platform.asl +++ b/src/mainboard/lenovo/x200/acpi/platform.asl @@ -100,33 +100,33 @@ Method(_WAK,1) // Power notification -External (\_PR_.CPU0, DeviceObj) -External (\_PR_.CPU1, DeviceObj) +External (\_PR_.CP00, DeviceObj) +External (\_PR_.CP01, DeviceObj) Method (PNOT) { If (MPEN) { If(And(PDC0, 0x08)) { - Notify (\_PR_.CPU0, 0x80) // _PPC + Notify (\_PR_.CP00, 0x80) // _PPC If (And(PDC0, 0x10)) { Sleep(100) - Notify(\_PR_.CPU0, 0x81) // _CST + Notify(\_PR_.CP00, 0x81) // _CST } } If(And(PDC1, 0x08)) { - Notify (\_PR_.CPU1, 0x80) // _PPC + Notify (\_PR_.CP01, 0x80) // _PPC If (And(PDC1, 0x10)) { Sleep(100) - Notify(\_PR_.CPU1, 0x81) // _CST + Notify(\_PR_.CP01, 0x81) // _CST } } } Else { // UP - Notify (\_PR_.CPU0, 0x80) + Notify (\_PR_.CP00, 0x80) Sleep(0x64) - Notify(\_PR_.CPU0, 0x81) + Notify(\_PR_.CP00, 0x81) } } diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl index e445d3c..873b089 100644 --- a/src/mainboard/roda/rk886ex/acpi/thermal.asl +++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl @@ -67,9 +67,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } // TC1 value for passive cooling diff --git a/src/mainboard/roda/rk9/acpi/platform.asl b/src/mainboard/roda/rk9/acpi/platform.asl index 3d4a214..decceaf 100644 --- a/src/mainboard/roda/rk9/acpi/platform.asl +++ b/src/mainboard/roda/rk9/acpi/platform.asl @@ -100,33 +100,33 @@ Method(_WAK,1) // Power notification -External (\_PR_.CPU0, DeviceObj) -External (\_PR_.CPU1, DeviceObj) +External (\_PR_.CP00, DeviceObj) +External (\_PR_.CP01, DeviceObj) Method (PNOT) { If (MPEN) { If(And(PDC0, 0x08)) { - Notify (\_PR_.CPU0, 0x80) // _PPC + Notify (\_PR_.CP00, 0x80) // _PPC If (And(PDC0, 0x10)) { Sleep(100) - Notify(\_PR_.CPU0, 0x81) // _CST + Notify(\_PR_.CP00, 0x81) // _CST } } If(And(PDC1, 0x08)) { - Notify (\_PR_.CPU1, 0x80) // _PPC + Notify (\_PR_.CP01, 0x80) // _PPC If (And(PDC1, 0x10)) { Sleep(100) - Notify(\_PR_.CPU1, 0x81) // _CST + Notify(\_PR_.CP01, 0x81) // _CST } } } Else { // UP - Notify (\_PR_.CPU0, 0x80) + Notify (\_PR_.CP00, 0x80) Sleep(0x64) - Notify(\_PR_.CPU0, 0x81) + Notify(\_PR_.CP00, 0x81) } // Notify the Batteries diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl index 6e28f17..f4868b4 100644 --- a/src/mainboard/roda/rk9/acpi/thermal.asl +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -86,9 +86,9 @@ Scope (\_TZ) Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } // TC1 value for passive cooling diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl index 8af607d..37daa36 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl @@ -30,8 +30,8 @@ Method(_PIC, 1, NotSerialized) } } -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) Scope(\_SB) { diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl index 02b1df1..fbcd0e7 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl @@ -56,9 +56,9 @@ Scope(\_TZ) { Method (_PSL, 0, Serialized) { If (MPEN) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ diff --git a/src/mainboard/siemens/sitemp_g1p1/fadt.c b/src/mainboard/siemens/sitemp_g1p1/fadt.c index f9acfe4..d62caa0 100644 --- a/src/mainboard/siemens/sitemp_g1p1/fadt.c +++ b/src/mainboard/siemens/sitemp_g1p1/fadt.c @@ -80,7 +80,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/technexion/tim5690/fadt.c b/src/mainboard/technexion/tim5690/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/technexion/tim5690/fadt.c +++ b/src/mainboard/technexion/tim5690/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/technexion/tim8690/fadt.c b/src/mainboard/technexion/tim8690/fadt.c index c238cbe..ec75a65 100644 --- a/src/mainboard/technexion/tim8690/fadt.c +++ b/src/mainboard/technexion/tim8690/fadt.c @@ -79,7 +79,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); diff --git a/src/mainboard/via/vt8454c/dsdt.asl b/src/mainboard/via/vt8454c/dsdt.asl index d13a6b7..4901041 100644 --- a/src/mainboard/via/vt8454c/dsdt.asl +++ b/src/mainboard/via/vt8454c/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) */ Scope (\_PR) { - Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {} + Processor (\_PR.CP00, 0x00, 0x00000410, 0x06) {} } /* For now only define 2 power states: diff --git a/src/northbridge/amd/amdk8/thermal_mixin.asl b/src/northbridge/amd/amdk8/thermal_mixin.asl index 62590ff..f6257a6 100644 --- a/src/northbridge/amd/amdk8/thermal_mixin.asl +++ b/src/northbridge/amd/amdk8/thermal_mixin.asl @@ -139,7 +139,7 @@ ThermalZone (K8T1) { Name(_UID, "k8-1") Name(_STR, Unicode("K8 compatible CPU Core 1 Thermal Sensor 2")) - Name(_TZD, Package () {\_PR.CPU0}) + Name(_TZD, Package () {\_PR.CP00}) Method(_STA) { Store(CORE, Local0) @@ -190,7 +190,7 @@ ThermalZone (K8T2) { Name(_UID, "k8-2") Name(_STR, Unicode("K8 compatible CPU Core 2 Thermal Sensor 1")) - Name(_TZD, Package () {\_PR.CPU0}) + Name(_TZD, Package () {\_PR.CP00}) Method(_STA) { Store(CORE, Local0) @@ -241,7 +241,7 @@ ThermalZone (K8T3) { Name(_UID, "k8-3") Name(_STR, Unicode("K8 compatible CPU Core 2 Thermal Sensor 2")) - Name(_TZD, Package () {\_PR.CPU0}) + Name(_TZD, Package () {\_PR.CP00}) Method(_STA) { Store(CORE, Local0) diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl index e569cf3..e82758c 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl @@ -147,16 +147,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index bb8e95e..9bc5549 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -157,16 +157,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index 79736bc..d210a95 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -109,16 +109,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 4279271..26f7514 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -147,16 +147,16 @@ Device (MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/soc/intel/baytrail/acpi/cpu.asl b/src/soc/intel/baytrail/acpi/cpu.asl index 16f62ba..f7e404d 100644 --- a/src/soc/intel/baytrail/acpi/cpu.asl +++ b/src/soc/intel/baytrail/acpi/cpu.asl @@ -20,21 +20,21 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } } @@ -42,12 +42,12 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } } @@ -55,12 +55,12 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } } @@ -68,10 +68,10 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl index 3cbfc5f..58c1c7b 100644 --- a/src/soc/intel/baytrail/acpi/dptf/cpu.asl +++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl @@ -1,8 +1,8 @@ -External (\_PR.CPU0._TSS, MethodObj) -External (\_PR.CPU0._TPC, MethodObj) -External (\_PR.CPU0._PTC, PkgObj) -External (\_PR.CPU0._TSD, PkgObj) -External (\_PR.CPU0._PSS, MethodObj) +External (\_PR.CP00._TSS, MethodObj) +External (\_PR.CP00._TPC, MethodObj) +External (\_PR.CP00._PTC, PkgObj) +External (\_PR.CP00._TSD, PkgObj) +External (\_PR.CP00._PSS, MethodObj) Device (TCPU) { @@ -24,8 +24,8 @@ Device (TCPU) Method (_TSS) { - If (CondRefOf (\_PR.CPU0._TSS)) { - Return (\_PR.CPU0._TSS) + If (CondRefOf (\_PR.CP00._TSS)) { + Return (\_PR.CP00._TSS) } Else { Return (Package () { @@ -36,8 +36,8 @@ Device (TCPU) Method (_TPC) { - If (CondRefOf (\_PR.CPU0._TPC)) { - Return (\_PR.CPU0._TPC) + If (CondRefOf (\_PR.CP00._TPC)) { + Return (\_PR.CP00._TPC) } Else { Return (0) } @@ -45,8 +45,8 @@ Device (TCPU) Method (_PTC) { - If (CondRefOf (\_PR.CPU0._PTC)) { - Return (\_PR.CPU0._PTC) + If (CondRefOf (\_PR.CP00._PTC)) { + Return (\_PR.CP00._PTC) } Else { Return (Package () { @@ -58,8 +58,8 @@ Device (TCPU) Method (_TSD) { - If (CondRefOf (\_PR.CPU0._TSD)) { - Return (\_PR.CPU0._TSD) + If (CondRefOf (\_PR.CP00._TSD)) { + Return (\_PR.CP00._TSD) } Else { Return (Package () { @@ -70,8 +70,8 @@ Device (TCPU) Method (_TDL) { - If (CondRefOf (\_PR.CPU0._TSS)) { - Store (SizeOf (\_PR.CPU0._TSS ()), Local0) + If (CondRefOf (\_PR.CP00._TSS)) { + Store (SizeOf (\_PR.CP00._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -98,8 +98,8 @@ Device (TCPU) Method (_PSS) { - If (CondRefOf (\_PR.CPU0._PSS)) { - Return (\_PR.CPU0._PSS) + If (CondRefOf (\_PR.CP00._PSS)) { + Return (\_PR.CP00._PSS) } Else { Return (Package () { @@ -113,8 +113,8 @@ Device (TCPU) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CPU0._PSS)) { - Store (SizeOf (\_PR.CPU0._PSS ()), Local0) + } ElseIf (CondRefOf (\_PR.CP00._PSS)) { + Store (SizeOf (\_PR.CP00._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else { diff --git a/src/soc/intel/broadwell/acpi/cpu.asl b/src/soc/intel/broadwell/acpi/cpu.asl index f0da2de..2921cea 100644 --- a/src/soc/intel/broadwell/acpi/cpu.asl +++ b/src/soc/intel/broadwell/acpi/cpu.asl @@ -18,31 +18,31 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) -External (\_PR.CPU4, DeviceObj) -External (\_PR.CPU5, DeviceObj) -External (\_PR.CPU6, DeviceObj) -External (\_PR.CPU7, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x81) // _CST + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST } } @@ -50,18 +50,18 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC - Notify (\_PR.CPU5, 0x80) // _PPC - Notify (\_PR.CPU6, 0x80) // _PPC - Notify (\_PR.CPU7, 0x80) // _PPC + Notify (\_PR.CP04, 0x80) // _PPC + Notify (\_PR.CP05, 0x80) // _PPC + Notify (\_PR.CP06, 0x80) // _PPC + Notify (\_PR.CP07, 0x80) // _PPC } } @@ -69,18 +69,18 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x82) // _TPC - Notify (\_PR.CPU5, 0x82) // _TPC - Notify (\_PR.CPU6, 0x82) // _TPC - Notify (\_PR.CPU7, 0x82) // _TPC + Notify (\_PR.CP04, 0x82) // _TPC + Notify (\_PR.CP05, 0x82) // _TPC + Notify (\_PR.CP06, 0x82) // _TPC + Notify (\_PR.CP07, 0x82) // _TPC } } @@ -90,33 +90,33 @@ Method (PPKG) If (LGreaterEqual (\PCNT, 8)) { Return (Package() { - \_PR.CPU0, - \_PR.CPU1, - \_PR.CPU2, - \_PR.CPU3, - \_PR.CPU4, - \_PR.CPU5, - \_PR.CPU6, - \_PR.CPU7 + \_PR.CP00, + \_PR.CP01, + \_PR.CP02, + \_PR.CP03, + \_PR.CP04, + \_PR.CP05, + \_PR.CP06, + \_PR.CP07 }) } ElseIf (LGreaterEqual (\PCNT, 4)) { Return (Package () { - \_PR.CPU0, - \_PR.CPU1, - \_PR.CPU2, - \_PR.CPU3 + \_PR.CP00, + \_PR.CP01, + \_PR.CP02, + \_PR.CP03 }) } ElseIf (LGreaterEqual (\PCNT, 2)) { Return (Package () { - \_PR.CPU0, - \_PR.CPU1 + \_PR.CP00, + \_PR.CP01 }) } Else { Return (Package () { - \_PR.CPU0 + \_PR.CP00 }) } } diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index 2aefda9..a2a8fb4 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -76,16 +76,16 @@ Scope (\_SB.PCI0.MCHC) * Package (6) { freq, power, tlat, blat, control, status } * } */ - External (\_PR.CPU0._PSS) + External (\_PR.CP00._PSS) Method (PSSS, 1, NotSerialized) { Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_PR.CPU0._PSS), Local1) + Store (SizeOf (\_PR.CP00._PSS), Local1) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/soc/intel/fsp_baytrail/acpi/cpu.asl b/src/soc/intel/fsp_baytrail/acpi/cpu.asl index 16f62ba..f7e404d 100644 --- a/src/soc/intel/fsp_baytrail/acpi/cpu.asl +++ b/src/soc/intel/fsp_baytrail/acpi/cpu.asl @@ -20,21 +20,21 @@ */ /* These devices are created at runtime */ -External (\_PR.CPU0, DeviceObj) -External (\_PR.CPU1, DeviceObj) -External (\_PR.CPU2, DeviceObj) -External (\_PR.CPU3, DeviceObj) +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x81) // _CST + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x81) // _CST + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST } } @@ -42,12 +42,12 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC - Notify (\_PR.CPU1, 0x80) // _PPC + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC - Notify (\_PR.CPU3, 0x80) // _PPC + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC } } @@ -55,12 +55,12 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x82) // _TPC - Notify (\_PR.CPU1, 0x82) // _TPC + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x82) // _TPC - Notify (\_PR.CPU3, 0x82) // _TPC + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC } } @@ -68,10 +68,10 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CPU0, \_PR.CPU1}) + Return (Package() {\_PR.CP00, \_PR.CP01}) } Else { - Return (Package() {\_PR.CPU0}) + Return (Package() {\_PR.CP00}) } } diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index fd2c268..b51edfb 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -147,7 +147,7 @@ static void hudson_init_acpi_ports(void) pm_write16(0x62, ACPI_PM1_CNT_BLK); pm_write16(0x64, ACPI_PM_TMR_BLK); pm_write16(0x68, ACPI_GPE0_BLK); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(0x66, ACPI_CPU_CONTROL); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 9442edc..2931328 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -83,7 +83,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) val = GPE0_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ val = CPU_CNT_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); val = 0; diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index e5382b4..2d40d3f 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -107,7 +107,7 @@ static void hudson_init_acpi_ports(void) pm_write16(0x62, ACPI_PM1_CNT_BLK); pm_write16(0x64, ACPI_PM_TMR_BLK); pm_write16(0x68, ACPI_GPE0_BLK); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(0x66, ACPI_CPU_CONTROL); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 855cbc4..94f33b7 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -56,7 +56,7 @@ static void sb700_acpi_init(void) pmio_write(0x28, ACPI_GPE0_BLK & 0xFF); pmio_write(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pmio_write(0x26, ACPI_CPU_CONTROL & 0xFF); pmio_write(0x27, ACPI_CPU_CONTROL >> 8); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 24aa200..69bc3bd 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -53,7 +53,7 @@ static void sb800_acpi_init(void) pmio_write(0x68, ACPI_GPE0_BLK & 0xFF); pmio_write(0x69, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pmio_write(0x66, ACPI_CPU_CONTROL & 0xFF); pmio_write(0x67, ACPI_CPU_CONTROL >> 8);

1 0

Patch set updated for coreboot: 59c9317 amd/amdfam10: Fix incorrect core count identification
by Timothy Pearson 11 Feb '15

11 Feb '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8421 -gerrit commit 59c9317674ad2dd02855c6855b915a730ff343b6 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Feb 10 21:15:39 2015 -0600 amd/amdfam10: Fix incorrect core count identification The core count identification code in the PowerNow! _PSS ACPI object generation code was incorrectly copied from the model_fxx code. This code has been rewritten to properly return the number of cores installed in the system. Change-Id: I19567486f2de9dc2c43970addf4d91fa3d233a99 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/powernow_acpi.c | 36 ++++++++++++++++++++++++++------- 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c index d08f9f9..8b3ae37 100644 --- a/src/cpu/amd/model_10xxx/powernow_acpi.c +++ b/src/cpu/amd/model_10xxx/powernow_acpi.c @@ -69,6 +69,13 @@ static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_p /* * For details of this algorithm, please refer to the BDKG 3.62 page 69 +* +* WARNING: The core count algorithm below assumes that all processors +* are identical, with the same number of active cores. While the BKDG +* states the BIOS must enforce this coreboot does not currently do so. +* As a result it is possible that this code may break if an illegal +* processor combination is installed. If it does break please fix the +* code in the proper locations! */ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) { @@ -106,15 +113,31 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) processor_brand[48] = 0; printk(BIOS_INFO, "processor_brand=%s\n", processor_brand); + uint32_t dtemp; + uint32_t cpuid_fms; + uint8_t model; + uint8_t node_count; + /* * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit. * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1 - * cmp_cap : 0x0 SingleCore ; 0x1 DualCore ; 0x2 TripleCore ; 0x3 QuadCore ; 0x5 QuintupleCore ; 0x6 HexCore + * cmp_cap : 0x0 SingleCore ; 0x1 DualCore ; 0x2 TripleCore ; 0x3 QuadCore ; 0x4 QuintupleCore ; 0x5 HexCore */ - printk(BIOS_INFO, "Pstates Algorithm ...\n"); - cmp_cap = - (pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) & - 0x7000) >> 12; + printk(BIOS_INFO, "Pstates algorithm ...\n"); + /* Get CPU model */ + cpuid_fms = cpuid_eax(0x80000001); + model = ((cpuid_fms & 0xf0000) >> 16) | ((cpuid_fms & 0xf0) >> 4); + /* Get number of cores */ + dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8); + cmp_cap = (dtemp & 0x3000) >> 12; + if ((model == 0x8) || (model == 0x9)) /* revision D */ + cmp_cap |= (dtemp & 0x8000) >> 13; + /* Get number of nodes */ + dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x60); + node_count = ((dtemp & 0x70) >> 4) + 1; + /* Compute total number of cores installed in system */ + cmp_cap++; + cmp_cap *= node_count; Pstate_num = 0; @@ -125,7 +148,6 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) goto write_pstates; } - uint32_t dtemp; uint8_t pviModeFlag; uint8_t Pstate_max; uint8_t cpufid; @@ -237,7 +259,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) } write_pstates: - for (index = 0; index < (cmp_cap + 1); index++) + for (index = 0; index < cmp_cap; index++) write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_power, Pstate_latency, Pstate_control, Pstate_status, index, pcontrol_blk, plen, onlyBSP);

1 0

Patch set updated for coreboot: f54478c cpu/amd/model_10xxx: add Propus (00100F52h BL-C2) equivalent id
by Nicolas Reinecke 11 Feb '15

11 Feb '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8355 -gerrit commit f54478ced4c2f1d67581447d3fd3e9d607c13475 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Wed Feb 11 23:01:17 2015 +0100 cpu/amd/model_10xxx: add Propus (00100F52h BL-C2) equivalent id Change-Id: I32eccfb4eae176e0155c53efaf463258653eefc2 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/cpu/amd/model_10xxx/update_microcode.c | 44 ++++++++---------------------- 1 file changed, 12 insertions(+), 32 deletions(-) diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index 25da838..f8bde9b 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -21,27 +21,6 @@ #include <stdint.h> #include <cpu/amd/microcode.h> -/* From the Revision Guide : - * Equivalent Processor Table for AMD Family 10h Processors - * - * Installed Processor Equivalent Processor - * Revision ID Revision ID - * 00100F00h 1000h - * 00100F01h 1000h - * 00100F02h 1000h - * 00100F20h 1020h - * 00100F21h (DR-B1) 1020h - * 00100F2Ah (DR-BA) 1020h - * 00100F22h (DR-B2) 1022h - * 00100F23h (DR-B3) 1022h - * 00100F42h (RB-C2) 1041h - * 00100F43h (RB-C3) 1043h - * 00100F62h (DA-C2) 1062h - * 00100F63h (DA-C3) 1043h - * 00100F81h (HY-D1) 1081h - * 00100FA0h (PH-E0) 10A0h - */ - struct id_mapping { uint32_t orig_id; uint16_t new_id; @@ -53,16 +32,17 @@ static u16 get_equivalent_processor_rev_id(u32 orig_id) { { 0x100f01, 0x1000 }, { 0x100f02, 0x1000 }, { 0x100f20, 0x1020 }, - { 0x100f21, 0x1020 }, - { 0x100f2A, 0x1020 }, - { 0x100f22, 0x1022 }, - { 0x100f23, 0x1022 }, - { 0x100f42, 0x1041 }, - { 0x100f43, 0x1043 }, - { 0x100f62, 0x1062 }, - { 0x100f63, 0x1043 }, - { 0x100f81, 0x1081 }, - { 0x100fa0, 0x10A0 }, + { 0x100f21, 0x1020 }, /* DR-B1 */ + { 0x100f2A, 0x1020 }, /* DR-BA */ + { 0x100f22, 0x1022 }, /* DR-B2 */ + { 0x100f23, 0x1022 }, /* DR-B3 */ + { 0x100f42, 0x1041 }, /* RB-C2 */ + { 0x100f43, 0x1043 }, /* RB-C3 */ + { 0x100f52, 0x1041 }, /* BL-C2 */ + { 0x100f62, 0x1062 }, /* DA-C2 */ + { 0x100f63, 0x1043 }, /* DA-C3 */ + { 0x100f81, 0x1081 }, /* HY-D1 */ + { 0x100fa0, 0x10A0 }, /* PH-E0 */ /* Array terminator */ { 0xffffff, 0x0000 }, @@ -73,7 +53,7 @@ static u16 get_equivalent_processor_rev_id(u32 orig_id) { new_id = 0; - for (i = 0; id_mapping_table[i].orig_id != 0xffffff; i++ ) { + for (i = 0; id_mapping_table[i].orig_id != 0xffffff; i++) { if (id_mapping_table[i].orig_id == orig_id) { new_id = id_mapping_table[i].new_id; break;

1 0

Patch merged into coreboot/master: 2f5bb65 asus/m4a785/Kconfig: Add vgabios PCI id
by gerrit＠coreboot.org 11 Feb '15

11 Feb '15

the following patch was just integrated into master: commit 2f5bb6548d3314c31cf8f935cb54f17a00a52cb7 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Jan 4 16:26:08 2015 +0100 asus/m4a785/Kconfig: Add vgabios PCI id The PCI id defaults to 1106,3230 -> via chrome 9 ... Tested on the board. Change-Id: I5ad91faec9c97f34c8ca48eee9198237e9ea8336 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/8177 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8177 for details. -gerrit

1 0

Patch merged into coreboot/master: fa0b3c8 cpu/amd/model_10xxx: update microcode
by gerrit＠coreboot.org 11 Feb '15

11 Feb '15

the following patch was just integrated into master: commit fa0b3c8cdd4754bca17f723ace5664b660399697 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Wed Feb 4 22:05:31 2015 +0100 cpu/amd/model_10xxx: update microcode microcode updates are extracted from: www.amd64.org/microcode.html Mircocode versions of 1020h and 1022h are more recent in coreboot than inside the AMD archive. Change-Id: I9f52accc1ebc7057890a769a059048e9982109d2 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/8354 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8354 for details. -gerrit

1 0

Patch merged into coreboot/master: 44d0fd9 Add Linux kernel's checkpatch.pl script
by gerrit＠coreboot.org 11 Feb '15

11 Feb '15

the following patch was just integrated into master: commit 44d0fd9841a1b8f2487ed9d886eb7c8245831d62 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 11 01:49:00 2015 +0100 Add Linux kernel's checkpatch.pl script Carefully staging to enable checkpatch for coreboot contributions. The biggest offender of the rules enforced by checkpatch I have found so far is ... Oh, you guessed it? It's checkpatch itself. Change-Id: Iaacbcd52c3bc22b083a24127a3ea17a7cc706245 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/8417 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8417 for details. -gerrit

1 0

New patch to review for coreboot: 9c362c6 NOTFORMERGE: Makefile.inc: don't use git for version timestamp
by Francis Rowe 11 Feb '15

11 Feb '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8423 -gerrit commit 9c362c64686c6022ffdc88551e83c4d898338106 Author: Francis Rowe <info(a)gluglug.org.uk> Date: Wed Feb 11 18:24:43 2015 +0000 NOTFORMERGE: Makefile.inc: don't use git for version timestamp If coreboot is built without the .git* files, there is this error: src/lib/version.c:38:75: error: expected expression before ';' This is because the COREBOOT_VERSION_TIMESTAMP define in build/build.h, as generated by Makefile.inc, relies on git. Change-Id: Ic6b857731f8cb212e30c627037577d837ac783b1 Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- Makefile.inc | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 0c6aafa..a900b97 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -276,13 +276,8 @@ $(obj)/build.h: .xcompile printf "#ifndef __BUILD_H\n" >> $(obj)/build.ht printf "#define __BUILD_H\n\n" >> $(obj)/build.ht printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht - if git update-index -q --refresh >/dev/null; ! git diff-index --quiet HEAD; then \ - printf "/* `LANG= TZ=UTC git log --date=local --pretty=format:%cd -1` UTC */\n" >> $(obj)/build.ht; \ - printf "#define COREBOOT_VERSION_TIMESTAMP `LANG= git log --pretty=format:%ct -1`\n" >> $(obj)/build.ht; \ - else \ - printf "/* `LANG= TZ=UTC date` */\n" >> $(obj)/build.ht; \ - printf "#define COREBOOT_VERSION_TIMESTAMP `LANG= date +%s`\n" >> $(obj)/build.ht; \ - fi + printf "/* `LANG= TZ=UTC date` */\n" >> $(obj)/build.ht; \ + printf "#define COREBOOT_VERSION_TIMESTAMP `LANG= date +%s`\n" >> $(obj)/build.ht; \ printf "#define COREBOOT_ORIGIN_GIT_REVISION \"`LANG= git log remotes/origin/master -1 --format=format:%h`\"\n" >> $(obj)/build.ht printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht

1 0

Patch set updated for coreboot: 667e042 intel/fsp_baytrail: Add Windows 8.1 boot support for Bay Trail SoCs
by Brenton Dong 11 Feb '15

11 Feb '15

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8408 -gerrit commit 667e0429e473cf0f13e422b9c3d611c281fb9840 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Tue Feb 10 14:02:31 2015 -0700 intel/fsp_baytrail: Add Windows 8.1 boot support for Bay Trail SoCs Add PCI Root Port IRQ Routing in a new file 'pcie.asl' needed for Windows. TEST=Boots to Windows 8.1 on MinnowBoard Max with FSP and Intel UEFI Payload. Change-Id: I1d01f9589407219f533c70fde867cb948751fb20 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/soc/intel/fsp_baytrail/acpi/pcie.asl | 166 +++++++++++++++++++++++ src/soc/intel/fsp_baytrail/acpi/southcluster.asl | 5 + src/soc/intel/fsp_baytrail/acpi/xhci.asl | 0 3 files changed, 171 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/acpi/pcie.asl b/src/soc/intel/fsp_baytrail/acpi/pcie.asl new file mode 100755 index 0000000..6491d19 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/acpi/pcie.asl @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(RP1P, Package() +{ + // PCIE Port #1 Slot + Package() {0x0000FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() {0x0000FFFF, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() {0x0000FFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() {0x0000FFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 }, +}) + +Name(RP1A, Package() +{ + // PCIE Port #1 Slot + Package() {0x0000FFFF, 0, 0, 16 }, + Package() {0x0000FFFF, 1, 0, 17 }, + Package() {0x0000FFFF, 2, 0, 18 }, + Package() {0x0000FFFF, 3, 0, 19 }, +}) + +Name(RP2P, Package() +{ + // PCIE Port #2 Slot + Package() {0x0000FFFF, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() {0x0000FFFF, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() {0x0000FFFF, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() {0x0000FFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 }, +}) + +Name(RP2A, Package() +{ + // PCIE Port #2 Slot + Package() {0x0000FFFF, 0, 0, 17 }, + Package() {0x0000FFFF, 1, 0, 18 }, + Package() {0x0000FFFF, 2, 0, 19 }, + Package() {0x0000FFFF, 3, 0, 16 }, +}) + +Name(RP3P, Package() +{ + // PCIE Port #3 Slot + Package() {0x0000FFFF, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() {0x0000FFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() {0x0000FFFF, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() {0x0000FFFF, 3, \_SB.PCI0.LPCB.LNKB, 0 }, +}) + +Name(RP3A, Package() +{ + // PCIE Port #3 Slot + Package() {0x0000FFFF, 0, 0, 18 }, + Package() {0x0000FFFF, 1, 0, 19 }, + Package() {0x0000FFFF, 2, 0, 16 }, + Package() {0x0000FFFF, 3, 0, 17 }, +}) + +Name(RP4P, Package() +{ + // PCIE Port #4 Slot + Package() {0x0000FFFF, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() {0x0000FFFF, 1, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() {0x0000FFFF, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() {0x0000FFFF, 3, \_SB.PCI0.LPCB.LNKC, 0 }, +}) + +Name(RP4A, Package() +{ + // PCIE Port #4 Slot + Package() {0x0000FFFF, 0, 0, 19 }, + Package() {0x0000FFFF, 1, 0, 16 }, + Package() {0x0000FFFF, 2, 0, 17 }, + Package() {0x0000FFFF, 3, 0, 18 }, +}) + +// +// PCIE Root Port #1 +// +Device(RP01) +{ + Name(_ADR, 0x001C0000) + Name(_PRW, Package() { + 0, 0 + }) + + Method(_PRT,0) { + If(PICM) { + Return (RP1A) + } Else { + Return (RP1P) + } + } +} + +// +// PCIE Root Port #2 +// +Device(RP02) +{ + Name(_ADR, 0x001C0001) + Name(_PRW, Package() { + 0, 0 + }) + + Method(_PRT,0) { + If(PICM) { + Return (RP2A) + } Else { + Return (RP2P) + } + } +} + +// +// PCIE Root Port #3 +// +Device(RP03) +{ + Name(_ADR, 0x001C0002) + Name(_PRW, Package() { + 0, 0 + }) + + Method(_PRT,0) { + If(PICM) { + Return (RP3A) + } Else { + Return (RP3P) + } + } +} + +// +// PCIE Root Port #4 +// +Device(RP04) +{ + Name(_ADR, 0x001C0003) + Name(_PRW, Package() { + 0, 0 + }) + + Method(_PRT,0) { + If(PICM) { + Return (RP4A) + } Else { + Return (RP4P) + } + } +} diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl old mode 100644 new mode 100755 index 3ee9ee0..f074a55 --- a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl +++ b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl @@ -259,6 +259,11 @@ Device (IOSF) #include "xhci.asl" #endif +#if INCLUDE_PCIE +// PCIE Device +#include "pcie.asl" +#endif + // IRQ routing for each PCI device #include "irqroute.asl" diff --git a/src/soc/intel/fsp_baytrail/acpi/xhci.asl b/src/soc/intel/fsp_baytrail/acpi/xhci.asl old mode 100644 new mode 100755

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coreboot-gerrit February 2015