coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: broadwell: Fix SATA Gen3 DTLE configuration registers
by gerrit＠coreboot.org 27 Dec '15

27 Dec '15

the following patch was just integrated into master: commit 791d0580b8961decbc9a841b58341340ac206c4f Author: Duncan Laurie <dlaurie(a)google.com> Date: Tue Dec 22 17:09:16 2015 -0800 broadwell: Fix SATA Gen3 DTLE configuration registers The port0 and port1 registers were swapped, which meant it did not work to apply the DTLE settings to the correct SATA port. This was tested on an unreleased mainboard but is verified with the documentation to be the correct register addresses now. Change-Id: Ifb8890a563a741129ec8ddf72e73ab021c7d33da Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/12793 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/12793 for details. -gerrit

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Patch merged into coreboot/master: broadwell: Fix CONFIG_SPI_CONSOLE usage
by gerrit＠coreboot.org 27 Dec '15

27 Dec '15

the following patch was just integrated into master: commit 9d08c4a5fd006e14060d03e590df1f31ce3e7c5c Author: Duncan Laurie <dlaurie(a)google.com> Date: Tue Dec 22 17:08:21 2015 -0800 broadwell: Fix CONFIG_SPI_CONSOLE usage Locking down the SPI controller with a specific opcode menu kills the SPI console. Skip this when the SPI console config option is enabled. This was tested using an em100 and google/samus board to ensure the console output does not stop at the finalize step. Change-Id: Ie460f583214b47544e92d4afa8ef862563a11e36 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/12792 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/12792 for details. -gerrit

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Patch set updated for coreboot: southbridge/intel/i82801gx: Add option to skip MADT irq override
by Damien Zammit 27 Dec '15

27 Dec '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12795 -gerrit commit 0e7867505b568a2ed61c4caa5eda56a4a6976b26 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Dec 23 16:54:29 2015 +1100 southbridge/intel/i82801gx: Add option to skip MADT irq override Provides Kconfig option IRQ9_MADT_OVERRIDE to skip overriding IRQ9 in MADT. Required on GA-G41M-ES2L mainboard. Without skipping this irq override, the above board reports: "irq9: nobody cared" in Linux kernel log and irq 9 gets disabled. Change-Id: I865ad79c7c89f6eaf91653fbda5762542702274c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/southbridge/intel/i82801gx/Kconfig | 6 ++++++ src/southbridge/intel/i82801gx/lpc.c | 8 ++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index c435b99..4d747fc 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -25,6 +25,12 @@ config SOUTHBRIDGE_INTEL_I82801GX if SOUTHBRIDGE_INTEL_I82801GX +config IRQ9_MADT_OVERRIDE + bool + default y + help + When unset, prevents ACPI from overriding IRQ9 in MADT + config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 4e9711c..407d336 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -474,9 +474,13 @@ unsigned long acpi_fill_madt(unsigned long current) /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); + if (IS_ENABLED(CONFIG_IRQ9_MADT_OVERRIDE)) { + current += acpi_create_madt_irqoverride( + (acpi_madt_irqoverride_t *) current, + 0, 9, 9, MP_IRQ_POLARITY_HIGH + | MP_IRQ_TRIGGER_LEVEL); + } return current; }

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Patch set updated for coreboot: northbridge/intel/x4x: Native raminit
by Damien Zammit 27 Dec '15

27 Dec '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11307 -gerrit commit 84575a51b38aaf0e3edd76f04c8590c7dbac11a1 Author: Damien Zammit <damien(a)zamaudio.com> Date: Thu Aug 20 00:37:05 2015 +1000 northbridge/intel/x4x: Native raminit Passes memtest86+ with either one or two sticks of 2GB ram but memory map needs a hole at 0xa0000000 to 0xc0000000 Change-Id: Ib34d862cb48b49c054a505fffcba1c17aeb39436 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/Makefile.inc | 2 + src/northbridge/intel/x4x/raminit.c | 491 +++++++ src/northbridge/intel/x4x/raminit_ddr2.c | 2082 ++++++++++++++++++++++++++++++ 3 files changed, 2575 insertions(+) diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 8d1247e..34d9b0f 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -17,6 +17,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y) romstage-y += early_init.c +romstage-y += raminit.c +romstage-y += raminit_ddr2.c romstage-y += ram_calc.c ramstage-y += acpi.c diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c new file mode 100644 index 0000000..10ff287 --- /dev/null +++ b/src/northbridge/intel/x4x/raminit.c @@ -0,0 +1,491 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <delay.h> +#include <halt.h> +#include <lib.h> +#include <northbridge/intel/x4x/x4x.h> +#include <pc80/mc146818rtc.h> +#include <spd.h> +#include <string.h> + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +static void sdram_read_spds(struct sysinfo *s) +{ + u8 i, j, chan; + int status = 0; + FOR_EACH_DIMM(i) { + for (j = 0; j < 64; j++) { + status = spd_read_byte(s->spd_map[i], j); + if (status < 0) { + s->dimms[i].card_type = 0; + break; + } + s->dimms[i].spd_data[j] = (u8) status; + if (j == 62) + s->dimms[i].card_type = ((u8) status) & 0x1f; + } + hexdump(s->dimms[i].spd_data, 64); + } + + s->spd_type = 0; + int fail = 1; + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + switch ((enum ddrxspd) s->dimms[i].spd_data[2]) { + case DDR2SPD: + if (s->spd_type == 0) { + s->spd_type = DDR2; + } else if (s->spd_type == DDR3) { + die("DIMM type mismatch\n"); + } + break; + case DDR3SPD: + default: + if (s->spd_type == 0) { + s->spd_type = DDR3; + } else if (s->spd_type == DDR2) { + die("DIMM type mismatch\n"); + } + break; + } + } + if (s->spd_type == DDR3) { + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + s->dimms[i].sides = (s->dimms[i].spd_data[5] & 0x0f) + 1; + s->dimms[i].ranks = ((s->dimms[i].spd_data[7] >> 3) & 0x7) + 1; + s->dimms[i].chip_capacity = (s->dimms[i].spd_data[4] & 0xf); + s->dimms[i].banks = 8; + s->dimms[i].rows = ((s->dimms[i].spd_data[5] >> 3) & 0x7) + 12; + s->dimms[i].cols = (s->dimms[i].spd_data[5] & 0x7) + 9; + s->dimms[i].cas_latencies = 0xfe; + s->dimms[i].cas_latencies &= (s->dimms[i].spd_data[14] << 1); + if (s->dimms[i].cas_latencies == 0) + s->dimms[i].cas_latencies = 0x40; + s->dimms[i].tAAmin = s->dimms[i].spd_data[16]; + s->dimms[i].tCKmin = s->dimms[i].spd_data[12]; + s->dimms[i].width = s->dimms[i].spd_data[7] & 0x7; + s->dimms[i].page_size = s->dimms[i].width * (1 << s->dimms[i].cols); // Bytes + s->dimms[i].tRAS = ((s->dimms[i].spd_data[21] & 0xf) << 8) | + s->dimms[i].spd_data[22]; + s->dimms[i].tRP = s->dimms[i].spd_data[20]; + s->dimms[i].tRCD = s->dimms[i].spd_data[18]; + s->dimms[i].tWR = s->dimms[i].spd_data[17]; + fail = 0; + } + } else if (s->spd_type == DDR2) { + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + s->dimms[i].sides = (s->dimms[i].spd_data[5] & 0x7) + 1; + s->dimms[i].banks = (s->dimms[i].spd_data[17] >> 2) - 1; + s->dimms[i].chip_capacity = s->dimms[i].banks; + s->dimms[i].rows = s->dimms[i].spd_data[3];// - 12; + s->dimms[i].cols = s->dimms[i].spd_data[4];// - 9; + s->dimms[i].cas_latencies = 0x78; + s->dimms[i].cas_latencies &= s->dimms[i].spd_data[18]; + if (s->dimms[i].cas_latencies == 0) + s->dimms[i].cas_latencies = 7; + s->dimms[i].tAAmin = s->dimms[i].spd_data[26]; + s->dimms[i].tCKmin = s->dimms[i].spd_data[25]; + s->dimms[i].width = (s->dimms[i].spd_data[13] >> 3) - 1; + s->dimms[i].page_size = (s->dimms[i].width+1) * (1 << s->dimms[i].cols); // Bytes + s->dimms[i].tRAS = s->dimms[i].spd_data[30]; + s->dimms[i].tRP = s->dimms[i].spd_data[27]; + s->dimms[i].tRCD = s->dimms[i].spd_data[29]; + s->dimms[i].tWR = s->dimms[i].spd_data[36]; + s->dimms[i].ranks = s->dimms[i].sides; // XXX + + printk(BIOS_DEBUG, "DIMM %d\n", i); + printk(BIOS_DEBUG, " Sides : %d\n", s->dimms[i].sides); + printk(BIOS_DEBUG, " Banks : %d\n", s->dimms[i].banks); + printk(BIOS_DEBUG, " Ranks : %d\n", s->dimms[i].ranks); + printk(BIOS_DEBUG, " Rows : %d\n", s->dimms[i].rows); + printk(BIOS_DEBUG, " Cols : %d\n", s->dimms[i].cols); + printk(BIOS_DEBUG, " Page size : %d\n", s->dimms[i].page_size); + printk(BIOS_DEBUG, " Width : %d\n", (s->dimms[i].width+1)*8); + fail = 0; + } + } + if (fail) { + die("No memory dimms, halt\n"); + } + + FOR_EACH_POPULATED_CHANNEL(s->dimms, chan) { + if (s->dimms[chan>>1].sides == 0) { + // NC + if (s->dimms[(chan>>1) + 1].sides == 0) { + // NC/NC + s->dimm_config[chan] = 0; + } else if (s->dimms[(chan>>1) + 1].sides == 1) { + // NC/SS + if (s->dimms[(chan>>1) + 1].width == 0) { + // NC/8SS + s->dimm_config[chan] = 4; + } else { + // NC/16SS + s->dimm_config[chan] = 12; + } + } else { + // NC/DS + if (s->dimms[(chan>>1) + 1].width == 0) { + // NC/8DS + s->dimm_config[chan] = 8; + } else { + // NOT SUPPORTED + die("16DS Not supported\n"); + } + } + } else if (s->dimms[chan>>1].sides == 1) { + // SS + if (s->dimms[(chan>>1) + 1].sides == 0) { + // SS/NC + if (s->dimms[chan>>1].width == 0) { + // 8SS/NC + s->dimm_config[chan] = 1; + } else { + // 16SS/NC + s->dimm_config[chan] = 3; + } + } else if (s->dimms[(chan>>1) + 1].sides == 1) { + // SS/SS + if (s->dimms[chan>>1].width == 0) { + if (s->dimms[(chan>>1) + 1].width == 0) { + // 8SS/8SS + s->dimm_config[chan] = 5; + } else { + // 8SS/16SS + s->dimm_config[chan] = 13; + } + } else { + if (s->dimms[(chan>>1) + 1].width == 0) { + // 16SS/8SS + s->dimm_config[chan] = 7; + } else { + // 16SS/16SS + s->dimm_config[chan] = 15; + } + } + } else { + // SS/DS + if (s->dimms[chan>>1].width == 0) { + if (s->dimms[(chan>>1) + 1].width == 0) { + // 8SS/8DS + s->dimm_config[chan] = 9; + } else { + die("16DS not supported\n"); + } + } else { + if (s->dimms[(chan>>1) + 1].width == 0) { + // 16SS/8DS + s->dimm_config[chan] = 11; + } else { + die("16DS not supported\n"); + } + } + } + } else { + // DS + if (s->dimms[(chan>>1) + 1].sides == 0) { + // DS/NC + if (s->dimms[chan>>1].width == 0) { + // 8DS/NC + s->dimm_config[chan] = 2; + } else { + die("16DS not supported\n"); + } + } else if (s->dimms[(chan>>1) + 1].sides == 1) { + // DS/SS + if (s->dimms[chan>>1].width == 0) { + if (s->dimms[(chan>>1) + 1].width == 0) { + // 8DS/8SS + s->dimm_config[chan] = 6; + } else { + // 8DS/16SS + s->dimm_config[chan] = 14; + } + } else { + die("16DS not supported\n"); + } + } else { + // DS/DS + if (s->dimms[chan>>1].width == 0 && s->dimms[(chan>>1)+1].width == 0) { + // 8DS/8DS + s->dimm_config[chan] = 10; + } + } + } + printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]); + } +} + +static u8 lsbpos(u8 val) //Forward +{ + u8 i; + for (i = 0; (i < 8) && ((val & (1 << i)) == 0); i++); + return i; +} + +static u8 msbpos(u8 val) //Reverse +{ + u8 i; + for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); + return i; +} + +static void mchinfo_ddr2(struct sysinfo *s) +{ + const u32 eax = cpuid_ext(0x04, 0).eax; + s->cores = ((eax >> 26) & 0x3f) + 1; + printk(BIOS_SPEW, "%d CPU cores\n", s->cores); + + u32 capid = pci_read_config16(PCI_DEV(0,0,0), 0xe8); + if (!(capid & (1<<(79-64)))) { + printk(BIOS_SPEW, "iTPM enabled\n"); + } + + capid = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); + if (!(capid & (1<<(57-32)))) { + printk(BIOS_SPEW, "ME enabled\n"); + } + + if (!(capid & (1<<(56-32)))) { + printk(BIOS_SPEW, "AMT enabled\n"); + } + + s->max_ddr2_mhz = (capid & (1<<(53-32)))?667:800; + printk(BIOS_SPEW, "Capable of DDR2 of %d MHz or lower\n", s->max_ddr2_mhz); + + if (!(capid & (1<<(48-32)))) { + printk(BIOS_SPEW, "VT-d enabled\n"); + } +} + +static void sdram_detect_ram_speed(struct sysinfo *s) +{ + u8 i; + u8 commoncas = 0; + u8 cas; + u8 lowcas; + u8 highcas; + u8 maxfreq; + u8 freq = 0; + + // Find max FSB speed + switch (MCHBAR32(0xc00) & 0x7) { + case 0x0: + s->max_fsb = FSB_CLOCK_1066MHz; + break; + case 0x2: + s->max_fsb = FSB_CLOCK_800MHz; + break; + case 0x4: + s->max_fsb = FSB_CLOCK_1333MHz; + break; + default: + die("Can't find FSB\n"); + break; + } + + // Find RAM speed + maxfreq = (u8) ((pci_read_config16(PCI_DEV(0,0,0), 0xea) >> 4) & 0x3f); + if (s->spd_type == DDR2) { + + // Limit frequency for MCH + maxfreq &= 0x7; + freq = MEM_CLOCK_800MHz; + if (maxfreq) { + freq = maxfreq; + } + if (freq > MEM_CLOCK_800MHz) { + freq = MEM_CLOCK_800MHz; + } + + // Detect a common CAS latency + commoncas = 0xff; + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + commoncas &= s->dimms[i].spd_data[18]; + } + if (commoncas == 0) { + die("No common CAS among dimms\n"); + } + + // Start with fastest common CAS + cas = 0; + highcas = msbpos(commoncas); + lowcas = lsbpos(commoncas); + + while (cas == 0 && highcas >= lowcas) { + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + switch (freq) { + case MEM_CLOCK_800MHz: + if ((s->dimms[i].spd_data[9] > 0x25) || + (s->dimms[i].spd_data[10] > 0x40)) { + // CAS too fast, lower it + highcas--; + break; + } else { + cas = highcas; + } + break; + case MEM_CLOCK_667MHz: + default: + if ((s->dimms[i].spd_data[9] > 0x30) || + (s->dimms[i].spd_data[10] > 0x45)) { + // CAS too fast, lower it + highcas--; + break; + } else { + cas = highcas; + } + break; + } + } + } + if (highcas < lowcas) { + // Timings not supported by MCH, lower the frequency + freq--; + cas = 0; + highcas = msbpos(commoncas); + lowcas = lsbpos(commoncas); + while (cas == 0 && highcas >= lowcas) { + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + switch (freq) { + case MEM_CLOCK_800MHz: + if ((s->dimms[i].spd_data[23] > 0x25) || + (s->dimms[i].spd_data[24] > 0x40)) { + // CAS too fast, lower it + highcas--; + break; + } else { + cas = highcas; + } + break; + case MEM_CLOCK_667MHz: + default: + if ((s->dimms[i].spd_data[23] > 0x30) || + (s->dimms[i].spd_data[24] > 0x45)) { + // CAS too fast, lower it + highcas--; + break; + } else { + cas = highcas; + } + break; + } + } + } + } + s->selected_timings.mem_clk = freq; + s->selected_timings.CAS = cas; + + } else { // DDR3 + // Limit frequency for MCH + maxfreq >>= 3; + freq = MEM_CLOCK_1333MHz; + if (maxfreq) { + freq = maxfreq + 2; + } + if (freq > MEM_CLOCK_1333MHz) { + freq = MEM_CLOCK_1333MHz; + } + + // Limit DDR speed to FSB speed + switch (s->max_fsb) { + case FSB_CLOCK_800MHz: + if (freq > MEM_CLOCK_800MHz) { + freq = MEM_CLOCK_800MHz; + } + break; + case FSB_CLOCK_1066MHz: + if (freq > MEM_CLOCK_1066MHz) { + freq = MEM_CLOCK_1066MHz; + } + break; + case FSB_CLOCK_1333MHz: + if (freq > MEM_CLOCK_1333MHz) { + freq = MEM_CLOCK_1333MHz; + } + break; + default: + die("Invalid FSB\n"); + break; + } + + // TODO: CAS detection for DDR3 + } +} + +/** + * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 + */ +void sdram_initialize(int boot_path, const u8 *spd_map) +{ + struct sysinfo s; + u8 reg8; + + printk(BIOS_DEBUG, "Setting up RAM controller.\n"); + + pci_write_config8(PCI_DEV(0,0,0), 0xdf, 0xff); + + memset(&s, 0, sizeof(struct sysinfo)); + + s.boot_path = boot_path; + s.spd_map[0] = spd_map[0]; + s.spd_map[1] = spd_map[1]; + s.spd_map[2] = spd_map[2]; + s.spd_map[3] = spd_map[3]; + + /* Detect dimms per channel */ + s.dimms_per_ch = 2; + reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xe9); + if (reg8 & 0x10) + s.dimms_per_ch = 1; + + printk(BIOS_DEBUG, "Dimms per channel: %d\n", s.dimms_per_ch); + + mchinfo_ddr2(&s); + + sdram_read_spds(&s); + + /* Choose Common Frequency */ + sdram_detect_ram_speed(&s); + + switch (s.spd_type) { + case DDR2: + raminit_ddr2(&s); + break; + case DDR3: + // FIXME Add: raminit_ddr3(&s); + break; + default: + die("Unknown DDR type\n"); + break; + } + + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80); + + reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf4); + pci_write_config8(PCI_DEV(0,0,0), 0xf4, reg8 | 1); + printk(BIOS_DEBUG, "RAM initialization finished.\n"); +} diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c new file mode 100644 index 0000000..b96ea23 --- /dev/null +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -0,0 +1,2082 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <commonlib/helpers.h> +#include <delay.h> +#include <northbridge/intel/x4x/x4x.h> + +static inline void barrier(void) +{ + asm volatile("mfence": : :"memory"); +} + +static u32 fsb2mhz(u32 speed) +{ + return (speed * 267) + 800; +} + +static u32 ddr2mhz(u32 speed) +{ + static const u16 mhz[] = { 0, 0, 667, 800, 1067, 1333 }; + + if (speed >= ARRAY_SIZE(mhz)) + return 0; + + return mhz[speed]; +} + +static u8 msbpos(u8 val) //Reverse +{ + u8 i; + for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); + return i; +} + +static void sdram_detect_smallest_params2(struct sysinfo *s) +{ + u16 mult[6] = { + 5000, // 400 + 3750, // 533 + 3000, // 667 + 2500, // 800 + 1875, // 1066 + 1500, // 1333 + }; + + u8 i; + u32 tmp; + u32 maxtras = 0; + u32 maxtrp = 0; + u32 maxtrcd = 0; + u32 maxtwr = 0; + u32 maxtrfc = 0; + u32 maxtwtr = 0; + u32 maxtrrd = 0; + u32 maxtrtp = 0; + + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + maxtras = MAX(maxtras, s->dimms[i].spd_data[30] * 1000); + maxtrp = MAX(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); + maxtrcd = MAX(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2); + maxtwr = MAX(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); + maxtrfc = MAX(maxtrfc, s->dimms[i].spd_data[42] * 1000 + + (s->dimms[i].spd_data[40] & 0xf)); + maxtwtr = MAX(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2); + maxtrrd = MAX(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2); + maxtrtp = MAX(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2); + } + for (i = 9; i < 24; i++) { + tmp = mult[s->selected_timings.mem_clk] * i; + if (tmp >= maxtras) { + s->selected_timings.tRAS = i; + break; + } + } + for (i = 3; i < 10; i++) { + tmp = mult[s->selected_timings.mem_clk] * i; + if (tmp >= maxtrp) { + s->selected_timings.tRP = i; + break; + } + } + for (i = 3; i < 10; i++) { + tmp = mult[s->selected_timings.mem_clk] * i; + if (tmp >= maxtrcd) { + s->selected_timings.tRCD = i; + break; + } + } + for (i = 3; i < 15; i++) { + tmp = mult[s->selected_timings.mem_clk] * i; + if (tmp >= maxtwr) { + s->selected_timings.tWR = i; + break; + } + } + for (i = 15; i < 78; i++) { + tmp = mult[s->selected_timings.mem_clk] * i; + if (tmp >= maxtrfc) { + s->selected_timings.tRFC = ((i + 16) & 0xfe) - 15; + break; + } + } + for (i = 4; i < 15; i++) { + tmp = mult[s->selected_timings.mem_clk] * i; + if (tmp >= maxtwtr) { + s->selected_timings.tWTR = i; + break; + } + } + for (i = 2; i < 15; i++) { + tmp = mult[s->selected_timings.mem_clk] * i; + if (tmp >= maxtrrd) { + s->selected_timings.tRRD = i; + break; + } + } + for (i = 4; i < 15; i++) { + tmp = mult[s->selected_timings.mem_clk] * i; + if (tmp >= maxtrtp) { + s->selected_timings.tRTP = i; + break; + } + } + + s->selected_timings.fsb_clk = s->max_fsb; + + printk(BIOS_DEBUG, "Selected timings:\n"); + printk(BIOS_DEBUG, " FSB: %dMHz\n", fsb2mhz(s->selected_timings.fsb_clk)); + printk(BIOS_DEBUG, " DDR: %dMHz\n", ddr2mhz(s->selected_timings.mem_clk)); + + printk(BIOS_DEBUG, " CAS: %d\n", s->selected_timings.CAS); + printk(BIOS_DEBUG, " tRAS: %d\n", s->selected_timings.tRAS); + printk(BIOS_DEBUG, " tRP: %d\n", s->selected_timings.tRP); + printk(BIOS_DEBUG, " tRCD: %d\n", s->selected_timings.tRCD); + printk(BIOS_DEBUG, " tWR: %d\n", s->selected_timings.tWR); + printk(BIOS_DEBUG, " tRFC: %d\n", s->selected_timings.tRFC); + printk(BIOS_DEBUG, " tWTR: %d\n", s->selected_timings.tWTR); + printk(BIOS_DEBUG, " tRRD: %d\n", s->selected_timings.tRRD); + printk(BIOS_DEBUG, " tRTP: %d\n", s->selected_timings.tRTP); +} + +static void clkcross_ddr2(struct sysinfo *s) +{ + u32 c04, c50, c54, x6d8, x6dc, x6e8, x6ec, x6f8, x6fc, x700, x704, x708, x70c; + + MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15); + + if ((s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) && + (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { + c04 = 0x1f1f1f1f; + c50 = 0x1a07070b; + c54 = 0x0; + x6d8 = 0x10000000; + x6dc = 0x20010208; + x6e8 = 0x04080000; + x6ec = 0x10010002; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x02000000; + x704 = 0x04000100; + x708 = 0x08000000; + x70c = 0x10200204; + } else if ((s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) && + (s->selected_timings.mem_clk == MEM_CLOCK_800MHz)) { + c04 = 0xffffffff; + c50 = 0x05030305; + c54 = 0x0000ffff; + x6d8 = 0x0; + x6dc = 0x08010204; + x6e8 = 0x0; + x6ec = 0x08010204; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x0; + x704 = 0x00020001; + x708 = 0x0; + x70c = 0x04080102; + } else if ((s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) && + (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { + c04 = 0x6d5b1f1f; + c50 = 0x0f0f0f0f; + c54 = 0x0; + x6d8 = 0x20000000; + x6dc = 0x80020410; + x6e8 = 0x02040008; + x6ec = 0x10000100; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x04000000; + x704 = 0x08000102; + x708 = 0x20000000; + x70c = 0x40010208; + } else if ((s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) && + (s->selected_timings.mem_clk == MEM_CLOCK_800MHz)) { + c04 = 0x07070707; + c50 = 0x06030303; + c54 = 0x0; + x6d8 = 0x0; + x6dc = 0x08010200; + x6e8 = 0x0; + x6ec = 0x04000102; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x0; + x704 = 0x00020001; + x708 = 0x0; + x70c = 0x02040801; + } else if ((s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) && + (s->selected_timings.mem_clk == MEM_CLOCK_1066MHz)) { + c04 = 0xffffffff; + c50 = 0x05030305; + c54 = 0x0000ffff; + x6d8 = 0x0; + x6dc = 0x04080102; + x6e8 = 0x0; + x6ec = 0x08010204; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x0; + x704 = 0x00020001; + x708 = 0x0; + x70c = 0x02040801; + } else if ((s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) && + (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { + c04 = 0x05050303; + c50 = 0xffffffff; + c54 = 0xffff0000; + x6d8 = 0x0; + x6dc = 0x08020000; + x6e8 = 0x0; + x6ec = 0x00020001; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x0; + x704 = 0x08010204; + x708 = 0x0; + x70c = 0x04010000; + } else if ((s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) && + (s->selected_timings.mem_clk == MEM_CLOCK_800MHz)) { + c04 = 0x0d0b0707; + c50 = 0x3e1f1f2f; + c54 = 0x01010000; + x6d8 = 0x0; + x6dc = 0x10020400; + x6e8 = 0x02000000; + x6ec = 0x00040100; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x04080000; + x704 = 0x00100102; + x708 = 0x0; + x70c = 0x08100200; + } else if ((s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) && + (s->selected_timings.mem_clk == MEM_CLOCK_1066MHz)) { + c04 = 0x0f0f0f0f; + c50 = 0x5b1f1f6d; + c54 = 0x0; + x6d8 = 0x0; + x6dc = 0x08010204; + x6e8 = 0x04000000; + x6ec = 0x00080102; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x02000408; + x704 = 0x00100001; + x708 = 0x0; + x70c = 0x04080102; + } else if ((s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) && + (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz)) { + c04 = 0xffffffff; + c50 = 0x05030305; + c54 = 0x0000ffff; + x6d8 = 0x0; + x6dc = 0x04080102; + x6e8 = 0x0; + x6ec = 0x04080102; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x0; + x704 = 0x0; + x708 = 0x0; + x70c = 0x02040801; + } else { + die("Unsupported DDR/FSB configuration\n"); + } + + MCHBAR32(0xc04) = c04; + MCHBAR32(0xc50) = c50; + MCHBAR32(0xc54) = c54; + MCHBAR8(0xc08) = MCHBAR8(0xc08) | (1 << 7); + + MCHBAR32(0x6d8) = x6d8; + MCHBAR32(0x6e0) = x6d8; + MCHBAR32(0x6dc) = x6dc; + MCHBAR32(0x6e4) = x6dc; + MCHBAR32(0x6e8) = x6e8; + MCHBAR32(0x6f0) = x6e8; + MCHBAR32(0x6ec) = x6ec; + MCHBAR32(0x6f4) = x6ec; + MCHBAR32(0x6f8) = x6f8; + MCHBAR32(0x6fc) = x6fc; + MCHBAR32(0x708) = x708; + MCHBAR32(0x70c) = x70c; +} + +static void checkreset_ddr2(struct sysinfo *s) +{ + u8 pmcon2; + u8 reset = 0; + +// MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0xf0000) | 0x10000; + + pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + if (!(pmcon2 & 0x80)) { + pmcon2 |= 0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); + reset = 1; + + /* do magic 0xf0 thing. */ + u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); + pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); + pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); + } + if (reset) { + printk(BIOS_DEBUG, "Reset...\n"); + outb(0xe, 0xcf9); + asm ("hlt"); + } + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80); +} + +static void setioclk_ddr2(struct sysinfo *s) +{ + MCHBAR32(0x1bc) = 0x08060402; + MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x200; + MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x100; + MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x20; + MCHBAR16(0x1c0) = MCHBAR16(0x1c0) & ~1; + switch (s->selected_timings.mem_clk) { + default: + case MEM_CLOCK_800MHz: + case MEM_CLOCK_1066MHz: + MCHBAR8(0x5d9) = (MCHBAR8(0x5d9) & ~0x2) | 0x2; + MCHBAR8(0x9d9) = (MCHBAR8(0x9d9) & ~0x2) | 0x2; + MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xc0; + MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xe0; + MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xa0; + break; + case MEM_CLOCK_667MHz: + case MEM_CLOCK_1333MHz: + MCHBAR8(0x5d9) = MCHBAR8(0x5d9) & ~0x2; + MCHBAR8(0x9d9) = MCHBAR8(0x9d9) & ~0x2; + MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0x40; + break; + } + MCHBAR32(0x594) = MCHBAR32(0x594) | (1 << 31); + MCHBAR32(0x994) = MCHBAR32(0x994) | (1 << 31); +} + +static void launch_ddr2(struct sysinfo *s) +{ + u8 i; + u32 launch1 = 0x58001117; + u32 launch2 = 0; + u32 launch3 = 0; + + if (s->selected_timings.CAS == 5) { + launch2 = 0x00220201; + } else if ((s->selected_timings.mem_clk == MEM_CLOCK_800MHz) && + (s->selected_timings.CAS == 6)) { + launch2 = 0x00230302; + } else { + die("Unsupported CAS & Frequency combination detected\n"); + } + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + MCHBAR32(0x400*i + 0x220) = launch1; + MCHBAR32(0x400*i + 0x224) = launch2; + MCHBAR32(0x400*i + 0x21c) = launch3; + MCHBAR32(0x400*i + 0x248) = MCHBAR32(0x400*i + 0x248) | (1 << 23); + } + + MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0x58000000) | 0x48000000; + MCHBAR32(0x2c0) = MCHBAR32(0x2c0) | 0x1e0; + MCHBAR32(0x2c4) = (MCHBAR32(0x2c4) & ~0xf) | 0xc; +} + +static void clkset0(u8 ch, u8 setting[5]) +{ + MCHBAR16(0x400*ch + 0x5a0) = (MCHBAR16(0x400*ch + 0x5a0) & ~0xc440) | + (setting[4] << 14) | + (setting[3] << 6) | + (setting[2] << 10); + MCHBAR8(0x400*ch + 0x581) = (MCHBAR8(0x400*ch + 0x581) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x581) = (MCHBAR8(0x400*ch + 0x581) & ~0xf) | + setting[0]; +} + +static void clkset1(u8 ch, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x5a0) = (MCHBAR32(0x400*ch + 0x5a0) & ~0x30880) | + (setting[4] << 16) | + (setting[3] << 7) | + (setting[2] << 11); + MCHBAR8(0x400*ch + 0x582) = (MCHBAR8(0x400*ch + 0x582) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x582) = (MCHBAR8(0x400*ch + 0x582) & ~0xf) | + setting[0]; +} + +static void ctrlset0(u8 ch, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x59c) = (MCHBAR32(0x400*ch + 0x59c) & ~0x3300000) | + (setting[4] << 24) | + (setting[3] << 20) | + (setting[2] << 21); + MCHBAR8(0x400*ch + 0x584) = (MCHBAR8(0x400*ch + 0x584) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x584) = (MCHBAR8(0x400*ch + 0x584) & ~0xf) | + setting[0]; +} + +static void ctrlset1(u8 ch, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x59c) = (MCHBAR32(0x400*ch + 0x59c) & ~0x18c00000) | + (setting[4] << 27) | + (setting[3] << 22) | + (setting[2] << 23); + MCHBAR8(0x400*ch + 0x585) = (MCHBAR8(0x400*ch + 0x585) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x585) = (MCHBAR8(0x400*ch + 0x585) & ~0xf) | + setting[0]; +} + +static void ctrlset2(u8 ch, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x598) = (MCHBAR32(0x400*ch + 0x598) & ~0x18c00000) | + (setting[4] << 14) | + (setting[3] << 12) | + (setting[2] << 13); + MCHBAR8(0x400*ch + 0x586) = (MCHBAR8(0x400*ch + 0x586) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x586) = (MCHBAR8(0x400*ch + 0x586) & ~0xf) | + setting[0]; +} + +static void ctrlset3(u8 ch, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x598) = (MCHBAR32(0x400*ch + 0x598) & ~0x18c00000) | + (setting[4] << 10) | + (setting[3] << 8) | + (setting[2] << 9); + MCHBAR8(0x400*ch + 0x587) = (MCHBAR8(0x400*ch + 0x587) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x587) = (MCHBAR8(0x400*ch + 0x587) & ~0xf) | + setting[0]; +} + +static void cmdset(u8 ch, u8 setting[5]) +{ + MCHBAR8(0x400*ch + 0x598) = (MCHBAR8(0x400*ch + 0x598) & ~0x30) | + (setting[4] << 4); + MCHBAR8(0x400*ch + 0x594) = (MCHBAR8(0x400*ch + 0x594) & ~0x60) | + (setting[3] << 5) | + (setting[2] << 6); + MCHBAR8(0x400*ch + 0x580) = (MCHBAR8(0x400*ch + 0x580) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x580) = (MCHBAR8(0x400*ch + 0x580) & ~0xf) | + setting[0]; +} + +static void dqsset(u8 ch, u8 lane, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x5fc) = MCHBAR32(0x400*ch + 0x5fc) & ~(2 << (lane*4)); + + MCHBAR32(0x400*ch + 0x5b4) = (MCHBAR32(0x400*ch + 0x5b4) & ~(0x201 << lane)) | + (setting[2] << (9 + lane)) | + (setting[3] << lane); + MCHBAR32(0x400*ch + 0x5b8) = (MCHBAR32(0x400*ch + 0x5b8) & ~(0x201 << lane)) | + (setting[2] << (9 + lane)) | + (setting[3] << lane); + MCHBAR32(0x400*ch + 0x5bc) = (MCHBAR32(0x400*ch + 0x5bc) & ~(0x201 << lane)) | + (setting[2] << (9 + lane)) | + (setting[3] << lane); + MCHBAR32(0x400*ch + 0x5c0) = (MCHBAR32(0x400*ch + 0x5c0) & ~(0x201 << lane)) | + (setting[2] << (9 + lane)) | + (setting[3] << lane); + + MCHBAR32(0x400*ch + 0x5c8) = (MCHBAR32(0x400*ch + 0x5c8) & ~(0x3 << (16+lane*2))) | + (setting[4] << (16+lane*2)); + MCHBAR32(0x400*ch + 0x5cc) = (MCHBAR32(0x400*ch + 0x5cc) & ~(0x3 << (16+lane*2))) | + (setting[4] << (16+lane*2)); + MCHBAR32(0x400*ch + 0x5d0) = (MCHBAR32(0x400*ch + 0x5d0) & ~(0x3 << (16+lane*2))) | + (setting[4] << (16+lane*2)); + MCHBAR32(0x400*ch + 0x5d4) = (MCHBAR32(0x400*ch + 0x5d4) & ~(0x3 << (16+lane*2))) | + (setting[4] << (16+lane*2)); + + MCHBAR8(0x400*ch + 0x520 + lane*4) = (MCHBAR8(0x400*ch + 0x520 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x520 + lane*4) = (MCHBAR8(0x400*ch + 0x520 + lane*4) & ~0xf) | + setting[0]; + MCHBAR8(0x400*ch + 0x521 + lane*4) = (MCHBAR8(0x400*ch + 0x521 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x521 + lane*4) = (MCHBAR8(0x400*ch + 0x521 + lane*4) & ~0xf) | + setting[0]; + MCHBAR8(0x400*ch + 0x522 + lane*4) = (MCHBAR8(0x400*ch + 0x522 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x522 + lane*4) = (MCHBAR8(0x400*ch + 0x522 + lane*4) & ~0xf) | + setting[0]; + MCHBAR8(0x400*ch + 0x523 + lane*4) = (MCHBAR8(0x400*ch + 0x523 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x523 + lane*4) = (MCHBAR8(0x400*ch + 0x523 + lane*4) & ~0xf) | + setting[0]; +} + +static void dqset(u8 ch, u8 lane, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x5fc) = MCHBAR32(0x400*ch + 0x5fc) & ~(1 << (lane*4)); + + MCHBAR32(0x400*ch + 0x5a4) = (MCHBAR32(0x400*ch + 0x5a4) & ~(0x201 << lane)) | + (setting[2] << (9+lane)) | + (setting[3] << lane); + MCHBAR32(0x400*ch + 0x5a8) = (MCHBAR32(0x400*ch + 0x5a8) & ~(0x201 << lane)) | + (setting[2] << (9+lane)) | + (setting[3] << lane); + MCHBAR32(0x400*ch + 0x5ac) = (MCHBAR32(0x400*ch + 0x5ac) & ~(0x201 << lane)) | + (setting[2] << (9+lane)) | + (setting[3] << lane); + MCHBAR32(0x400*ch + 0x5b0) = (MCHBAR32(0x400*ch + 0x5b0) & ~(0x201 << lane)) | + (setting[2] << (9+lane)) | + (setting[3] << lane); + + MCHBAR32(0x400*ch + 0x5c8) = (MCHBAR32(0x400*ch + 0x5c8) & ~(0x3 << (lane*2))) | + (setting[4] << (2*lane)); + MCHBAR32(0x400*ch + 0x5cc) = (MCHBAR32(0x400*ch + 0x5cc) & ~(0x3 << (lane*2))) | + (setting[4] << (2*lane)); + MCHBAR32(0x400*ch + 0x5d0) = (MCHBAR32(0x400*ch + 0x5d0) & ~(0x3 << (lane*2))) | + (setting[4] << (2*lane)); + MCHBAR32(0x400*ch + 0x5d4) = (MCHBAR32(0x400*ch + 0x5d4) & ~(0x3 << (lane*2))) | + (setting[4] << (2*lane)); + + MCHBAR8(0x400*ch + 0x500 + lane*4) = (MCHBAR8(0x400*ch + 0x500 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x500 + lane*4) = (MCHBAR8(0x400*ch + 0x500 + lane*4) & ~0xf) | + setting[0]; + MCHBAR8(0x400*ch + 0x501 + lane*4) = (MCHBAR8(0x400*ch + 0x501 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x501 + lane*4) = (MCHBAR8(0x400*ch + 0x501 + lane*4) & ~0xf) | + setting[0]; + MCHBAR8(0x400*ch + 0x502 + lane*4) = (MCHBAR8(0x400*ch + 0x502 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x502 + lane*4) = (MCHBAR8(0x400*ch + 0x502 + lane*4) & ~0xf) | + setting[0]; + MCHBAR8(0x400*ch + 0x503 + lane*4) = (MCHBAR8(0x400*ch + 0x503 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x503 + lane*4) = (MCHBAR8(0x400*ch + 0x503 + lane*4) & ~0xf) | + setting[0]; +} + +static void timings_ddr2(struct sysinfo *s) +{ + u8 i; + u8 twl, ta1, ta2, ta3, ta4; + u8 reg8; + u8 flag1 = 0; + u8 flag2 = 0; + u16 reg16; + u32 reg32; + u16 ddr, fsb; + u8 trpmod = 0; + u8 bankmod = 1; + u8 pagemod = 0; + + u16 fsb2ps[3] = { + 5000, // 800 + 3750, // 1067 + 3000 // 1333 + }; + + u16 ddr2ps[6] = { + 5000, // 400 + 3750, // 533 + 3000, // 667 + 2500, // 800 + 1875, // 1067 + 1500 // 1333 + }; + + u16 lut1[6] = { + 0, + 0, + 2600, + 3120, + 4171, + 5200 + }; + + ta1 = 6; + ta2 = 6; + ta3 = 5; + ta4 = 8; + + twl = s->selected_timings.CAS - 1; + + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + if (s->dimms[i].banks == 1) { // 8 banks + trpmod = 1; + bankmod = 0; + } + if (s->dimms[i].page_size == 2048) { + pagemod = 1; + } + } + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + MCHBAR8(0x400*i + 0x2f6) = MCHBAR8(0x400*i + 0x2f6) | 0x3; + MCHBAR8(0x400*i + 0x228) = (MCHBAR8(0x400*i + 0x228) & ~0x7) | 0x2; + MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf0) | (twl << 4); + MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf) | + s->selected_timings.CAS; + MCHBAR16(0x400*i + 0x265) = (MCHBAR16(0x400*i + 0x265) & ~0x3f00) | + ((s->selected_timings.CAS + 9) << 8); + + reg16 = (s->selected_timings.tRAS << 11) | + ((twl + 4 + s->selected_timings.tWR) << 6) | + ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; + MCHBAR16(0x400*i + 0x250) = reg16; + + reg32 = (bankmod << 21) | + (s->selected_timings.tRRD << 17) | + (s->selected_timings.tRP << 13) | + ((s->selected_timings.tRP + trpmod) << 9) | + s->selected_timings.tRFC; + reg8 = (MCHBAR8(0x400*i + 0x26f) >> 1) & 1; + if (bankmod) { + switch (s->selected_timings.mem_clk) { + default: + case MEM_CLOCK_667MHz: + if (reg8) { + if (pagemod) { + reg32 |= 16 << 22; + } else { + reg32 |= 12 << 22; + } + } else { + if (pagemod) { + reg32 |= 18 << 22; + } else { + reg32 |= 14 << 22; + } + } + break; + case MEM_CLOCK_800MHz: + if (reg8) { + if (pagemod) { + reg32 |= 18 << 22; + } else { + reg32 |= 14 << 22; + } + } else { + if (pagemod) { + reg32 |= 20 << 22; + } else { + reg32 |= 16 << 22; + } + } + break; + } + } + MCHBAR32(0x400*i + 0x252) = reg32; + + MCHBAR16(0x400*i + 0x256) = (s->selected_timings.tRCD << 12) | + (0x4 << 8) | (ta2 << 4) | ta4; + + MCHBAR32(0x400*i + 0x258) = (s->selected_timings.tRCD << 17) | + ((twl + 4 + s->selected_timings.tWTR) << 12) | + (ta3 << 8) | (4 << 4) | ta1; + + MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) | + s->selected_timings.tRFC; + + MCHBAR16(0x400*i + 0x260) = (MCHBAR16(0x400*i + 0x260) & ~0x3fe) | (100 << 1); + MCHBAR8(0x400*i + 0x264) = 0xff; + MCHBAR8(0x400*i + 0x25d) = (MCHBAR8(0x400*i + 0x25d) & ~0x3f) | + s->selected_timings.tRAS; + MCHBAR16(0x400*i + 0x244) = 0x2310; + + switch (s->selected_timings.mem_clk) { + case MEM_CLOCK_667MHz: + reg8 = 0; + break; + default: + reg8 = 1; + break; + } + + MCHBAR8(0x400*i + 0x246) = (MCHBAR8(0x400*i + 0x246) & ~0x1f) | + (reg8 << 2) | 1; + + fsb = fsb2ps[s->selected_timings.fsb_clk]; + ddr = ddr2ps[s->selected_timings.mem_clk]; + reg32 = (u32)((s->selected_timings.CAS + 7 + reg8) * ddr); + reg32 = (u32)((reg32 / fsb) << 8); + reg32 |= 0x0e000000; + if ((fsb2mhz(s->selected_timings.fsb_clk) / + ddr2mhz(s->selected_timings.mem_clk)) > 2) { + reg32 |= 1 << 24; + } + MCHBAR32(0x400*i + 0x248) = (MCHBAR32(0x400*i + 0x248) & ~0x0f001f00) | + reg32; + + if (twl > 2) { + flag1 = 1; + } + if (s->selected_timings.mem_clk >= MEM_CLOCK_800MHz) { + flag2 = 1; + } + reg16 = (u8)(twl - 1 - flag1 - flag2); + reg16 |= reg16 << 4; + if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) { + if (reg16) { + reg16--; + } + } + reg16 |= flag1 << 8; + reg16 |= flag2 << 9; + MCHBAR16(0x400*i + 0x24d) = (MCHBAR16(0x400*i + 0x24d) & ~0x1ff) | reg16; + MCHBAR16(0x400*i + 0x25e) = 0x15a5; + MCHBAR32(0x400*i + 0x265) = MCHBAR32(0x400*i + 0x265) & ~0x1f; + MCHBAR32(0x400*i + 0x269) = (MCHBAR32(0x400*i + 0x269) & ~0x000fffff) | + (0x3f << 14) | lut1[s->selected_timings.mem_clk]; + MCHBAR8(0x400*i + 0x274) = MCHBAR8(0x400*i + 0x274) | 1; + MCHBAR8(0x400*i + 0x24c) = MCHBAR8(0x400*i + 0x24c) & ~0x3; + + reg16 = 0; + switch (s->selected_timings.mem_clk) { + default: + case MEM_CLOCK_667MHz: + reg16 = 0x99; + break; + case MEM_CLOCK_800MHz: + if (s->selected_timings.CAS == 5) { + reg16 = 0x19a; + } else if (s->selected_timings.CAS == 6) { + reg16 = 0x9a; + } + break; + } + reg16 &= 0x7; + reg16 += twl + 9; + reg16 <<= 10; + MCHBAR16(0x400*i + 0x24d) = (MCHBAR16(0x400*i + 0x24d) & ~0x7c00) | reg16; + MCHBAR8(0x400*i + 0x267) = (MCHBAR8(0x400*i + 0x267) & ~0x3f) | 0x13; + MCHBAR8(0x400*i + 0x268) = (MCHBAR8(0x400*i + 0x268) & ~0xff) | 0x4a; + + reg16 = (MCHBAR16(0x400*i + 0x269) & 0xc000) >> 2; + reg16 += 2 << 12; + reg16 |= (0x15 << 6) | 0x1f; + MCHBAR16(0x400*i + 0x26d) = (MCHBAR16(0x400*i + 0x26d) & ~0x7fff) | reg16; + + reg32 = (1 << 25) | (6 << 27); + MCHBAR32(0x400*i + 0x269) = (MCHBAR32(0x400*i + 0x269) & ~0xfa300000) | reg32; + MCHBAR8(0x400*i + 0x271) = MCHBAR8(0x400*i + 0x271) & ~0x80; + MCHBAR8(0x400*i + 0x274) = MCHBAR8(0x400*i + 0x274) & ~0x6; + } // END EACH POPULATED CHANNEL + + reg16 = 0x1f << 5; + reg16 |= 0xe << 10; + MCHBAR16(0x125) = (MCHBAR16(0x125) & ~0x3fe0) | reg16; + MCHBAR16(0x127) = (MCHBAR16(0x127) & ~0x7ff) | 0x540; + MCHBAR8(0x129) = MCHBAR8(0x129) | 0x1f; + MCHBAR8(0x12c) = MCHBAR8(0x12c) | 0xa0; + MCHBAR32(0x241) = (MCHBAR32(0x241) & ~0x1ffff) | 0x11; + MCHBAR32(0x641) = (MCHBAR32(0x641) & ~0x1ffff) | 0x11; + MCHBAR8(0x246) = MCHBAR8(0x246) & ~0x10; + MCHBAR8(0x646) = MCHBAR8(0x646) & ~0x10; + MCHBAR32(0x120) = (2 << 29) | (1 << 28) | (1 << 23) | 0xd7f5f; + reg8 = (u8)((MCHBAR32(0x252) & 0x1e000) >> 13); + MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf0) | (reg8 << 4); + reg8 = (u8)((MCHBAR32(0x258) & ~0x1e0000) >> 17); + MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf) | reg8; + MCHBAR8(0x12f) = 0x4c; + reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9); + MCHBAR32(0x6c0) = (MCHBAR32(0x6c0) & ~0xffffff00) | reg32; + MCHBAR8(0x6c4) = (MCHBAR8(0x6c4) & ~0x7) | 0x2; +} + +static void dll_ddr2(struct sysinfo *s) +{ + u8 i, j, r, reg8, clk, async; + u16 reg16 = 0; + u32 reg32 = 0; + u8 lane; + + MCHBAR16(0x180) = (MCHBAR16(0x180) & ~0x7e06) | 0xc04; + MCHBAR16(0x182) = (MCHBAR16(0x182) & ~0x3ff) | 0xc8; + MCHBAR16(0x18a) = (MCHBAR16(0x18a) & ~0x1f1f) | 0x0f0f; + MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x8020) | 0x100; + MCHBAR8(0x194) = (MCHBAR8(0x194) & ~0x77) | 0x33; + switch (s->selected_timings.mem_clk) { + default: + case MEM_CLOCK_667MHz: + reg16 = (0xa << 9) | 0xa; + break; + case MEM_CLOCK_800MHz: + reg16 = (0x9 << 9) | 0x9; + break; + } + MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x1e0f) | reg16; + MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x2030) | 0x2010; + udelay(1); + MCHBAR16(0x198) = MCHBAR16(0x198) & ~0x100; + + MCHBAR16(0x1c8) = (MCHBAR16(0x1c8) & ~0x1f) | 0xd; + + udelay(1); + MCHBAR8(0x190) = MCHBAR8(0x190) & ~1; + udelay(1); // 533ns + MCHBAR32(0x198) = MCHBAR32(0x198) & ~0x11554000; + udelay(1); + MCHBAR32(0x198) = MCHBAR32(0x198) & ~0x1455; + udelay(1); + MCHBAR8(0x583) = MCHBAR8(0x583) & ~0x1c; + MCHBAR8(0x983) = MCHBAR8(0x983) & ~0x1c; + udelay(1); // 533ns + MCHBAR8(0x583) = MCHBAR8(0x583) & ~0x3; + MCHBAR8(0x983) = MCHBAR8(0x983) & ~0x3; + udelay(1); // 533ns + + // ME related + MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x7ffffff) | 0x551803; + + MCHBAR16(0x1b4) = MCHBAR16(0x1b4) & ~0x800; + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0xf0; + + FOR_EACH_CHANNEL(i) { + reg16 = 0; + MCHBAR16(0x400*i + 0x59c) = MCHBAR16(0x400*i + 0x59c) & ~0x3000; + + reg32 = 0; + FOR_EACH_RANK_IN_CHANNEL(r) if (!RANK_IS_POPULATED(s->dimms, i, r)) { + reg32 |= 0x111 << r; + } + MCHBAR32(0x400*i + 0x59c) = (MCHBAR32(0x400*i + 0x59c) & ~0xfff) | reg32; + MCHBAR8(0x400*i + 0x594) = MCHBAR8(0x400*i + 0x594) & ~1; + + if (!CHANNEL_IS_POPULATED(s->dimms, i)) { + printk(BIOS_DEBUG, "No dimms in channel %d\n", i); + reg8 = 0x3f; + } else if(ONLY_DIMMA_IS_POPULATED(s->dimms, i)) { + printk(BIOS_DEBUG, "DimmA populated only in channel %d\n", i); + reg8 = 0x38; + } else if(ONLY_DIMMB_IS_POPULATED(s->dimms, i)) { + printk(BIOS_DEBUG, "DimmB populated only in channel %d\n", i); + reg8 = 0x7; + } else if(BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { + printk(BIOS_DEBUG, "Both dimms populated in channel %d\n", i); + reg8 = 0; + } else { + die("Unhandled case\n"); + } + + //reg8 = 0x00; // FIXME dont switch on all clocks anyway + + MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0) & ~0x3f000000) | + ((u32)(reg8 << 24)); + } // END EACH CHANNEL + + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1; + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; + + // Update DLL timing + MCHBAR8(0x1a4) = MCHBAR8(0x1a4) & ~0x80; + MCHBAR8(0x1a4) = MCHBAR8(0x1a4) | 0x40; + MCHBAR16(0x5f0) = (MCHBAR16(0x5f0) & ~0x400) | 0x400; + + u8 dll_setting_667[23][5] = { + // tap pi db delay + {13, 0, 1,0, 0}, + {4, 1, 0,0, 0}, + {13, 0, 1,0, 0}, + {4, 5, 0,0, 0}, + {4, 1, 0,0, 0}, + {4, 1, 0,0, 0}, + {4, 1, 0,0, 0}, + {1, 5, 1,1, 1}, + {1, 6, 1,1, 1}, + {2, 0, 1,1, 1}, + {2, 1, 1,1, 1}, + {2, 1, 1,1, 1}, + {14, 6, 1,0, 0}, + {14, 3, 1,0, 0}, + {14, 0, 1,0, 0}, + {9, 0, 0,0, 1}, + {9, 1, 0,0, 1}, + {9, 2, 0,0, 1}, + {9, 2, 0,0, 1}, + {9, 1, 0,0, 1}, + {6, 4, 0,0, 1}, + {6, 2, 0,0, 1}, + {5, 4, 0,0, 1} + }; + + u8 dll_setting_800[23][5] = { + // tap pi db delay + {11, 5, 1,0, 0}, + {0, 5, 1,1, 0}, + {11, 5, 1,0, 0}, + {1, 4, 1,1, 0}, + {0, 5, 1,1, 0}, + {0, 5, 1,1, 0}, + {0, 5, 1,1, 0}, + {2, 5, 1,1, 1}, + {2, 6, 1,1, 1}, + {3, 0, 1,1, 1}, + {3, 0, 1,1, 1}, + {3, 3, 1,1, 1}, + {2, 0, 1,1, 1}, + {1, 3, 1,1, 1}, + {0, 3, 1,1, 1}, + {9, 3, 0,0, 1}, + {9, 4, 0,0, 1}, + {9, 5, 0,0, 1}, + {9, 6, 0,0, 1}, + {10, 0, 0,0, 1}, + {8, 1, 0,0, 1}, + {7, 5, 0,0, 1}, + {6, 2, 0,0, 1} + }; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + MCHBAR16(0x400*i + 0x5f0) = (MCHBAR16(0x400*i + 0x5f0) & ~0x3fc) | 0x3fc; + MCHBAR32(0x400*i + 0x5fc) = MCHBAR32(0x400*i + 0x5fc) & ~0xcccccccc; + MCHBAR8(0x400*i + 0x5d9) = (MCHBAR8(0x400*i + 0x5d9) & ~0xf0) | 0x70; + MCHBAR16(0x400*i + 0x590) = (MCHBAR16(0x400*i + 0x590) & ~0xffff) | 0x5555; + } + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { + clkset0(i, &dll_setting_667[CLKSET0][0]); + clkset1(i, &dll_setting_667[CLKSET1][0]); + ctrlset0(i, &dll_setting_667[CTRL0][0]); + ctrlset1(i, &dll_setting_667[CTRL1][0]); + ctrlset2(i, &dll_setting_667[CTRL2][0]); + ctrlset3(i, &dll_setting_667[CTRL3][0]); + cmdset(i, &dll_setting_667[CMD][0]); + } else { + clkset0(i, &dll_setting_800[CLKSET0][0]); + clkset1(i, &dll_setting_800[CLKSET1][0]); + ctrlset0(i, &dll_setting_800[CTRL0][0]); + ctrlset1(i, &dll_setting_800[CTRL1][0]); + ctrlset2(i, &dll_setting_800[CTRL2][0]); + ctrlset3(i, &dll_setting_800[CTRL3][0]); + cmdset(i, &dll_setting_800[CMD][0]); + } + } + + // XXX if not async mode + MCHBAR16(0x180) = MCHBAR16(0x180) & ~0x8200; + MCHBAR8(0x180) = MCHBAR8(0x180) | 0x4; + j = 0; + for (i = 0; i < 16; i++) { + MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; + MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; + while (MCHBAR8(0x180) & 0x10); + if (MCHBAR32(0x184) == 0xffffffff) { + j++; + if (j >= 2) + break; + + if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { + j = 2; + break; + } + } else { + j = 0; + } + } + if (i == 1 || ((i == 0) && s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { + j = 0; + i++; + for (; i < 16; i++) { + MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; + MCHBAR8(0x180) = MCHBAR8(0x180) | 0x4; + while (MCHBAR8(0x180) & 0x10); + if (MCHBAR32(0x184) == 0) { + i++; + break; + } + } + for (; i < 16; i++) { + MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; + MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; + while (MCHBAR8(0x180) & 0x10); + if (MCHBAR32(0x184) == 0xffffffff) { + j++; + if (j >= 2) + break; + } else { + j = 0; + } + } + if (j < 2) { + MCHBAR8(0x1c8) = MCHBAR8(0x1c8) & ~0x1f; + MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; + while (MCHBAR8(0x180) & 0x10); + j = 2; + } + } + + if (j < 2) { + MCHBAR8(0x1c8) = MCHBAR8(0x1c8) & ~0x1f; + async = 1; + } + + clk = 0x1a; + if (async != 1) { + reg8 = MCHBAR8(0x188) & 0x1e; + if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz && + s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) { + clk = 0x10; + } else if (s->selected_timings.mem_clk == MEM_CLOCK_800MHz) { + clk = 0x10; + } else { + clk = 0x1a; + } + } + MCHBAR8(0x180) = MCHBAR8(0x180) & ~0x80; + + if ((s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) && + (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { + i = MCHBAR8(0x180) & 0xf; + i = (i + 10) % 14; + MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; + MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; + while(MCHBAR8(0x180) & 0x10); + } + + reg8 = MCHBAR8(0x188) & ~1; + MCHBAR8(0x188) = reg8; + reg8 &= ~0x3e; + reg8 |= clk; + MCHBAR8(0x188) = reg8; + reg8 |= 1; + MCHBAR8(0x188) = reg8; + + if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) { + MCHBAR8(0x18c) = MCHBAR8(0x18c) | 1; + } + + // Program DQ/DQS dll settings + reg32 = 0; + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + for (lane = 0; lane < 8; lane++) { + if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { + reg32 = 0x06db7777; + } else if (s->selected_timings.mem_clk == MEM_CLOCK_800MHz) { + reg32 = 0x00007777; + } + MCHBAR32(0x400*i + 0x540 + lane*4) = + (MCHBAR32(0x400*i + 0x540 + lane*4) & 0x0fffffff) | + reg32; + } + } + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { + for (lane = 0; lane < 8; lane++) { + dqsset(i, lane, &dll_setting_667[DQS1+lane][0]); + } + for (lane = 0; lane < 8; lane++) { + dqset(i, lane, &dll_setting_667[DQ1+lane][0]); + } + } else { + for (lane = 0; lane < 8; lane++) { + dqsset(i, lane, &dll_setting_800[DQS1+lane][0]); + } + for (lane = 0; lane < 8; lane++) { + dqset(i, lane, &dll_setting_800[DQ1+lane][0]); + } + } + } +} + +static void rcomp_ddr2(struct sysinfo *s) +{ + u8 i, j, k; + u32 x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0D0C0B0A, 0x04040404, 0x08070605, 0x0C0B0A09, 0x100F0E0D }; + u16 x378[6] = { 0, 0xAAAA, 0x7777, 0x7777, 0x7777, 0x7777 }; + u32 x382[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 }; + u32 x386[6] = { 0, 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 }; + u32 x38a[6] = { 0, 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 }; + u32 x38e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808 }; + u32 x392[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202 }; + u32 x396[6] = { 0, 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303 }; + u32 x39a[6] = { 0, 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 }; + u32 x39e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 }; + u16 addr[6] = { 0x31c, 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c }; + u8 bit[6] = { 0, 0, 1, 1, 0, 0 }; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + for (j = 0; j < 6; j++) { + if (j == 0) { + MCHBAR32(0x400*i + addr[j]) = + (MCHBAR32(0x400*i + addr[j]) & ~0xff000) | 0xaa000; + MCHBAR16(0x400*i + 0x320) = (MCHBAR16(0x400*i + 0x320) & ~0xffff) | 0x6666; + for (k = 0; k < 8; k++) { + MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2)) = + (MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2)) & ~0x3f3f3f3f) | x32a[k]; + MCHBAR32(0x400*i + addr[j] + 0x2e + (k << 2)) = + (MCHBAR32(0x400*i + addr[j] + 0x2e + (k << 2)) & ~0x3f3f3f3f) | x32a[k]; + } + } else { + MCHBAR16(0x400*i + addr[j]) = (MCHBAR16(0x400*i + addr[j]) & ~0xf000) | 0xa000; + MCHBAR16(0x400*i + addr[j] + 4) = (MCHBAR16(0x400*i + addr[j] + 4) & ~0xffff) | + x378[j]; + MCHBAR32(0x400*i + addr[j] + 0xe) = + (MCHBAR32(0x400*i + addr[j] + 0xe) & ~0x3f3f3f3f) | x382[j]; + MCHBAR32(0x400*i + addr[j] + 0x12) = + (MCHBAR32(0x400*i + addr[j] + 0x12) & ~0x3f3f3f3f) | x386[j]; + MCHBAR32(0x400*i + addr[j] + 0x16) = + (MCHBAR32(0x400*i + addr[j] + 0x16) & ~0x3f3f3f3f) | x38a[j]; + MCHBAR32(0x400*i + addr[j] + 0x1a) = + (MCHBAR32(0x400*i + addr[j] + 0x1a) & ~0x3f3f3f3f) | x38e[j]; + MCHBAR32(0x400*i + addr[j] + 0x1e) = + (MCHBAR32(0x400*i + addr[j] + 0x1e) & ~0x3f3f3f3f) | x392[j]; + MCHBAR32(0x400*i + addr[j] + 0x22) = + (MCHBAR32(0x400*i + addr[j] + 0x22) & ~0x3f3f3f3f) | x396[j]; + MCHBAR32(0x400*i + addr[j] + 0x26) = + (MCHBAR32(0x400*i + addr[j] + 0x26) & ~0x3f3f3f3f) | x39a[j]; + MCHBAR32(0x400*i + addr[j] + 0x2a) = + (MCHBAR32(0x400*i + addr[j] + 0x2a) & ~0x3f3f3f3f) | x39e[j]; + } + MCHBAR8(0x400*i + addr[j]) = (MCHBAR8(0x400*i + addr[j]) & ~1) | bit[j]; + } + MCHBAR8(0x400*i + 0x45a) = (MCHBAR8(0x400*i + 0x45a) & ~0x3f) | 0x12; + MCHBAR8(0x400*i + 0x45e) = (MCHBAR8(0x400*i + 0x45e) & ~0x3f) | 0x12; + MCHBAR8(0x400*i + 0x462) = (MCHBAR8(0x400*i + 0x462) & ~0x3f) | 0x12; + MCHBAR8(0x400*i + 0x466) = (MCHBAR8(0x400*i + 0x466) & ~0x3f) | 0x12; + } // END EACH POPULATED CHANNEL + + MCHBAR32(0x134) = (MCHBAR32(0x134) & ~0x63c00) | 0x63c00; + MCHBAR16(0x174) = (MCHBAR16(0x174) & ~0x63ff) | 0x63ff; + MCHBAR16(0x178) = 0x0135; + MCHBAR32(0x130) = (MCHBAR32(0x130) & ~0x7bdffe0) | 0x7a9ffa0; + + if (!CHANNEL_IS_POPULATED(s->dimms, 0)) { + MCHBAR32(0x130) = MCHBAR32(0x130) & ~(1 << 27); + } + if (!CHANNEL_IS_POPULATED(s->dimms, 1)) { + MCHBAR32(0x130) = MCHBAR32(0x130) & ~(1 << 28); + } + + MCHBAR8(0x130) = MCHBAR8(0x130) | 1; +} + +static void odt_ddr2(struct sysinfo *s) +{ + u8 i; + u16 odt[16][2] = { + { 0x0000,0x0000 }, // NC_NC + { 0x0000,0x0001 }, // x8SS_NC + { 0x0000,0x0011 }, // x8DS_NC + { 0x0000,0x0001 }, // x16SS_NC + { 0x0004,0x0000 }, // NC_x8SS + { 0x0101,0x0404 }, // x8SS_x8SS + { 0x0101,0x4444 }, // x8DS_x8SS + { 0x0101,0x0404 }, // x16SS_x8SS + { 0x0044,0x0000 }, // NC_x8DS + { 0x1111,0x0404 }, // x8SS_x8DS + { 0x1111,0x4444 }, // x8DS_x8DS + { 0x1111,0x0404 }, // x16SS_x8DS + { 0x0004,0x0000 }, // NC_x16SS + { 0x0101,0x0404 }, // x8SS_x16SS + { 0x0101,0x4444 }, // x8DS_x16SS + { 0x0101,0x0404 }, // x16SS_x16SS + }; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + MCHBAR16(0x400*i + 0x298) = odt[s->dimm_config[i]][1]; + MCHBAR16(0x400*i + 0x294) = odt[s->dimm_config[i]][0]; + MCHBAR16(0x400*i + 0x29c) = (MCHBAR16(0x400*i + 0x29c) & ~0xfff) | 0x66b; + MCHBAR32(0x400*i + 0x260) = (MCHBAR32(0x400*i + 0x260) & ~0x70e3c00) | 0x3063c00; + } +} + +static void dojedec_ddr2(u8 r, u8 ch, u8 cmd, u16 val) +{ + u32 addr = (ch << 29) | (r*0x08000000); + volatile u32 rubbish; + + MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | cmd; + MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | cmd; + rubbish = read32((void*)((val<<3) | addr)); + udelay(10); + MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | NORMALOP_CMD; + MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | NORMALOP_CMD; +} + +static void jedec_ddr2(struct sysinfo *s) +{ + u8 i; + u16 mrsval, ch, r, v; + + u8 odt[16][4] = { + {0x00, 0x00, 0x00, 0x00}, + {0x01, 0x00, 0x00, 0x00}, + {0x01, 0x01, 0x00, 0x00}, + {0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x01, 0x00}, + {0x11, 0x00, 0x11, 0x00}, + {0x11, 0x11, 0x11, 0x00}, + {0x11, 0x00, 0x11, 0x00}, + {0x00, 0x00, 0x01, 0x01}, + {0x11, 0x00, 0x11, 0x11}, + {0x11, 0x11, 0x11, 0x11}, + {0x11, 0x00, 0x11, 0x11}, + {0x00, 0x00, 0x01, 0x00}, + {0x11, 0x00, 0x11, 0x00}, + {0x11, 0x11, 0x11, 0x00}, + {0x11, 0x00, 0x11, 0x00} + }; + + u16 jedec[12][2] = { + {NOP_CMD, 0x0}, + {PRECHARGE_CMD, 0x0}, + {EMRS2_CMD, 0x0}, + {EMRS3_CMD, 0x0}, + {EMRS1_CMD, 0x0}, + {MRS_CMD, 0x100}, // DLL Reset + {PRECHARGE_CMD, 0x0}, + {CBR_CMD, 0x0}, + {CBR_CMD, 0x0}, + {MRS_CMD, 0x0}, // DLL out of reset + {EMRS1_CMD, 0x380}, // OCD calib default + {EMRS1_CMD, 0x0} + }; + + mrsval = (s->selected_timings.CAS << 4) | ((s->selected_timings.tWR - 1) << 9) | 0xb; + + printk(BIOS_DEBUG, "MRS...\n"); + + udelay(200); + + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + printk(BIOS_DEBUG, "CH%d: Found Rank %d\n", ch, r); + for (i = 0; i < 12; i++) { + v = jedec[i][1]; + switch (jedec[i][0]) { + case EMRS1_CMD: + v |= (odt[s->dimm_config[ch]][r] << 2); + break; + case MRS_CMD: + v |= mrsval; + break; + default: + break; + } + dojedec_ddr2(r + ch*4, ch, jedec[i][0], v); + udelay(1); + //printk(BIOS_DEBUG, "Jedec step %d\n", i); + } + } + printk(BIOS_DEBUG, "MRS done\n"); +} + +static u8 sampledqs(u16 mchloc, u32 addr, u8 hilow, u8 repeat) +{ + u8 dqsmatch = 1; + volatile u32 strobe; + + while (repeat-- > 0) { + MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0x2; + udelay(2); + MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2; + udelay(2); + MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0x2; + udelay(2); + MCHBAR8(0x9d8) = MCHBAR8(0x9d8) | 0x2; + udelay(2); + barrier(); + strobe = read32((u32 *)addr); + barrier(); + if (((MCHBAR32(mchloc) & 0x40) >> 6) != hilow) { + dqsmatch = 0; + } + } + return dqsmatch; +} + +static void rcven_ddr2(struct sysinfo *s) +{ + u8 i, reg8, ch, lane; + u32 addr; + u8 tap = 0; + u8 savecc, savemedium, savetap, coarsecommon, medium; + u8 lanecoarse[8] = {0}; + u8 mincoarse = 0xff; + u8 pitap[2][8]; + u16 coarsectrl[2]; + u16 coarsedelay[2]; + u16 mediumphase[2]; + u16 readdelay[2]; + u16 mchbar; + MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xc; + MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0xc; + MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + addr = (ch << 29); + for (i = 0; !RANK_IS_POPULATED(s->dimms, ch, i); i++) { + addr += 128*1024*1024; + } + for (lane = 0; lane < 8; lane++) { + printk(BIOS_DEBUG, "Channel %d, Lane %d addr=0x%08x\n", ch, lane, addr); +//trylaneagain: + coarsecommon = (s->selected_timings.CAS - 1); + switch (lane) { + case 0: case 1: medium = 0; break; + case 2: case 3: medium = 1; break; + case 4: case 5: medium = 2; break; + case 6: case 7: medium = 3; break; + default: medium = 0; break; + } + mchbar = 0x400*ch + 0x561 + (lane << 2); + tap = 0; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | + (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & ~(3 << (lane*2))) | + (medium << (lane*2)); + MCHBAR8(0x400*ch + 0x560 + lane*4) = MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0xf; + MCHBAR8(0x400*ch + 0x560 + lane*4) = MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0x70; + savecc = coarsecommon; + savemedium = medium; + savetap = 0; + + MCHBAR16(0x400*ch + 0x588) = (MCHBAR16(0x400*ch + 0x588) & ~(3 << (lane*2))) | + (1 << (lane*2)); + + printk(BIOS_DEBUG, "rcven 0.1 coarse=%d\n", coarsecommon); + while (sampledqs(mchbar, addr, 1, 1) == 1) { + if (medium < 3) { + medium++; + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } else { + medium = 0; + coarsecommon++; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } + if (coarsecommon > 16) { + die("Coarse > 16: DQS tuning failed, halt\n"); + break; + } + } + printk(BIOS_DEBUG, " GOT IT (high -> low transition) coarse=%d medium=%d\n", coarsecommon, medium); + + savemedium = medium; + savecc = coarsecommon; + if (medium < 3) { + medium++; + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } else { + medium = 0; + coarsecommon++; + + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | + (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & ~(3 << (lane*2))) | + (medium << (lane*2)); + } + + printk(BIOS_DEBUG, "rcven 0.2\n"); + while (sampledqs(mchbar, addr, 0, 1) == 1) { + savemedium = medium; + savecc = coarsecommon; + if (medium < 3) { + medium++; + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } else { + medium = 0; + coarsecommon++; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } + if (coarsecommon > 16) { + die("Coarse DQS tuning 2 failed, halt\n"); + break; + } + } + printk(BIOS_DEBUG, " GOT IT (low -> high transition) coarse=%d medium=%d\n", coarsecommon, medium); + + + coarsecommon = savecc; + medium = savemedium; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + + printk(BIOS_DEBUG, "rcven 0.3\n"); + tap = 0; + while (sampledqs(mchbar, addr, 1, 1) == 0) { + savetap = tap; + tap++; + if (tap > 14) { + break; + } + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = + (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0xf) | tap; + } + + tap = savetap; + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = + (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0xf) | tap; + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = + (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0x70) | 0x30; + if (medium < 3) { + medium++; + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } else { + medium = 0; + coarsecommon++; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } + if (sampledqs(mchbar, addr, 1, 1) == 0) { + die("Not at DQS high, doh\n"); + } + + printk(BIOS_DEBUG, "rcven 0.4\n"); + while (sampledqs(mchbar, addr, 1, 1) == 1) { + coarsecommon--; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + if (coarsecommon == 0) { + die("Couldn't find DQS-high 0 indicator, halt\n"); + break; + } + } + printk(BIOS_DEBUG, " GOT IT (high -> low transition) coarse=%d medium=%d\n", coarsecommon, medium); + + printk(BIOS_DEBUG, "rcven 0.5\n"); + while (sampledqs(mchbar, addr, 0, 1) == 1) { + savemedium = medium; + savecc = coarsecommon; + if (medium < 3) { + medium++; + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } else { + medium = 0; + coarsecommon++; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } + if (coarsecommon > 16) { + die("Coarse DQS tuning 5 failed, halt\n"); + break; + } + } + printk(BIOS_DEBUG, " GOT IT (low -> high transition) coarse=%d medium=%d\n", coarsecommon, medium); + + printk(BIOS_DEBUG, "rcven 0.6\n"); + coarsecommon = savecc; + medium = savemedium; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + while (sampledqs(mchbar, addr, 1, 1) == 0) { + savetap = tap; + tap++; + if (tap > 14) { + break; + } + MCHBAR8(0x400*ch + 0x560 + lane*4) = + (MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0xf) | tap; + } + tap = savetap; + MCHBAR8(0x400*ch + 0x560 + lane*4) = + (MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0xf) | tap; + MCHBAR8(0x400*ch + 0x560 + lane*4) = + (MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0x70) | 0x70; + + pitap[ch][lane] = 0x70 | tap; + + MCHBAR16(0x400*ch + 0x588) = MCHBAR16(0x400*ch + 0x588) & ~(3 << (lane*2)); + lanecoarse[lane] = coarsecommon; + printk(BIOS_DEBUG, "rcven 0.7\n"); + } // END EACH LANE + + // Find minimum coarse value + for (lane = 0; lane < 8; lane++) { + if (mincoarse > lanecoarse[lane]) { + mincoarse = lanecoarse[lane]; + } + } + + printk(BIOS_DEBUG, "Found min coarse value = %d\n", mincoarse); + + for (lane = 0; lane < 8; lane++) { + reg8 = (lanecoarse[lane] == 0) ? 0 : lanecoarse[lane] - mincoarse; + MCHBAR16(0x400*ch + 0x5fa) = (MCHBAR16(0x400*ch + 0x5fa) & ~(3 << (lane*2))) | + (reg8 << (lane*2)); + } + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | (mincoarse << 16); + coarsectrl[ch] = mincoarse; + coarsedelay[ch] = MCHBAR16(0x400*ch + 0x5fa); + mediumphase[ch] = MCHBAR16(0x400*ch + 0x58c); + readdelay[ch] = MCHBAR16(0x400*ch + 0x588); + } // END EACH POPULATED CHANNEL + +/* Resume support */ + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) { + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = + (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0xf) | pitap[ch][lane]; + } + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | + (coarsectrl[ch] << 16); + MCHBAR16(0x400*ch + 0x5fa) = coarsedelay[ch]; + MCHBAR16(0x400*ch + 0x58c) = mediumphase[ch]; + } + printk(BIOS_DEBUG, "End rcven\n"); +} + +static void dradrb_ddr2(struct sysinfo *s) +{ + u8 map, i, ch, r, rankpop0, rankpop1; + u32 c0dra = 0; + u32 c1dra = 0; + u32 c0drb = 0; + u32 c1drb = 0; + u32 dra; + u32 dra0; + u32 dra1; + u16 totalmemorymb; + u16 size, offset; + u8 dratab[2][2][2][4] = { + { + { + {0xff, 0xff, 0xff, 0xff}, + {0xff, 0x00, 0x02, 0xff} + }, + { + {0xff, 0x01, 0xff, 0xff}, + {0xff, 0x03, 0xff, 0xff} + } + }, + { + { + {0xff, 0xff, 0xff, 0xff}, + {0xff, 0x04, 0x06, 0x08} + }, + { + {0xff, 0xff, 0xff, 0xff}, + {0x05, 0x07, 0x09, 0xff} + } + } + }; + + u8 drbtab[10] = {0x04, 0x02, 0x08, 0x04, 0x08, 0x04, 0x10, 0x08, 0x20, 0x10}; + + // DRA + rankpop0 = 0; + rankpop1 = 0; + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + if ((s->dimms[ch<<1].card_type && ((r) < s->dimms[ch<<1].ranks))) { + i = ch << 1; + } else { + i = (ch << 1) + 1; + } + dra = dratab[s->dimms[i].banks] + [s->dimms[i].width] + [s->dimms[i].cols-9] + [s->dimms[i].rows-12]; + if (s->dimms[i].banks == 1) { + dra |= 0x80; + } + if (ch == 0) { + c0dra |= dra << (r*8); + rankpop0 |= 1 << r; + } else { + c1dra |= dra << (r*8); + rankpop1 |= 1 << r; + } + } + MCHBAR32(0x208) = c0dra; + MCHBAR32(0x608) = c1dra; + + MCHBAR8(0x262) = (MCHBAR8(0x262) & ~0xf0) | ((rankpop0 << 4) & 0xf0); + MCHBAR8(0x662) = (MCHBAR8(0x662) & ~0xf0) | ((rankpop1 << 4) & 0xf0); + + if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) { + MCHBAR8(0x260) = MCHBAR8(0x260) | 1; + } + if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || ONLY_DIMMB_IS_POPULATED(s->dimms, 1)) { + MCHBAR8(0x660) = MCHBAR8(0x660) | 1; + } + + // DRB + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + if ((s->dimms[ch<<1].card_type && ((r) < s->dimms[ch<<1].ranks))) { + i = ch << 1; + } else { + i = (ch << 1) + 1; + } + if (ch == 0) { + dra0 = (c0dra >> (8*r)) & 0x7f; + c0drb = (u16)(c0drb + drbtab[dra0]); + s->dimms[i].rank_capacity_mb = drbtab[dra0] << 6; + MCHBAR16(0x200 + 2*r) = c0drb; + } else { + dra1 = (c1dra >> (8*r)) & 0x7f; + c1drb = (u16)(c1drb + drbtab[dra1]); + s->dimms[i].rank_capacity_mb = drbtab[dra1] << 6; + MCHBAR16(0x600 + 2*r) = c1drb; + } + } + + s->channel_capacity[0] = c0drb << 6; + s->channel_capacity[1] = c1drb << 6; + totalmemorymb = s->channel_capacity[0] + s->channel_capacity[1]; + printk(BIOS_DEBUG, "Total memory: %d + %d = %dMiB\n", + s->channel_capacity[0], s->channel_capacity[1], totalmemorymb); + + rankpop1 >>= 4; + if (rankpop1) { + MCHBAR16(0x600 + 2*msbpos(rankpop1)) = c0drb + c1drb; + MCHBAR16(0x602 + 2*msbpos(rankpop1)) = c0drb + c1drb; + MCHBAR16(0x604 + 2*msbpos(rankpop1)) = c0drb + c1drb; + MCHBAR16(0x606 + 2*msbpos(rankpop1)) = c0drb + c1drb; + } + + MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2; + MCHBAR16(0x104) = 0; + size = s->channel_capacity[0] + s->channel_capacity[1]; + MCHBAR16(0x102) = size; + map = 0; + if (s->channel_capacity[0] == 0) { + map = 0; + } else if (s->channel_capacity[1] == 0) { + map |= 0x20; + } else { + map |= 0x40; + } + map |= 0x18; + if (s->channel_capacity[0] <= s->channel_capacity[1]) { + map |= 0x5; + } else if (s->channel_capacity[0] > s->channel_capacity[1]) { + map |= 0x4; + } + MCHBAR8(0x110) = map; + MCHBAR16(0x10e) = 0; + if (s->channel_capacity[1] != 0) { + offset = 0; + } else if (s->channel_capacity[0] > s->channel_capacity[1]) { + offset = size; + } else { + offset = 0; + } + MCHBAR16(0x108) = offset; + MCHBAR16(0x10a) = 0; +} + +static void mmap_ddr2(struct sysinfo *s) +{ + u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud, gfxbase, gttbase, tsegbase; + u16 ggc; + u16 ggc2uma[] = { 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; + u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; + + ggc = pci_read_config16(PCI_DEV(0,0,0), 0x52); + gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; + gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; + tsegsize = 1; // 1MB TSEG + mmiosize = 0x400; // 1GB MMIO + tom = s->channel_capacity[0] + s->channel_capacity[1]; + tolud = MIN(0x1000 - mmiosize, tom); + touud = tom; + gfxbase = tolud - gfxsize; + gttbase = gfxbase - gttsize; + tsegbase = gttbase - tsegsize; + + pci_write_config16(PCI_DEV(0,0,0), 0xb0, tolud << 4); + pci_write_config16(PCI_DEV(0,0,0), 0xa0, tom >> 6); + pci_write_config16(PCI_DEV(0,0,0), 0xa2, touud); + pci_write_config32(PCI_DEV(0,0,0), 0xa4, gfxbase << 20); + pci_write_config32(PCI_DEV(0,0,0), 0xa8, gttbase << 20); + pci_write_config32(PCI_DEV(0,0,0), 0xac, tsegbase << 20); +} + +static void enhanced_ddr2(struct sysinfo *s) +{ + u8 ch, reg8; + + MCHBAR32(0xfb0) = 0x1000d024; + MCHBAR32(0xfb4) = 0xc842; + MCHBAR32(0xfbc) = 0xf; + MCHBAR32(0xfc4) = 0xfe22244; + MCHBAR8(0x12f) = 0x5c; + MCHBAR8(0xfb0) = (MCHBAR8(0xfb0) & ~1) | 1; + MCHBAR8(0x12f) = MCHBAR8(0x12f) | 0x2; + MCHBAR8(0x6c0) = (MCHBAR8(0x6c0) & ~0xf0) | 0xa0; + MCHBAR32(0xfa8) = 0x30d400; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1; + MCHBAR32(0x400*ch + 0x278) = 0x88141881; + MCHBAR16(0x400*ch + 0x27c) = 0x0041; + MCHBAR8(0x400*ch + 0x292) = 0xf2; + MCHBAR16(0x400*ch + 0x272) = MCHBAR16(0x400*ch + 0x272) | 0x100; + MCHBAR8(0x400*ch + 0x243) = (MCHBAR8(0x400*ch + 0x243) & ~0x2) | 1; + MCHBAR32(0x400*ch + 0x288) = 0x8040200; + MCHBAR32(0x400*ch + 0x28c) = 0xff402010; + MCHBAR32(0x400*ch + 0x290) = 0x4f2091c; + } + + reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf0); + pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 | 1); + MCHBAR32(0xfa0) = (MCHBAR32(0xfa0) & ~0x20002) | 0x2; + MCHBAR32(0xfa4) = (MCHBAR32(0xfa4) & ~0x219100c3) | 0x219100c2; + MCHBAR32(0x2c) = 0x44a53; + MCHBAR32(0x30) = 0x1f5a86; + MCHBAR32(0x34) = 0x1902810; + MCHBAR32(0x38) = 0xf7000000; + MCHBAR32(0x3c) = 0x23014410; + MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0x8f038000) | 0x8f038000; + MCHBAR32(0x20) = 0x33001; + pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 & ~1); +} + +static void power_ddr2(struct sysinfo *s) +{ + u32 reg1, reg2, reg3, reg4, clkgate, x592; + u8 lane, ch; + u8 twl = 0; + u16 x264, x23c; + + twl = s->selected_timings.CAS - 1; + x264 = 0x78; + switch (s->selected_timings.mem_clk) { + default: + case MEM_CLOCK_667MHz: + reg1 = 0x99; + reg2 = 0x1048a9; + clkgate = 0x230000; + x23c = 0x7a89; + break; + case MEM_CLOCK_800MHz: + if (s->selected_timings.CAS == 5) { + reg1 = 0x19a; + reg2 = 0x1048aa; + } else { + reg1 = 0x9a; + reg2 = 0x2158aa; + x264 = 0x89; + } + clkgate = 0x280000; + x23c = 0x7b89; + break; + } + reg3 = 0x232; + reg4 = 0x2864; + + if (CHANNEL_IS_POPULATED(s->dimms, 0) && CHANNEL_IS_POPULATED(s->dimms, 1)) { + MCHBAR32(0x14) = 0x0010461f; + } else { + MCHBAR32(0x14) = 0x0010691f; + } + MCHBAR32(0x18) = 0xdf6437f7; + MCHBAR32(0x1c) = 0x0; + MCHBAR32(0x24) = (MCHBAR32(0x24) & ~0xe0000000) | 0x30000000; + MCHBAR32(0x44) = (MCHBAR32(0x44) & ~0x1fef0000) | 0x6b0000; + MCHBAR16(0x115) = (u16) reg1; + MCHBAR32(0x117) = (MCHBAR32(0x117) & ~0xffffff) | reg2; + MCHBAR8(0x124) = 0x7; + MCHBAR16(0x12a) = (MCHBAR16(0x12a) & 0) | 0x80; + MCHBAR8(0x12c) = (MCHBAR8(0x12c) & 0) | 0xa0; + MCHBAR16(0x174) = MCHBAR16(0x174) & ~(1 << 15); + MCHBAR16(0x188) = (MCHBAR16(0x188) & ~0x1f00) | 0x1f00; + MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0x8; + MCHBAR8(0x192) = (MCHBAR8(0x192) & ~1) | 1; + MCHBAR8(0x193) = (MCHBAR8(0x193) & ~0xf) | 0xf; + MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x480) | 0x80; + MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0x1fff) | 0x3f; // | clockgatingiii + MCHBAR32(0x6d1) = (MCHBAR32(0x6d1) & ~0xff03ff) | 0x100 | clkgate; + MCHBAR8(0x212) = (MCHBAR8(0x212) & ~0x7f) | 0x7f; + MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0xffff0) | 0xcc5f0; + MCHBAR8(0x2c4) = (MCHBAR8(0x2c4) & ~0x70) | 0x70; + MCHBAR32(0x2d1) = (MCHBAR32(0x2d1) & ~0xffffff) | 0xff2831; // | clockgatingi + MCHBAR32(0x2d4) = 0x40453600; + MCHBAR32(0x300) = 0xc0b0a08; + MCHBAR32(0x304) = 0x6040201; + MCHBAR32(0x30c) = (MCHBAR32(0x30c) & ~0x43c0f) | 0x41405; + MCHBAR16(0x610) = 0x232; + MCHBAR16(0x612) = 0x2864; + MCHBAR32(0x62c) = (MCHBAR32(0x62c) & ~0xc000000) | 0x4000000; + MCHBAR32(0xae4) = 0; + MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0xf0000) | 0x10000; + MCHBAR32(0xf00) = 0x393a3b3c; + MCHBAR32(0xf04) = 0x3d3e3f40; + MCHBAR32(0xf08) = 0x393a3b3c; + MCHBAR32(0xf0c) = 0x3d3e3f40; + MCHBAR32(0xf18) = MCHBAR32(0xf18) & ~0xfff00001; + MCHBAR32(0xf48) = 0xfff0ffe0; + MCHBAR32(0xf4c) = 0xffc0ff00; + MCHBAR32(0xf50) = 0xfc00f000; + MCHBAR32(0xf54) = 0xc0008000; + MCHBAR32(0xf6c) = (MCHBAR32(0xf6c) & ~0xffff0000) | 0xffff0000; + MCHBAR32(0xfac) = MCHBAR32(0xfac) & ~0x80000000; + MCHBAR32(0xfb8) = MCHBAR32(0xfb8) & ~0xff000000; + MCHBAR32(0xfbc) = (MCHBAR32(0xfbc) & ~0x7f800) | 0xf000; + MCHBAR32(0x1104) = 0x3003232; + MCHBAR32(0x1108) = 0x74; + if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) { + MCHBAR32(0x110c) = 0xaa; + } else { + MCHBAR32(0x110c) = 0x100; + } + MCHBAR32(0x1110) = 0x10810350 & ~0x78; + MCHBAR32(0x1114) = 0; + if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { + twl = 5; + } else { + twl = 6; + } + x592 = 0xff; + if (pci_read_config8(PCI_DEV(0,0,0), 0x8) < 3) { + x592 = ~0x4; + } + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + MCHBAR8(0x400*ch + 0x239) = twl + 15; + MCHBAR16(0x400*ch + 0x23c) = x23c; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0x706033) | 0x406033; + MCHBAR32(0x400*ch + 0x260) = (MCHBAR32(0x400*ch + 0x260) & ~(1 << 16)) | (1 << 16); + MCHBAR8(0x400*ch + 0x264) = x264; + MCHBAR8(0x400*ch + 0x592) = (MCHBAR8(0x400*ch + 0x592) & ~0x3f) | (0x3c & x592); + MCHBAR8(0x400*ch + 0x593) = (MCHBAR8(0x400*ch + 0x593) & ~0x1f) | 0x1e; + } + + for (lane = 0; lane < 8; lane++) { + MCHBAR8(0x561 + (lane << 2)) = MCHBAR8(0x561 + (lane << 2)) & ~(1 << 3); + } +} + +void raminit_ddr2(struct sysinfo *s) +{ + u8 ch; + u8 r, bank; + u32 reg32; + + // Select timings based on SPD info + sdram_detect_smallest_params2(s); + + // Reset if required + checkreset_ddr2(s); + + // Clear self refresh + MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3; + + // Clear host clk gate reg + MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; + + // Select DDR2 + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; + + // Set freq + MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | + (s->selected_timings.mem_clk << 4) | (1 << 10); + + // Overwrite freq if chipset rejects it + s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; + if (s->selected_timings.mem_clk > (s->max_fsb + 3)) { + die("Error: DDR is faster than FSB, halt\n"); + } + + udelay(250000); + + // Program clock crossing + clkcross_ddr2(s); + printk(BIOS_DEBUG, "Done clk crossing\n"); + + // DDR2 IO + setioclk_ddr2(s); + printk(BIOS_DEBUG, "Done I/O clk\n"); + + // Grant to launch + launch_ddr2(s); + printk(BIOS_DEBUG, "Done launch\n"); + + // Program DDR2 timings + timings_ddr2(s); + printk(BIOS_DEBUG, "Done timings\n"); + + // Program DLL + dll_ddr2(s); + + // RCOMP + rcomp_ddr2(s); + printk(BIOS_DEBUG, "RCOMP\n"); + + // ODT + odt_ddr2(s); + printk(BIOS_DEBUG, "Done ODT\n"); + + // RCOMP update + while ((MCHBAR8(0x130) & 1) != 0 ); + printk(BIOS_DEBUG, "Done RCOMP update\n"); + + // Set defaults + MCHBAR32(0x260) = (MCHBAR32(0x260) & ~1) | 0xf00000; + MCHBAR32(0x660) = (MCHBAR32(0x660) & ~1) | 0xf00000; + MCHBAR32(0x208) = 0x01010101; + MCHBAR32(0x608) = 0x01010101; + MCHBAR32(0x200) = 0x00040002; + MCHBAR32(0x204) = 0x00080006; + MCHBAR32(0x600) = 0x00040002; + MCHBAR32(0x604) = 0x00100006; + MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2; + MCHBAR32(0x104) = 0; + MCHBAR16(0x102) = 0x400; + MCHBAR8(0x100) = (2 << 5) | (3 << 3); + MCHBAR16(0x10e) = 0; + MCHBAR32(0x108) = 0; + pci_write_config16(PCI_DEV(0,0,0), 0xb0, 0x4000); + pci_write_config16(PCI_DEV(0,0,0), 0xa0, 0x0010); + pci_write_config16(PCI_DEV(0,0,0), 0xa2, 0x0400); + pci_write_config32(PCI_DEV(0,0,0), 0xa4, 0x40000000); + pci_write_config32(PCI_DEV(0,0,0), 0xa8, 0x40000000); + pci_write_config32(PCI_DEV(0,0,0), 0xac, 0x40000000); + + // IOBUFACT + if (CHANNEL_IS_POPULATED(s->dimms, 0)) { + MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x3f; + MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x7; + } + if (CHANNEL_IS_POPULATED(s->dimms, 1)) { + if (pci_read_config8(PCI_DEV(0,0,0), 0x8) < 2) { + MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x3f; + MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 1; + } + MCHBAR8(0x9dd) = (MCHBAR8(0x9dd) & ~0x3f) | 0x3f; + MCHBAR8(0x9d8) = MCHBAR8(0x9d8) | 0x7; + } + + // Pre jedec + MCHBAR8(0x40) = MCHBAR8(0x40) | 0x2; + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + MCHBAR32(0x400*ch + 0x260) = MCHBAR32(0x400*ch + 0x260) | (1 << 27); + } + MCHBAR16(0x212) = (MCHBAR16(0x212) & ~0xf000) | 0xf000; + MCHBAR16(0x212) = (MCHBAR16(0x212) & ~0xf00) | 0xf00; + printk(BIOS_DEBUG, "Done pre-jedec\n"); + + // JEDEC reset + jedec_ddr2(s); + + printk(BIOS_DEBUG, "Done jedec steps\n"); + + // After JEDEC reset + MCHBAR8(0x40) = MCHBAR8(0x40) & ~0x2; + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { + reg32 = (2 << 18) | (3 << 13) | (5 << 8); + } else { + reg32 = (2 << 18) | (3 << 13) | (4 << 8); + } + MCHBAR32(0x400*ch + 0x274) = (MCHBAR32(0x400*ch + 0x274) & ~0xfff00) | reg32; + MCHBAR8(0x400*ch + 0x274) = MCHBAR8(0x400*ch + 0x274) & ~0x80; + MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1; + MCHBAR32(0x400*ch + 0x278) = 0x88141881; + MCHBAR16(0x400*ch + 0x27c) = 0x41; + MCHBAR8(0x400*ch + 0x292) = 0xf2; + MCHBAR8(0x400*ch + 0x271) = (MCHBAR8(0x400*ch + 0x271) & ~0xe) | 0xe; + } + MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 0x8; + MCHBAR8(0x2c3) = MCHBAR8(0x2c3) | 0x40; + MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 0x4; + + printk(BIOS_DEBUG, "Done post-jedec\n"); + + // Set DDR2 init complete + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + MCHBAR32(0x400*ch + 0x268) = (MCHBAR32(0x400*ch + 0x268) & ~0xc0000000) | 0xc0000000; + } + + // Receive enable + rcven_ddr2(s); + printk(BIOS_DEBUG, "Done rcven\n"); + + // Finish rcven + FOR_EACH_CHANNEL(ch) { + MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) & ~0xe; + MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x2; + MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x4; + MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x8; + } + MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; + MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80; + MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; + + // Dummy writes / reads + volatile u32 data; + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + for (bank = 0; bank < 4; bank++) { + reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); + write32((u32 *)reg32, 0xffffffff); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); + write32((u32 *)reg32, 0x00000000); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + } + } + printk(BIOS_DEBUG, "Done dummy reads\n"); + + // XXX tRD + + // XXX Write training + + // XXX Read training + + // DRADRB + dradrb_ddr2(s); + printk(BIOS_DEBUG, "Done DRADRB\n"); + + // Memory map + mmap_ddr2(s); + printk(BIOS_DEBUG, "Done memory map\n"); + + // Enhanced mode + enhanced_ddr2(s); + printk(BIOS_DEBUG, "Done enhanced mode\n"); + + // Periodic RCOMP + MCHBAR16(0x160) = (MCHBAR16(0x160) & ~0xfff) | 0x999; + MCHBAR16(0x1b4) = MCHBAR16(0x1b4) | 0x3000; + MCHBAR8(0x130) = MCHBAR8(0x130) | 0x82; + printk(BIOS_DEBUG, "Done PRCOMP\n"); + + // Power settings + power_ddr2(s); + printk(BIOS_DEBUG, "Done power settings\n"); + + // ME related + //MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); + + printk(BIOS_DEBUG, "Done ddr2\n"); +}

1 0

Patch set updated for coreboot: gigabyte/ga-g41m-es2l: Add mainboard
by Damien Zammit 27 Dec '15

27 Dec '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11306 -gerrit commit 6f1ac32375b4475d4688faac875f12ffb03db364 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Aug 19 15:23:32 2015 +1000 gigabyte/ga-g41m-es2l: Add mainboard Board uses x4x native raminit Board boots into Debian 8 with full graphics VGA: - VGA native init works in grub with analog connector - Fails to boot with both channels of ram populated Change-Id: I7417813456817529b8cbaace45cefe47467d0a82 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 47 ++++++ src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name | 2 + src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc | 1 + src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl | 1 + .../gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl | 34 +++++ .../gigabyte/ga-g41m-es2l/acpi/platform.asl | 28 ++++ .../gigabyte/ga-g41m-es2l/acpi/superio.asl | 1 + .../gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl | 66 +++++++++ src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c | 42 ++++++ src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt | 5 + src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 37 +++++ src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 120 +++++++++++++++ src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl | 43 ++++++ src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c | 8 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 163 +++++++++++++++++++++ 15 files changed, 598 insertions(+) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig new file mode 100644 index 0000000..fc0c229 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -0,0 +1,47 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_GIGABYTE_GA_G41M_ES2L + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_ITE_IT8718F + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT + +config IRQ9_MADT_OVERRIDE + bool + default n + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config MAINBOARD_DIR + string + default "gigabyte/ga-g41m-es2l" + +config MAINBOARD_PART_NUMBER + string + default "GA-G41M-ES2L" + +endif # BOARD_GIGABYTE_GA_G41M_ES2L diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name new file mode 100644 index 0000000..e685ce1 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_G41M_ES2L + bool "GA-G41M-ES2L" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc new file mode 100644 index 0000000..f9621db --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += cstates.c diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..0a69f3d --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x001effff, 0, 0, 17}, + Package() { 0x001effff, 1, 0, 20}, + Package() { 0x001effff, 2, 0, 16}, + Package() { 0x001effff, 3, 0, 16}, + }) +} Else { + Return (Package() { + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x001effff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x001effff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + }) +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl new file mode 100644 index 0000000..fdfe73d --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for x4x */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + If (PICM) { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, 0, 16 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, 0, 22 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 23 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 16 }, + Package() { 0x001dffff, 0, 0, 23 }, + /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 0, 0, 18 }, + }) + } Else { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c new file mode 100644 index 0000000..d9d8032 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <arch/ioapic.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->lptp = 0; /* LPT port */ + gnvs->fdcp = 0; /* Floppy Disk Controller */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->cmap = 0x01; /* Enable COM 1 port */ +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt b/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt new file mode 100644 index 0000000..44ed73a --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt @@ -0,0 +1,5 @@ +Category: desktop +Board URL: +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c new file mode 100644 index 0000000..dbac2ed --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <device/device.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +static acpi_cstate_t cst_entries[] = { + { + /* acpi C1 / cpu C1 */ + 1, 0x01, 1000, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 } + }, + { + /* acpi C2 / cpu C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } + }, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb new file mode 100644 index 0000000..6d85337 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -0,0 +1,120 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + register "slfm" = "1" + register "c5" = "1" + register "c6" = "1" + end + end + device domain 0 on # PCI domain + subsystemid 0x1458 0x5000 inherit + device pci 0.0 on # Host Bridge + subsystemid 0x1458 0x5000 + end + device pci 1.0 off end # PCI Bridge to Management Engine + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1458 0xd000 + end + device pci 2.1 off end # Integrated graphics controller 2 + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x40" + + device pci 1b.0 on # Audio + subsystemid 0x1458 0xa002 + end + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2 (NIC) + device pci 00.0 on # PCI 10ec:8168 + subsystemid 0x1458 0xe000 + end + end + device pci 1c.2 on end # PCIe 3 + device pci 1c.3 on end # PCIe 4 + device pci 1d.0 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.1 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.2 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.3 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.7 on # USB + subsystemid 0x1458 0x5006 + end + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8718f # Super I/O + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + irq 0x70 = 0 + io 0x62 = 0x000 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 1 + io 0x62 = 0x64 + end + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + end + end + device pci 1f.1 off end # PATA/IDE + device pci 1f.2 on # SATA + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on # SMbus + subsystemid 0x1458 0x5001 + end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl new file mode 100644 index 0000000..e11eb39 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801gx/i82801gx.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c new file mode 100644 index 0000000..4d5ccf4 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c @@ -0,0 +1,8 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c new file mode 100644 index 0000000..6bae128 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <northbridge/intel/x4x/x4x.h> +#include <cpu/x86/bist.h> +#include <superio/ite/it8718f/it8718f.h> +#include <superio/ite/common/ite.h> +#include <lib.h> +#include <cpu/intel/romstage.h> +#include <arch/stages.h> +#include <cbmem.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) +#define SUPERIO_DEV PNP_DEV(0x2e, 0) + +/* Early mainboard specific GPIO setup. + * We should use standard gpio.h eventually + */ + +static void mb_gpio_init(void) +{ + device_t dev; + + /* Southbridge GPIOs. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); + + outl(0x1f15f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe2e9ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xe0d7fcc3, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000e7, DEFAULT_GPIOBASE + 0x30); + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); + outl(0x00000083, DEFAULT_GPIOBASE + 0x38); + + /* Set default power management registers */ + pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1); + outw(0x0011, DEFAULT_PMBASE + 0x00); + outw(0x0120, DEFAULT_PMBASE + 0x02); + outl(0x00001c01, DEFAULT_PMBASE + 0x04); + outl(0x00bb29d2, DEFAULT_PMBASE + 0x08); + outl(0x000000a0, DEFAULT_PMBASE + 0x10); + outl(0xc5000000, DEFAULT_PMBASE + 0x28); + outl(0x00000040, DEFAULT_PMBASE + 0x2c); + outw(0x13e0, DEFAULT_PMBASE + 0x44); + outw(0x003f, DEFAULT_PMBASE + 0x60); + outw(0x0800, DEFAULT_PMBASE + 0x68); + outw(0x0008, DEFAULT_PMBASE + 0x6a); + outw(0x003f, DEFAULT_PMBASE + 0x72); + + /* Set default GPIOs on superio */ + ite_reg_write(GPIO_DEV, 0x25, 0x00); + ite_reg_write(GPIO_DEV, 0x26, 0xc7); + ite_reg_write(GPIO_DEV, 0x27, 0x80); + ite_reg_write(GPIO_DEV, 0x28, 0x41); + ite_reg_write(GPIO_DEV, 0x29, 0x0a); + ite_reg_write(GPIO_DEV, 0x2c, 0x01); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_reg_write(GPIO_DEV, 0x72, 0x00); + ite_reg_write(GPIO_DEV, 0x73, 0x00); + ite_reg_write(GPIO_DEV, 0xbb, 0x40); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc1, 0xc7); + ite_reg_write(GPIO_DEV, 0xc2, 0x80); + ite_reg_write(GPIO_DEV, 0xc3, 0x01); + ite_reg_write(GPIO_DEV, 0xc4, 0x0a); + ite_reg_write(GPIO_DEV, 0xc8, 0x00); + ite_reg_write(GPIO_DEV, 0xc9, 0x04); + ite_reg_write(GPIO_DEV, 0xcb, 0x00); + ite_reg_write(GPIO_DEV, 0xcc, 0x02); + ite_reg_write(GPIO_DEV, 0xf0, 0x10); + ite_reg_write(GPIO_DEV, 0xf1, 0x40); + ite_reg_write(GPIO_DEV, 0xf6, 0x26); + ite_reg_write(GPIO_DEV, 0xfc, 0x52); + + ite_reg_write(EC_DEV, 0xf0, 0x80); + ite_reg_write(EC_DEV, 0xf1, 0x00); + ite_reg_write(EC_DEV, 0xf2, 0x0a); + ite_reg_write(EC_DEV, 0xf3, 0x80); + ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 + + /* IRQ routing */ + RCBA32(0x3100) = 0x00002210; + RCBA32(0x3104) = 0x00002100; + RCBA32(0x3108) = 0x10004321; + RCBA32(0x310c) = 0x00214321; + RCBA32(0x3110) = 0x00000001; + RCBA32(0x3140) = 0x00410032; + RCBA32(0x3144) = 0x32100237; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + RCBA8(0x31ff); +} + +static void ich7_enable_lpc(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); + + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c); +} + +void main(unsigned long bist) +{ + // ch0 ch1 + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + + /* Disable watchdog timer and route port 80 to LPC */ + RCBA32(0x3410) = (RCBA32(0x3410) | 0x20);// & ~0x4; + + /* Set southbridge and Super I/O GPIOs. */ + mb_gpio_init(); + + ich7_enable_lpc(); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ + ite_reg_write(GPIO_DEV, 0xEF, 0x7E); + + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + x4x_early_init(); + + printk(BIOS_DEBUG, "Initializing memory\n"); + sdram_initialize(0, spd_addrmap); + quick_ram_check(); + printk(BIOS_DEBUG, "Memory initialized\n"); +}

1 0

Patch set updated for coreboot: northbridge/intel/x4x: Intel 4-series northbridge support
by Damien Zammit 27 Dec '15

27 Dec '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11305 -gerrit commit 01bec4a3947d7daed305c12d5a4e89b5b0fe3e86 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Aug 19 15:16:59 2015 +1000 northbridge/intel/x4x: Intel 4-series northbridge support Boots to console on Gigabyte GA-G41M-ES2L Ram initialization *not* included in this patch VGA native init works on analog connector Change-Id: I5262f73fd03d5e5c12e9f11d027bdfbbf0ddde82 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/Kconfig | 1 + src/northbridge/intel/x4x/Kconfig | 39 ++++ src/northbridge/intel/x4x/Makefile.inc | 27 +++ src/northbridge/intel/x4x/acpi.c | 57 +++++ src/northbridge/intel/x4x/acpi/hostbridge.asl | 234 +++++++++++++++++++ src/northbridge/intel/x4x/acpi/peg.asl | 42 ++++ src/northbridge/intel/x4x/acpi/x4x.asl | 49 ++++ src/northbridge/intel/x4x/bootblock.c | 32 +++ src/northbridge/intel/x4x/chip.h | 26 +++ src/northbridge/intel/x4x/early_init.c | 58 +++++ src/northbridge/intel/x4x/gma.c | 286 +++++++++++++++++++++++ src/northbridge/intel/x4x/iomap.h | 28 +++ src/northbridge/intel/x4x/northbridge.c | 234 +++++++++++++++++++ src/northbridge/intel/x4x/ram_calc.c | 88 +++++++ src/northbridge/intel/x4x/x4x.h | 320 ++++++++++++++++++++++++++ 15 files changed, 1521 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 38cf855..c30702f 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -358,6 +358,7 @@ source "src/mainboard/Kconfig" config CBFS_SIZE hex "Size of CBFS filesystem in ROM" default 0x100000 if HAVE_INTEL_FIRMWARE || \ + NORTHBRIDGE_INTEL_X4X || \ NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || \ NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig new file mode 100644 index 0000000..c330fd5 --- /dev/null +++ b/src/northbridge/intel/x4x/Kconfig @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config NORTHBRIDGE_INTEL_X4X + bool + +if NORTHBRIDGE_INTEL_X4X + +config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy + def_bool y + select HAVE_DEBUG_RAM_SETUP + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + select VGA + select INTEL_GMA_ACPI + select LATE_CBMEM_INIT + +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/x4x/bootblock.c" + +config VGA_BIOS_ID + string + default "8086,2e32" + +endif diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc new file mode 100644 index 0000000..8d1247e --- /dev/null +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -0,0 +1,27 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 secunet Security Networks AG +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y) + +romstage-y += early_init.c +romstage-y += ram_calc.c + +ramstage-y += acpi.c +ramstage-y += ram_calc.c +ramstage-y += gma.c +ramstage-y += northbridge.c + +endif diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c new file mode 100644 index 0000000..386096c --- /dev/null +++ b/src/northbridge/intel/x4x/acpi.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cbmem.h> +#include <arch/acpigen.h> +#include <cpu/cpu.h> +#include "x4x.h" + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + u32 pciexbar = 0; + u32 length = 0; + + dev = dev_find_slot(0, PCI_DEVFN(0,0)); + if (!decode_pciebar(&pciexbar, &length)) + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, + pciexbar, 0x0, 0x0, (length >> 20) - 1); + + return current; +} + +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long start, + struct acpi_rsdp *rsdp) +{ + unsigned long current; + current = acpi_align_current(start); + + printk(BIOS_DEBUG, "current = %lx\n", current); + + return current; +} diff --git a/src/northbridge/intel/x4x/acpi/hostbridge.asl b/src/northbridge/intel/x4x/acpi/hostbridge.asl new file mode 100644 index 0000000..530fdfa --- /dev/null +++ b/src/northbridge/intel/x4x/acpi/hostbridge.asl @@ -0,0 +1,234 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/ioapic.h> + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_ADR, 0) +Name(_BBN, 0) + +Device (MCHC) +{ + Name(_ADR, 0x00000000) // 0:0.0 + + OperationRegion(MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset (0x40), // EPBAR + EPEN, 1, // Enable + , 11, // + EPBR, 24, // EPBAR + + Offset (0x48), // MCHBAR + MHEN, 1, // Enable + , 13, // + MHBR, 22, // MCHBAR + + Offset (0x60), // PCIe BAR + PXEN, 1, // Enable + PXSZ, 2, // BAR size + , 23, // + PXBR, 10, // PCIe BAR + + Offset (0x68), // DMIBAR + DMEN, 1, // Enable + , 11, // + DMBR, 24, // DMIBAR + + // ... + + Offset (0x90), // PAM0 + , 4, + PM0H, 2, + , 2, + Offset (0x91), // PAM1 + PM1L, 2, + , 2, + PM1H, 2, + , 2, + Offset (0x92), // PAM2 + PM2L, 2, + , 2, + PM2H, 2, + , 2, + Offset (0x93), // PAM3 + PM3L, 2, + , 2, + PM3H, 2, + , 2, + Offset (0x94), // PAM4 + PM4L, 2, + , 2, + PM4H, 2, + , 2, + Offset (0x95), // PAM5 + PM5L, 2, + , 2, + PM5H, 2, + , 2, + Offset (0x96), // PAM6 + PM6L, 2, + , 2, + PM6H, 2, + , 2, + + Offset (0xa0), // Top of Used Memory + TOM, 8, + + Offset (0xb0), // Top of Low Used Memory + , 4, + TLUD, 12, + } + +} + +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfebfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + IO_APIC_ADDR,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) + +// Current Resource Settings + +Method (_CRS, 0, Serialized) +{ + // Find PCI resource area in MCRS + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) + + // Fix up PCI memory region: + // Enter actual TOLUD. The TOLUD register contains bits 20-31 of + // the top of memory address. + ShiftLeft (^MCHC.TLUD, 20, PMIN) + Add(Subtract(PMAX, PMIN), 1, PLEN) + + Return (MCRS) +} + +/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ +#include "acpi/x4x_pci_irqs.asl" diff --git a/src/northbridge/intel/x4x/acpi/peg.asl b/src/northbridge/intel/x4x/acpi/peg.asl new file mode 100644 index 0000000..f2314c2 --- /dev/null +++ b/src/northbridge/intel/x4x/acpi/peg.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PEGP) +{ + Name (_ADR, 0x00010000) + + // PCI Interrupt Routing. + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0001ffff, 0, 0, 16 }, + Package() { 0x0001ffff, 1, 0, 17 }, + Package() { 0x0001ffff, 2, 0, 18 }, + Package() { 0x0001ffff, 3, 0, 19 }, + }) + } Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } + + } +} diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl new file mode 100644 index 0000000..7724d8e --- /dev/null +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "hostbridge.asl" +#include "../iomap.h" + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) + Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) + Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} + +// PCIe graphics port 0:1.0 +#include "peg.asl" + +// Integrated graphics 0:2.0 +#include <drivers/intel/gma/acpi/non-pch.asl> diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c new file mode 100644 index 0000000..adcaa89 --- /dev/null +++ b/src/northbridge/intel/x4x/bootblock.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> + +#define D0F0_PCIEXBAR_LO 0x60 +#define TPMBASE 0xfed40000 +#define TPM32(x) *((volatile u32 *)(TPMBASE + x)) + +static void bootblock_northbridge_init(void) +{ + uint32_t reg32; + + /* Disable LaGrande Technology (LT) */ + reg32 = TPM32(0); + + reg32 = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; + pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg32); +} diff --git a/src/northbridge/intel/x4x/chip.h b/src/northbridge/intel/x4x/chip.h new file mode 100644 index 0000000..1fb54cc --- /dev/null +++ b/src/northbridge/intel/x4x/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef NORTHBRIDGE_INTEL_X4X_CHIP_H +#define NORTHBRIDGE_INTEL_X4X_CHIP_H + +#include <drivers/intel/gma/i915.h> + +struct northbridge_intel_x4x_config { + struct i915_gpu_controller_info gfx; +}; + +#endif diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c new file mode 100644 index 0000000..1d43e0a --- /dev/null +++ b/src/northbridge/intel/x4x/early_init.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include "x4x.h" + +void x4x_early_init(void) +{ + u16 reg16; + + const device_t d0f0 = PCI_DEV(0, 0, 0); + + /* Setup MCHBAR. */ + pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); + + /* Setup DMIBAR. */ + pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); + + /* Setup EPBAR. */ + pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); + + /* Setup PMBASE */ + pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1); + + /* Setup HECIBAR */ + pci_write_config32(PCI_DEV(0,3,0), 0x10, DEFAULT_HECIBAR); + reg16 = pci_read_config16(PCI_DEV(0,3,0), 0x4); + pci_write_config16(PCI_DEV(0,3,0), 0x4, reg16 | 0x6); + + /* Set C0000-FFFFF to access RAM on both reads and writes */ + pci_write_config8(d0f0, D0F0_PAM(0), 0x30); + pci_write_config8(d0f0, D0F0_PAM(1), 0x33); + pci_write_config8(d0f0, D0F0_PAM(2), 0x33); + pci_write_config8(d0f0, D0F0_PAM(3), 0x33); + pci_write_config8(d0f0, D0F0_PAM(4), 0x33); + pci_write_config8(d0f0, D0F0_PAM(5), 0x33); + pci_write_config8(d0f0, D0F0_PAM(6), 0x33); + + /* Enable internal GFX */ + pci_write_config16(d0f0, D0F0_GGC, 0x0170); + + reg16 = pci_read_config16(d0f0, D0F0_DEVEN); + pci_write_config16(d0f0, D0F0_DEVEN, reg16 | 0x8); +} diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c new file mode 100644 index 0000000..7891229 --- /dev/null +++ b/src/northbridge/intel/x4x/gma.c @@ -0,0 +1,286 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Chromium OS Authors + * Copyright (C) 2013 Vladimir Serbinenko + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <kconfig.h> + +#include "drivers/intel/gma/i915_reg.h" +#include "chip.h" +#include "x4x.h" +#include <drivers/intel/gma/intel_bios.h> +#include <drivers/intel/gma/i915.h> +#include <pc80/vga.h> +#include <pc80/vga_io.h> + +static struct resource *gtt_res = NULL; + +void gtt_write(u32 reg, u32 data) +{ + write32(res2mmio(gtt_res, reg, 0), data); +} + +static void intel_gma_init(const struct northbridge_intel_x4x_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) +{ + + int i; + u32 hactive, vactive; + vga_gr_write(0x18, 0); + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); + write32(mmio + DPLL_MD(1), 0x3); + + vga_misc_write(0x67); + + const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = 640; + vactive = 400; + + vga_textmode_init(); + + mdelay(1); + write32(mmio + FP0(0), 0x31108); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + mdelay(1); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + HTOTAL(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HSYNC(0), + ((hactive - 1) << 16) + | (hactive - 1)); + + write32(mmio + VTOTAL(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VSYNC(0), + ((vactive - 1) << 16) + | (vactive - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); + + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0xa0000000); + + mdelay(1); + + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + + write32(mmio + VGACNTRL, 0x0); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + PP_CONTROL, PANEL_POWER_ON); + + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); +} + +static void gma_func0_init(struct device *dev) +{ + u32 reg32; + + /* IGD needs to be Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Init graphics power management */ + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + + struct northbridge_intel_x4x_config *conf = dev->chip_info; + + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); + } else { + u32 physbase; + struct resource *lfb_res; + struct resource *pio_res; + + lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); + pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); + + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + + if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base + && lfb_res && lfb_res->base) { + printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, + pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE "); + } + + /* Post VBIOS init */ + /* Enable Backlight */ + gtt_write(BLC_PWM_CTL2, (1 << 31)); + if (conf->gfx.backlight == 0) + gtt_write(BLC_PWM_CTL, 0x06100610); + else + gtt_write(BLC_PWM_CTL, conf->gfx.backlight); +} + +static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & + 0xffff)); + } +} + +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_x4x_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(device_t device) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + +static struct pci_operations gma_pci_ops = { + .set_subsystem = gma_set_subsystem, +}; + +static struct device_operations gma_func0_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, + .init = gma_func0_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = &gma_pci_ops, +}; + +static const unsigned short pci_device_ids[] = +{ + 0x2e32, 0 +}; + +static const struct pci_driver gma __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h new file mode 100644 index 0000000..34153c1 --- /dev/null +++ b/src/northbridge/intel/x4x/iomap.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef X4X_IOMAP_H +#define X4X_IOMAP_H + +/* 4 KB per PCIe device */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define DEFAULT_HECIBAR 0xfed10000 + +#endif /* X4X_IOMAP_H */ diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c new file mode 100644 index 0000000..c5a8968 --- /dev/null +++ b/src/northbridge/intel/x4x/northbridge.c @@ -0,0 +1,234 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/hypertransport.h> +#include <stdlib.h> +#include <string.h> +#include <cpu/cpu.h> +#include <boot/tables.h> +#include <arch/acpi.h> +#include <northbridge/intel/x4x/chip.h> +#include <northbridge/intel/x4x/x4x.h> + +/* Reserve segments A and B: + * + * 0xa0000 - 0xbffff: legacy VGA + */ +static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_size_k = 128; + +static void mch_domain_read_resources(device_t dev) +{ + u64 tom, touud; + u32 tomk, tsegk, tolud, usable_tomk; + u32 pcie_config_base, pcie_config_size; + u32 uma_sizek = 0; + + /* 1024KiB TSEG */ + tsegk = 1 << 10; + + pci_domain_read_resources(dev); + + /* Top of Upper Usable DRAM, including remap */ + touud = pci_read_config16(dev, D0F0_TOUUD); + touud <<= 20; + + /* Top of Lower Usable DRAM */ + tolud = pci_read_config16(dev, D0F0_TOLUD) & 0xfff0; + tolud <<= 16; + + /* Top of Memory - does not account for any UMA */ + tom = pci_read_config16(dev, D0F0_TOM) & 0x01ff; + tom <<= 26; + + printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", + touud, tolud, tom); + + tomk = tolud >> 10; + + /* Graphics memory comes next */ + const u16 ggc = pci_read_config16(dev, D0F0_GGC); + printk(BIOS_DEBUG, "IGD decoded, subtracting "); + + /* Graphics memory */ + const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); + printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); + + /* GTT Graphics Stolen Memory Size (GGMS) */ + const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); + printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); + + uma_sizek = gms_sizek + gsm_sizek + tsegk; + usable_tomk = tomk - uma_sizek; + + printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10); + + /* Report the memory regions */ + ram_resource(dev, 3, 0, legacy_hole_base_k); + ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, + (usable_tomk - (legacy_hole_base_k + legacy_hole_size_k))); + + /* + * If >= 4GB installed then memory from TOLUD to 4GB + * is remapped above TOM, TOUUD will account for both + */ + touud >>= 10; /* Convert to KB */ + if (touud > 4096 * 1024) { + ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); + printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", + (touud >> 10) - 4096); + } + + printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x " + "size=0x%08x\n", usable_tomk << 10, uma_sizek << 10); + fixed_mem_resource(dev, 6, usable_tomk, uma_sizek, IORESOURCE_RESERVE); + + /* Some strange hole, reserve it */ + //fixed_mem_resource(dev, 7, usable_tomk - (0x02000000 >> 10), 0x02000000 >> 10, IORESOURCE_RESERVE); + + if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { + printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " + "size=0x%x\n", pcie_config_base, pcie_config_size); + fixed_mem_resource(dev, 7, pcie_config_base >> 10, + pcie_config_size >> 10, IORESOURCE_RESERVE); + } +} + +static void mch_domain_set_resources(device_t dev) +{ + struct resource *resource; + int i; + + for (i = 3; i < 8; ++i) { + /* Report read resources. */ + resource = probe_resource(dev, i); + if (resource) + report_resource_stored(dev, resource, ""); + } + + assign_resources(dev->link_list); +} + +static void mch_domain_init(device_t dev) +{ + u32 reg32; + + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); +} + +static struct device_operations pci_domain_ops = { + .read_resources = mch_domain_read_resources, + .set_resources = mch_domain_set_resources, + .enable_resources = NULL, + .init = mch_domain_init, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, + .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt_generator = generate_cpu_entries, +}; + + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = cpu_bus_init, + .scan_bus = 0, +}; + + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; +#if CONFIG_HAVE_ACPI_RESUME + switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { + case SKPAD_NORMAL_BOOT_MAGIC: + printk(BIOS_DEBUG, "Normal boot.\n"); + acpi_slp_type=0; + break; + case SKPAD_ACPI_S3_MAGIC: + printk(BIOS_DEBUG, "S3 Resume.\n"); + acpi_slp_type=3; + break; + default: + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + acpi_slp_type=0; + break; + } +#endif + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +static void x4x_init(void *const chip_info) +{ + int dev, fn, bit_base; + + struct device *const d0f0 = dev_find_slot(0, 0); + + /* Hide internal functions based on devicetree info. */ + for (dev = 3; dev > 0; --dev) { + switch (dev) { + case 3: /* ME */ + fn = 3; + bit_base = 6; + break; + case 2: /* IGD */ + fn = 1; + bit_base = 3; + break; + case 1: /* PEG */ + fn = 0; + bit_base = 1; + break; + } + for (; fn >= 0; --fn) { + const struct device *const d = + dev_find_slot(0, PCI_DEVFN(dev, fn)); + if (!d || d->enabled) continue; + const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); + pci_write_config32(d0f0, D0F0_DEVEN, + deven & ~(1 << (bit_base + fn))); + } + } + + const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); + if (!(deven & (0xf << 6))) + pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); +} + +struct chip_operations northbridge_intel_x4x_ops = { + CHIP_NAME("Intel 4-Series Northbridge") + .enable_dev = enable_dev, + .init = x4x_init, +}; diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c new file mode 100644 index 0000000..f11b19a --- /dev/null +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <commonlib/helpers.h> +#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include <northbridge/intel/x4x/x4x.h> + +/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ +u32 decode_igd_memory_size(const u32 gms) +{ + static const u16 ggc2uma[] = { 0, 0, 0, 0, 0, + 32, 48, 64, 128, 256, 96, 160, 224, 352 }; + + if (gms > ARRAY_SIZE(ggc2uma)) + die("Bad Graphics Mode Select (GMS) setting.\n"); + + return ggc2uma[gms] << 10; +} + +/** Decodes used GTT Graphics Memory Size (GGMS) to kilobytes. */ +u32 decode_igd_gtt_size(const u32 gsm) +{ + static const u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; + + if (gsm > ARRAY_SIZE(ggc2gtt)) + die("Bad GTT Graphics Memory Size (GGMS) setting.\n"); + + return ggc2gtt[gsm] << 10; +} + +u8 decode_pciebar(u32 *const base, u32 *const len) +{ + *base = 0; + *len = 0; + const pci_devfn_t dev = PCI_DEV(0,0,0); + u32 pciexbar = 0; + u32 pciexbar_reg; + u32 reg32; + int max_buses; + const struct { + u16 num_buses; + u32 addr_mask; + } busmask[] = { + {256, 0xf0000000}, + {128, 0xf8000000}, + {64, 0xfc000000}, + {0, 0}, + }; + + pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); + + if (!(pciexbar_reg & 1)) { + printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); + return 0; + } + + reg32 = (pciexbar_reg >> 1) & 3; + pciexbar = pciexbar_reg & busmask[reg32].addr_mask; + max_buses = busmask[reg32].num_buses; + + if (!pciexbar) { + printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); + return 0; + } + + *base = pciexbar; + *len = max_buses << 20; + return 1; +} diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h new file mode 100644 index 0000000..89ca931 --- /dev/null +++ b/src/northbridge/intel/x4x/x4x.h @@ -0,0 +1,320 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * 2012 secunet Security Networks AG + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __NORTHBRIDGE_INTEL_X4X_H__ +#define __NORTHBRIDGE_INTEL_X4X_H__ + +#include <northbridge/intel/x4x/iomap.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +/* + * D0:F0 + */ +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PMBASE 0x78 +#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_SMRAM 0x9d +#define D0F0_ESMRAMC 0x9e +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_TOLUD 0xb0 +#define D0F0_GBSM 0xa4 +#define D0F0_BGSM 0xa8 +#define D0F0_TSEG 0xac +#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define D0F0_CAPID0 0xe0 + +/* + * D1:F0 PEG + */ +#define PEG_CAP 0xa2 +#define SLOTCAP 0xb4 +#define PEGLC 0xec +#define D1F0_VCCAP 0x104 +#define D1F0_VC0RCTL 0x114 + +/* + * Graphics frequencies + */ +#define GCFGC_PCIDEV PCI_DEV(0, 2, 0) +#define GCFGC_OFFSET 0xf0 +#define GCFGC_CR_SHIFT 0 +#define GCFGC_CR_MASK (0xf << GCFGC_CR_SHIFT) +#define GCFGC_CS_SHIFT 8 +#define GCFGC_CS_MASK (0xf << GCFGC_CS_SHIFT) +#define GCFGC_CD_SHIFT 12 +#define GCFGC_CD_MASK (0x1 << GCFGC_CD_SHIFT) +#define GCFGC_UPDATE_SHIFT 5 +#define GCFGC_UPDATE (0x1 << GCFGC_UPDATE_SHIFT) + +/* + * MCHBAR + */ + +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) + +#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ +#define PMSTS_WARM_RESET (1 << 1) +#define PMSTS_BOTH_SELFREFRESH (1 << 0) + +#define CLKCFG_MCHBAR 0x0c00 +#define CLKCFG_FSBCLK_SHIFT 0 +#define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT) +#define CLKCFG_MEMCLK_SHIFT 4 +#define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT) +#define CLKCFG_UPDATE (1 << 12) + +#define SSKPD_MCHBAR 0x0c1c +#define SSKPD_CLK_SHIFT 0 +#define SSKPD_CLK_MASK (7 << SSKPD_CLK_SHIFT) + +/* + * DMIBAR + */ + +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) + +#define DMIVC0RCTL 0x14 +#define DMIVC1RCTL 0x20 +#define DMIVC1RSTS 0x26 +#define DMIESD 0x44 +#define DMILE1D 0x50 +#define DMILE1A 0x58 +#define DMILE2D 0x60 +#define DMILE2A 0x68 + +/* + * EPBAR + */ + +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) + +#define EPESD 0x44 +#define EPLE1D 0x50 +#define EPLE1A 0x58 +#define EPLE2D 0x60 + +#define NOP_CMD 0x2 +#define PRECHARGE_CMD 0x4 +#define MRS_CMD 0x6 +#define EMRS_CMD 0x8 +#define EMRS1_CMD (EMRS_CMD | 0x10) +#define EMRS2_CMD (EMRS_CMD | 0x20) +#define EMRS3_CMD (EMRS_CMD | 0x30) +#define ZQCAL_CMD 0xa +#define CBR_CMD 0xc +#define NORMALOP_CMD 0xe + +#define TOTAL_CHANNELS 2 +#define TOTAL_DIMMS 4 + +#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) +#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != 0) +#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ + !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) +#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \ + !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2))) +#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))) +#define FOR_EACH_DIMM(idx) \ + for (idx = 0; idx < TOTAL_DIMMS; ++idx) +#define FOR_EACH_POPULATED_DIMM(dimms, idx) \ + FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) +#define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0)) +#define CHANNEL_IS_CARDF(dimms, idx) ((dimms[idx<<1].card_type == 0xf) || (dimms[(idx<<1) + 1].card_type == 0xf)) +#define IF_CHANNEL_POPULATED(dimms, idx) if ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0)) +#define FOR_EACH_CHANNEL(idx) \ + for (idx = 0; idx < TOTAL_CHANNELS; ++idx) +#define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ + FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx) + +#define RANKS_PER_CHANNEL 4 +#define RANK_IS_POPULATED(dimms, ch, r) \ + ((dimms[ch<<1].card_type && ((r) < dimms[ch<<1].ranks)) || \ + (dimms[(ch<<1) + 1].card_type && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) +#define IF_RANK_POPULATED(dimms, ch, r) \ + if ((dimms[ch<<1].card_type && ((r) < dimms[ch<<1].ranks)) || \ + (dimms[(ch<<1) + 1].card_type && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) +#define FOR_EACH_RANK_IN_CHANNEL(r) \ + for (r = 0; r < RANKS_PER_CHANNEL; ++r) +#define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \ + FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r) +#define FOR_EACH_RANK(ch, r) \ + FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r) +#define FOR_EACH_POPULATED_RANK(dimms, ch, r) \ + FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r) + +#define DDR3_MAX_CAS 18 + +enum fsb_clock { + FSB_CLOCK_800MHz = 0, + FSB_CLOCK_1066MHz = 1, + FSB_CLOCK_1333MHz = 2, +}; + +enum mem_clock { + MEM_CLOCK_400MHz = 0, + MEM_CLOCK_533MHz = 1, + MEM_CLOCK_667MHz = 2, + MEM_CLOCK_800MHz = 3, + MEM_CLOCK_1066MHz = 4, + MEM_CLOCK_1333MHz = 5, +}; + +enum ddr { + DDR2 = 2, + DDR3 = 3, +}; + +enum ddrxspd { + DDR2SPD = 0x8, + DDR3SPD = 0xb, +}; + +enum chip_width { /* as in DDR3 spd */ + CHIP_WIDTH_x4 = 0, + CHIP_WIDTH_x8 = 1, + CHIP_WIDTH_x16 = 2, + CHIP_WIDTH_x32 = 3, +}; + +enum chip_cap { /* as in DDR3 spd */ + CHIP_CAP_256M = 0, + CHIP_CAP_512M = 1, + CHIP_CAP_1G = 2, + CHIP_CAP_2G = 3, + CHIP_CAP_4G = 4, + CHIP_CAP_8G = 5, + CHIP_CAP_16G = 6, +}; + +struct timings { + unsigned int CAS; + enum fsb_clock fsb_clk; + enum mem_clock mem_clk; + unsigned int tRAS; + unsigned int tRP; + unsigned int tRCD; + unsigned int tWR; + unsigned int tRFC; + unsigned int tWTR; + unsigned int tRRD; + unsigned int tRTP; +}; + +struct dimminfo { + unsigned int card_type; /* 0x0: unpopulated, + 0xa - 0xf: raw card type A - F */ + enum chip_width width; + enum chip_cap chip_capacity; + unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ + unsigned int sides; + unsigned int banks; + unsigned int ranks; + unsigned int rows; + unsigned int cols; + unsigned int cas_latencies; + unsigned int tAAmin; + unsigned int tCKmin; + unsigned int tWR; + unsigned int tRP; + unsigned int tRCD; + unsigned int tRAS; + unsigned int rank_capacity_mb; /* per rank in Mega Bytes */ + u8 spd_data[256]; +}; + +/* The setup is up to two DIMMs per channel */ +struct sysinfo { + int txt_enabled; + int cores; + int boot_path; + int max_ddr2_mhz; + int max_ddr3_mt; + enum fsb_clock max_fsb; + int max_fsb_mhz; + int max_render_mhz; + int enable_igd; + int enable_peg; + u16 ggc; + + int dimm_config[2]; + int dimms_per_ch; + int spd_type; + int channel_capacity[2]; + struct timings selected_timings; + struct dimminfo dimms[4]; + u8 spd_map[4]; +}; + +enum ddr2_signals { + CLKSET0 = 0, + CTRL0, + CLKSET1, + CMD, + CTRL1, + CTRL2, + CTRL3, + DQS1, + DQS2, + DQS3, + DQS4, + DQS5, + DQS6, + DQS7, + DQS8, + DQ1, + DQ2, + DQ3, + DQ4, + DQ5, + DQ6, + DQ7, + DQ8 +}; + +void x4x_early_init(void); +u32 decode_igd_memory_size(u32 gms); +u32 decode_igd_gtt_size(u32 gsm); +u8 decode_pciebar(u32 *const base, u32 *const len); +void sdram_initialize(int boot_path, const u8 *spd_map); +void raminit_ddr2(struct sysinfo *); + +struct acpi_rsdp; +unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); + +#endif /* __NORTHBRIDGE_INTEL_X4X_H__ */

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New patch to review for coreboot: genbuild_h.sh: Get current rev for git revision, not origin/master
by Martin Roth 27 Dec '15

27 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12807 -gerrit commit d990807636d8a6410aa900f2954fb965e3cad361 Author: Martin Roth <martinroth(a)google.com> Date: Sat Dec 26 19:55:31 2015 -0700 genbuild_h.sh: Get current rev for git revision, not origin/master Using origin/master as the git revision breaks reproducibility, giving different values depending on when the code was pulled from the repo at coreboot.org. By using the current revision instead, we get identical builds. Change-Id: If4be6e048d6c8e417b8c074199745900ccd82b49 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/genbuild_h/genbuild_h.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index 0fac0d0..4c8f602 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -25,7 +25,7 @@ export TZ=UTC top=`dirname $0`/../.. if [ -d "${top}/.git" -a -x "$(command -v git)" ]; then - GITREV=$(LANG= git log remotes/origin/master -1 --format=format:%h) + GITREV=$(LANG= git log -1 --format=format:%h) TIMESOURCE=git DATE=$(git log --pretty=format:%ct -1) else

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Patch set updated for coreboot: broadwell: Fix CONFIG_SPI_CONSOLE usage
by Duncan Laurie 27 Dec '15

27 Dec '15

Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12792 -gerrit commit 9a162de846ded577786a7eb413c0823ffb0df12b Author: Duncan Laurie <dlaurie(a)google.com> Date: Tue Dec 22 17:08:21 2015 -0800 broadwell: Fix CONFIG_SPI_CONSOLE usage Locking down the SPI controller with a specific opcode menu kills the SPI console. Skip this when the SPI console config option is enabled. This was tested using an em100 and google/samus board to ensure the console output does not stop at the finalize step. Change-Id: Ie460f583214b47544e92d4afa8ef862563a11e36 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/soc/intel/broadwell/finalize.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 15bd03c..9645348 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -56,6 +56,7 @@ const struct reg_script system_agent_finalize_script[] = { }; const struct reg_script pch_finalize_script[] = { +#if !IS_ENABLED(CONFIG_SPI_CONSOLE) /* Set SPI opcode menu */ REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP, SPI_OPPREFIX), @@ -69,6 +70,7 @@ const struct reg_script pch_finalize_script[] = { /* Lock SPIBAR */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, SPIBAR_HSFS_FLOCKDN), +#endif /* TC Lockdown */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)),

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Patch set updated for coreboot: broadwell: Fix SATA Gen3 DTLE configuration registers
by Duncan Laurie 27 Dec '15

27 Dec '15

Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12793 -gerrit commit 38bdcdcd834537107ed2f01b3105ada31204ff57 Author: Duncan Laurie <dlaurie(a)google.com> Date: Tue Dec 22 17:09:16 2015 -0800 broadwell: Fix SATA Gen3 DTLE configuration registers The port0 and port1 registers were swapped, which meant it did not work to apply the DTLE settings to the correct SATA port. This was tested on an unreleased mainboard but is verified with the documentation to be the correct register addresses now. Change-Id: Ifb8890a563a741129ec8ddf72e73ab021c7d33da Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/soc/intel/broadwell/include/soc/sata.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/broadwell/include/soc/sata.h b/src/soc/intel/broadwell/include/soc/sata.h index 987bc3c..d1aa45d 100644 --- a/src/soc/intel/broadwell/include/soc/sata.h +++ b/src/soc/intel/broadwell/include/soc/sata.h @@ -27,10 +27,10 @@ #define SATA_SECRT88_VADJ_MASK 0xff #define SATA_SECRT88_VADJ_SHIFT 16 -#define SATA_IOBP_SP0DTLE_DATA 0xea002550 -#define SATA_IOBP_SP0DTLE_EDGE 0xea002554 -#define SATA_IOBP_SP1DTLE_DATA 0xea002750 -#define SATA_IOBP_SP1DTLE_EDGE 0xea002754 +#define SATA_IOBP_SP0DTLE_DATA 0xea002750 +#define SATA_IOBP_SP0DTLE_EDGE 0xea002754 +#define SATA_IOBP_SP1DTLE_DATA 0xea002550 +#define SATA_IOBP_SP1DTLE_EDGE 0xea002554 #define SATA_DTLE_MASK 0xF #define SATA_DTLE_DATA_SHIFT 24

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Patch set updated for coreboot: soc/intel/broadwell: Add back support for EHCI debug setup
by Duncan Laurie 27 Dec '15

27 Dec '15

Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12794 -gerrit commit bcf5e4637ebb5b921b4d81334b440717cf3eb2e3 Author: Duncan Laurie <dlaurie(a)google.com> Date: Tue Dec 22 17:15:29 2015 -0800 soc/intel/broadwell: Add back support for EHCI debug setup The EHCI debug device setup code was removed from broadwell in commit 49ee5ef: http://review.coreboot.org/11874 However the generic device setup code is in the southbridge/common/intel directory while broadwell is in the soc directory so this is not used. Add it back to the broadwell soc to fix undefined reference compile errors with 'pci_ehci_dbg_dev' and 'pci_ehci_dbg_enable'. This was tested to compile and produce romstage and ramstage output on a google/samus board. Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/soc/intel/broadwell/Makefile.inc | 2 ++ src/soc/intel/broadwell/usb_debug.c | 59 ++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index e10704b..4da8c20 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -60,6 +60,8 @@ ramstage-y += systemagent.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-y += tsc_freq.c +romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c +ramstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-y += ehci.c ramstage-y += xhci.c smm-y += xhci.c diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/usb_debug.c new file mode 100644 index 0000000..fffebf0 --- /dev/null +++ b/src/soc/intel/broadwell/usb_debug.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ehci.h> +#include <device/pci_def.h> + +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + u32 class; + pci_devfn_t dev = PCI_DEV(0, 0x1d, 0); + + class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; + if (class != PCI_EHCI_CLASSCODE) + return 0; + + return dev; +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +{ + /* Hardcoded to physical port 1 */ +} + +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) +{ + u32 tmp32; + + if (!dev) + return; + + /* Set the EHCI BAR address. */ + pci_write_config32(dev, EHCI_BAR_INDEX, base); + + /* Enable access to the EHCI memory space registers. */ + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + + /* Force ownership of hte Debug Port to the EHCI controller. */ + tmp32 = read32((void *)(base + CONFIG_EHCI_DEBUG_OFFSET)); + tmp32 |= (1 << 30); + write32((void *)(base + CONFIG_EHCI_DEBUG_OFFSET), tmp32); +}

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coreboot-gerrit December 2015