coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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752 discussions

Patch set updated for coreboot: lenovo/x200: Revise onboard IRQ routing
by Nico Huber 30 Dec '15

30 Dec '15

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12813 -gerrit commit 0688122cff40e62cad04bed970b27625aa9a7325 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Dec 29 23:35:37 2015 +0100 lenovo/x200: Revise onboard IRQ routing All southbridge interrupt pin and routing registers (D*IP and D*IR) are left at their default values (see ICH9 datasheet) and this file just has to reflect them. Change-Id: I687262556d918311757fda9afda9ebfdd7edf947 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl index 4a9ede8..aefdf94 100644 --- a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl +++ b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl @@ -28,6 +28,8 @@ Method(_PRT) Package() { 0x0001ffff, 0, 0, 16 }, // Onboard graphics (IGD) 0:2.0 Package() { 0x0002ffff, 0, 0, 16 }, + // Onboard GbE + Package() { 0x0019ffff, 0, 0, 16 }, // USB and EHCI 0:1a.x Package() { 0x001affff, 0, 0, 16 }, Package() { 0x001affff, 1, 0, 17 }, @@ -36,16 +38,14 @@ Method(_PRT) Package() { 0x001bffff, 0, 0, 16 }, // PCIe Root Ports 0:1c.x Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, // USB and EHCI 0:1d.x Package() { 0x001dffff, 0, 0, 16 }, Package() { 0x001dffff, 1, 0, 17 }, Package() { 0x001dffff, 2, 0, 18 }, - // FIXME - // CardBus/IEEE1394 0:1e.2, 0:1e.3 - // Package() { 0x001effff, 0, 0, 22 }, - // Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 16 }, + // LPC bridge sub devices 0:1f.x Package() { 0x001fffff, 1, 0, 17 }, Package() { 0x001fffff, 2, 0, 18 } }) @@ -55,6 +55,8 @@ Method(_PRT) Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // Onboard graphics (IGD) 0:2.0 Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard GbE + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB and EHCI 0:1a.x Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, @@ -63,16 +65,14 @@ Method(_PRT) Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // PCIe Root Ports 0:1c.x Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB and EHCI 0:1d.x Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - // FIXME - // CardBus/IEEE1394 0:1e.2, 0:1e.3 - // Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // LPC bridge sub devices 0:1f.x Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 } })

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Patch set updated for coreboot: nb/intel/gm45: Export low-power and (SFF) options
by Nico Huber 30 Dec '15

30 Dec '15

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12814 -gerrit commit 21981324ed5676c1dfd131031526dc20e49a978e Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Dec 30 00:17:27 2015 +0100 nb/intel/gm45: Export low-power and (SFF) options Make the low-power and small form factor (SFF) options overridable from romstage main. Also disable both options by default. That's ok as there aren't yet any in-tree users of the GS45 chipset. As a nice side-effect, this adds X200s support to the lenovo/x200 port. Change-Id: I94373851262e6d424cf4885ceca7260c31bc9f61 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/intel/gm45/gm45.h | 4 +++- src/northbridge/intel/gm45/raminit.c | 13 ++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index ded2dbf..c018321 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -130,7 +130,6 @@ typedef struct { int txt_enabled; int cores; gmch_gfx_t gfx_type; - int gs45_low_power_mode; /* low power mode of GMCH_GS45 */ int max_ddr2_mhz; int max_ddr3_mt; fsb_clock_t max_fsb; @@ -140,10 +139,13 @@ typedef struct { int enable_peg; u16 ggc; + /* to be filled in romstage main: */ int spd_type; timings_t selected_timings; dimminfo_t dimms[2]; u8 spd_map[4]; + int gs45_low_power_mode; /* low power mode of GMCH_GS45 */ + int sff; /* small form factor option (soldered down DIMM) */ } sysinfo_t; #define TOTAL_CHANNELS 2 #define CHANNEL_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index d4d00de..ab54abc 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -80,7 +80,6 @@ void get_gmch_info(sysinfo_t *sysinfo) sysinfo->gfx_type = gmch_gfx_types[gfx_variant][render_freq]; else sysinfo->gfx_type = GMCH_UNKNOWN; - sysinfo->gs45_low_power_mode = 0; switch (sysinfo->gfx_type) { case GMCH_GM45: printk(BIOS_SPEW, "GMCH: GM45\n"); @@ -104,8 +103,8 @@ void get_gmch_info(sysinfo_t *sysinfo) printk(BIOS_SPEW, "GMCH: GS40\n"); break; case GMCH_GS45: - printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n"); - sysinfo->gs45_low_power_mode = 1; + printk(BIOS_SPEW, "GMCH: GS45, using %s-power mode\n", + sysinfo->gs45_low_power_mode ? "low" : "high"); break; case GMCH_PM45: printk(BIOS_SPEW, "GMCH: PM45\n"); @@ -1688,7 +1687,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) { const dimminfo_t *const dimms = sysinfo->dimms; const timings_t *const timings = &sysinfo->selected_timings; - const int sff = sysinfo->gfx_type == GMCH_GS45; int ch; u8 reg8; @@ -1730,7 +1728,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) configure_dram_control_mode(timings, dimms); /* Initialize RCOMP. */ - rcomp_initialization(sysinfo->stepping, sff); + rcomp_initialization(sysinfo->stepping, sysinfo->sff); /* Power-up DRAM. */ dram_powerup(s3resume); @@ -1743,7 +1741,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) MCHBAR32(CxDCLKDIS_MCHBAR(ch)) |= CxDCLKDIS_ENABLE; /* Enable On-Die Termination. */ - odt_setup(timings, sff); + odt_setup(timings, sysinfo->sff); /* Miscellaneous settings. */ misc_settings(timings, sysinfo->stepping); /* Program clock crossing registers. */ @@ -1751,7 +1749,8 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Program egress VC1 timings. */ vc1_program_timings(timings->fsb_clock); /* Perform system-memory i/o initialization. */ - memory_io_init(timings->mem_clock, dimms, sysinfo->stepping, sff); + memory_io_init(timings->mem_clock, dimms, + sysinfo->stepping, sysinfo->sff); /* Initialize memory map with dummy values of 128MB per rank with a page size of 4KB. This makes the JEDEC initialization code easier. */

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Patch set updated for coreboot: lenovo/x200: Revise onboard IRQ routing
by Nico Huber 30 Dec '15

30 Dec '15

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12813 -gerrit commit 6c78d559e587cc7dda6388564a254e864ce0eb26 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Dec 29 23:35:37 2015 +0100 lenovo/x200: Revise onboard IRQ routing All southbridge interrupt pin and routing registers (D*IP and D*IR) are left at their default values (see ICH9 datasheet) and this file just has to reflect them. Change-Id: I687262556d918311757fda9afda9ebfdd7edf947 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- 3rdparty/blobs | 2 +- src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl | 24 ++++++++++++------------ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index b0eeddd..aab093f 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit b0eeddd4f5c583818e66521f2552cd3448b357b2 +Subproject commit aab093f0824b6d26b57a1ce220ba0d577e37ad49 diff --git a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl index 4a9ede8..aefdf94 100644 --- a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl +++ b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl @@ -28,6 +28,8 @@ Method(_PRT) Package() { 0x0001ffff, 0, 0, 16 }, // Onboard graphics (IGD) 0:2.0 Package() { 0x0002ffff, 0, 0, 16 }, + // Onboard GbE + Package() { 0x0019ffff, 0, 0, 16 }, // USB and EHCI 0:1a.x Package() { 0x001affff, 0, 0, 16 }, Package() { 0x001affff, 1, 0, 17 }, @@ -36,16 +38,14 @@ Method(_PRT) Package() { 0x001bffff, 0, 0, 16 }, // PCIe Root Ports 0:1c.x Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, // USB and EHCI 0:1d.x Package() { 0x001dffff, 0, 0, 16 }, Package() { 0x001dffff, 1, 0, 17 }, Package() { 0x001dffff, 2, 0, 18 }, - // FIXME - // CardBus/IEEE1394 0:1e.2, 0:1e.3 - // Package() { 0x001effff, 0, 0, 22 }, - // Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 16 }, + // LPC bridge sub devices 0:1f.x Package() { 0x001fffff, 1, 0, 17 }, Package() { 0x001fffff, 2, 0, 18 } }) @@ -55,6 +55,8 @@ Method(_PRT) Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // Onboard graphics (IGD) 0:2.0 Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard GbE + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB and EHCI 0:1a.x Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, @@ -63,16 +65,14 @@ Method(_PRT) Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // PCIe Root Ports 0:1c.x Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB and EHCI 0:1d.x Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - // FIXME - // CardBus/IEEE1394 0:1e.2, 0:1e.3 - // Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // LPC bridge sub devices 0:1f.x Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 } })

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Patch set updated for coreboot: nb/intel/gm45: Export low-power and (SFF) options
by Nico Huber 30 Dec '15

30 Dec '15

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12814 -gerrit commit 6ee72cecdf64dc9013e79a0969e4c7a97c50f0c5 Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Dec 30 00:17:27 2015 +0100 nb/intel/gm45: Export low-power and (SFF) options Make the low-power and small form factor (SFF) options overridable from romstage main. Also disable both options by default. That's ok as there aren't yet any in-tree users of the GS45 chipset. As a nice side-effect, this adds X200s support to the lenovo/x200 port. Change-Id: I94373851262e6d424cf4885ceca7260c31bc9f61 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/intel/gm45/gm45.h | 4 +++- src/northbridge/intel/gm45/raminit.c | 13 ++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index ded2dbf..c018321 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -130,7 +130,6 @@ typedef struct { int txt_enabled; int cores; gmch_gfx_t gfx_type; - int gs45_low_power_mode; /* low power mode of GMCH_GS45 */ int max_ddr2_mhz; int max_ddr3_mt; fsb_clock_t max_fsb; @@ -140,10 +139,13 @@ typedef struct { int enable_peg; u16 ggc; + /* to be filled in romstage main: */ int spd_type; timings_t selected_timings; dimminfo_t dimms[2]; u8 spd_map[4]; + int gs45_low_power_mode; /* low power mode of GMCH_GS45 */ + int sff; /* small form factor option (soldered down DIMM) */ } sysinfo_t; #define TOTAL_CHANNELS 2 #define CHANNEL_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index d4d00de..ab54abc 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -80,7 +80,6 @@ void get_gmch_info(sysinfo_t *sysinfo) sysinfo->gfx_type = gmch_gfx_types[gfx_variant][render_freq]; else sysinfo->gfx_type = GMCH_UNKNOWN; - sysinfo->gs45_low_power_mode = 0; switch (sysinfo->gfx_type) { case GMCH_GM45: printk(BIOS_SPEW, "GMCH: GM45\n"); @@ -104,8 +103,8 @@ void get_gmch_info(sysinfo_t *sysinfo) printk(BIOS_SPEW, "GMCH: GS40\n"); break; case GMCH_GS45: - printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n"); - sysinfo->gs45_low_power_mode = 1; + printk(BIOS_SPEW, "GMCH: GS45, using %s-power mode\n", + sysinfo->gs45_low_power_mode ? "low" : "high"); break; case GMCH_PM45: printk(BIOS_SPEW, "GMCH: PM45\n"); @@ -1688,7 +1687,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) { const dimminfo_t *const dimms = sysinfo->dimms; const timings_t *const timings = &sysinfo->selected_timings; - const int sff = sysinfo->gfx_type == GMCH_GS45; int ch; u8 reg8; @@ -1730,7 +1728,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) configure_dram_control_mode(timings, dimms); /* Initialize RCOMP. */ - rcomp_initialization(sysinfo->stepping, sff); + rcomp_initialization(sysinfo->stepping, sysinfo->sff); /* Power-up DRAM. */ dram_powerup(s3resume); @@ -1743,7 +1741,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) MCHBAR32(CxDCLKDIS_MCHBAR(ch)) |= CxDCLKDIS_ENABLE; /* Enable On-Die Termination. */ - odt_setup(timings, sff); + odt_setup(timings, sysinfo->sff); /* Miscellaneous settings. */ misc_settings(timings, sysinfo->stepping); /* Program clock crossing registers. */ @@ -1751,7 +1749,8 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Program egress VC1 timings. */ vc1_program_timings(timings->fsb_clock); /* Perform system-memory i/o initialization. */ - memory_io_init(timings->mem_clock, dimms, sysinfo->stepping, sff); + memory_io_init(timings->mem_clock, dimms, + sysinfo->stepping, sysinfo->sff); /* Initialize memory map with dummy values of 128MB per rank with a page size of 4KB. This makes the JEDEC initialization code easier. */

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New patch to review for coreboot: nb/intel/gm45: Export low-power and (SFF) options
by Nico Huber 30 Dec '15

30 Dec '15

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12814 -gerrit commit 14bfab7162c0f1648316cd189bde530c286d3096 Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Dec 30 00:17:27 2015 +0100 nb/intel/gm45: Export low-power and (SFF) options Make the low-power and small form factor (SFF) options overridable from romstage main. Also disable both options by default. That's ok as there aren't yet any in-tree users of the GS45 chipset. As a nice side-effect, this adds X200s support to the lenovo/x200 port. Change-Id: I94373851262e6d424cf4885ceca7260c31bc9f61 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/intel/gm45/gm45.h | 4 +++- src/northbridge/intel/gm45/raminit.c | 13 ++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index ded2dbf..c018321 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -130,7 +130,6 @@ typedef struct { int txt_enabled; int cores; gmch_gfx_t gfx_type; - int gs45_low_power_mode; /* low power mode of GMCH_GS45 */ int max_ddr2_mhz; int max_ddr3_mt; fsb_clock_t max_fsb; @@ -140,10 +139,13 @@ typedef struct { int enable_peg; u16 ggc; + /* to be filled in romstage main: */ int spd_type; timings_t selected_timings; dimminfo_t dimms[2]; u8 spd_map[4]; + int gs45_low_power_mode; /* low power mode of GMCH_GS45 */ + int sff; /* small form factor option (soldered down DIMM) */ } sysinfo_t; #define TOTAL_CHANNELS 2 #define CHANNEL_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index d4d00de..ab54abc 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -80,7 +80,6 @@ void get_gmch_info(sysinfo_t *sysinfo) sysinfo->gfx_type = gmch_gfx_types[gfx_variant][render_freq]; else sysinfo->gfx_type = GMCH_UNKNOWN; - sysinfo->gs45_low_power_mode = 0; switch (sysinfo->gfx_type) { case GMCH_GM45: printk(BIOS_SPEW, "GMCH: GM45\n"); @@ -104,8 +103,8 @@ void get_gmch_info(sysinfo_t *sysinfo) printk(BIOS_SPEW, "GMCH: GS40\n"); break; case GMCH_GS45: - printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n"); - sysinfo->gs45_low_power_mode = 1; + printk(BIOS_SPEW, "GMCH: GS45, using %s-power mode\n", + sysinfo->gs45_low_power_mode ? "low" : "high"); break; case GMCH_PM45: printk(BIOS_SPEW, "GMCH: PM45\n"); @@ -1688,7 +1687,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) { const dimminfo_t *const dimms = sysinfo->dimms; const timings_t *const timings = &sysinfo->selected_timings; - const int sff = sysinfo->gfx_type == GMCH_GS45; int ch; u8 reg8; @@ -1730,7 +1728,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) configure_dram_control_mode(timings, dimms); /* Initialize RCOMP. */ - rcomp_initialization(sysinfo->stepping, sff); + rcomp_initialization(sysinfo->stepping, sysinfo->sff); /* Power-up DRAM. */ dram_powerup(s3resume); @@ -1743,7 +1741,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) MCHBAR32(CxDCLKDIS_MCHBAR(ch)) |= CxDCLKDIS_ENABLE; /* Enable On-Die Termination. */ - odt_setup(timings, sff); + odt_setup(timings, sysinfo->sff); /* Miscellaneous settings. */ misc_settings(timings, sysinfo->stepping); /* Program clock crossing registers. */ @@ -1751,7 +1749,8 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Program egress VC1 timings. */ vc1_program_timings(timings->fsb_clock); /* Perform system-memory i/o initialization. */ - memory_io_init(timings->mem_clock, dimms, sysinfo->stepping, sff); + memory_io_init(timings->mem_clock, dimms, + sysinfo->stepping, sysinfo->sff); /* Initialize memory map with dummy values of 128MB per rank with a page size of 4KB. This makes the JEDEC initialization code easier. */

1 0

New patch to review for coreboot: lenovo/x200: Revise onboard IRQ routing
by Nico Huber 30 Dec '15

30 Dec '15

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12813 -gerrit commit f3e0d24d781c0803b9862a0f68b2dd567ce34dea Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Dec 29 23:35:37 2015 +0100 lenovo/x200: Revise onboard IRQ routing All southbridge interrupt pin and routing registers (D*IP and D*IR) are left at their default values (see ICH9 datasheet) and this file just has to reflect them. Change-Id: I687262556d918311757fda9afda9ebfdd7edf947 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- 3rdparty/blobs | 2 +- src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl | 24 ++++++++++++------------ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index b0eeddd..aab093f 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit b0eeddd4f5c583818e66521f2552cd3448b357b2 +Subproject commit aab093f0824b6d26b57a1ce220ba0d577e37ad49 diff --git a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl index 4a9ede8..aefdf94 100644 --- a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl +++ b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl @@ -28,6 +28,8 @@ Method(_PRT) Package() { 0x0001ffff, 0, 0, 16 }, // Onboard graphics (IGD) 0:2.0 Package() { 0x0002ffff, 0, 0, 16 }, + // Onboard GbE + Package() { 0x0019ffff, 0, 0, 16 }, // USB and EHCI 0:1a.x Package() { 0x001affff, 0, 0, 16 }, Package() { 0x001affff, 1, 0, 17 }, @@ -36,16 +38,14 @@ Method(_PRT) Package() { 0x001bffff, 0, 0, 16 }, // PCIe Root Ports 0:1c.x Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, // USB and EHCI 0:1d.x Package() { 0x001dffff, 0, 0, 16 }, Package() { 0x001dffff, 1, 0, 17 }, Package() { 0x001dffff, 2, 0, 18 }, - // FIXME - // CardBus/IEEE1394 0:1e.2, 0:1e.3 - // Package() { 0x001effff, 0, 0, 22 }, - // Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 16 }, + // LPC bridge sub devices 0:1f.x Package() { 0x001fffff, 1, 0, 17 }, Package() { 0x001fffff, 2, 0, 18 } }) @@ -55,6 +55,8 @@ Method(_PRT) Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // Onboard graphics (IGD) 0:2.0 Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard GbE + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB and EHCI 0:1a.x Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, @@ -63,16 +65,14 @@ Method(_PRT) Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // PCIe Root Ports 0:1c.x Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB and EHCI 0:1d.x Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - // FIXME - // CardBus/IEEE1394 0:1e.2, 0:1e.3 - // Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // LPC bridge sub devices 0:1f.x Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 } })

1 0

Patch set updated for coreboot: x86 chipsets: Link non-code flow CHIPSET_BOOTBLOCK_INCLUDE files
by Alexandru Gagniuc 30 Dec '15

30 Dec '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11856 -gerrit commit 91892b662a7fe11dc92e60eaeb9479bcd4ddefc8 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Oct 5 08:00:51 2015 -0700 x86 chipsets: Link non-code flow CHIPSET_BOOTBLOCK_INCLUDE files Non-code flow assembly stubs do not have to be included in bootblock.S, now that we have more freedom in bootblock linking. Rather than bringing these stubs to the config system, just link them in the bootblock. Note that we cannot fully remove CHIPSET_BOOTBLOCK_INCLUDE at this point, as some intel SOCs use this stub for code flow. objdump -h build/cbfs/fallback/bootblock.debug on a few random boards confirms that the appropriate sections are still included in the final binary. Change-Id: Id3f9ece14e399c1cc83090f407780c4a05a076f0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/dmp/vortex86ex/Kconfig | 4 - src/cpu/dmp/vortex86ex/Makefile.inc | 2 + src/cpu/dmp/vortex86ex/biosdata.S | 80 +++++++++++++ src/cpu/dmp/vortex86ex/biosdata.inc | 80 ------------- src/cpu/dmp/vortex86ex/biosdata_ex.S | 172 +++++++++++++++++++++++++++ src/cpu/dmp/vortex86ex/biosdata_ex.inc | 172 --------------------------- src/cpu/dmp/vortex86ex/chipset_bootblock.inc | 2 - src/northbridge/via/vx800/Kconfig | 8 -- src/northbridge/via/vx800/Makefile.inc | 1 + src/northbridge/via/vx800/romstrap.S | 47 ++++++++ src/northbridge/via/vx800/romstrap.inc | 47 -------- src/northbridge/via/vx900/Kconfig | 4 - src/northbridge/via/vx900/Makefile.inc | 1 + src/northbridge/via/vx900/romstrap.S | 56 +++++++++ src/northbridge/via/vx900/romstrap.inc | 56 --------- src/southbridge/nvidia/ck804/Kconfig | 4 - src/southbridge/nvidia/ck804/Makefile.inc | 1 + src/southbridge/nvidia/ck804/romstrap.S | 55 +++++++++ src/southbridge/nvidia/ck804/romstrap.inc | 55 --------- src/southbridge/nvidia/mcp55/Kconfig | 4 - src/southbridge/nvidia/mcp55/Makefile.inc | 1 + src/southbridge/nvidia/mcp55/romstrap.S | 55 +++++++++ src/southbridge/nvidia/mcp55/romstrap.inc | 55 --------- src/southbridge/sis/sis966/Kconfig | 4 - src/southbridge/sis/sis966/Makefile.inc | 1 + src/southbridge/sis/sis966/romstrap.S | 62 ++++++++++ src/southbridge/sis/sis966/romstrap.inc | 62 ---------- src/southbridge/via/k8t890/Kconfig | 4 - src/southbridge/via/k8t890/Makefile.inc | 1 + src/southbridge/via/k8t890/romstrap.S | 99 +++++++++++++++ src/southbridge/via/k8t890/romstrap.inc | 99 --------------- 31 files changed, 634 insertions(+), 660 deletions(-) diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index 1f43f76..1af7ec4 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -73,8 +73,4 @@ config PLL_500_375_33 endchoice -config CHIPSET_BOOTBLOCK_INCLUDE - string - default "cpu/dmp/vortex86ex/chipset_bootblock.inc" - endif diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc index 76df34c..6b4d0ba 100644 --- a/src/cpu/dmp/vortex86ex/Makefile.inc +++ b/src/cpu/dmp/vortex86ex/Makefile.inc @@ -21,5 +21,7 @@ subdirs-y += ../../x86/smm bootblock-y += biosdata.ld bootblock-y += biosdata_ex.ld +bootblock-y += biosdata.S +bootblock-y += biosdata_ex.S ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/cpu/dmp/vortex86ex/biosdata.S b/src/cpu/dmp/vortex86ex/biosdata.S new file mode 100644 index 0000000..c08242a --- /dev/null +++ b/src/cpu/dmp/vortex86ex/biosdata.S @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .section ".dmp_reserved", "a", @progbits + + .skip 0x3c000 - 0x3bc00, 0xff + +.previous + + .section ".dmp_kbd_fw_part2", "a", @progbits + + .skip 0x3d000 - 0x3c000, 0xff + +.previous + + .section ".dmp_mtbf_low_cnt", "a", @progbits + + .skip 0x3e000 - 0x3d000, 0xff + +.previous + + .section ".dmp_kbd_fw_part1", "a", @progbits + + #include "dmp_kbd_fw_part1.inc" + +.previous + + .section ".dmp_spi_flash_disk_driver", "a", @progbits + + .skip 0x3f800 - 0x3f000, 0xff + +.previous + + .section ".dmp_frontdoor", "a", @progbits + + .skip 0x3fd00 - 0x3f800, 0xff + +.previous + + .section ".dmp_isoinfo", "a", @progbits + + .skip 26 * 16, 0xff + +.previous + + .section ".dmp_isodata_checksum", "a", @progbits + + .skip 8, 0xff + +.previous + + .section ".dmp_mac", "a", @progbits + + .skip 6, 0xff + +.previous + + .section ".dmp_mtbf_limit", "a", @progbits + + .skip 3, 0xff + +.previous + + .section ".dmp_isodata", "a", @progbits + + .skip 32, 0xff + +.previous diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc deleted file mode 100644 index c08242a..0000000 --- a/src/cpu/dmp/vortex86ex/biosdata.inc +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 DMP Electronics Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".dmp_reserved", "a", @progbits - - .skip 0x3c000 - 0x3bc00, 0xff - -.previous - - .section ".dmp_kbd_fw_part2", "a", @progbits - - .skip 0x3d000 - 0x3c000, 0xff - -.previous - - .section ".dmp_mtbf_low_cnt", "a", @progbits - - .skip 0x3e000 - 0x3d000, 0xff - -.previous - - .section ".dmp_kbd_fw_part1", "a", @progbits - - #include "dmp_kbd_fw_part1.inc" - -.previous - - .section ".dmp_spi_flash_disk_driver", "a", @progbits - - .skip 0x3f800 - 0x3f000, 0xff - -.previous - - .section ".dmp_frontdoor", "a", @progbits - - .skip 0x3fd00 - 0x3f800, 0xff - -.previous - - .section ".dmp_isoinfo", "a", @progbits - - .skip 26 * 16, 0xff - -.previous - - .section ".dmp_isodata_checksum", "a", @progbits - - .skip 8, 0xff - -.previous - - .section ".dmp_mac", "a", @progbits - - .skip 6, 0xff - -.previous - - .section ".dmp_mtbf_limit", "a", @progbits - - .skip 3, 0xff - -.previous - - .section ".dmp_isodata", "a", @progbits - - .skip 32, 0xff - -.previous diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.S b/src/cpu/dmp/vortex86ex/biosdata_ex.S new file mode 100644 index 0000000..5ed17c6 --- /dev/null +++ b/src/cpu/dmp/vortex86ex/biosdata_ex.S @@ -0,0 +1,172 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "config.h" + +/* +PLL Freq = 25 * NS /(MS * 2^RS) +CPU Freq = PLL/(CPU_DIV+2) +DRAM Freq = PLL/2(DRAM_DIV+1) + +DDR3 +CPU/DRAM/PCI B6 B7 BB BC BD BF +200/200/33 30 03 0F 02 8F 07 +300/300/33 48 03 0F 02 1F 07 +300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable +300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable +300/300/100 48 03 23 02 7F 07 +400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing +400/200/100 60 43 23 02 4F 07 +400/400/33 60 03 0F 02 BF 09 +500/250/33 50 42 0F 02 DF 07 +500/500/33 78 03 0F 02 4F 09 +400/300/33 90 53 0F 02 3F 07 +400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable +400/300/100 90 53 23 02 9F 07 +444/333/33 A0 53 0F 02 5F 08 +466/350/33 A8 53 0F 02 DF 09 +500/375/33 B4 53 0F 02 AF 09 +*/ + +#if CONFIG_PLL_200_200_33 + // 200/200/33 30 03 0F 02 8F 07 + byte_fffb6 = 0x30 + byte_fffb7 = 0x03 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_300_300_33 + // 300/300/33 48 03 0F 02 1F 07 + byte_fffb6 = 0x48 + byte_fffb7 = 0x03 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_300_300_100 + // 300/300/100 48 03 23 02 7F 07 + byte_fffb6 = 0x48 + byte_fffb7 = 0x03 + byte_fffbb = 0x23 + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_400_200_33 + // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing + byte_fffb6 = 0x60 + byte_fffb7 = 0x43 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_400_200_100 + // 400/200/100 60 43 23 02 4F 07 + byte_fffb6 = 0x60 + byte_fffb7 = 0x43 + byte_fffbb = 0x23 + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_400_400_33 + // 400/400/33 60 03 0F 02 BF 09 + byte_fffb6 = 0x60 + byte_fffb7 = 0x03 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x09 +#elif CONFIG_PLL_500_250_33 + // 500/250/33 50 42 0F 02 DF 07 + byte_fffb6 = 0x50 + byte_fffb7 = 0x42 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_500_500_33 + // 500/500/33 78 03 0F 02 4F 09 + byte_fffb6 = 0x78 + byte_fffb7 = 0x03 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x09 +#elif CONFIG_PLL_400_300_33 + // 400/300/33 90 53 0F 02 3F 07 + byte_fffb6 = 0x90 + byte_fffb7 = 0x53 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_400_300_100 + // 400/300/100 90 53 23 02 9F 07 + byte_fffb6 = 0x90 + byte_fffb7 = 0x53 + byte_fffbb = 0x23 + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_444_333_33 + // 444/333/33 A0 53 0F 02 5F 08 + byte_fffb6 = 0xa0 + byte_fffb7 = 0x53 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x08 +#elif CONFIG_PLL_466_350_33 + // 466/350/33 A8 53 0F 02 DF 09 + byte_fffb6 = 0xa8 + byte_fffb7 = 0x53 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x09 +#elif CONFIG_PLL_500_375_33 + // 500/375/33 B4 53 0F 02 AF 09 + byte_fffb6 = 0xb4 + byte_fffb7 = 0x53 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x09 +#else + #error Error Strap PLL config. +#endif + +tmp_sum = byte_fffb6 + byte_fffb7 + byte_fffbb + byte_fffbc +pll_checksum = ((tmp_sum >> 8) & 0x3) + ((tmp_sum >> 4) & 0x0f) + (tmp_sum & 0x0f) + +byte_fffbd = ((pll_checksum & 0x0f) << 4) | 0x0f + + .section ".a9123_crossbar_config", "a", @progbits + + .skip 0x3fdf0 - 0x3fd00, 0xff + +.previous + + .section ".a9123_strap_1", "a", @progbits + + .byte byte_fffb6, byte_fffb7 + +.previous + + .section ".a9123_strap_2", "a", @progbits + + .byte byte_fffbb, byte_fffbc, byte_fffbd, byte_fffbe, byte_fffbf + +.previous diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.inc b/src/cpu/dmp/vortex86ex/biosdata_ex.inc deleted file mode 100644 index 5ed17c6..0000000 --- a/src/cpu/dmp/vortex86ex/biosdata_ex.inc +++ /dev/null @@ -1,172 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 DMP Electronics Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "config.h" - -/* -PLL Freq = 25 * NS /(MS * 2^RS) -CPU Freq = PLL/(CPU_DIV+2) -DRAM Freq = PLL/2(DRAM_DIV+1) - -DDR3 -CPU/DRAM/PCI B6 B7 BB BC BD BF -200/200/33 30 03 0F 02 8F 07 -300/300/33 48 03 0F 02 1F 07 -300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable -300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable -300/300/100 48 03 23 02 7F 07 -400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing -400/200/100 60 43 23 02 4F 07 -400/400/33 60 03 0F 02 BF 09 -500/250/33 50 42 0F 02 DF 07 -500/500/33 78 03 0F 02 4F 09 -400/300/33 90 53 0F 02 3F 07 -400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable -400/300/100 90 53 23 02 9F 07 -444/333/33 A0 53 0F 02 5F 08 -466/350/33 A8 53 0F 02 DF 09 -500/375/33 B4 53 0F 02 AF 09 -*/ - -#if CONFIG_PLL_200_200_33 - // 200/200/33 30 03 0F 02 8F 07 - byte_fffb6 = 0x30 - byte_fffb7 = 0x03 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_300_300_33 - // 300/300/33 48 03 0F 02 1F 07 - byte_fffb6 = 0x48 - byte_fffb7 = 0x03 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_300_300_100 - // 300/300/100 48 03 23 02 7F 07 - byte_fffb6 = 0x48 - byte_fffb7 = 0x03 - byte_fffbb = 0x23 - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_400_200_33 - // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing - byte_fffb6 = 0x60 - byte_fffb7 = 0x43 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_400_200_100 - // 400/200/100 60 43 23 02 4F 07 - byte_fffb6 = 0x60 - byte_fffb7 = 0x43 - byte_fffbb = 0x23 - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_400_400_33 - // 400/400/33 60 03 0F 02 BF 09 - byte_fffb6 = 0x60 - byte_fffb7 = 0x03 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x09 -#elif CONFIG_PLL_500_250_33 - // 500/250/33 50 42 0F 02 DF 07 - byte_fffb6 = 0x50 - byte_fffb7 = 0x42 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_500_500_33 - // 500/500/33 78 03 0F 02 4F 09 - byte_fffb6 = 0x78 - byte_fffb7 = 0x03 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x09 -#elif CONFIG_PLL_400_300_33 - // 400/300/33 90 53 0F 02 3F 07 - byte_fffb6 = 0x90 - byte_fffb7 = 0x53 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_400_300_100 - // 400/300/100 90 53 23 02 9F 07 - byte_fffb6 = 0x90 - byte_fffb7 = 0x53 - byte_fffbb = 0x23 - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_444_333_33 - // 444/333/33 A0 53 0F 02 5F 08 - byte_fffb6 = 0xa0 - byte_fffb7 = 0x53 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x08 -#elif CONFIG_PLL_466_350_33 - // 466/350/33 A8 53 0F 02 DF 09 - byte_fffb6 = 0xa8 - byte_fffb7 = 0x53 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x09 -#elif CONFIG_PLL_500_375_33 - // 500/375/33 B4 53 0F 02 AF 09 - byte_fffb6 = 0xb4 - byte_fffb7 = 0x53 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x09 -#else - #error Error Strap PLL config. -#endif - -tmp_sum = byte_fffb6 + byte_fffb7 + byte_fffbb + byte_fffbc -pll_checksum = ((tmp_sum >> 8) & 0x3) + ((tmp_sum >> 4) & 0x0f) + (tmp_sum & 0x0f) - -byte_fffbd = ((pll_checksum & 0x0f) << 4) | 0x0f - - .section ".a9123_crossbar_config", "a", @progbits - - .skip 0x3fdf0 - 0x3fd00, 0xff - -.previous - - .section ".a9123_strap_1", "a", @progbits - - .byte byte_fffb6, byte_fffb7 - -.previous - - .section ".a9123_strap_2", "a", @progbits - - .byte byte_fffbb, byte_fffbc, byte_fffbd, byte_fffbe, byte_fffbf - -.previous diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc deleted file mode 100644 index bdcda1d..0000000 --- a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc +++ /dev/null @@ -1,2 +0,0 @@ -#include "biosdata.inc" -#include "biosdata_ex.inc" diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index d7d5349..9eb84fb 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -3,11 +3,3 @@ config NORTHBRIDGE_VIA_VX800 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select LATE_CBMEM_INIT - -if NORTHBRIDGE_VIA_VX800 - -config CHIPSET_BOOTBLOCK_INCLUDE - string - default "northbridge/via/vx800/romstrap.inc" - -endif diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc index 069ea8e..90574ed 100644 --- a/src/northbridge/via/vx800/Makefile.inc +++ b/src/northbridge/via/vx800/Makefile.inc @@ -22,5 +22,6 @@ ramstage-y += lpc.c ramstage-y += ide.c bootblock-y += romstrap.ld +bootblock-y += romstrap.S endif diff --git a/src/northbridge/via/vx800/romstrap.S b/src/northbridge/via/vx800/romstrap.S new file mode 100644 index 0000000..82b5b4b --- /dev/null +++ b/src/northbridge/via/vx800/romstrap.S @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer) + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file constructs the ROM strap table for K8T890 and K8M890 */ + + .section ".romstrap", "a", @progbits + + .globl __romstrap_start +__romstrap_start: +tblpointer: + .long 0x55aa66cc + .long 0x88012554 + .long 0x77107777 + .long 0x00770814 + + + .long 0x00000000 + .long 0x00000000 + .long 0x00000000 + .long 0x00000000 + +/* + * The pointer to above table should be at 0xffffffd0, + * the table itself MUST be aligned to 128B it seems! + */ +rspointers: + .long tblpointer // It will be 0xffffffd0 + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/northbridge/via/vx800/romstrap.inc b/src/northbridge/via/vx800/romstrap.inc deleted file mode 100644 index 82b5b4b..0000000 --- a/src/northbridge/via/vx800/romstrap.inc +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer) - * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file constructs the ROM strap table for K8T890 and K8M890 */ - - .section ".romstrap", "a", @progbits - - .globl __romstrap_start -__romstrap_start: -tblpointer: - .long 0x55aa66cc - .long 0x88012554 - .long 0x77107777 - .long 0x00770814 - - - .long 0x00000000 - .long 0x00000000 - .long 0x00000000 - .long 0x00000000 - -/* - * The pointer to above table should be at 0xffffffd0, - * the table itself MUST be aligned to 128B it seems! - */ -rspointers: - .long tblpointer // It will be 0xffffffd0 - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index c7641d1..2d2dffa 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -39,8 +39,4 @@ config VGA_BIOS_ID string default "1106,7122" -config CHIPSET_BOOTBLOCK_INCLUDE - string - default "northbridge/via/vx900/romstrap.inc" - endif diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index 4cac1e7..44f0ae0 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -44,5 +44,6 @@ ramstage-y += ./../../../drivers/pc80/vga/vga_io.c bootblock-y += romstrap.ld +bootblock-y += romstrap.S endif diff --git a/src/northbridge/via/vx900/romstrap.S b/src/northbridge/via/vx900/romstrap.S new file mode 100644 index 0000000..26c1ee6 --- /dev/null +++ b/src/northbridge/via/vx900/romstrap.S @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer) + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* As extracted from the manufacturer's ROM, the romstrap table looks like: + * .long 0x77886047 .long 0x00777777 + * .long 0x00000000 .long 0x00000000 + * .long 0x00888888 .long 0x00AA1111 + * .long 0x00000000 .long 0x00000000 + * + * The vendor BIOS then adjusts some of these settings very early on. Instead of + * adjusting those settings in code, we work them in the romstrap table. + * + */ +/* This file constructs the ROM strap table for VX900 */ + + .section ".romstrap", "a", @progbits + + .globl __romstrap_start +__romstrap_start: +tblpointer: + .long 0x77886047 + .long 0x00777777 + .long 0x00000000 + .long 0x00000000 + .long 0x00888888 + .long 0x00AA1111 + .long 0x00000000 + .long 0x00000000 + +/* + * The pointer to above table should be at 0xffffffd0, + * the table itself MUST be aligned to 128B it seems! + */ +rspointers: + .long tblpointer // It will be 0xffffffd0 + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/northbridge/via/vx900/romstrap.inc b/src/northbridge/via/vx900/romstrap.inc deleted file mode 100644 index 26c1ee6..0000000 --- a/src/northbridge/via/vx900/romstrap.inc +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer) - * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* As extracted from the manufacturer's ROM, the romstrap table looks like: - * .long 0x77886047 .long 0x00777777 - * .long 0x00000000 .long 0x00000000 - * .long 0x00888888 .long 0x00AA1111 - * .long 0x00000000 .long 0x00000000 - * - * The vendor BIOS then adjusts some of these settings very early on. Instead of - * adjusting those settings in code, we work them in the romstrap table. - * - */ -/* This file constructs the ROM strap table for VX900 */ - - .section ".romstrap", "a", @progbits - - .globl __romstrap_start -__romstrap_start: -tblpointer: - .long 0x77886047 - .long 0x00777777 - .long 0x00000000 - .long 0x00000000 - .long 0x00888888 - .long 0x00AA1111 - .long 0x00000000 - .long 0x00000000 - -/* - * The pointer to above table should be at 0xffffffd0, - * the table itself MUST be aligned to 128B it seems! - */ -rspointers: - .long tblpointer // It will be 0xffffffd0 - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 42dce07..dbd24b7 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -42,8 +42,4 @@ config HPET_MIN_TICKS hex default 0xfa -config CHIPSET_BOOTBLOCK_INCLUDE - string - default "southbridge/nvidia/ck804/romstrap.inc" - endif diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index 69dd4b2..554a440 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -22,5 +22,6 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c bootblock-y += romstrap.ld +bootblock-y += romstrap.S endif diff --git a/src/southbridge/nvidia/ck804/romstrap.S b/src/southbridge/nvidia/ck804/romstrap.S new file mode 100644 index 0000000..5a20107 --- /dev/null +++ b/src/southbridge/nvidia/ck804/romstrap.S @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .section ".romstrap", "a", @progbits + + + .align 16 + .globl __romstrap_start +__romstrap_start: +rstables: + .long 0x2b16d065 + .long 0x0 + .long 0x0 + .long linkedlist + +linkedlist: + .long 0x0003001C // 10h + .long 0x08000000 // 14h + .long 0x00000000 // 18h + .long 0xFFFFFFFF // 1Ch + + .long 0xFFFFFFFF // 20h + .long 0xFFFFFFFF // 24h + .long 0xFFFFFFFF // 28h + .long 0xFFFFFFFF // 2Ch + + .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 + .long 0x000000E0 // 34h, MAC address high 4 byte + + .long 0x002309CE // 38h, UUID low 4 byte + .long 0x00E08100 // 3Ch, UUID high 4 byte + +rspointers: + .long rstables // It will be 0xffffffe0 + .long rstables + .long rstables + .long rstables + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/southbridge/nvidia/ck804/romstrap.inc b/src/southbridge/nvidia/ck804/romstrap.inc deleted file mode 100644 index 5a20107..0000000 --- a/src/southbridge/nvidia/ck804/romstrap.inc +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".romstrap", "a", @progbits - - - .align 16 - .globl __romstrap_start -__romstrap_start: -rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist - -linkedlist: - .long 0x0003001C // 10h - .long 0x08000000 // 14h - .long 0x00000000 // 18h - .long 0xFFFFFFFF // 1Ch - - .long 0xFFFFFFFF // 20h - .long 0xFFFFFFFF // 24h - .long 0xFFFFFFFF // 28h - .long 0xFFFFFFFF // 2Ch - - .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 - .long 0x000000E0 // 34h, MAC address high 4 byte - - .long 0x002309CE // 38h, UUID low 4 byte - .long 0x00E08100 // 3Ch, UUID high 4 byte - -rspointers: - .long rstables // It will be 0xffffffe0 - .long rstables - .long rstables - .long rstables - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 666d3f8..89aa452 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -42,8 +42,4 @@ config MCP55_PCI_E_X_3 int default 4 -config CHIPSET_BOOTBLOCK_INCLUDE - string - default "southbridge/nvidia/mcp55/romstrap.inc" - endif diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 74ef14c..db275cc 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -25,5 +25,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c endif bootblock-y += romstrap.ld +bootblock-y += romstrap.S endif diff --git a/src/southbridge/nvidia/mcp55/romstrap.S b/src/southbridge/nvidia/mcp55/romstrap.S new file mode 100644 index 0000000..ff170a9 --- /dev/null +++ b/src/southbridge/nvidia/mcp55/romstrap.S @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .section ".romstrap", "a", @progbits + + + .globl __romstrap_start +__romstrap_start: +rstables: + .long 0x2b16d065 + .long 0x0 + .long 0x0 + .long linkedlist + +linkedlist: + .long 0x0003001C // 10h + .long 0x08000000 // 14h + .long 0x00000000 // 18h + .long 0xFFFFFFFF // 1Ch + + .long 0xFFFFFFFF // 20h + .long 0xFFFFFFFF // 24h + .long 0xFFFFFFFF // 28h + .long 0xFFFFFFFF // 2Ch + + .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 + .long 0x000000E0 // 34h, MAC address high 4 byte + + .long 0x002309CE // 38h, UUID low 4 byte + .long 0x00E08100 // 3Ch, UUID high 4 byte + +rspointers: + .long rstables // It will be 0xffffffe0 + .long rstables + .long rstables + .long rstables + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/southbridge/nvidia/mcp55/romstrap.inc b/src/southbridge/nvidia/mcp55/romstrap.inc deleted file mode 100644 index ff170a9..0000000 --- a/src/southbridge/nvidia/mcp55/romstrap.inc +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".romstrap", "a", @progbits - - - .globl __romstrap_start -__romstrap_start: -rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist - -linkedlist: - .long 0x0003001C // 10h - .long 0x08000000 // 14h - .long 0x00000000 // 18h - .long 0xFFFFFFFF // 1Ch - - .long 0xFFFFFFFF // 20h - .long 0xFFFFFFFF // 24h - .long 0xFFFFFFFF // 28h - .long 0xFFFFFFFF // 2Ch - - .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 - .long 0x000000E0 // 34h, MAC address high 4 byte - - .long 0x002309CE // 38h, UUID low 4 byte - .long 0x00E08100 // 3Ch, UUID high 4 byte - -rspointers: - .long rstables // It will be 0xffffffe0 - .long rstables - .long rstables - .long rstables - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 20f3bff..c6023a9 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -14,8 +14,4 @@ config EHCI_BAR hex default 0xfef00000 -config CHIPSET_BOOTBLOCK_INCLUDE - string - default "southbridge/sis/sis966/romstrap.inc" - endif diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index e703e1f..fa37762 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -16,5 +16,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c bootblock-y += romstrap.ld +bootblock-y += romstrap.S endif diff --git a/src/southbridge/sis/sis966/romstrap.S b/src/southbridge/sis/sis966/romstrap.S new file mode 100644 index 0000000..1eb39e3 --- /dev/null +++ b/src/southbridge/sis/sis966/romstrap.S @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) + * Written by Morgan Tsai <my_tsai(a)sis.com> for SiS. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .section ".romstrap", "a", @progbits + + + .globl __romstrap_start +__romstrap_start: +rstables: + .long 0x2b16d065 + .long 0x0 + .long 0x0 + .long linkedlist + +linkedlist: + .long 0x0003001C // 10h + .long 0x08000000 // 14h + .long 0x00000000 // 18h + .long 0xFFFFFFFF // 1Ch + + .long 0xFFFFFFFF // 20h + .long 0xFFFFFFFF // 24h + .long 0xFFFFFFFF // 28h + .long 0xFFFFFFFF // 2Ch + + .long 0x56341200 // 30h, MAC address low 4 byte ---> keep it in 0xffffffc0 + .long 0x00009078 // 34h, MAC address high 4 byte + + .long 0x002309CE // 38h, UUID low 4 byte + .long 0x00E08100 // 3Ch, UUID high 4 byte + + .long 0x00402000 //Firmware trap for SiS761+966 + .long 0xE043A800 + .long 0x00180000 + .long 0x1421C402 + +rspointers: + .long rstables // It will be 0xffffffe0 + .long rstables + .long rstables + .long rstables + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/southbridge/sis/sis966/romstrap.inc b/src/southbridge/sis/sis966/romstrap.inc deleted file mode 100644 index 1eb39e3..0000000 --- a/src/southbridge/sis/sis966/romstrap.inc +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai(a)sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".romstrap", "a", @progbits - - - .globl __romstrap_start -__romstrap_start: -rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist - -linkedlist: - .long 0x0003001C // 10h - .long 0x08000000 // 14h - .long 0x00000000 // 18h - .long 0xFFFFFFFF // 1Ch - - .long 0xFFFFFFFF // 20h - .long 0xFFFFFFFF // 24h - .long 0xFFFFFFFF // 28h - .long 0xFFFFFFFF // 2Ch - - .long 0x56341200 // 30h, MAC address low 4 byte ---> keep it in 0xffffffc0 - .long 0x00009078 // 34h, MAC address high 4 byte - - .long 0x002309CE // 38h, UUID low 4 byte - .long 0x00E08100 // 3Ch, UUID high 4 byte - - .long 0x00402000 //Firmware trap for SiS761+966 - .long 0xE043A800 - .long 0x00180000 - .long 0x1421C402 - -rspointers: - .long rstables // It will be 0xffffffe0 - .long rstables - .long rstables - .long rstables - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index 76be0c1..f6e51dc 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -51,8 +51,4 @@ config VIDEO_MB default -1 if K8M890_VIDEO_MB_CMOS depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN -config CHIPSET_BOOTBLOCK_INCLUDE - string - default "southbridge/via/k8t890/romstrap.inc" - endif # SOUTHBRIDGE_K8T890 diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 2789499..ed6d3ed 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -11,5 +11,6 @@ ramstage-y += error.c ramstage-y += chrome.c bootblock-y += romstrap.ld +bootblock-y += romstrap.S endif diff --git a/src/southbridge/via/k8t890/romstrap.S b/src/southbridge/via/k8t890/romstrap.S new file mode 100644 index 0000000..2115eaa --- /dev/null +++ b/src/southbridge/via/k8t890/romstrap.S @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer) + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file constructs the ROM strap table for K8T890 and K8M890 */ + +.section ".romstrap", "a", @progbits + +.globl __romstrap_start +.globl __romstrap_end + +__romstrap_start: + +/* + * Below are some Dev0 Func2 HT control registers values, + * depending on strap pin, one of below lines is used. + */ +#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD + +tblpointer: +.long 0x50220000, 0X619707C2 +.long 0x50220000, 0X619707C2 +.long 0x50220000, 0X619707C2 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 + +#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 + +tblpointer: +.long 0x504400FF, 0x61970FC2 //;200M +.long 0x504400FF, 0x61970FC2 //;400M +.long 0x504400FF, 0x61970FC2 //;600M +.long 0x504400FF, 0x61970FC2 //;800M +.long 0x504400FF, 0x61970FC2 //;1000M +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 + + +#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890 + +tblpointer: +.long 0x504400AA, 0x61970FC2 //;200M +.long 0x504400AA, 0x61970FC2 //;400M +.long 0x504400AA, 0x61970FC2 //;600M +.long 0x504400AA, 0x61970FC2 //;800M +.long 0x504400AA, 0x61970FC2 //;1000M +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 + +#endif +/* + * The pointer to above table should be at 0xffffd, + * the table itself MUST be aligned to 128B it seems! + */ +.long tblpointer - 0xFFF00000 + +__romstrap_end: + +.previous diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc deleted file mode 100644 index 2115eaa..0000000 --- a/src/southbridge/via/k8t890/romstrap.inc +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer) - * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file constructs the ROM strap table for K8T890 and K8M890 */ - -.section ".romstrap", "a", @progbits - -.globl __romstrap_start -.globl __romstrap_end - -__romstrap_start: - -/* - * Below are some Dev0 Func2 HT control registers values, - * depending on strap pin, one of below lines is used. - */ -#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD - -tblpointer: -.long 0x50220000, 0X619707C2 -.long 0x50220000, 0X619707C2 -.long 0x50220000, 0X619707C2 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 - -#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 - -tblpointer: -.long 0x504400FF, 0x61970FC2 //;200M -.long 0x504400FF, 0x61970FC2 //;400M -.long 0x504400FF, 0x61970FC2 //;600M -.long 0x504400FF, 0x61970FC2 //;800M -.long 0x504400FF, 0x61970FC2 //;1000M -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 - - -#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890 - -tblpointer: -.long 0x504400AA, 0x61970FC2 //;200M -.long 0x504400AA, 0x61970FC2 //;400M -.long 0x504400AA, 0x61970FC2 //;600M -.long 0x504400AA, 0x61970FC2 //;800M -.long 0x504400AA, 0x61970FC2 //;1000M -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 - -#endif -/* - * The pointer to above table should be at 0xffffd, - * the table itself MUST be aligned to 128B it seems! - */ -.long tblpointer - 0xFFF00000 - -__romstrap_end: - -.previous

1 0

New patch to review for coreboot: buildgcc: Add 'g++' and 'clang' to the list of to-be-installed tools
by Marko Käning 29 Dec '15

29 Dec '15

Marko Käning (mk-lists(a)mailbox.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12812 -gerrit commit 69c1a4e276f0451a9fc7b3b446df814d85fbb020 Author: Marko Käning <mk-lists(a)mailbox.org> Date: Tue Dec 29 23:53:04 2015 +0100 buildgcc: Add 'g++' and 'clang' to the list of to-be-installed tools Change-Id: I1f9c435293f7ad4ea82f6b08dfdc6c10c0494e35 Signed-off-by: Marko Käning <mk-lists(a)mailbox.org> --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 77e8bbd..fe6ddcf 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -139,7 +139,7 @@ searchtool() # A workaround for OSX 10.9 and some BSDs, whose nongnu # patch and tar also work. if [ $UNAME = "Darwin" -o $UNAME = "FreeBSD" -o $UNAME = "NetBSD" -o $UNAME = "OpenBSD" ]; then - if [ "$1" = "patch" -o "$1" = "tar" ]; then + if [ "$1" = "patch" -o "$1" = "tar" -o "$1" = "g++" -o "$1" = "clang" ]; then if [ -x "$(which $1 2>/dev/null)" ]; then echo $1 return

1 0

Patch merged into coreboot/master: x86: Align CBFS on top of ROM
by gerrit＠coreboot.org 29 Dec '15

29 Dec '15

the following patch was just integrated into master: commit 65e33c08a9a88c52baaadaf515b9591856115a77 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Dec 28 20:17:13 2015 +0100 x86: Align CBFS on top of ROM Since the introduction of the new (interim?) master header, coreboot searches the whole ROM for CBFS entries. Fix that by aligning it on top of the ROM. Change-Id: I080cd4b746169a36462a49baff5e114b1f6f224a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/12810 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12810 for details. -gerrit

1 0

Patch set updated for coreboot: MAINTAINERS: Designate Intel maintainers for FSP 1.0 Baytrail
by Martin Roth 29 Dec '15

29 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11894 -gerrit commit 7c0fbb32391343d7ad0f169ae553252971aaadb1 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 13 17:30:04 2015 -0700 MAINTAINERS: Designate Intel maintainers for FSP 1.0 Baytrail After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I62b2eaec8270ac1fce5bfbee3b3da68aba116b0f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Martin Roth <martinroth(a)google.com> --- MAINTAINERS | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 9680a50..bb12251 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -154,14 +154,21 @@ F: src/mainboard/intel/cougar_canyon2/ F: src/mainboard/intel/stargo2/ INTEL MINNOWBOARD MAX MAINBOARD +M: Huang Jin <huang.jin(a)intel.com> +M: York Yang <york.yang(a)intel.com> M: Martin Roth <gaumless(a)gmail.com> -S: Maintained +S: Supported F: src/mainboard/intel/minnowmax/ -INTEL FSP BAYTRAIL CHIP +INTEL FSP BAYTRAIL CHIP & CRBs +M: Huang Jin <huang.jin(a)intel.com> +M: York Yang <york.yang(a)intel.com> M: Martin Roth <gaumless(a)gmail.com> -S: Odd Fixes +S: Supported F: src/soc/intel/fsp_baytrail/ +F: src/vendorcode/intel/fsp1_0/baytrail/ +F: src/mainboard/intel/bakersport_fsp/ +F: src/mainboard/intel/bayleybay_fsp/ FSP 1.0 RANGELEY & CRB M: David Guckian <david.guckian(a)intel.com> @@ -179,10 +186,11 @@ S: Supported F: src/mainboard/intel/littleplains/ INTEL FSP 1.0 +M: Huang Jin <huang.jin(a)intel.com> +M: York Yang <york.yang(a)intel.com> M: Martin Roth <gaumless(a)gmail.com> -S: Odd Fixes +S: Supported F: src/drivers/intel/fsp1_0/ -F: src/vendorcode/intel/fsp1_0/ INTEL FSP 1.1 M: Lee Leahy <leroy.p.leahy(a)intel.com>

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coreboot-gerrit December 2015